Section 1: Project Week I Report

Introduction
⚫ Objective
The overall objective is to design a speed measuring device based on HB100 module and
STM32 microcontroller. The initial stage for the project is to manipulate the original signal
from the radar to access the appropriate signal for further processing. A bandpass filter
with amplification was designed to eliminate the noise and amplify the radar output
signal. Besides, a DC offset is needed to shift the signal upward or downward to make it
within the proper voltage range. The processed signal should be within a range from 0
to 3.3 𝑉, and would then be taken for Fast Fourier Transform in STM32 microcontroller.

During the first project session, HB100 implementation was conducted, the
corresponding waveform was checked to determine the gain factor and offset voltage
level. Besides, doppler frequencies were computed for the refence of cut-off frequencies
of the bandpass filter. The passive components were selected accordingly. Simulation was
made to check the performance of the filter. Eventually, the filter circuit was constructed
on both breadboard and stripboard.

⚫ Background Information
According to Doppler principal, if a signal has been generated by a radar, the frequency
of the reflected signal has the following mathematical relationship with the target velocity:
𝑓𝑡
𝑓𝑑 = 2𝑣 ∙ 𝑐𝑜𝑠𝜃 𝑒𝑞𝑛. 1
𝑐
Where:
𝑓𝑑 is doppler frequency
𝑓𝑡 is transmit frequency
𝑣 is the relative velocity between radar and the moving object
𝑐 is the speed of light
𝜃 is angle between radar and the moving object

The assumptions were made that 𝑓𝑡 was in typical setting (which is 10.525 𝐺𝐻𝑧) and
𝜃 was 90°.

Figure 1. HB100 Radar module

1
 Figure 1 displays the diagram and layout of HB100 radar module in which the IF pin can
generate signal. The reflected signal frequency varies according to doppler principal, and
the reflected frequency is denoted by 𝑓𝑑 .

There is a build-in ADC in STM32 microcontroller, but STM32s are only capable to process
signal within a range from 0 to 3.3 𝑉.

⚫ Method
The HB100 radar module was powered by a DC power supply, the IF pin was connected
to input probe of an oscilloscope.

Figure 2. Output signal of HB100

The waveform generated by radar module was shown on figure 2, the peak-to-peak value
was around 96 𝑚𝑉 . An amplification factor was chosen to be 30. Theoretically, the
amplified signal is from 3.72 𝑉 to 0.84 𝑉, which has surpassed acceptable maximum
voltage, so the DC offset level should be:

0 𝑉 − 0.84 𝑉 < 𝑉𝑜𝑓𝑓𝑠𝑒𝑡 < 3.3 𝑉 − 3.72𝑉 𝑒𝑞𝑛. 2

The offset voltage should be from −0.84 𝑉 to −0.42 𝑉.

Target velocity was from 4 𝑚/𝑠 to 60𝑚/𝑠 thus, according to equation 1, the frequency
of output signal is from 78 𝐻𝑧 to 1170 𝐻𝑧, which is also the cut-off frequencies of the
filter passband.

2
 Figure 3. Schematic of the bandpass filter

Figure 3 shows the circuit of the bandpass filter, the component values follow the
equations below:
1
𝑓ℎ = = 78 𝐻𝑧 𝑒𝑞𝑛. 3
2𝜋𝑅1 𝐶1
1
𝑓𝑙 = = 1170 𝐻𝑧 𝑒𝑞𝑛. 4
2𝜋𝑅2 𝐶2
𝑅4
𝐺 =1+ 𝑒𝑞𝑛. 5
𝑅3

The 𝑅1 , 𝑅2 , 𝑅3 , 𝑅4 values were selected to be 10 𝑘Ω , 300𝑘Ω , 10𝑘Ω , 300𝑘Ω

respectively while 𝐶1 and 𝐶2 were 204 𝑛𝐹 and 0.5 𝑛𝐹 respectively.

V(n003)
35dB
28dB
21dB
14dB 78.37Hz,26.81dB 1.17KHz,26.34dB
7dB
0dB
-7dB
-14dB
-21dB
-28dB
-35dB
-42dB
-49dB
100mHz 1Hz 10Hz 100Hz 1KHz 10KHz 100KHz 1MHz

Figure 4. simulated result of bandpass filter.

A simulation was implemented with LTspice, the amplitude response was shown in figure
4. For signal in cut-off frequency, the amplitude can be boosted by around 26 𝑑𝐵, namely
19.95 times of input signal. The maximum amplification factor was computed to be
28.21.

The filter circuit was built and tested on a breadboard before soldered with stripboard.
During the test, ±5𝑉 DC power supply was used to power up the op-amp, the input
signal was sinusoidal signal from a sinewave generator. In the practical context, no 0.5 𝑛𝐹
capacitor was available in the lab so 2 1 𝑛𝐹 capacitors were connected in series. Since
the amplitude of output signal from HB100 was around 124 𝑚𝑉 , the sinewave was

3
 initialized to be 100 𝑚𝑉. Input signals with 3 different frequencies (50𝐻𝑧, 500𝐻𝑧 and
1500 𝐻𝑧 ) were tested orderly. Non-zero DC offset was fed to signal from sinewave
generator during each test.

⚫ Result

Figure 5. 50 𝐻𝑧 signal testing result

Figure 5 shows the filter output when signal was in 50 𝐻𝑧. The peak-to-peak value was
boosted from 200 𝑚𝑉 to 1.32 𝑚𝑉 which means the output voltage was amplified for
6.6 times. When input offset was set to be 0, there was still 20 𝑚𝑉 offset remained for
output signal.

Figure 6. 500 𝐻𝑧 signal testing result

4
 Figure 6 demonstrates the output waveform when a 500 𝐻𝑧 signal was fed to the filter.
The amplified 𝑉𝑝𝑝 was 2.08 𝑉 which indicates that the output signal was increased by
10.4 times. Still, a 40 𝑚𝑉 offset remains when input offset was modified to be 0.

Figure 7. 1500 𝐻𝑧 signal testing result (temporarily blank)

The result for 1500 𝐻𝑧 signal has yet taken and will be added when the lab is available.

V(n003)
35dB
28dB
21dB
14dB 499.94Hz,28.85dB
49.74Hz,24.43dB 1.50KHz,25.05dB
7dB
0dB
-7dB
-14dB
-21dB
-28dB
-35dB
-42dB
-49dB
100mHz 1Hz 10Hz 100Hz 1KHz 10KHz 100KHz 1MHz

Figure 8. Amplitude response at 3 different frequencies

The amplitude response for the tested frequencies was marked in figure 8. By exponential
computation, the ideal amplification factor for 50𝐻𝑧, 500 𝐻𝑧 and 1500 𝐻𝑧 is 16.65,
27.70 and 17.89 respectively, far higher than the tested values.

The DC offset of output signal kept constant regardless of how input offset was changed.
This phenomenon has occurred for both real circuit testing and simulation. A slight
positive offset was generated during the test. Besides, the offset shows an increasing
trend when frequency of input signal increased. No offset was observed in simulation
result.

⚫ Discussion
The difference of the decibel value between simulated result and tested result was
8.04 𝑑𝐵 (50 𝐻𝑧 ) and 8.41 𝑑𝐵 (500 𝐻𝑧 ) respectively. The two difference values are
close to each other and show increasing tendency when frequency increased. An
approximation on practical amplitude response was made. The amplitude responses for
simulated result and approximated practical result are demonstrated with figure 9.

5
 Figure 9. Amplitude response curves of simulated and tested result

In figure 9, the green curve represents the simulated amplitude response while the blue
curve denote the practical amplitude response. One explanation for the difference
between those curves is the input impedance which caused an extra voltage drop.
Consequently, the input voltage had experienced a decline before transferring through
the filtering system. This voltage drop can be mitigated by having larger 𝑅1 value
(correspondingly, 𝐶1 value should be lowered).

For the amplification circuit, in practical situation, there is an extra resistor cascade to
both 𝑅3 and 𝑅4 , if the added resistors are identical, the practical gain can be expressed:
𝑅4 + Δ𝑅
𝐺𝑝 = +1
𝑅3 + Δ𝑅
(𝐺𝑖 − 1)𝑅3 + Δ𝑅
𝐺𝑝 = +1
𝑅3 + Δ𝑅
𝐺𝑖 (𝑅3 + Δ𝑅) (𝐺𝑖 − 1)Δ𝑅 + 𝑅3
𝐺𝑝 = − +1
𝑅3 + Δ𝑅 𝑅3 + Δ𝑅
(𝐺𝑖 − 2)Δ𝑅
𝐺𝑝 = 𝐺𝑖 − 𝑒𝑞𝑛. 6
𝑅3 + Δ𝑅

According to equation 6, the error between practical gain 𝐺𝑝 and ideal gain 𝐺𝑖 can be
enlarged when either Δ𝑅 or 𝐺𝑖 increased. Since Δ𝑅 cannot be decreased easily, one
way to drive down the error and energy loss is to add another filtering system and
decrease the amplification factor for each system. This strategy can also provide a
superior performance in noise elimination.

For the DC offset, the capacitor 𝐶1 which was directly connected to input port has
blocked the added DC voltage so no matter how input offset was changed, the output
offset kept constant. Thus, the offset cannot be fed by merely changing the input offset.

The voltage level of the undesired positive DC offset was low, so it was neglected.

⚫ Conclusion
For the amplification circuit, the signal was not distorted but a power loss occurred, the
prime reasons were assumed to be the input impedance and the existence of unwanted
resistors (Δ𝑅) connected to both 𝑅3 and 𝑅4 . To mitigate the adverse impact, 𝑅1 value
can be increased to weaken the voltage drop. One more filtering system can be

6
 introduced into the circuit to provide a better noise reduction performance while
decrease the error in amplification factor. For each filtering circuit, the proportion
between 𝑅3 and 𝑅4 need to be lowered.

The offset voltage cannot be introduced by modifying input signal, but a proposal was to
Voffset

connect a voltage divider to output port. And feed the voltage divider with a DC power
supply. Schematic shown in figure 10.
V1

Voffset
R4
1
300k
R3
10k R10
10k
V+ U1 R2
C1
Vin
LT1498 300k
V-

204e-9
C2 R11
R1 10k
0.5e-9
10k

Figure 10. Filtering system with DC offset

The resistors used in potential divider can be replaced by potentiometers to modify the
offset voltage timely.

7
Section 2: Filter Design Assignment
Task 1. Evaluation on 3 Various Filters

⚫ Butterworth filter
Butterworth filters are termed as the maximally-flat-response filter [1], which means they
possess the highest level of gain flatness in passband. Besides, when identically ordered,
the roll-off rate in transition band of a Butterworth filter is higher than that of a Bessel
filter and lower than a Chebyshev filter. Besides, Butterworth filters generate moderate
overshoot and ringing in transient response when a pulse signal is fed as input.

⚫ Chebyshev filter
Chebyshev filters are characterized for their steep roll off rate after cut-off frequency, so
a lower order Chebyshev filter could satisfy the specifications compared to Butterworth
filters. But Chebyshev filters exhibit less linear-phase characteristic than Butterworth
filters [2]. Besides, they show more overshoot and ringing in transient response than
Butterworth filters.

⚫ Bessel filter
One prime advantage of Bessel filters is their linear phase response which provide
identical time shift for each signal component to prevent the distortion of the combined
signal. Bessel filters are widely used where a constant group delay is critical (for example
in analogue video signal processing) [3]. Besides, Bessel filters possess excellent response
to a pulse input [1]. The main disadvantage of Bessel filters is their low roll off speed.

Task 2. High-pass Butterworth Filter in Sallen-Key topology

⚫ Deciding Order Number

According to the specification, stopband attenuation is 30dB so amplitude response in
50Hz is:
20 log|𝐻(𝜔 = 2𝜋50)| = −3𝑑𝐵 − 30𝑑𝐵 = −33𝑑𝐵 𝑒𝑞𝑛. 1

Substituting 𝜔 = 2𝜋 ∙ 50𝐻𝑧 into equation 2 below:

1
|𝐻(𝑗𝜔)| = 𝑒𝑞𝑛. 2
𝜔 2𝑁
√1 + ( 𝑝 )
𝜔
N is computed:
1
𝑁 = 𝑙𝑜𝑔2 [103.3 − 1] ≈ 5.48 𝑒𝑞𝑛. 3
2

To evaluate either 5th-order or 6th-order filter satisfy the given specification, stopband
attenuation for N = 5 and 6 are calculated:

8
 100 2×5
𝐴𝑡𝑡𝑒𝑛𝑢𝑎𝑡𝑖𝑜𝑛 (𝑁 = 5) = −3𝑑𝐵 − [−10 log (1 + ( ) )] ≈ 27.107𝑑𝐵 𝑒𝑞𝑛. 4
50

100 2×6
𝐴𝑡𝑡𝑒𝑛𝑢𝑎𝑡𝑖𝑜𝑛 (𝑁 = 6) = −3𝑑𝐵 − [−10 log (1 + ( ) )] ≈ 33.125𝑑𝐵 𝑒𝑞𝑛. 5
50

Since the 5th-order filter have a stopband attenuation closer to 30dB, the order is selected
to be 5.

⚫ Rearranging Transfer Function

According to Butterworth polynomial table, the transfer function for a 5th-order
Butterworth lowpass filter is:

1
𝐻𝑙𝑜𝑤 (𝑠) = 𝑒𝑞𝑛. 6
(1 + 𝑠)(1 + 0.618𝑠 + 𝑠 2 )(1 + 1.618𝑠 + 𝑠 2 )

To get high pass filter transfer function, each individual term from 𝐻𝑙𝑜𝑤 (𝑠) can be
𝜔𝑐
rewritten by switching 𝑠 with 𝑠
:

1 𝑠
𝐻1 (𝑠) = 𝜔𝑐 = 𝑠 + 𝜔 𝑒𝑞𝑛. 7
1+ 𝑠 𝑐

1 𝑠2
𝐻2 (𝑠) = = 𝑒𝑞𝑛. 8
𝜔 𝜔 2 𝑠 2 + 0.618𝜔𝑐 𝑠 + 𝜔𝑐2
1 + 0.618 𝑠𝑐 + ( 𝑠𝑐 )

1 𝑠2
𝐻3 (𝑠) = = 𝑒𝑞𝑛. 9
𝜔 𝜔 2 𝑠 2 + 1.618𝜔𝑐 𝑠 + 𝜔𝑐2
1 + 1.618 𝑠𝑐 + ( 𝑠𝑐 )

General form frequency responses can be accessed by substituting 𝑗𝜔 into 𝑠 and

dividing 𝜔𝑐 or 𝜔𝑐2 for both numerator and denominator:

𝑗𝜔
𝑗𝜔 𝜔𝑐
𝐻1 (𝑗𝜔) = = 𝑒𝑞𝑛. 10
𝑗𝜔 + 𝜔𝑐 𝑗𝜔 + 1
𝜔𝑐

𝜔 2
−𝜔 2 − (𝜔 )
𝑐
𝐻2 (𝑗𝜔) = = 𝑒𝑞𝑛. 11
−𝜔 2 + 0.618𝑗𝜔𝑐 𝜔 + 𝜔𝑐2 𝜔 2 1 𝑗𝜔
−( ) + +1
𝜔𝑐 𝑄1 𝜔𝑐

𝜔 2
−𝜔2 − (𝜔 )
𝑐
𝐻3 (𝑗𝜔) = = 𝑒𝑞𝑛. 12
−𝜔 2 + 1.618𝑗𝜔𝑐 𝜔 + 𝜔𝑐2 𝜔 2 1 𝑗𝜔
−( ) + +1
𝜔𝑐 𝑄2 𝜔𝑐

9
⚫ First Order Filter Design

V1
C1

C
V
R1
R

Figure 1. schematic of 1st order high pass filter

In figure 1, the mathematical relationship between output and input voltage can be
expressed:

𝑉𝑜𝑢𝑡 (𝑡) + 𝑉𝑐 = 𝑉𝑖𝑛 (𝑡) 𝑒𝑞𝑛. 13

1
𝑉𝑜𝑢𝑡 (𝑡) + ∫ 𝑉0 (𝑡) 𝑑𝑡 = 𝑉𝑖𝑛 (𝑡) 𝑒𝑞𝑛. 14
𝑅𝐶

Taking Laplace Transform:

1
𝑉̃𝑜𝑢𝑡 (𝑠) + 𝑉̃ (𝑠) = 𝑉̃𝑖𝑛 (𝑠) 𝑒𝑞𝑛. 15
𝑠𝑅𝐶 𝑜𝑢𝑡
𝑉̃𝑜𝑢𝑡 (𝑠) 𝑠
= 𝑒𝑞𝑛. 16
𝑉̃𝑖𝑛 (𝑠) 𝑠+
1
𝑅𝐶
1
Comparing equation 16 with 𝐻1 (𝑠), 𝜔𝑐 =
𝑅𝐶

According to H62EPC notes, the selected resistor values should be from 1 𝑘Ω to 100 𝑘Ω
(to prevent overlarge current flow in op-amps and restrict Johnson noise) while the
capacitor value should be in a range from 1 𝑛𝐹 to several 𝜇𝐹 (small capacitance can
lead to comparable parasitic capacitance and large capacitance could make the whole
circuit bulky).

The capacitor is selected to be 470 𝑛𝐹. So, the resistance of the resistor is:

1 1
𝑅1 = = ≈ 3.39 𝑘Ω 𝑒𝑞𝑛. 17
𝜔𝑐 ∙ 𝐶 470 × 10−9 𝐹 × 2𝜋 × 100𝐻𝑧

⚫ First-Stage 2nd Order Filter Design

Referring to a filter design specification in “Active Low Pass Filter Design”, two sets of

10
capacitor and resistor can be set in ratios to simplify the designing process [1]. Thus, the
components are assigned:

𝑅1𝑎 = 𝑅 𝑒𝑞𝑛. 18
𝑅2𝑎 = 𝑚1 𝑅 𝑒𝑞𝑛. 19
𝐶1𝑎 = 𝐶 𝑒𝑞𝑛. 20
𝐶2𝑎 = 𝑛1 𝐶 𝑒𝑞𝑛. 21

The value of corner frequency 𝑓𝑐 is:

1 1
𝑓𝑐 = = 𝑒𝑞𝑛. 22
2𝜋√𝑅1𝑎 𝑅2𝑎 𝐶1𝑎 𝐶2𝑎 2𝜋𝑅𝐶 √𝑚1 𝑛1

𝑄1 value can be rewritten:

√𝑅1𝑎 𝑅2𝑎 𝐶1𝑎 𝐶2𝑎 𝑅𝐶 √𝑚1 𝑛1 √𝑚1 𝑛1

𝑄1 = = = 𝑒𝑞𝑛. 23
𝑅1𝑎 𝐶1𝑎 + 𝑅1𝑎 𝐶2𝑎 𝑅1𝑎 𝐶(𝑛1 + 1) 𝑛1 + 1

According to equation 11, 𝑄1 equals:

1
𝑄1 = ≈ 1.618 𝑒𝑞𝑛. 24
0.618

The equation for quality factor (both 𝑄1 and 𝑄2 ) can be rewritten:

√𝑚𝑛 = 𝑄(𝑛 + 1)
𝑄 2 (𝑛 + 1)2
𝑚=
𝑛
1
𝑚 = 𝑄 2 (𝑛 + + 2) 𝑒𝑞𝑛. 25
𝑛

When 𝑛 = 1, 𝑚 has the minimum value 4𝑄 2 , which is roughly 10.47 in the first-stage
2nd order filter. It means the value for selected 𝑅 value should be no more than 9.54 𝑘Ω
otherwise resistance of 𝑅1𝑎 would be larger than 100 𝑘Ω , which could cause
unneglectable Johnson noise. So, to provide a wider selection range for resistor value, 𝑚
should be minimized. Thus, for the first-stage 2nd order filter, 𝑚 = 10.47, 𝑛 = 1.

For 𝑅 and 𝐶 value, the equation of cut-off frequency can be rearranged:

1 1
𝑓𝑐 = = 𝑒𝑞𝑛. 26
2𝜋𝑅𝐶 ∙ 𝑄1 (𝑛1 + 1) 2𝜋𝑅𝐶 × 3.236

1
𝑅𝐶 = ≈ 4.92 × 10−4 𝐻𝑧 −1 𝑒𝑞𝑛. 27
2𝜋 × 100𝐻𝑧 × 3.236
11
 To provide an appropriate value for 𝑅 , the 𝐶 value is selected to be 100 𝑛𝐹 . The
corresponding 𝑅 value is:
1
𝑅= ≈ 4.92𝑘Ω 𝑒𝑞𝑛. 28
2𝜋 × 100𝐻𝑧 × 3.236 × 100 × 10−9 𝐹

Component coefficients for the first-stage 2nd order filter are:

𝑅1𝑎 = 4.92 𝑘Ω 𝑒𝑞𝑛. 29
𝑅2𝑎 = 10.47 × 4.92𝑘Ω ≈ 51.49 𝑘Ω 𝑒𝑞𝑛. 30
𝐶1𝑎 = 𝐶2𝑎 = 100 𝑛𝐹 𝑒𝑞𝑛. 31

⚫ Second-Stage 2nd Order Filter Design

Components for second-stage filter:

𝑅1𝑏 = 𝑅′ 𝑒𝑞𝑛. 32
𝑅2𝑏 = 𝑚2 𝑅′ 𝑒𝑞𝑛. 33
𝐶1𝑏 = 𝐶′ 𝑒𝑞𝑛. 34
𝐶2𝑏 = 𝑛2 𝐶′ 𝑒𝑞𝑛. 35

According to quality factor equation:

√𝑅1𝑏 𝑅2𝑏 𝐶1𝑏 𝐶2𝑏 𝑅′𝐶′√𝑚2 𝑛2 √𝑚2 𝑛2
𝑄2 = = = 𝑒𝑞𝑛. 36
𝑅1𝑏 𝐶1𝑏 + 𝑅1𝑏 𝐶2𝑏 𝑅1𝑏 𝐶′(𝑛2 + 1) 𝑛2 + 1
𝑄2 ≈ 0.618 𝑒𝑞𝑛. 37
1
𝑚2 = 𝑄22 (𝑛2 + + 2) 𝑒𝑞𝑛. 38
𝑛2

𝑛2 is chosen to be 1 thus 𝑚 is computed to be roughly 1.53.

Referring to corner frequency of the filter:

1 1
𝑓𝑐 = = 𝑒𝑞𝑛. 39
2𝜋𝑅′𝐶′ ∙ 𝑄2 (𝑛2 + 1) 2𝜋𝑅′𝐶′ × 1.236
1
𝑅′𝐶 ′ = ≈ 1.29 × 10−3 𝑒𝑞𝑛. 40
2𝜋 × 100𝐻𝑧 × 1.236

To minimize the difference between the exact component values and E24 reference
values. 𝐶′ is assigned to be 30 𝑛𝐹.

Corresponding 𝑅′ value is:

1
𝑅′ = ≈ 42.9𝑘Ω 𝑒𝑞𝑛. 41
2𝜋 × 100𝐻𝑧 × 1.236 × 30 × 10−9 𝐹

Component values for second-stage 2nd order filter:

12
 𝑅1𝑏 = 49.2 𝑘Ω 𝑒𝑞𝑛. 42
𝑅2𝑏 = 1.53 × 49.2𝑘Ω ≈ 75.28 𝑘Ω 𝑒𝑞𝑛. 43
𝐶1𝑏 = 𝐶2𝑏 = 30 𝑛𝐹 𝑒𝑞𝑛. 44

⚫ AC Simulation Analysis
Vin

V+

V-
V1 V2 V3

AC 1 5 -5
SINE(0 1 20)
R5
R3
75.28k
51.49k

V+
V+
U2
U1 C5 C4
C1 C3 C2
Vin LT1498

V-
LT1498 30n 30n

V-
470n 100n 100n
R4
R1 R2
3.39k 49.2k
4.92k
.tran 0.05

;ac dec 100 0.1 100000000k

Figure 2. Schematic of overall circuit.

All filters are combined to form the whole circuit (shown in figure 2).
V(n001)
60dB
30dB 50.40Hz,-28.37dB
0dB
-30dB
10.02Hz,-97.55dB
-60dB 100.90Hz,-3.54dB
-90dB
-120dB
1.02Hz,-196.78dB
-150dB
-180dB
-210dB
-240dB
-270dB
-300dB
100mHz 1Hz 10Hz 100Hz 1KHz 10KHz 100KHz 1MHz 10MHz 100MHz 1GHz 10GHz 100GHz

Figure 3. Amplitude response of figure

The amplitude response accessed by AC analysis is shown in figure 3. Referring to data

points, when 𝑓 equals 1 𝐻𝑧 and 10 𝐻𝑧, the roll off rate is around 99.23/𝑑𝑒𝑐, which
is close to the standard roll off rate of a 5th-order filter.

The magnitude is roughly −3.54 𝑑𝐵 when frequency reaches 100 𝐻𝑧. For frequency at
50 𝐻𝑧, the magnitude is at around −28.37 𝑑𝐵. So, the stop band attenuation is:

𝐴𝑡𝑡𝑒𝑛𝑢𝑎𝑡𝑖𝑜𝑛(𝑟𝑒𝑎𝑙) = −3.54𝑑𝐵 − (−28.37𝑑𝐵) = 24.83 𝑑𝐵 𝑒𝑞𝑛. 45

The simulated attenuation is lower than the theoretical value which is 27.107 𝑑𝐵 ,
partially because of the relatively low magnitude when 𝑓 is at 100 𝐻𝑧 . Besides, to
guarantee a higher simplicity of circuit, no voltage follower was connected between each

13
 single filters, this might also lead to the difference between computed and simulated
stopband attenuation value.

When frequency is at 103.06 𝐻𝑧, the amplitude response is at around −3.10 𝑑𝐵, thus
−3 𝑑𝐵 point is roughly at 103.06 Hz.

⚫ Discussion on High cut-off Frequency

Figure 4. Amplitude response

Figure 4 exhibits the amplitude response when signal go through the 1st order filter, the
first two filters and the overall filters. The high cut-off frequency is around 10.16 𝑀𝐻𝑧
(marked with red arrow and text). When frequency is increased far larger than 10 𝑀𝐻𝑧,
the adjacent lines have difference at around 40 𝑑𝐵 and there is no high cut-off
frequency for the green curve. So, it was assumed that the high cut-off frequency is
caused by the restriction of the practical op-amp (LT1498). Referring to LT1498 data sheet,
the gain-bandwidth product of LT1498 is 10 𝑀𝐻𝑧, which confirmed the assumption.

⚫ Transient Simulation Analysis

V(n001)
1.2V
1.0V
0.8V
29.93ms,1.05V
0.6V
0.4V
0.2V
0.0V
-0.2V
-0.4V
-0.6V 32.46ms,-1.01V
-0.8V
-1.0V
-1.2V
0ms 5ms 10ms 15ms 20ms 25ms 30ms 35ms 40ms 45ms 50ms

Figure 5. Waveform for 200 Hz signal

Figure 5 demonstrates the waveform of output signal from the filter when input signal is
at 200 𝐻𝑧 . Theoretically, for signal which have frequency higher than 100 𝐻𝑧 , the
output signal should be around 1 𝑉. The simulated output signal has magnitude close to
1 𝑉 , which match the predicted result for passband signal. Thus, the simulated result
match the theoretical result.

According to the simulated amplitude response from LTspice, the gain of the filter is
approximately 0.3 𝑑𝐵 at 200 𝐻𝑧 which means magnitude of output voltage can be
around 1.035 times of the input signal. But figure 5 shows that the peak and bottom
value is 1.05 𝑉 and −1.01 𝑉 respectively, which means a small DC component is

14
introduced. The voltage level for DC component is small, so for passband signal, it is
neglectable.

V(n001)
40mV
36mV
32mV
28mV
35.020833ms,18.788727mV
24mV
20mV
16mV
12mV
8mV
4mV
0mV
-4mV
0ms 5ms 10ms 15ms 20ms 25ms 30ms 35ms 40ms 45ms 50ms

Figure 6. Waveform for 10 𝐻𝑧 signal

Theoretically, the output signal should be close to 0 at 10 𝐻𝑧. The amplitude response
for 10 𝐻𝑧 is simulated to be roughly −97.55 𝑑𝐵 which means the output signal should
be around 1.33 × 10−5 times of the input signal. But figure 6 shows that an
unneglectable DC offset was involved.

Figure 7. Output signal at 3 different points

Figure 8. schematic of filter with extra capacitor on output point

The waveforms V(n001), V(n002), V(n003) shown in figure 6 denote voltage in n1, n2 and
n3 points (points are marked in figure 8). An extra 100𝑛𝐹 capacitor was added after n1
to block the generated DC offset and furtherly discuss the value of the DC offset (the extra
capacitor was excluded in the submitted LTspice files). Amplitude response in point n1

15
 and n3 are identical thus no impact was made after including the extra capacitor. The
waveform at n3 point has amplitude at ±13.2 𝜇𝑉 which match the simulated amplitude
response.

V(n002) denotes the voltage level at the output port of the first-stage 2nd order filter.
Specifically, the first-stage filter generates DC component at around 12.87 𝑚𝑉 .
Furthermore, the overall filter generated DC offset at roughly 18.815 𝑚𝑉. The generated
DC offset for a 10 𝐻𝑧 signal is far higher than that of a 200 𝐻𝑧 signal (shown in former
part). So, the DC component is frequency dependent.

Task 3. Further Analysis on the High Pass Filter

⚫ Simulation with E24 Series Components

Vin

V+

V-

V5 V3 V4

AC 1 5 -5
SINE(0 1 10)
R5
R3
75k
51k

V+
V+

U2 C6
U1 n2 C5 C4 n1 n3
C1 C3 C2
Vin LT1498 100n

V-
LT1498 30n 30n
V-

470n 100n 100n

R4
R1 R2
3.3k 51k
5.1k
;tran 0.5
.ac dec 100 0.1 100000000k

Figure 9. Circuit schematic with practical capacitance and resistance

Referring to the “Preferred Component Value Calculator” [4], the practical values for
resistors and capacitors are computed (shown in figure 9).

V(n001)
60dB
30dB
0dB
-30dB
-60dB 103.06Hz,-3.10dB
-90dB
-120dB
-150dB
-180dB
-210dB
-240dB
-270dB
-300dB
100mHz 1Hz 10Hz 100Hz 1KHz 10KHz 100KHz 1MHz 10MHz 100MHz 1GHz 10GHz 100GHz

Figure 10. Waveform for circuit with practical components

Amplitude response for a more practical filter is shown in figure 10. The new
−3𝑑𝐵 frequency is around 104.31 𝐻𝑧

16
⚫ High Pass Filter with Amplification

Vin

V+

V-
V1 V2 V3

AC 1 5 -5 R6
SINE(0 1 10)
R5 R
R3
75.28k R7
51.49k

V+
R

V+
U2 C6
U1 n2 C5 C4 n1 n3
C1 C3 C2
Vin LT1498 100n

V-
LT1498 30n 30n

V-
470n 100n 100n
R4
R1 R2
3.39k 49.2k
4.92k
.tran 0.5
;ac dec 100 0.1 100000000k

Figure 11. High pass filter with gain

To include a gain to the filter, extra resistors 𝑅6 and 𝑅7 can be added onto the second-
stage filter (shown in figure 11).

For the high pass filter, when gain is not 1 , the quality factor 𝑄 should be
rewritten [5]:

√𝑅4 𝑅5 𝐶4 𝐶5
𝑄= 𝑒𝑞𝑛. 46
𝑅4 (𝐶4 + 𝐶5 ) + 𝑅5 𝐶4 (1 − 𝐾)

Quality factor is no longer independent from gain when gain is not 1. Therefore,
to include an amplification within the circuit, all the passive component for the
second-stage filter ( 𝑅4 , 𝑅5 , 𝐶4 , 𝐶5 ) should be modified to keep 𝑄 value
unchanged.

The value of 𝐾 is:

𝑅6
𝐾 =1+ 𝑒𝑞𝑛. 47
𝑅7

Similar operation can be made for the first-stage filter either, the overall gain is
the product of each gain.

17
Reference
[1] ”Active Lowpass Filter Design”, TI Application Note [Link] [Link]
/lit/an/sloa049b/[Link]

[2] [Link]
byshev,of%20design%20for%20specific%20cases.

[3] [Link]

[4] [Link]

[5] “Texas Instruments Application Report: Analysis of Sallen-Key Architecture”, TI Application

Note [Link] [Link]

18