ATRIA INSTITUTE OF TECHNOLOGY

(Affiliated To Visvesvaraya Technological University, Belgaum)

Anandanagar, Bangalore-24

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ANALOG CIRCUITS LAB MANUAL

FOURTH SEMESTER ELECTRONICS AND COMMUNICATION

SUBJECT CODE: 18ECL48

2019-20
 ATRIA INSTITUTE OF TECHNOLOGY
(Affiliated To Visvesvaraya Technological University, Belgaum)
Anandanagar, Bangalore-24

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ANALOG CIRCUITS LAB MANUAL

The Computer Networks Laboratory Manual pertaining IV semester ECE

has been prepared as per VTU syllabus and all the experiments are designed, tested
and verified according to the experiment list.

This manual typically contains practical/lab sessions related to know the

function and design of various analog circuits like amplifiers, oscillators, filters
etc. Simulation of circuits using multisim helps the students to relate this to the
subject for better understanding. Students are advised to thoroughly go through this
manual as it provides them practical insights.

Good Luck for your Enjoyable Laboratory Sessions

Sl.No. CONTENT Page.No.
PART-A (Hardware)
1 Common Emitter Amplifier 3-6
2 JFET/MOSFET Amplifier 7-10
3 a) Colpitts Oscillator 11-14
b) Crystal Oscillator
4 Second order active Low-Pass Filter and High Pass 15-19
Filter
5 Adder, Integrator and Differentiator using Op-Amp 20-24
6 a) Voltage comparator & Zero Crossing detector 25-29
b) Schmitt Trigger

7 a) 4-bit R-2R ladder network 30-33

b) 4-bit R-2R DAC using mod-16 counter

8 Monostable and Astable Multivibrator using 555 34-38

timer
PART-B (Simulation)
1 Narrow Band-pass Filter and Narrow band-reject 39-42
filter
2 Precision Half Wave and Full Wave Rectifier 43-46
3 RC Phase Shift and Hartley Oscillator 47-50
4 Monostable Multivibrator and AstableMultivibrator 51-56
using 555 Timer
 DEPARTMENT VISION & MISSION

Vision
“Imparting quality technical education through interdisciplinary research & innovation
towards moulding the young talent with professional competence and ethical values for
developing inclusive and sustainable technology in the area of Electronics and
Communication Engineering”.

Mission
Create conducive environment for the holistic development of students and staff members.
⮚ Provide quality technical education to produce industry ready engineers with an
entrepreneurial and research outlook.
⮚ Establish centers of excellence in collaboration with industries/universities for
exposing the students to latest technologies.
⮚ Nurture the students to actively participate in solving the societal problems and
uphold ethics and morality.
⮚ To train the students to meet global challenges in interdisciplinary fields by
inculcating a quest for modern technologies in the emerging areas.
 AC Lab

ATRIA INSTITUTE OF TECHNOLOGY

st
1 Main, AG's Colony, Anandanagar, Bangalore- 560024
Department of Electronics and Communication

ANALOG CIRCUITS LABORATORY

Sub code: 18ECL48 Class: IV SEM EC

Course Learning Objectives: This laboratory course enables students to

 Understand the circuit configurations and connectivity of BJT and FET Amplifiers
and Study of frequency response
 Design and test of analog circuits using OPAMPs
 Understand the feedback configurations of transistor and OPAMP circuits
 Use of circuit simulation for the analysis of electronic circuits.

Course Outcomes: On the completion of this laboratory course, the students will be able
to:
 Design analog circuits using BJT/FETs and evaluate their performance characteristics.
 Design analog circuits using OPAMPs for different applications
 Simulate and analyze analog circuits that usesICs for different electronic applications.

Conduct of Practical Examination:

 All laboratory experiments are to be included for practical examination.
 Students are allowed to pick one experiment from the lot.
 Strictly follow the instructions as printed on the cover page of answer script for
breakup of marks.
 Change of experiment is allowed only once and Marks allotted to the procedure part
to be made zero.

PART A : Hardware Experiments

1. Design and setup the Common Source JFET/MOSFET amplifier and plot the frequency
response.

2. Design and set up the BJT common emitter voltage amplifier with and without feedback
and determine the gain- bandwidth product, input and output impedances.

3. Design and set-up BJT/FET i) Colpitts Oscillator, and ii) Crystal Oscillator

4. Design active second order Butterworth low pass and high pass filters.

5. Design Adder, Integrator and Differentiator circuits using Op-Amp

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6. Test a comparator circuit and design a Schmitt trigger for the given UTP and LTP values
and obtain the hysteresis.

7. Design 4 bit R – 2R Op-Amp Digital to Analog Converter (i) using 4 bit binary input
from toggle switches and (ii) by generating digital inputs using mod-16 counter.

8. Design Monostable and AstableMultivibrator using 555 Timer.

PART-B : Simulation using EDA software (EDWinXP, PSpice, MultiSim, Proteus,

CircuitLab orany other equivalent tool can be used)

1. RC Phase shift oscillator and Hartley oscillator

2. Narrow Band-pass Filter and Narrow band-reject filter
3. Precision Half and full wave rectifier
4. Monostable and AstableMultivibrator using 555 Timer.

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EXPERIMENT 1
COMMON EMITTER AMPLIFIER

Aim: Design and set up the BJT common emitter amplifier using voltage divider bias with and without
feedback and determine the gain- bandwidth product from its frequency response.

Components and equipments required: Transistor – SL100, Resistors - 470 Ω, 1KΩ, 10KΩ - 2nos, and
33KΩ, Capacitors 100μf, 0.22μf and 0.47μf, Power Supply, 10Hz – 3MHz Signal generator, CRO,
Connecting wires and Bread board/Spring board with spring terminals.

Design:
Transistor: SL100
Let VCC = 12V; IC = 4.5 mA; VE = 1.2V; VCE = 6V;
hFE = 100.
Given VE = 1.2V. Therefore RE = VE / IE VE / IC =266.67Ω; RE =270Ω
Writing KVL for the Collector loop we get, VCC = ICRC + VCE + VE
RC = (VCC – VCE – VE) / IC = (12-6-1.2)V/4mA=1.06KΩ; RC = 1 KΩ
hFE RE = 10R2
Assume R2=2.7KΩ,
VB = (Vcc x R2 ) / (R1 + R2)
Hence R1 = 14.14 KΩ ; R1 = 15 KΩ
Use CC1 = 0.47µF
Use CC2 = 0.47µF
Use CE =47µF

Circuit Diagram of amplifier without feedback

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Circuit Diagram of amplifier with feedback. (introduce a resistor in the emitter circuit)

Procedure:
Follow the same procedure for both circuits
1. After making the connections, switch on the D.C. power supply and check the D.C. conditions without
any input signal and record in table below:
2. Select sine wave input and set the input signal frequency ≥10f1 (Say = 10 KHz. This will be a convenient
‘Mid – frequency’).
3. Observe the input wave form and output wave form on a dual channel CRO.
4. Adjust the input amplitude such that the output waveform is just undistorted (or in the verge of becoming
distorted). Measure the amplitude of the Input Signal now. This amplitude is the Maximum Signal
Handling Capacity of your amplifier.
5. Decrease the input voltage to a convenient value such that the output is undistorted. Say 20mV. Measure
the corresponding o/p voltage. Calculate mid-band gain, AM = Vo (p-p) / Vin (p-p).
6. Keeping the input voltage constant, go on reducing the frequency until the output voltage reduces to
0.707 times its value at 10 KHz. The frequency at which this happens gives you the Lower Cut-off
frequency (f1).
7. Keeping the input voltage constant, go on increasing the frequency until the output voltage decreases to
0.707 times its value at 10 KHz. The frequency at which this happens gives you the Upper Cut-off
frequency (f2).
8. Thus you have pre-determined f1 and f2. Find the amplifier band width,
BW = f2 – f1
9. Determine Gain Bandwidth product (GBW product) which is a Figure of Merit of your amplifier as GBW
= AM x BW.
10. Now repeat the experiment by recording values of output voltage versus frequency keeping the input

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voltage at a constant value convenient to you. You should take at least 5 readings below f1 and 5 readings
above f1, at least 5 readings in the mid band, at least 5 readings below f2 and 5 readings above f2.
11. Plot graphs of AV versus Frequency, f and /or M, dB versus Frequency, f on a semi log graph paper.
From the graph determine: Mid –band - gain, Lower and Upper Cut-off frequencies and Band width.
Compute the GBW product and verify with answer obtained earlier.

Observation: Use the tabular column separately for each circuit

Vin (P-P) = …….. V
AV= VO (P-P)/Vin (P-P)
M = 20log (AV), dB

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Expected graph

Result:

Thus the frequency response analysis of CE amplifier with and without feedback are done.

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EXPERIMENT 2

2.JFET/MOSFET AMPLIFIER

Aim: Design, setup and plot the frequency response of Common Source JFET/MOSFET amplifier and
obtain the bandwidth.

Components and equipments required: JFET – BFW10, Resistors - 180 Ω, 1KΩ, 10KΩ and 1MΩ,
Capacitors 47μf, 0.1μf and 0.047μf, Power Supply, 10Hz – 3MHz Signal generator, CRO, Connecting wires
and Bread board/Spring board with spring terminals.

Design:
For BFW10 Junction FET specifications are as below:
VDS max = 30 V, VGS off = -8 V, IDSS min = 8mA, IDSS max = 20mA
Choose IDSS (Min + Max)/2 = (8 + 20)/2= 14 mA,
VP = Max/2 = - 4 V and gm = 3.5 to 6.5 m-mhos
Quiscent-Conditions: IDQ = IDSS/2 = 7mA,
Let IDQ = 5 mA. VDD=12V, VDSQ=VDD / 2=6V
Using these values, we get

let Rs = 330Ω

With this choice of Rs, VS = RSIDQ = 1.65 V

Let RD=1.0 KΩ

RG may be chosen arbitrarily but should be large enough such that overall input impedance is not affected
much. Let RG=1.0 MΩ
CC1 = 1/2лf1Ri will be very small because of large Ri and chosen to be much larger so that it does not
decide f1. Thus CC1=0.1μF
Let RL=10KΩ and f1=300Hz
Typical value of output admittance for BFW10, gd =85μ Mhos
That is, rd =1/ gd = 12KΩ. Therefore RD||rd ≈RD=1KΩ
Now, CC2=1/2лf1 (RD+RL) =0.0482μF Thus select CC2=0.047μF
Choosing XCs=RS/10 = 18Ω at f1/2=150Hz, we get CS=58.9μF let CS=47μF or CS= 100 μF

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Circuit Diagram:

Procedure:
1. Switch on the D.C. power supply and check the D.C. conditions without any input signal and record in
table below:

2. Select
sine wave
input and set the input signal frequency ≥10f1 (Say = 10 KHz. This will be a convenient ‘Mid – frequency’).
3. Observe the input wave form and output wave form on a dual channel CRO.
4. Adjust the input amplitude such that the output waveform is just undistorted (or in the verge of becoming
distorted). Measure the amplitude of the Input Signal now. This amplitude is the Maximum Signal
Handling Capacity of your amplifier.
5. Decrease the input voltage to a convenient value such that the output is undistorted. Say 100mV. Measure
the corresponding o/p voltage. Calculate mid-band gain, AM = Vo (p-p) / Vin (p-p).
6. Keeping the input voltage constant, go on reducing the frequency until the output voltage reduces to
0.707 times its value at 10 KHz. The frequency at which this happens gives you the Lower Cut-off
frequency (f1).
7. Keeping the input voltage constant, go on increasing the frequency until the output voltage decreases to
0.707 times its value at 10 KHz. The frequency at which this happens gives you the Upper Cut-off

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frequency (f2).
8. Thus you have pre-determined f1 and f2. Find the amplifier band width, BW = f2 – f1
9. Determine Gain Bandwidth product (GBW product) which is a Figure of Merit of your amplifier as GBW
= AM x BW.
10. Now repeat the experiment by recording values of output voltage versus frequency keeping the input
voltage at a constant value convenient to you. You should take at least five readings below f1 and 5 readings
above f1, at least 5 readings in the mid band, at least 5 readings below f2 and 5 readings above f2.
11. Plot graphs of AV versus Frequency, f and /or M, dB versus Frequency, f on a semi-log graph paper.
From the graph determine: Mid –band - gain, Lower and Upper Cut-off frequencies and Band width.
Compute the GBW product and verify with answer obtained earlier.
Vin (P-P) = ……..Volts (Constant)

Result:

Thus the frequency response analysis of JFET and MOSFTET amplifier are analysed.

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Plot of Voltage Gain AV versus frequency

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EXPERIMENT 3

3(a).COLPITTS OSCILLATOR

Aim: Design and set-up the following tuned oscillator circuit using BJT, and determine the frequency of
oscillation.
Colpitts Oscillator

LC oscillators are generally used as RF oscillators since they generally used to create high frequency
oscillations. In Colpitts oscillator an LC tank circuit is used for selection of frequency of oscillation. A
voltage divider biased common emitter amplifier is used as amplifier. The amplifier and tank circuit
together provides a phase shift of 360 degrees to satisfy Barkhausen criterion.

Components and equipments required: Transistor SL 100, Resistors 470Ω, 1KΩ 10KΩ and 33 KΩ;
Capacitors 0.1μf - 3nos, Discrete inductances 100 μH – 2 nos, Capacitor 470 pF – 2nos, Power supply,
CRO, Connecting wires etc.
Design:
BJT- Amplifier design is same as given in Common Emitter Amplifier.

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Circuit Diagram:

Procedure:
1. Switch on the Power Supply and check the D.C conditions by removing the coupling capacitor CC1 or
CC2.
2. Connect the coupling capacitors and obtain an output waveform on the CRO. If the o/p is distorted adjust
1- KΩ Potentiometer (R3) to get perfect SINE wave.
3. Measure the period of oscillation and calculate the frequency of oscillation.
4. Compare the measured frequency with re-computed theoretical value for the component values
connected.

Observation:

Result: The frequency of oscillation is …..

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3.(b)CRYSTAL OSCILLATOR

Aim: Design and set-up the crystal oscillator and determine the frequency of oscillation.

Components and equipments required:

Transistor SL 100, Crystal – 2MHz, Resistors 470Ω, 1KΩ 10KΩ and 33 KΩ; Capacitors 0.1μf - 2nos,
Power supply, CRO, Connecting wires etc.

Theory:
Crystal oscillators are used in order to get stable sinusoidal signals despite of variations in temperature,
humidity, transistor and circuit parameters. A piezo electric crystal is used in this oscillator as resonant tank
circuit. Crystal works under the principal of piezo-electric effect. i.e., when an AC signal applied across the
crystal, it vibrates at the frequency of the applied voltage. Conversely if the crystal is forced to vibrate it will
generate an AC signal. Commonly used crystals are Quartz, Rochelle salt etc.

Design:
Let VCC = 12V;
ICQ = 4mA;
VE = (1/10) VCC to (1/5) VCC;
VCE=Vcc/2 = 6V;
hFE = 100.

To find RE: Let us choose VE = 2 V

RE = VE / IE= VE / IC =2 V/ 4 mA =500 Ω; let RE =470Ω
VCC = ICRC + VCEQ + VEQ
RC = (VCC – VCEQ– VEQ) / ICQ = 4.0 V/ 4mA =1.0K Ω; RC= 1K Ω

Assume R2=10kΩ.
VB = VE + VBE = 2 + 0.6 = 2.6V
I2 = Current through R2= VB /R2 = 0.26mA or 260μA

The base current IB = IC / hFE= 4mA / 100= 0.04mA= 40μA

(hFE = βDC = 100, a working value; It varies from 50 to 280 for SL 100)
I1 = Current through R1 = IB+I2 = 300 μA
VR1=VCC– VB=12 – 2.6 =9.4V
R1 =VR1/ I1= 9.4V/300 μA =9400/300 KΩ =31.33KΩ R1 = 33K Ω
CE = CC =0.1μF (Arbitrary, any value which gives a reactance < 10 Ω at Crystal frequency may be used.
reactance of a Capacitor XC = (1/2πfC);

For C = 0.1 μF, XC = 0.8Ω at 2 MHz)

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Circuit Diagram:

Procedure:
1. Switch on the Power Supply and before inserting the crystal check the D.C conditions by removing the
coupling capacitor CC1 or CC2.
2. Insert the crystal and the coupling capacitors and obtain the output waveform on the CRO. If the o/p is
distorted vary 1- KΩ Potentiometer (R3)to get perfect SINE wave.
3. Measure the period of oscillation and calculate the frequency of oscillation.
4. Compare with frequency marked on the crystal.

Observation:

Result:

Thus the given crystal oscillator designed frequency has been verified.

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EXPERIMENT-4
Design active second order Butterworth low pass and high pass filters.

Second Order Active Low Pass Filter

Aim:-To design active second order Butterworth low pass for cutoff frequency 5KHz

Components Required: Op-Amp µA-741, Resistors, Capacitor, Signal Generator,

CRO, Fixed Power supply +12V,0,-12V.

Circuit Diagram:

Figure1. Second order active low pass filter.

Design:

Let Af =1.568 & fc=5KHz

Af = [1 + (Rf/R1)]
1.568-1 = Rf / R1
Rf =5.6 KΩ, When R1=10 KΩ
fc = 1 / 2πRc assume c=0.01µF
R=R2=R3=1 / (2πX 5x103 X 0.01x10-6) = 3.3KΩ
(We can also Choose Rf = (1 kΩ resistor + 10 kΩ potentiometer) for better gain )
Procedure:-
1. Ckt connections are made as shown in the fig.
2. Input voltage is kept constant at 2V p-p
3. The input frequency is varied from 100Hz to 30 KHz
4. At each step corresponding output is measured.
5. The gain in dB is calculated by using the formula AF=20 log (Vo/Vi )

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6. The graph of gain v/s frequency is plotted on the graph sheet.

7. The higher cut-off frequency, roll-off rate are calculated and compared with
Theoretical values.
To find the Roll-off factor for LPF:- Keep the input signal amplitude constant, adjust the
input frequency at 10fc,note the output signal amplitude. The difference in the gain of the
filter at fc and 10fc gives the roll-off factor.
Tabular Column:

Frequency Vo G = 20 log Frequency Vo G = 20 log

f volts (Vo/Vi) db f volts (Vo/Vi) db

100 Hz 2 kHz
200 Hz 3 kHz

300 Hz 4 kHz
400 Hz 5 kHz
500 Hz 6 kHz
600 Hz 7 kHz
700 Hz 8 kHz
800 Hz 9 kHz
900 Hz 10 kHz

1 kHz 20khz

Graph: Frequency Response for Low Pass Filter

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Result: -

Cut-off frequency = ___________ ,

Roll-off factor = ___________

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Second Order Active High Pass Filter

Aim: To design an active second order high pass filter for cutoff frequency 5 KHz

Components Required: Op-Amp µA-741, Resistors, Capacitor, Signal Generator,

CRO, Fixed Power supply +12V,0,-12V.
Circuit Diagram:

Figure2. Second order active High pass filter.

Design:
Let Af =1.568 & fc=5KHz
Af = [1 + (Rf/R1)]
1.568-1 = Rf / R1
Rf =5.6 KΩ , When R1=10 KΩ
fc = 1 / 2πRc assume c=0.01µF
R=R2=R3=1 / (2πX 5x103 X 0.01x10-6) = 3.3KΩ

Procedure:
1. Ckt connections are made as shown in the fig.
2. Input voltage is kept constant at (2V P-P)
3. The input frequency is varied from 100Hz to 50 KHz
4. At each step corresponding output readings are measured.
5. The gain in dB is calculated by using the formula Af=20 log vo/vi
6. The graph of gain v/s frequency is plotted on the graph sheet.
7. The higher cut-off frequency, roll-off rate are calculated and compared with theoretical
values.
To find the Roll-off factor for HPF:- Keep the input signal amplitude constant, adjust the
input frequency at 0.1fc,note the output signal amplitude. The difference in the gain of the
filter at fc and 0.1fc gives the roll-off factor

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Tabular Column:

Frequency Vo G = 20 log Frequency Vo G = 20 log

Hz volts (Vo/Vi) db f volts (Vo/Vi)
100 Hz 2 kHz
200 Hz 3 kHz
300 Hz 4 kHz
400 Hz 5 kHz
500 Hz 6 kHz
600 Hz 7 kHz
700 Hz 8 kHz
800 Hz 9 kHz
900 Hz 10 kHz
1 kHz 20kHz

Graph: Frequency Response for High Pass Filter

Result: -

Cut-off frequency = ___________

Roll-off factor = ___________

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EXPERIMENT-5
Aim: To design operational amplifier as Adder, Integrator and Differentiator

Components: Op-Amp μA 741, Resistors, Capacitor, Signal Generator, CRO, Fixed Power
supply +12V,0,-12V.

a) Op-Amps as summer( Inverting)

Circuit Diagram:

Design :
Design a summing amplifier to obtain a output of –6V. Since inputs are given to Inverting
terminal, output is given by,
Rf Rf Rf 
V0   V1  V2  V3 
 R1 R2 R3 

 Let Rf = R = R1 = R2 = R3 = 1K and R4 = R5 = R6 = 1K
Applying voltage divider method to the circuit
V1 = Vin ;
( R5  R6 )Vin
V2  = 2/3 Vin
R4  R5  R6
( R6 )Vin
V3  = 1/3 Vin
R4  R5  R6

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Procedure :
 Connections are made as shown in the circuit diagram.
 With the chosen values of Rf, Ri, and R3, provide DC voltages V1, V2, and V3 from
VRPS.
 Measure the output voltage and compare it with the designed value.
 Repeat the above procedure providing AC sinusoidal signal of frequency 1KHz for
V1, V2 and V3 and observe the output waveform.

Expected waveforms:
Vo
6v
For AC inputs:
V1
3V
Vi

V2
2V

V3
1V

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b) Op-amp as a integrator:
Circuit Diagram:

Design :
Design a integrator circuit for different values of R and C. Since input is given to Inverting
terminal, the output of integrator is given by
V0 = (1/RC)ƪ Vi.dt
Note: Requirement for integration is RC>>T, where T is the time period of input signal.
Consider input square wave of frequency 1 KHz
 T = 1/f= 1 ms
Since RC >> T, let RC = 10 T = 10ms
For C = 0.1 f, R = (10*10ms)/C = 100K
Choose,R = 100K and C = 0.1 f
Procedure:
 Connections are made as shown in the circuit diagram.
 The input square wave signal (Vi) is set to 4V(p-p) of 1KHz frequency.
 For the chosen values of Rand C, Observe the output Waveform (Vo) on the CRO and
verify it with the expected waveforms.
 Repeat the experiment for different values of R and C (RC = 10T, RC = T, RC=0.1T).
Expected waveforms: vi

vo

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c) Op-amp as a differentiator:

Circuit Diagram:

Design :
Design a differentiator circuit for different values of R and C. Since input is given to
inverting terminal, the output of differentiator is given by
dVi
Vo =  RC
dt
Note: Requirement for integration is RC<< T, where T is the time period of input signal.
Consider input square wave of frequency 1 KHz
1
T= = 1 ms
f
1
Since RC << T, let RC = T = 0.1 T
10
for C = 0.1 f
0.1  10 3
R= = 1K
0.1  10 6
choose, R = 1K and C = 0.1 f

Procedure :
 Connections are made as shown in the circuit diagram.
 The input square wave signal (Vi) is set to 4V(p-p) of 1KHz frequency.
 For the chosen values of Rand C, Observe the output Waveform (Vo) on the CRO and
verify it with the expected waveforms.
 Repeat the experiment for triangular waveform.
 Repeat the experiment for different values of R and C (RC = 10T, RC = T, RC=0.1T) .

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Expected waveforms:

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EXPERIMENT-6

6(a)Voltage comparator and Zero crossing detector

Aim: To verify the operation of an op – amp as voltage comparator and zero crossing
detector.

Procedure:
1. Connect the circuit as shown in the figure

2. Apply the supply voltages of +15V to pin 7 and -15V to pin 4 of IC 741 respectively
from IC Trainer kit. Connect the ground to the ground point.

3. Set the reference voltage as 1V DC.

4. Apply sine wave of 10Vp-p with1KHz frequency from the function generator as Vi.

5. Check the output in CRO and calculate the amplitude of the output wave form.

6. Compare the output wave form amplitude with input signal amplitude.

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Result:

Thus the function of comparator is studied and output waveform has been observed.

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6(b).SCHMITT TRIGGER

Aim : To design a Schmitt trigger circuit for the given specifications and hence to plot its
output
wave form and transfer characteristics.

APPARATUS REQUIRED
1. OPAMP-741
2. RESISTORS
3. BOARD AND
CONNECTING WIRES

Procedure :
1. Connections are made as shown in the circuit diagram.
2. A sinusoidal input whose amplitude is greater than the magnitude of the UTP & LTP is
applied, a square wave output is obtained and observed on the CRO.
3. UTP & LTP points are noted.
4. To obtain transfer characteristics, input is applied to channel A and output to channel B.
5. UTP & LTP are measured on the transfer characteristics.

Note : The amplitude of the input voltage should be greater than the magnitude of
UTP & LTP level.

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WAVEFORMS:

TRANSFER CHARACTERISTICS:

Result :

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EXPERIMENT-7
4 bit R-2R Ladder Network
Aim: (a) Design 4 bit R – 2R Op-Amp Digital to Analog Converter (i) using 4 bit binary
input from toggle switches.
Components required: Op-Amp µA-741, Resistors, Signal Generator, CRO, Fixed Power
supply +12V,0,-12V.

Circuit Diagram:

Design:

Procedure:
1. Connections are made as shown in the circuit diagram.
2. The input B0 B1 B2 B3 are connected to the input toggle switches.
3. Give the binary form (0000 to 1111) and measure the output of OP-AMP using digital
multimeter and verify it with the theoretical value.
4. Plot the Graph of binary input versus the output Voltage of an OP-AMP.

Tabular Column:

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Sl no Binary Inputs Theoretical Practical

B3 B2 B1 B0 Values Values
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Ideal graph for binary input versus output voltage:

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Aim: (b) Design 4 bit R – 2R Op-Amp Digital to Analog Converter using Mod-16
Counter

Components required: Op-Amp µA-741, IC 7493, Resistors, Signal Generator, CRO,

Fixed Power supply +12V,0,-12V

Circuit Diagram:

Procedure:
1. Connections are made as shown in the circuit diagram.
2. The input D0 D1 D2 D3 are connected to the input toggle switches.
3. Measure the output of OP-AMP using digital multimeter and verify it with the theoretical
value.
4. Plot the Graph of binary input versus the output Voltage of an OP-AMP.

Tabular Column:
Sl no Binary Inputs Theoretical Practical
B3 B2 B1 B0 Values Values
1
2
3
4
5
6
7
8
9
10
11

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12
13
14
15
16

Ideal graph for binary input versus output voltage:

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EXPERIMENT -8

Aim: - To Design of Monostable and Astable Multivibrator using 555 Timer

Components required: 555 Timer, Resistor, Capacitor, Power supply +5V, 0, CRO.
a) Astable Multivibrator (free running oscillator ): -
Circuit:

Design: -
Output time period of oscillations = T=T on + Toff
Charging time Ton = 0.693 (RA+RB) C1
Discharge time Toff = 0.693 RB.C1
Ton Ton
Duty cycle D =  =0.75
Ton  Toff T
1
Let T =  1msce,
f
Toff = 0.693 RB.C1
0.25x10-3 =0.693 RB x0.1x10-6
RB = 3.6 K choose as 3.3 K
Ton = 0.693 (RA+RB) C1
0.75x10-3 =0.693 (RA +3.3 K) x0.1x10-6
RA=7.2 K choose as 6.8 K
Here VLT = Lower threshold voltage = Vcc/3 = 1.66V
VUT = Upper threshold voltage = 2Vcc/3 = 3.33V

Procedure: -
1. Connections are made as shown in the circuit diagram

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2. Switch on the DC power supply unit

3. Observe the wave form on CRO at pin 3 and measure the o/p pulse amplitude and
also measure Ton & Toff.
4. Observe the waveforms across C1 (Vc) & measure the max & min voltage levels &
verify VUT & VLT.
5. Compare the capacitor voltage Vc with the output waveform Vo & note that capacitor
charges & Vc rises exponentially when output is high, the capacitor C1 discharges through
RB & the discharge transistor & Vc falls exponentially when output is low.
6. Calculate the duty cycle & the output frequency f & verify with the designed values.

Waveform:

Tabular Column:
Parameters Theoretically Practically
Frequency
Duty cycle
Ton
Toff
VLT = Vcc/3

VUT =2Vcc/3

Result: - Designed values are verified.

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b) Monostable Multivibrator circuits Using 555 Timer.

Components required: Op-Amp μA 741, Capacitor, Function Generator
Fixed Power supply +12V,0,-12V, CRO.

Circuit:

Design:
Let output pulse width = Delay time t d 0.5 msec
Output delay time Td = 1.1 RA.C

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Waveforms: -

Input
Input Trigger pulses

Trigger

Voltage waveform at pin no.2

Output voltage at pin 3

Output

Td t
T

Procedure: -
1. Connections are made as shown in Figure
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2. Switch on the power supply and observe the output waveforms on CRO at pin no 3
and measure the output delay time T d and verify with the designed values and also observe
the waveforms at pin no 2 – trigger input terminal & at pin no 7, also measure the voltage
levels.

Result: -
Output delay time is verified.

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SOFTWARE EXPERIMENTS:

EXPERIMENT 1
NARROWBAND PASS AND NARROW BAND REJECT FILTER:
Aim
The frequency response of a narrow-bandwidth active band-pass filter will be
measured and the results will be compared to theoretical expectations.

Software Used:
MULTISIM 3.0

Theory:
The operational amplifier band-pass filter circuit on the right uses a high-pass and a
low-pass filter section to obtain a band-pass response.
The RC network, R2 and C2, in its negative feedback path provides the low-pass portion of
the band-pass response.
Series connected C1 and R1 provide the high- pass portion.
This circuit has a typical second order resonant response of the form:

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It is important to note that the bandwidth of this filter is the sum of the cutoff frequencies of
the individual sections:β=ω1-ω2 and not β=ω1+ω2
The bandwidth does approach the traditional definition of bandwidth, when the cutoff
frequencies are over a decade apart. Β=ω1-ω2
The actual cutoff frequencies are the frequencies where the magnitude of the filter’s transfer
function is equal to -3 dB of its maximum value. The theoretical values of these frequencies
are most easily found by simulation. Solutions using Maple are also provided in the analysis
section of this experiment.
Frequency and Bandwidth Calculations
Given: w1 = 1/R1C1 and w2 = 1/R2C2. K = R2/R1. Calculations below are for w1 = 10 and
w2 = 100. Input w1 and w2 for your filter. calculate the filter’s cutoff frequencies

Result:

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Narrow Band Reject Filter:

Step 1: select notch frequency that is the frequency to be rejected. Mostly such filters are
used to remove power line frequency that is 50 Hz. So take Fn = 50 Hz

Step 2: assume capacitor value C as 1 micro F (because frequency is too low the capacitor
value should be large)

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Fig. 5: Screenshot of calculations required to find resistance for Notch Filter

Step 5: to construct T network with C – R/2 – C, we need R/2 value. So connect two

resistors in parallel of same value R

Step 6: to construct T network with R – 2C – R, we need 2C value. So connect two
capacitors in parallel of same value C

Result:

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EXPERIMENT 2

PRECISION HALF AND FULL WAVE RECTIFIER:

Precision Half-Wave Rectifier The Superdiode
Aim:
To simulate the half wave rectifier circuit and to check its transfer characteristics.

Software Used:
MULTISIM 3.0

Theory:
There are many applications for precision rectifiers, and most are suitable for use in audio
circuits. A half wave precision rectifier is implemented using an op amp, and includes the
diode in the feedback
loop. This effectively cancels the forward voltage drop of the diode, so very low level signals
(well below the diode's forward voltage) can still be rectified with minimal error.
Components required:
Resistor=1KΩ, diode IN4007, op-amp 741

Circuit diagram:

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Result:

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Precision Full Wave Rectifier

Change amplitude to 0.5 V.The plots of Vin and Vout vs time. Provide plot of Vout
vs Vin. What is the peak value for the output voltage? Now modify your circuit to construct
a Precision Full Wave Rectifier (Fig.4). 4.3.2 Precision Full Wave Rectifier A Precision
Full-Wave Rectifier consists of superdiode DA (see Fig.3) and an inverting amp with unity
gain connected to regular diode DB.

Replace DA with a superdiode and the diode DB and the inverting amplifier with the
inverting precision half-wave rectifier to get the Precision Full Wave Rectifier.
Provide the plots of Vin (Vi) and Vout (Vo) vs time. Provide plot of Vout (Vo) vs Vin (Vi).
What is the peak value for the output voltage? Place CL = 47 μF in parallel with RL. This
will create a Peak Detector. Adjust the values of RL and CL until you achieve reasonable DC
voltage level. L5: Provide peak voltage (VP) before placing the capacitor. Provide ripple
voltage (VR), and dc voltage (VDC) after placing the capacitor
Result:

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EXPERIMENT 3
RC PHASE SHIFT OSCILLATOR
AIM
To setup RC phase shiftoscillator for 1 KHz and
(i) plot the output waveform
(ii) measure the frequency of oscillation
Software Used:
MULTISIM 3.0
PRINCIPLE
An oscillator is an electronic circuit for generating ac signal voltage with a dc supply as the
only input requirement. The frequency of the generated signal is decided by the circuit
elements. An oscillator requires an amplifier a frequency selective network and positive
feedback from the output o
the input. The Barkhausen criteria for sustained oscillator is Aβ = 1, where A is gain of the
amplifier
and β is the feedback factor.
If common emitter amplifier is used with resistive collector load, there is an
180ophaseshift between input and output. The feedback network introduces an additional
180ophaseshift at a particular frequency. The three section RC network offers 180ophaseshift
and the β
of . Hence for unity gain feedback, the gain of the amplifier should be 29. The phaseshift
oscillator
is particularly useful as audio frequency generator. The frequency of oscillation is given by .

From the given component values, the frequency of oscillation

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Model graph:

Result:

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HARTLEY OSCILLATOR
AIM:
To design and set up a Hartley oscillator using BJT and to observe the sinusoidal output
waveform.
APPARATUS REQUIRED:

THEORY:
The Hartley oscillator is an electronic oscillator circuit in which the oscillation frequency is
determined by a tuned circuit consisting of capacitors and inductors, that is, an LC oscillator.
The Hartley oscillator is distinguished by a tank circuit consisting of two series-connected
coils (or, often, a tapped coil) in parallel with a capacitor, with an amplifier between the
relatively high impedance across the entire LC tank and the relatively low voltage/high
current point between the coils. The Hartley oscillator is the dual of the Colpitts oscillator
which uses a voltage divider made of two capacitors rather than two inductors. Although
there is no requirement for there to be mutual coupling between the two coil segments, the
circuit is usually implemented using a tapped coil, with the feedback taken from the tap, as
shown here. The optimal tapping point (or ratio of coil inductances) depends on the
amplifying device used, which may be a bipolar junction transistor.
DESIGN PROCEDURE:
Select a appropriate transistor and note down its specification such as VCE,IC(MAX),
hfe(max) and Vbe(sat).
VCC= VCEQ+ ICQ(RC+RE)
R2=S* RE
VCC[R2/( R1+ R2)= VBE+VBE(SAT)
VR1+VR2=VCC

CIRCUIT DIAGRAM

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MODEL GRAPH

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EXPERIMENT 4
Design of Monostable Multivibrator Circuit using 555
Timer
AIM: To construct and study the operation of a monostable multivibrator using 555 IC timer.
Software Used:
MULTISIM 3.0
:

THEORY:
It has one stable and one quasi stable state. The circuit is useful for generating single output
pulse of time duration in response to a triggering signal. The width of the output pulse
depends only on external components connected to the op-amp. The diode gives a negative
triggering pulse. When the output is +Vsat, a diode clamps the capacitor voltage to 0.7V then,
a negative going triggering impulse magnitude Vi passing through RC and the negative
triggering pulse is applied to the positive terminal. Let us assume that the circuit is instable
state. The output V0i is at +Vsat. The diode D1 conducts and Vc the voltage across the
capacitor ‘C’ gets clamped to 0.7V,the voltage at the positive input terminal through R1R2
potentiometer divider is +ßVsat. Now, if a negative trigger of magnitude Vi is applied to the
positive terminal so that the effective signal is less than 0.7V.the output of the Op-Amp will
switch from +Vsat to –Vsat. The diode will now get reverse biased and the capacitor starts
charging exponentially to –Vsat. When the capacitor charge Vc becomes slightly more
negative than –ßVsat, the output of the op-amp switches back to +Vsat.
DESIGN:
The capacitor ‘C’ now starts charging to +Vsat through R until Vc is 0.7V.

CIRCUIT DIAGRAM:

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Result : The waveform is observed and verified with stated condition.

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Design of Astable Multivibrator Circuit using 555 Timer:

AIM: To construct and study the operation of a monostable multivibrator using 555 IC timer.
APPARATUS:

THEORY:
In the 555 Oscillator above, pin 2 and pin 6 are connected together allowing the circuit to
retrigger itself on each and every cycle allowing it to operate as a free running oscillator.
During each cycle capacitor, C charges up through both timing resistors, R1 and R2 but
discharges itself only through resistor, R2 as the other side of R2 is connected to the
discharge terminal, pin 7. Then the capacitor charges up to 2/3Vcc (the upper comparator
limit) which is determined by the 0.693(R1+R2)C combination and discharges itself down to
1/3Vcc (the lower comparator limit) determined by the 0.693(R2.C) combination. This results
in an output waveform whose voltage level is approximately equal to Vcc - 1.5V and whose
output "ON" and "OFF" time periods are determined by the capacitor and resistors
combinations. The individual times required completing one charge and discharge cycle of
the output is therefore given as:

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Result & Discussion: The waveform was traced and compared with the designed theoretical
one.

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