Analog Devices and Circuits

UNIT - II: MOS FETs and BJTs

Course content:
MOS FET: Device structure and physical operation, current-voltage characteristics, MOS
capacitance-voltage characteristics, MOSFET operation as a switch and as a linear amplifier
BJT: Device structure and physical operation, current-voltage characteristics, BJT operation as
a switch and as an amplifier

Course Objectives
• To know about the physical structure and operation of MOSFETs and BJTs

Course Outcomes
CO2: characterize the current flow in BJTs and MOSFETs and study their applications
as switch and as an amplifier.

Course Content:

2.1 Introduction to MOSFET

Compared to BJTs,

• MOSFETs can be made quite small (i.e., requiring a small area on the silicon IC
chip)
• Their manufacturing process is relatively simple.
• Their operation requires comparatively little power.
• It is possible to pack large numbers of MOSFETs (>200 million) on a single IC
chip, very-large-scale-integrated (VLSI) circuits such as those for memory and
microprocessors.
• Analog circuits such as amplifiers and filters are also implemented in MOS
technology, in smaller less-dense chips.
• Both analog and digital functions are increasingly being implemented on the
same IC chip, in what is known as mixed-signal design.
2.2 MOSFET: Device structure and physical operation
2.2.1 Device Structure
• Figure 2.1, shows the physical structure of the n-channel enhancement-type
MOSFET. The transistor is fabricated on a p-type substrate, which is a single-
crystal silicon wafer that provides physical support for the device.
• Two heavily doped n-type regions, indicated in the figure 2.1 as the n+ source
and the n+ drain regions, are created in the substrate.
• A thin layer of silicon dioxide (Sio2) of thickness tox (typically 2 - 50 nm), which
is an excellent electrical insulator, is grown on the surface of the substrate,
covering the area between the source and drain regions.
• Metal is deposited on top of the oxide layer to form the gate electrode of the
device. Metal contacts are also made to the source region, the drain region, and
the substrate, also known as the body.
• Thus four terminals are brought out: the gate terminal (G), the source terminal
(S), the drain terminal (D), and the substrate or body terminal (B).
• The name Metal Oxide Semiconductor FET is so because metal is not used for
gate electrode. Most of modern MOSFETs are fabricated using silicon-gate
technology, in which a certain type of silicon, called poly-silicon, is used to form
the gate electrode of MOSFET operation and characteristics applies irrespective
of the type of gate electrode.
• Another name for the MOSFET is the insulated-gate FET or IGFET. This name
also arises from the physical structure of the device, emphasizing the fact that
the gate electrode is electrically insulated from the device body (by the oxide
layer). It is this insulation that causes the current in the gate terminal to be
extremely small (of the order of (of the order of 10-15 A).
Fig. 2.1: Physical structure of the enhancement-type NMOS transistor: (a)
perspective view (b) cross-section. Typically L = 0.1 to 3 µm, W= 0.2 to 100 µm,

and the thickness of the oxide layer (toxis in the range of 2 nm to 50 nm).

• Observe that the substrate forms p-n junctions with the source and drain
regions. In normal operation these p-n junctions are kept reverse-biased at all
times.
• Since the drain will be at a positive voltage relative to the source, the two p-n
junctions can be effectively cut off by simply connecting the substrate terminal
to the source terminal.
• Thus, here, the substrate will be considered as having no effect on device
operation, and the MOSFET will be treated as a three-terminal device, with the
terminals being the gate (G), the source (S), and the drain (D).
• It will be shown that a voltage applied to the gate controls current flow between
source and drain. This current will flow in the longitudinal direction from drain
to source in the region labeled "channel region."
• This channel region has a length L and a width W, two important parameters of
the MOSFET. Typically, L is in the range of 0.1 µm to 3 µm, and W is in the
range of 0.2 µm to 100 µm.
• Finally, the MOSFET is a symmetrical device so that its source and drain can
be interchanged with no change in device characteristics.

2.2.2 Operation with No Gate Voltage

• With no bias voltage applied to the gate, two back-to-back diodes exist in series
between drain and source.
• One diode is formed by the p-n junction between the n+ drain region and the p-
type substrate, and the other diode is formed by the p-n junction between the
p-type substrate and the n+ source region.
 • These back-to-back diodes prevent current conduction from drain to source
when a voltage vDS is applied. In fact, the path between drain and source has a
very high resistance (of the order of 1012 Ω).

2.2.3 Creating a Channel for Current Flow

• Assume when the source and Drain are grounded, and applied a positive voltage
to the gate.
• Since the source is grounded, the gate voltage appears in effect between gate
and source and thus is denoted vGS. The positive voltage on the gate causes, the
free holes (which are positively charged) to be repelled from the region of the
substrate under the gate (the channel region). These holes are pushed
downward into the substrate, leaving behind a carrier-depletion region.
• The depletion region is populated by the bound negative charge associated with
the acceptor atoms. These charges are "uncovered" because the neutralizing
holes have been pushed downward into the substrate.

• As well, the positive gate voltage attracts electrons from the n + source and drain
regions (where they are in abundance) into the channel region. When a
sufficient number of electrons accumulate near the surface of the substrate
under the gate, an n region is in effect created, connecting the source and drain
regions, as indicated in Fig. 2.2.

• Now if a voltage is applied between drain and source, current flows through this
induced n region, carried by the mobile electrons. The induced n region thus
forms a channel for current flow from drain to source and is aptly called so.
Correspondingly, the MOSFET of Fig. 2.2 is called an n-channel MOSFET or,
alternatively, an NMOS transistor.

• An n-channel MOSFET is formed in a p-type substrate: The channel is created

by inverting the substrate surface from p type to n type. Hence the induced
channel is also called an inversion layer.
Fig. 2.2: The enhancement-type NMOS transistor with a positive voltage
applied to the gate. An n channel is induced at the top of the substrate beneath
the gate.

• The value of vGS at which a sufficient number of mobile electrons accumulate

in the channel region to form a conducting channel is called the threshold
voltage and is denoted Vt. Vt for an n-channel FET is positive. The value of Vt
is controlled during device fabrication and typically lies in the range of 0.5 V
to 1.0 V.
• The gate and the channel region of the MOSFET form a parallel-plate
capacitor, with the oxide layer acting as the capacitor dielectric.
• The positive gate voltage causes positive charge to accumulate on the top plate
of the capacitor (the gate electrode).
• The corresponding negative charge on the bottom plate is formed by the
electrons in the induced channel. An electric field thus develops in the vertical
direction.
• It is this field that controls the amount of charge in the channel, and thus it
determines the channel conductivity and, in turn, the current that will flow
through the channel when a voltage vDS is applied.

2.2.4 Applying a Small vDS

• Having induced a channel, if we apply a positive voltage vDS between drain and
source, as shown in Fig.2.3. Consider the case where vDS is small (i.e., 50 mV
or so).
• The voltage vDS causes a current iD to flow through the induced n channel.
Current is carried by free electrons traveling from source to drain (hence the
 names source and drain). By convention, the direction of current flow is
opposite to that of the flow of negative charge. Thus the current in the channel,
iD, will be from drain to source, as indicated in Fig. 2.3.
• The magnitude of iD depends on the density of electrons in the channel, which
in turn depends on the magnitude of vGS. Specifically, for vGS = Vt, the channel
is just induced and the current conducted is still negligibly small.
• As vGS exceeds Vt more electrons are attracted into the channel. We may
visualize the increase in charge carriers in the channel as an increase in the
channel depth. The result is a channel of increased conductance or,
equivalently, reduced resistance.
• In fact, the conductance of the channel is proportional to the excess gate
voltage (vGS - Vt), also known as the effective voltage or the overdrive
voltage. It follows that the current iD will be proportional to (vGS - Vt) and, to
the voltage vDS that causes iD to flow.

Fig. 2.3: An NMOS transistor with vGS>Vt, and with a small vDS applied. The
device acts as a resistance whose value is determined by vGS. Specifically, the
channel conductance is proportional to (vGS- Vt) and thus iD is proportional to
(vGS - Vt)vDS.
Fig. 2.4: The iD - vDS characteristics of MOSFET in Fig.4.3 when the voltage
applied between drain and source, vDS is kept small. The device operates as a
linear resistor whose value is controlled by vGS.
• Figure 2.4 shows a sketch of iD versus vDS for various values of vGS. We observe
that the MOSFET is operating as a linear resistance whose value is controlled
by vGS. The resistance is infinite for vGS<Vt, and its value decreases as vGS
exceeds Vt.
• Conclusion: For the MOSFET to conduct, a channel has to be induced. Then,
increasing vGS above the threshold voltage Vt, enhances the channel, hence the
names enhancement-mode operation and enhancement-type MOSFET.
Finally, we note that the current that leaves the source terminal (iS) is equal
to the current that enter the drain terminal (iD), and the gate current iG = 0.

2.1.5 Operation as vDS is increased

• If vDS is increased, vGS is to be held constant at a value greater than Vt. Referring
to Fig. 3.5, and vDS appears as a voltage drop across the length of the channel.
That is, as we travel along the channel from source to drain, the voltage
(measured relative to the source) increases from 0 to vDS.
• Thus the voltage between the gate and points along the channel decreases from
vGS at the source end to (vGS - vDS) at the drain end.
• Since the channel depth depends on this voltage, we find that the channel is no
longer of uniform depth; rather, the channel will take the tapered form shown in
Fig. 2.5, being deepest at the source end and shallowest at the drain end.
 • As vDS is increased, the channel becomes more tapered and its resistance
increases correspondingly.
• Thus the iD-vDS curve does not continue as a straight line but bends as shown in
Fig. 2.6.
• Eventually, when vDS is increased to the value that reduces the voltage between
gate and channel at the drain end to Vt - that is,
vGD = Vt or (vGS–vDS) = Vt or vDS = vGS - Vt
the channel depth at the drain end decreases to almost zero, and the channel is
said to be pinched off.
• Increasing vDS beyond this value has little effect on the channel shape, and the
current through the channel remains constant at the value reached for vDS = (vGS
- Vt).
• The drain current thus saturates at this value, and the MOSFET is said to have
entered the saturation region of operation. The voltage vDS at which saturation
occurs is denoted vDS(sat).
VDS(sat) = (VGS - Vt) (2.1)
• Obviously, for every value of vGS>Vt, there is a corresponding value of vDS(sat).The
device operates in the saturation region if vDS>vDS(sat).
• The region of the iD-vDS characteristic obtained for vDS<vDS(sat) is called the triode
region.

Fig. 2.5: Operation of the enhancement NMOS transistor as vDS is increased.

The induced channel acquires a tapered shape, and its resistance increases as
vDS is increased. Here, vGS is kept constant at a value > Vt.
Fig. 2.6: The drain current iD versus the drain-to-source voltage vDS for an
enhancement-type NMOS transistor operated with vGS>Vt.
• To visualize the effect of vDS, consider Fig. 2.7 in which channel is modified as vDS
is increased while vGS is kept constant.

Fig.2.7: Increasing vDS causes the channel to acquire a tapered shape.

Eventually, as vDS reaches (vGS - Vt), the channel is pinched off at the drain end.
Increasing vDS above (vGS - Vt), has little effect on the channel's shape.

• Theoretically, any increase in vDS above VDS(sat) which is equal to (vGS - Vt),has no
effect on the channel shape and simply appears across the depletion region
surrounding the channel and the n+ drain region.
Drain Current Equation:

(i) Cut-off region: iD = 0

 (ii) Triode region:

(iii) Saturation region:

• The value of the current at the edge of the triode region or, equivalently, at the
beginning of the saturation region can be obtained by substituting vDS = (vGS - Vt)
resulting in

This is the expression for the iD-vDS characteristic in the saturation

region.

• It gives the saturation value of iD corresponding to the given vGS (we know that in
saturation iD remains constant for a given vGS as vDS is varied).
• In the expressions in Eqs. (2.5) and (2.6), µnC0x is a constant determined by the
process technology used to fabricate the n-channel MOSFET. It is known as the
process transconductance parameter.

Kn’ = µnCox

• The product of the process transconductance parameter Kn’ and the transistor
aspect ratio (W/L) is the MOSFET transconductance parameter kn,

• The MOSFET transconductance parameter kn, and has the dimensions of

A/V2:

• The iD-vDS expressions in Eqs. (2.5) and (2.6) can be written in terms of kn' as
follows:

[Triode region]
 [Saturation region]

Where (µnC0X) and kn' can be interchangeable.

• From the drain current equations in triode and saturation we can see that the
drain current is proportional to the ratio of the channel width W to the channel
length L, known as the aspect ratio of the MOSFET. The values of W and L can
be selected by the circuit designer to obtain the desired i-v characteristics.

2.2.5 The p-Channel MOSFET

• A p-channel enhancement-type MOSFET (PMOS transistor), fabricated on an n-
type substrate with p+ regions for the drain and source, has holes as charge
carriers.
• The device operates in the same manner as the n-channel device except that vGS
and vDS are negative and the threshold voltage Vt is negative. Also, the current iD
enters the source terminal and leaves through the drain terminal.
• PMOS technology originally dominated MOS manufacturing. Because NMOS
devices can be made smaller and thus operate faster, and because NMOS
historically required lower supply voltages than PMOS, NMOS technology has
virtually replaced PMOS.
• PMOS transistor is most familiar for two reasons: a) PMOS devices are still
available for discrete-circuit design, and b) both PMOS and NMOS transistors are
utilized in complementary MOS or CMOS circuits, which is currently the
dominant MOS technology.
2.3 Current – Voltage characteristics
These characteristics can be measured at dc or at low frequencies and thus are
called static characteristics.

2.3.1 Circuit Symbol

• Figure 2.10(a) shows the circuit symbol for the n-channel enhancement-type
MOSFET. The spacing between the two vertical lines that represent the gate and
the channel indicates the fact that the gate electrode is insulated from the body
of the device. The polarity of the p - type substrate (body) and the n channel is
indicated by the arrowhead on the line representing the body (B). This arrowhead
also indicates the polarity of the transistor, namely, that it is an n-channel device.
 • In Fig. 2.10(b), an arrowhead is placed on the source terminal, thus
distinguishing it from the drain terminal. The arrowhead points in the normal
direction of current flow and thus indicates the polarity of the device (i.e., n
channel). Observe that in the modified symbol, there is no need to show the
arrowhead on the body line.
• The circuit symbol of Fig. 2.10(b) clearly distinguishes the source from the drain,
in practice it is the polarity of the voltage impressed across the device that
determines source and drain; the drain is always positive relative to the source in
an n-channel FET.
• In applications where the source is connected to the body of the device, a further
simplification of the circuit symbol is possible, as indicated in Fig. 2.10(c).

Fig.2.10: (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b)
Modified circuit symbol with an arrowhead on the source terminal to
distinguish it from the drain and to indicate device polarity (i.e., n channel), (c)
Simplified circuit symbol to be used when the source is connected to the body
or when the effect of the body on device operation is unimportant.

2.3.2 The iD -vDS characteristics

Figure 2.11(a) shows an n-channel enhancement-type MOSFET with voltages vGS and
vDS applied and with the normal directions of current flow indicated. This circuit can
be used to measure the iD- vDS characteristics, which are a family of curves, each
measured at a constant vGS. We expect each of the iD- vDS curves to have the shape
shown in Fig. 2.6. From Fig. 2.11(b), which shows a typical set of iD- vDS
characteristics.
Figure 2.11 (a) An n-channel enhancement type MOSFET with VGS and VDS applied
and with the normal directions of current flow indicated (b) The i D – vDS
characteristics for a device with Kn’ (W/L) = 1.0 mA / V2

The characteristic curves in Fig. 2.11(b) indicate that there are three distinct regions
of operation:
a) the cutoff region – FET can be used as an OFF switch
b) the triode region - FET can be used as an ON switch
c) the saturation region - FET can be used as an amplifier

• The device is cut off when vGS<Vt. To operate the MOSFET in the triode region we
must first induce a channel,
vGS >Vt (Induced channel) (2.8)
and then keep vDS small enough so that the channel remains continuous. This is
achieved by ensuring that the gate-to-drain voltage is
VGD>Vt (Continuous channel) (2.9)
This condition can be stated explicitly in terms of vDS by writing
vGD= vGS + vSD = v GS - vDS
thus, (vGS - vDS) >Vt
which can be rearranged to obtain
vDS < (vGS - Vt) (continuous channel) (2.10)
• Either Eq. (2.9) or Eq. (2.10) can be used to obtain triode-region operation. In
words, then-channel enhancement-type MOSFET operates in the triode region when
vGS is greater than Vt and the drain voltage is lower than the gate voltage by at least
Vt volts.
• In the triode region, the iD- vDS characteristics can be described by the relationship
of Eq. (2.5), which we repeat here,

--- (2.11)
Where, µnC0X=kn' is called the process transconductance parameter; its value is
determined by the fabrication technology.
• If vDS is sufficiently small so that we can neglect the vDS2 term in Eq. (3.11), we obtain
for the iD- vDS characteristics near the origin the relationship

--- (2.12)
This linear relationship represents the operation of the MOS transistor as a
linear resistance, rDS whose value is controlled by vGS. Specifically, for vGS set to a
value VGS, rDS is given by

--- (2.13)
The rDS can be expressed in terms of the gate-to-source overdrive voltage,
VOV = VGS - Vt --- (2.14)

--- (2.15)
Eq. (2.12)is based on the assumption that vDS< 2V0V.
To operate the MOSFET in the saturation region, a channel must be induced,

---- (2.16)
and pinched off at the drain end by raising vDS to a value that results in the gate-to-
drain voltage falling below Vt,

--- (2.17)
This condition can be expressed explicitly in terms of vDS as

--- (2.18)
In words, the n-channel enhancement-type MOSFET operates in the saturation region
when vGS is greater than Vt , and the drain voltage does not fall below the gate voltage
by more than Vt volts.
• The boundary between the triode region and the saturation region is characterized
by

---- (2.19)

Substituting this value of vDS into Eq. (2.11) gives the saturation value of the
current iD as

---- (2.20)
• Thus in saturation the MOSFET provides a drain current whose value is
independent of the drain voltage vDS and is determined by the gate voltage vGS
according to the square-law relationship in Eq. (2.20), a sketch of which is shown
in Fig. 2.12.
• Since the drain current is independent of the drain voltage, the saturated MOSFET
behaves as an ideal current source whose value is controlled by vGS according to
the nonlinear relationship in Eq. (2.20).
• Figure 2.13 shows a circuit representation of this view of MOSFET operation in the
saturation region. This is a large-signal equivalent-circuit model.

Fig. 2.11: The iD- vDS characteristic for an enhancement type NMOS transistor
in saturation.
Fig. 2.12: Large-signal equivalent-circuit model of an n-channel MOSFET
operating in the saturation region.

2.3.3 Finite Output Resistance in Saturation

• Equation (2.12) and the corresponding large-signal equivalent circuit in Fig.
2.13 indicate that in saturation, iD is independent of vDS.
• Thus a change ΔvDS in the drain-to-source voltage causes a zero change in iD,
which implies that the incremental resistance looking into the drain o f a
saturated MOSFET is infinite.
• Once the channel is pinched off at the drain end, further increases in vDS have no
effect on the channel's shape.
• But in practice as vDS is increased, the channel pinch-off point is moved slightly
away from the drain, toward the source. This is illustrated in Fig. 3.15, from
which we can observe that the voltage across the channel remains constant at
vGS -Vt = vDS (sat) and the additional voltage applied to the drain appears as a
voltage drop across the narrow depletion region between the end of the channel
and the drain region.
• This voltage accelerates the electrons that reach the drain end of the channel and
sweeps them across the depletion region into the drain. That (with depletion—
layer widening) the channel length is in effect reduced, from L to L – ΔL, a
phenomenon known as channel-length modulation.
• Since iD is inversely proportional to the channel length (Eq. 3.20), iD increases with
vDS.
Fig.2.14:Increasing vDS beyond vDS (sat) causes the channel pinch-off point to
move slightly away from the drain, thus reducing the effective channel length
(by ΔL).

• To account for the dependence of iD on vDS in saturation, we replace L in Eq. (2.20)

with L - ΔL to obtain

Assuming that (ΔL/L) << 1 and ΔL is proportional to vDS, ΔL = λ'vDS

where, λ' is a process-technology parameter with the dimensions of µm/V, we
get

It follows that λ is a process-technology parameter with the dimensions of V -1

and that, for a given process; λ is inversely proportional to the length selected
for the channel. In terms of λ, the expression for iD becomes

--- (3.22)
• A typical set of iD-vDS characteristics showing the effect of channel-length
modulation is displayed in Fig. 2.16.
 • The observed linear dependence of iD on vDS in the saturation region is
represented in Eq. (2.22) by the factor (1 + λ vDS).
• From Fig. 2.16 we observe that when the straight-line iD-vDS characteristics
are extrapolated they intercept the vDS -axis at the point vDS = -VA, where VA is
a positive voltage.
• Equation (2.22), however, indicates that iD = 0 at vDS = - 1 / λ. It follows that
VA= 1/ λ

Where, VA' is a process-technology parameter with the dimensions of V/µm.

Fig. 2.15: Effect of vDS on iD in the saturation region. The MOSFET parameter
VA depends on the process technology and, for a given process, is proportional
to the channel length L.

• Equation (2.22) indicates that when channel-length modulation is taken into

account, the saturation values of iD depend on vDS.
• Thus, for a given vGS, a change ΔvDS yields a corresponding change ΔiD in the
drain current iD.
• It follows that the output resistance of the current source representing iD in
saturation is no longer infinite. Defining the output resistance rO as

--- (2.23)
And using Eq. (2.22) results in
 ----- (2.24)
which can be written as

--- (2.25)

or equivalently
where ID is the drain current with-out channel-length modulation taken into
account. Thus the output resistance is inversely proportional to the drain
current.
• Fig. 2.16 shows the large-signal equivalent circuit model incorporating rO.

Fig. 2.16: Large-signal equivalent circuit model of the n-channel MOSFET

in saturation, incorporating the output resistance r0. The output
resistance models the linear dependence of iD on vDS and is given by
Eq.(2.22)

2.5 MOSFET as an amplifier and as a switch

• The MOSFET is used in the design of amplifier circuits. When it is operated in
the saturation region, acts as a voltage-controlled current source: Changes in
the gate-to-source voltage, vGS gives rise to changes in the drain current iD.
Thus the saturated MOSFET can be used as a transconductance amplifier.
• Since for linear amplification (in amplifiers whose output signal is linearly
related to their input signal) it is necessary to obtain linear amplification from
a fundamentally nonlinear device is dc biasing the MOSFET to operate at a
certain appropriate VGS and a corresponding I D and then superimposing the
 voltage signal to be amplified, vgs on the dc bias voltage VGS. By keeping vgs a
small value, the resulting change in drain current id can be made proportional
to vgs.
• Large signal operation: From the voltage transfer characteristics it is
observed the region over which the transistor can be biased to operate as a
small-signal amplifier as well as the region where it can be operated as a
switch. MOS switches find application in both analog and digital circuits.
2.5.1 Large-signal operation - The transfer characteristics
• The basic structure of the most commonly used MOSFET amplifier, the
common-source (CS) circuit or grounded-source circuit is shown in fig. 2.24
(a).
Fig. 2.24: (a) Basic structure of common-source amplifier, (b) Graphical
construction to determine the transfer characteristics of CS amplifier, (c)
Transfer characteristics showing operation as an amplifier biased at point Q

• The circuit is viewd as a two-port network, since the grounded source terminal
is common to both the input port, between gate and source, and the output
port between drain and source. The basic control action of MOSFET is that
changes in vGSgive rise to changes in iD, we are using a resistor RD to obtain
an output voltage v0,
v0 = vDS =VDD - RDiD --- (2.35)
• In this way transconductance amplifier is converted into voltage amplifier.
• Voltage transfer characteristics: These are the plots between the output
voltage for various values of input voltage. The transfer characteristics are
obtained in two ways: graphically and analytically.

2.5.2 Operation as a switch

• When the MOSFET is used as a switch, it is operated at the extreme points of
the transfer curve.
• The device is turned off by keeping vI<Vtresulting in operation some where on
the segment XA with v0 –VDD.
 • The switch is turned on by applying a voltage close to V DD, resulting in
operation close to point C with v0very small (at C, v0=V0C)
• The common source MOS circuit can be used as a logic inverter with the “low”
voltage level close to 0V and the “hign” level close to V DD.
2.5.3 Operation as a Linear Amplifier
• To operate the MOSFET as an amplifier it should be in the saturation mode
segment of the transfer curve.
• The device is biased at a point close to the middle of the curve; point Q is a
good example of an appropriate bias point. It is also called as quiescent point.
• The voltage signal to be amplified vi is then superimposed on the dc voltage
VIQ as shown in Fig.2.24(c)
• The value of vi is sufficiently small to operate in linear segment of the transfer
curve, the resulting output voltage signal v0will be proportional to vi i.e., the
amplifier will be very nearly linear, and v0 will have the same waveform as vi
except it will be larger by a factor equal to voltage gain (A v) of the amplifier at
Q. Where,

• Thus the voltage gain is equal to the slope of the transfer curve at the bias
point Q. It is observed that the slope is negative, and thus the CS amplifier is
inverting. This is also shown in Fig. 3.24(c)

2.6 Device structure and physical operation of BJT

2.6.1 Simplified structure and modes of operation
➢ The BJT consists of three semiconductor regions emitter region, base region,
collector region.
➢ There are two types of transistors
• PNP (collector-p type, emitter- p type, base –n type)
• NPN (collector-n type, emitter- n type, base- p type)
 Fig. 2.25: A simplified structure of (a) the npn transistor; (b) the pnp
transistor

➢ The transistor can be operated in three regions depending on the bias condition
➢ The active mode is forward active mode which is used as an amplifier.
➢ The cut off and saturation mode are called reverse active (or inverse active)
used for switching purpose.
Table 2.1: BJT modes of operation

2.6.2 Operation of the npn transistor in active mode

 Fig. 2.26: Current flow in an npn transistor biased to operate in the active
mode

➢ In active mode operation the emitter to base junction is made forward biased and
collector to base junction is reverse biased.
➢ The current is mainly due to diffusion current components and the drift of
minority charge carrier currents are neglected. The current that flows across the
emitter – base junction will constitute the emitter current iE. The direction of iE
is out of the emitter lead, which is in the direction of hole current and opposite
to the direction of the electron current .the emitter current is mostly dominated
by the hole current since electrons are large in number.
➢ Let us consider the electrons injected from the emitter to base since the base is
very thin, the electron concentration will be highest at the emitter side and lowest
at collector side as in the case of any forward biased pn junction the
concentration np(0) will be proportional to

…. (2.46)

Where, np0 is thermal equilibrium of minority electron concentration in base

region
vBE is base to emitter voltage
VT is thermal voltage (=25mv)

…. (2.47)
Where, AE = cross-sectional area
Q = charge carriers
 Dn = electron diffusion constant

Fig. 2.27: Profiles of minority-carrier concentrations in the base and in the

emitter of an npn transistor operating in the active mode: vBE > 0 and vCB = 0.

➢ Some of the electrons diffusing from the base region will combine with holes,
which are majority carriers in base. As base is very thin the loss of electrons by
this diffusion is very small hence the minority charge carrier current can be very
small.
The collector current
➢ The diffusion electrons reach the collector base region. As the collector is more
positive than base the electrons get accumulates across the collector region, then
the collector current will be given as

…. (4.3)

…. (4.4)

➢ Here the collector current ic does not depends on the collector to base voltage
vCB.
➢ From the above equation the scaling current is inversely proportional to width of
the depletion region and directly proportional to the area of EB junction.
➢ Typically is in the range of 10-12 to 10-18 .the scaling current doubles for every 5
degree rise in temperature as it is a function of ni which is proportional to
temperature. The scaling current also varies with respect to area, where for same
vBE voltage the collector current varies for larger device to smaller device.

The Base Current

➢ The base current is composed of two components .the first current component is
due to holes injected from base to emitter region. It is given by

…. (4.5)

Where Dp is diffusion constant

Lp is diffusion length
ND is doping concentration
➢ The second component is due to the holes supplied by external circuit to replace
the holes lost by recombination process. It is given by the total charge to average
life time that a hole combine with electron denoted by τ b.

Where,

iB2 = Qn/τb (4.6)

The minority carrier charge stored In the base region, Qn can be found by referring
Fig. 2.27. Qn is represented by the area of the triangle under the straight-line
distribution in the base, thus

Substituting for np(0) from Eq.(4.1) and replacing np(0) by ni2 / NA gives

which can be substituted in Eq.(4.6) to obtain

Combining Eqs. (4.5) and (4.8) and utilizing Eq.(4.4), we obtain for the total base
current iB

Comparing Eqs. (4.3) and (4.9), we see that iB can be expressed as a fraction of iC as
follows: iB = iC / β (4.10)

where β is given by

➢ Where the beta is transistor constant varies from 50 to 200. For special case
diodes it will be 1000 and is called as common emitter current gain.

The emitter current

➢ The emitter current is given by the sum of base and collector current

Use of Eqs. (4.10) and (4.13) gives

Alternatively, we can express Eq. (4.14) in the form

where the constant α is related to β by

Thus the emitter current in Eq. (4.15) can be written

Finally, we can use Eq. (4.17) to express β in terms of α; that is,

Where, alpha is called common base current gain since it is very small. Typically
alpha is always less than 1.

Fig. 2.28: Large signal equivalent circuit models of npn operating in forward
active mode

2.5.3 Structure of actual transistors

Fig. 2.29: Cross-section of an npn BJT

2.6.4 Operation in the saturation mode

Fig. 2.32: Concentration profile of the minority carriers (electrons) in the base
of an npn transistor operating in the saturation mode.

➢ When vCB is lower than 0.4 V the transistor enters into saturation mode. Then
current equation from Ebers Moll model can be given by

➢ The first term is a resultant current of Emitter base junction and the second term
is the resultant of forward bias of collector base junction. The second term plays
important role when vBC exceeds 0.4V.

2.6.5 The pnp transistor

➢ The pnp transistor usually works in active mode of operation. The voltage vEB
causes p-type more potential than n-type which makes it forward bias (base-
emitter junction). The collector-base junction is reverse biased by the voltage vBC.
➢ Unlike in pnp transistor the current is mainly due to holes in pnp transistor.

Fig. 2.34: Current flow in a pnp transistor biased to operate in the active
mode.
2.7 Current–Voltage Characteristics
2.7.1 Circuit symbols and conventions
➢ The polarity of the device (pnp or npn) is indicated by the direction of the
arrowhead on the emitter.
➢ The current flows from top to bottom and voltages are high at top and lower at
bottom.
➢ An npn transistor whose EBJ is forward biased will operate in the active mode
as long as the collector voltage does not fall below that of the base by more than
approximately 0.4V.
➢ The current denoted ICBO is the reverse current flowing from collector to base with
the emitter open-circuited.

Fig. 2.35: Voltage polarities and current flow in transistors biased in the active
mode

2.7.2 Graphical representation of Transistor characteristics

➢ The exponential relationship between the ic and vBE is as follows

➢ The ic- VBE characteristics of a npn transistor are as follows:

Fig. 2.36: Effect of temperature on the iC–vBE characteristic. At a constant
emitter current (broken line), vBE changes by –2 mV/°C.

Fig. 2.37: The iC–vCB characteristics of an npn transistor

➢ For a pnp transistor, the characteristics will be identical with vBE replaced with
vEB.
➢ The common base characteristics are the plots between iC and vCB for various
values of iE is as follows
➢ Each of the characteristic curves intersect the vertical axis at the current level
equal to αIE

2.7.3 Dependence of iC on the collector voltage: The Early effect

➢ At low values of vCE as the collector voltage goes below that of the base by more
than 0.4V the collector base junction becomes forward biased and transistor
leaves active mode and enters saturation mode.
➢ The characteristic lines meet at a point on the negative vCE axis, at vCE=-VA. The
voltage VA is called Early voltage.
➢ At a given value of vBE, increasing vEC increases the reverse-bias voltage on the
collector-base junction and thus increases the width of the depletion region.
➢ This in turn results in a decrease in the effective base width W. This is the Early
effect.
 Fig. 2.38: (a) Conceptual circuit for measuring the iC–vCE characteristics of
the BJT. (b) The iC–vCE characteristics of a practical BJT.

➢ The linear dependence of ic on vCE can be accounted for by assuming that I s

remains constant and including the factor (1+Vce/VA) in the equation for iC as
follows

The nonzero slope of the ic-VcE straight lines indicates that the output
resistance looking into the collector is not infinite. Rather, it is finite and
defined by

--- (2.36)

Using Eq. (4.36) we can show that

--- (2.37)

where Ic and VCE are the coordinates of the point at which the BJT is operating
on the particular ic-vCE curve (i.e., the curve obtained for vBE = VBE). Alternatively, we
can write

--- (2.38a)
where I'C is the value of the collector current with the Early effect neglected; that is,

--- (2.38b)

Fig. 2.39: Large-signal equivalent-circuit models of an npn BJT operating in the

active mode in the common-emitter configuration.

2.8 The BJT as an amplifier and as a switch

➢ The two major applications of BJT are signal amplifier, and as a digital-circuit
switch. The basis for the amplifier application is the fact that when the BJT is
operated in the active mode, it acts as a voltage-controlled current source.
a) Changes in the base-emitter voltage vBE gives rise to changes in the collector
current ic. Thus in the active mode the BJT can be used to implement a trans-
conductance amplifier. Voltage amplification can be obtained simply by passing
the collector current through a resistance Rc.
b) Since the collector current ic is exponentially related to v BE, we will bias the
transistor to operate at a dc base-emitter voltage VBE and a corresponding dc
collector current IC.
c) Then superimpose the signal to be amplified, vbe, on the dc voltage V BE. By
keeping the amplitude of the signal vbe small, we will be able to constrain the
transistor to operate on a short, almost linear segment of the ic-vBE characteristic.
Thus, the change in collector current, ic, will be linearly related to vbe.
d) From the transfer characteristic of the circuit, we will be able to see clearly the
region over which the circuit can be operated as a linear amplifier. We also will
be able to see how the BJT can be employed as a switch.
Fig. 2.43: (a) Basic common-emitter amplifier circuit (b) Transfer characteristic
of the circuit in (a). The amplifier is biased at a point Q, and a small voltage
signal vI is superimposed on the dc bias voltage VBE. The resulting output signal
v0appears superimposed on the dc collector voltage VCE. The amplitude of v0is
larger than that of vI by the voltage gain Av.

2.7.1 Amplifier Gain

➢ To operate the BJT as a linear amplifier, it must be biased at a point in the active
region. Figure 2.43 (b) shows such a bias point, labeled Q (for quiescent point),
and characterized by a dc base-emitter voltage VBE and a dc collector-emitter
voltage VCE. If the collector current at this value of VBE is denoted IC , that is,

then from the circuit in Fig. 2.43(a) we can write

VCE = VCC - RC IC (4.46)
➢ If the signal to be amplified, vI is superimposed on VBE and kept sufficiently small,
as indicated in Fig. 2.44b), the instantaneous operating point will be constrained
to a relatively short, almost-linear segment of the transfer curve around the bias
point Q.
➢ The slope of this linear segment will be equal to the slope of the tangent to the
transfer curve at Q. This slope is the voltage gain of the amplifier for small-input
signals around Q.
➢ An expression for the small-signal gain AV can be found by differentiating the
expression in Eq. (5.2) and evaluating the derivative at point Q; that is, for vI =
VBE,
 using Eq. (4.45), we can express AV in compact form:

Where, VRC is the dc voltage drop across RC,

VRC = VCC - VCE (4.49)
➢ Observe that the CE amplifier is inverting; that is, the output signal is 180° out
of phase relative to the input signal. The simple expression in Eq. (4.48) indicates
that the voltage gain of the common-emitter amplifier is the ratio of the dc voltage
drop across RC to the thermal voltage VT (= 25 mV at room temperature).
➢ It follows that to maximize the voltage gain we should use as large a voltage drop
across RC as possible.
➢ For a given value of VCC, Eq. (4.49) indicates that to increase VRC we have to
operate at a lower VCE. However, reference to Fig. 4.18 (b) shows that a lower VCE
means a bias point Q close to the end of the active region segment, which might
not leave sufficient room for the negative-output signal swing without the
amplifier entering the saturation region.
➢ If this happens, the negative peaks of the waveform of v0 will be flattened.
➢ It is the need to allow sufficient room for output signal swing that determines the
most effective placement of the bias point Q on the active-region segment, YZ, of
the transfer curve.
➢ Placing Q too high on this segment not only results in reduced gain (because V RC
is lower) but could possibly limit the available range of positive signal swing. At
the positive end, the limitation is imposed by the BJT cutting off, in which event
the positive-output peaks would be clipped off at a level equal to VCC.
➢ Finally, it is useful to note that the theoretical maximum gain AV is obtained by
biasing the BJT at the edge of saturation, which of course would not leave any
room for negative signal swing. The resulting gain is given by
➢ Although the gain can be increased by using a larger supply voltage, other
considerations come into play when determining an appropriate value for VCC. In
fact, the trend has been toward using lower and lower supply voltages, currently
approaching 1 V or so. At such low supply voltages, large gain values can be
obtained by replacing the resistance RC with a constant-current source.

2.7.2 Operation as a Switch

➢ To operate the BJT as a switch, we utilize the cut-off and the saturation modes
of operation. To illustrate, consider once more the common-emitter circuit shown
in Fig. 2.44 as the input vI is varied.
➢ For vI less than about 0.5 V, the transistor will be cut off; thus iB = 0, iC= 0, and
vC = VCC. In this state, node C is disconnected from ground; the switch is in the
open (OFF) position.
➢ To turn the transistor ON, we have to increase vI above 0.5 V. In fact, for
appreciable
currents to flow, vBE should be about 0.7 V and vI should be higher. The base
current will be

and the collector current will be iC = β iB (4.53)

which applies only when the device is in the active mode. This will be the case
as long as the CBJ is not forward biased, that is, as long as vC>vB - 0.4 V, where
vC is given by
vC =VCC - iC RC (4.54)
 Fig. 2.44: A simple circuit used to illustrate the different modes of
operation of the BJT.
➢ As vI is increased, iB will increase (Eq. 4.52), iC will correspondingly increase (Eq.
4.53), and vC will decrease (Eq.4.54). Eventually, vC will become lower than vB by
0.4 V, at which point the transistor leaves the active region and enters the
saturation region. This edge-of-saturation (EOS) point is defined by

Where, assume that VBE is approximately 0.7 V, and

The corresponding value of vI required to drive the transistor to the edge-of-

saturation can be found from

(2.57)
➢ Increasing vI above vI(EOS) increases the base current, which drives the transistor
deeper into saturation.
➢ The collector-to-emitter voltage, however, decreases only slightly. As a reasonable
approximation, we shall assume that for a saturated transistor, VCE (sat) is
approximately equal to 0.2 V. The collector current then remains nearly constant
at IC (sat),

(2.58)
➢ Forcing more current into the base has very little effect on IC (sat) and VCE (sat).
In this state the switch is closed (ON), with a low closure resistance RCE (sat) and
a small offset voltage VCE off.
➢ Finally, in saturation one can force the transistor to operate at any desired β
below the normal value; that is, the ratio of the collector current IC (sat) to the
base current can be set at will and is therefore called the forced β,

(2.59)

The ratio of IB to IB (EOS) is known as the overdrive factor.