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63 views73 pagesDocument 83
Uploaded by
Prerna ChoudharyCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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UPTUNOTES.COM
enabling learning.
Unit-1
© Introduction to Microprocessor
© Microprocessor architecture and its operations
© Memory, Input & output devices
© Logic devices for interfacing
8085 MPU, Example of an 8085 based
ee ‘Ans : Accumulator register, Temporary register, Instruction register, Stack Pointer, Program
Counter are the various registers in 8085.
Q2. What are the various flags used in 80857
Ans:Sign flag, Zero flag, Auxillary flag, Parity flag, Carry flag.
Q3. What is Stack Pointer?
Ans : Stack pointer is a special purpose 16-bit register in the Microprocessor, which holds the
address of the top of the stack.
Q4. What is Program Counter?
un counter holds the address of either the first byte of the next ins!
ion or the address of the next byte of a multi byte i
i, address, & control signals.
QS. What is Tri-state Logic?
‘Ans :Three Logie Levels are uscd and they are High, Low, High impedance state. The high
and low are normal logic levels & high impedance state is electrical open circuit conditions.
Tri-state logic has a third line called enable line.
Q9. Give an example of One Address Microprocessor.
Ans :8085 is a oue address microprocessor. Ans :TRAP, RST7.5, RST6.5, RSTS.5, INTR.
(Q12. What are Software Interrupts?
Ans :RSTO, RST1, RST2, RST3, RST4, RSTS, RST6, RST7.
Q13. Which Interrupt has the highest priority?
Ans :TRAP has the highest priority.
Q14. Name $ different addressing modes.
Q15. How many interrupts are there in 80857
Q19. Why crystal is a preferred
Ans :Because of high stability, large Q (Quality Factor) & the frequency that doesn’t drift
with aging. Crystal is used as a clock source most of the times.
Q20. What does Quality Factor Mean?
Ans : The Quality factor is also defined, as Q. So it is a number, which reflects the lossness of
a circuit. Higher the Q, the lower are the losses. Ans :The signals of the 8085 microprocessor based on their functions can be classified
into 7 categories namely:
Frequency and power signals
Address and data buses
‘The control bus
Interrupt Signals
Serial Input / Output signals
Q23. Mention the various functional blocks of the 8085 Microprocessor,
Ans :The various functional blocks of the 8085 microprocessor are: a ya UPTUNOTES.COM
enabling learning.
Input Unit: + Accept i data and instructions from the outside world, + Convert it to a form
‘that the computer a can understand. + Supply the converted data to the computer system for
further processing.
TeoutTnit_ L—{_Storaee_ }—+[ Outwur uait |
r
Control Unit
ALU
: The storage tnit of the computer holds data and instructions
operations viz, >, <,=,
Control Unit: It controls all ‘control unit instructs the input
unit, where to store the data after It controls the flow of data and
instructions from the storage unit to ALU.
Central Processing Unit: The control uit and ALU of the computer are together nown as
the Central Processing Unit (CPU). The CPU is like brain performs the following functions:
1. Control Unit
2. Arithmetic logic Unit
3. Registers
4. Bus Data Bus: Data bus lines are bi-directional, because CPU can read data on these lines from
memory or from a port, as well as send data out on these lines to a memory location or to a
port,
Address Bus: The address bus carries addresses and is one way bus from microprocessor to
the memory or other devices. Address bus width determines the maximum possible memory
capacity of
have various lines which have specific Funct inating
operations.
technology.
It has the following configuration
8-bit data bus
16-bit address bus, which can address upto 64KB
A 16-bit program counter
A 16-bit stack pointer
Six 8-bit registers arranged in pairs: BC, DE, HL
Requires +5V supply to operate at 3,2 MEIZ single phase clock
It is used in washing machines, microwave oveus, mobile phones, etc. - 'UPTUNOTES.COM
ister used to perform arithmetic, logical, VO &
need SOMA fear ning..
Arithmetic and logic wnit:As the name suggests, it perfonus arithmeli¢’ aud logical
operations like Addition, Subtraction, AND, OR, ete. on 8-bil data.
Stack polnter: It is also a 16-bit tepist like stack, which is always
incremented/decremented by 2 during push & pop operations.
‘Temporary register:It is an 8-bit register, which holds the temporary data of arithmetic and
logical operations.
Flag register:It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1
depending upon the result stored in the accumulator.
These are the set of 5 flip-flops -Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), Carry
© UPTUNOTES.COM
LP bndBting learning.
Instruction register and decoder:It is an 8-bit register. When an instruction is fetched from
memory then it is stored in the Instruction register. Instruction decoder decodes the
information present in the Instruction register.
Timing and control units]t provides. timing and control signal (o the microprocessor to
perform operations, Following are the timing and control signals, which control external and
intemal circuits ~
« Control Signals: READY, RD’, WR’, ALE.
«Status Signals: SO, Si, 1O/M’
« DMA Signals: HOLD, HLDA
«RESET Signals: RESET IN, RESET OUT
Interrupt control:As the name suggests it controls the interrupts during a process. When a
microprocessor is executing a main program and whenever an interrupt occurs, the
shifts the control from the main program to process the incomti
st is completed, the control goes back to the main progr:
8085 microprocessor: INTR, RST 7.5, RST 65, RST
wrols the scrial data
nd SOD (Serial ourp
i
bef
5
i
Address bus:A15-A8, it caries the most significant 8-bits of
memoryflO address.
Data bus:AD7-ADO, it carries the least significant 8-bit
address and data bus.
Control and status signals
‘These signals are used to identify the nature of operation.
‘There are 3 control signal and 3 status signals.
TSP EEEESS OEE ET
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fig td Moe Guritten into a
«ALE — Il is a positive going pulse generated when a new operation is started by the
microprocessor, When the pulse goes high, it indicates address. When the pulse goes
down il indicates data,
Three status signals are JO/M, SO & S1.
TO/M: This signal is used to differentiate between 10 and Memory operations, i.e. when it is
high indicates 10 operation and when it is low then it indicates memory operation.
S1 & SO: These signals are used to identify the type of current operation.
Power supply:There are 2 power supply signals ~ VCC & VSS. VCC indicates +5v power
supply and VSS indicates ground signal.
READY ~ This signal indicates tha ice is ready to send or receive data, If
READY is low, then the CPU has to wait for READY to go high.
HOLD — This signal indicates that another master is requesting the use of the address
and data buses.
HLDA (HOLD Acknowledge) — It indicates that the CPU has received the HOLD
request and it will relinguisl the bus in the next clock cycle. IILDA is set to low after
the HOLD signal is removed. whenever a RIM instruction is executed.
Q28. Explain Flags in 8085 microprocessor.
Ans: The Flag register is a Special Purpose Register. Depending upon the value of resull after any
arithmetic and logical operation the flag bits become set (1) or reset (0). In 8085 microprocessor, fag
‘Tegister consists of 8 bits and only 5 of them are tseful.
The 5 flags are:
a Ber iatae aes ees
number is negative and the sign flag becomes set, i.c. 1. If the MSB is ©, it indicates the
number is positive and the sign flag becomes reset ic. 0.
1 -carry out from bit 3 on addition or
O-otherwise
Parity Flag (P) ~ If after any arithmetic or logical operation the result has even parity, an
even number of 1 bits, the parity register becomes set ie. 1, otherwise it becomes reset ie. 0.
| accumulator has even number of 1 bits
O-accumulator bas odd parity UPTUNOTES.COM:
Q29. Explain the basic operation of
Instruction.
pesmi aia 006 010) °81 (1001
Se
© The 8085 sends the contents of PC as am address on the address bus and activates RD
‘control signal nt
© Upon receiving the address and RD signal memory puts the contents of addressed
memory location on the data bus which is an opcode of an instruction. Meanwhile, PC
is incremented to point the next memory location in the program sequence,
* RD signal is deactivated and opcode is loaded onto the register via internal bus of
microprocessor.
© The instruction decoding unit decodes the instruction and provides instruction to the
timing and control unit to generate necessary signals for instruction execution.
Q30: Explain the Demultiplexing of AD2- ADo.
‘The demultiplexing of lower half of an address is done by using external latch and ALE
signal ftom 8085 gure shows the hardware connection for latching the lower haf of an
circuit half address bus and input of the latch Unit-2 QI. Write a prog il
at locations 2000H And 200111
ne QRS LAL eu
Ans :By making use of the Push & Pop instructions the program can be written as:
+ LXISP, 4000H - this step initiates the SP at 4000h.
+ PUSH PSW - the contents of the accunmalator and flag are pushed into the stack.
POPB
MOV A,B
‘STA 2000H
MOV A.C
* STA 2001H
* HLT
Q2. Classify Interrupts on the basts of Signals. State thelr differences.
Ans :On the basis of level the signals can be classified into the following
the case of other hardware interrupts the locations is saved im the stack.
Q4. Explain briefly the TRAP Input for the 8085,
‘Ans :The TRAP input is sensitive to both edge and level. _ a UPTUNOTES.COM
QS. Explain briefly what happens when the INTR Signal goes high in the 8085.
Ans: The INTR is a maskable interrupt for the 8085. It has the lowest priority and is also non
vectored. When this INTR signal goes into the high state the following things occur / take
place:
1. For every instruction that is executed the 8085 checks the status of this interrupt/
2. Till an instruction is completed the signal of INTR will remain high. een
instruction is completed the processor sends an acknowledgement signal INT.
3. Al 1con auilT geal eae lee Wasi eeeda cet ie date bus fc
transfer.
4. Once the new instruction is received the processor saves the address of new
instruction into the STACK and an interrupt service subroutine begins.
Itis also possible between a and a register.
Also it can occur between an input/output device and an accumulator.
In reality data is never transferred it can only be copied from one location to another.
Q8. What differences can you state between the HLT And HOLD States?
Ans:The Holdis « hardware inpul whereas HLT is a software instruction.
1, When the HLT state is executed the processor simply stops and the buses are driven
to tri state. No form of acknowledgement signal is given out by the processor. o the HOLD state it gives out an HLDA signal. This
by other
eabling learning..
Involved In a Fetch Cycle.
‘Ans: Fetch eyele is the time required to fetch an opcode from a particular location in
memory.
1. General Fetch Cycles consist of 3T states.
2. The first T state involves the sending of the memory address stored in the Program
‘Counter to the memory.
3. During the second T state the contents of the addressed memory is read ( this
generally is the opcode at the specified location)
4. In the third T state the opcode is sent to the Instruction register through the data bus
for execution.
5. For slower memories the processors has the provision to get in to the WAIT cycles as
well,
Q10. What are Walt states in microprocessors? Explain in brief.
Q13. Why do you use XRA A instruction?
Ans:The XRA A instruction is used to clear the contents of the Accumulator and store the
value OOH. Lae un ute AITS
Q14 Explain Addressing Modes in 8085 microprocesvor. .
Am: AddreningMadeatases — CN QD/ing learning.
‘These are the instructions used to transfer the data from one register to another register, from
the memory fo the register, and from the register to the memory without any alteration in the
content. Addressing modes in 8085 is classified into 5 groups ~
Immediate addressing mode: In this mode, the 8/16-bit data is specified in the instruction
itself as oue of its operand. For example: MVIK. 20F: means 20F is copied into register K.
Register addressing mede:In this mode, the data is copied from one register to another. For
example: MOV K, B: means data in register B is copied to register K.
Direct addressing mode:In this mode, the data is directly copied from the given address to
the register. For example: LDB S000K: means the data at address 5000K is copied to
register B.
Ex: i) ADD B ii) SUB C ii) INR Div)
Group Il - LOGICAL INSTRUCTIONS:
The instructions which performs the logical operations like AND, OR, Exclusive-OR,
complement, compare and rotate instructions are grouped under this heading. The flag
conditions are altered after execution of an instruction in this group.
ORA B ii) XRA A iii) RAR
Group IV - BRANCHING INSTRUCTIONS:
The instructions that are used to transfer the program control from one memory location to
another memory location are grouped under this heading.
Ex: i) 32.4200 ii) RST 7 iii) CALL 4300 UPTUNOTES.COM
Group V - MACHINE: ie.
Includes the instructions
execution, Teepe
(16: Fxplatn Memory interfacing with 6043 fletop toca 117117...
‘Ans: Microprocessor need to access memory quite frequently to read instructions and data
stored in memory; the interface circuit enables that access. The interface process involves
designing a circuit that will match the memory requirements with the microprocessor
signal.Memory has certain signal requirements (o read from and write into memory. Similarly
Microprocessor initiates the set of signals when it wants to read from and write into memory
Address Address
memory signal RD". i
MEMW" ). Memory places data byte during 12 and that is read by the
Function of memory interfacing is that the
microprocessor shonld be able to read from and write into a given register of a memory chip:
Select the Chip
© Identify the register
© Enable the appropriate buffer age
: ee eee ae = of
STA 3001H ;quotient
HLT
ARRANGE DATA ARRAY IN ASCENDING ORDER
LX H,2000 ‘LOOP: MOV AM
INXH
CMP M
JC SKIP
QIB. Describe Instructions of 8085 pp.
Ans.
MOV
MOV
16 bit address
‘Add_ memory to A = %
Avatar |
10
Add B & C to H
L 16-bit address
Q19. Explain keyboard & display interfacing with 8085.
Ams. In a microprocessor b system, when keyboard and 7-seament LED display is interfaced.
using ports or latches then the processor has to carry the following task.
© Key debouncing
© Keycode generation
* Sending display code to LED i 79.
The clock signal for 8279 is obtained by dividing the output clock signal of 8085 by a
clock divider circuit.
‘The chip select signal is obtained from the UO address decoder of the 8085 system.
The chip select signals for /O mapped devices are generated by using a 3-to-8
decoder,
“The address lines Ad, AS and A6 are used as input to decoder.
“The address line A7 and the control signal IO/M (low) are used as enable for decoder,
“The chip sclect signal IOCS-3 is used to select 8279. _ UPTUNOTES.COM
The cirenit has 6 mumbers of 7-scgment LEDs and so the 8279 has to be programmed in
encoded scan. (Because in decoded scan, only 4 numbers of 7-segment LEDs can be
interfaced)
«In encoded scan the output of scan lines will be binary count, Therefore an external,
3-to-8 decoder is used to decode the scan lines SLO, SLI and SL2 of 8279 to produce
eight scan lines SO 10 S7.
‘The decoded scan lines SO and S1 are common for keyboard and display.
‘The decoded scan lines $2 to $5 are used only for display and the decoded scan lines
‘86 and S7 are not used in the system.
Anode and Cathode drivers are provided to take care of the current
BC 158 are used as driver transistors.
‘of 8279 as columns and
© Ahexa key is placed at the it row and column, A key press will
in and row line will be high.
short the row and column, Normally the col
During scanning the 8279 will output binary count on SIO to SI.3, which is decoded
by decoder to make a row ns zero. When a row is zero the 8279 reads the cokumns. If
there is a key press then the corresponding column will be zero.
1£ 8279 detects a key press then it wait for debounce time and again read the columns
to generate key code. Explain Timing Diagram o
Ans; TIMING DIAGRAM for various machine cycles:
The machine cycles are the basic operations performed by the processor, while instructions
are executed. The time taken for performing each machine cycle is expressed in terms of T-
states One T-state is the time period of one clock cycle of the microprocessor. The various
machine cycles are
1. Opeode fetch . pulse. The timing diagram for IO/M read are shown in
1,72, Tis i Lae baa cree t AD? ADO
it has wore Bread inte ae
173. ALE is asserted at the beginning of T] of each bus cycle and is
negated towards the end of T1. ALE is active during T1 ouly and is used as the clock pulse to
latch the address (AD; #@ ADo) during T1. The RD is asserted near the beginning of T2. It
ends at the end of T3. As soon as the RD becomes active, it forces the memory or VO port to
assert data. RD becomes inactive towards the end of T3, causing the port or memory to
terminate the data,
eT eth et ee 1 ee ee ee
WL
corny
ae Posen
Pe. Byerde ptt enabling learning..
Unit-3
. Additional data transfer and 16 bit arithmetic instruction
to memory RAL aba RU inbédedllorse CINE...
Ans. RAL (ROTATE ACCUMULATOR LEFT THROUGH CARRY):
This instruction rotate the content of accumulator left by one position through carry flag. Bit
his placed in carry flag and carry flag is placed in least significant position bit Do,
RRC (ROTATE ACCUMULATOR RIGHT):
This instruction rotates the content of accummlator right by one position. Bit Dp is placed in
position of D; as well as in carry.
(Q2. What does the operation CPI does?
‘Ams. CPI does the operation of comparison of immediate data with accumulator. The
specified byte is compare with the content of accumulator.
Q3. What do you understand by stack?
Ans. The program sequence is transferred to address specified by operand. Before the
‘transfer, the address of next instruction to CALL is pushed on the stack.
Q7. What is RET instruction?
Ans. This instruction pops the return address from the stack and loads program counter with
‘the return address. It transfers the program control to the instruction next to CALL in the
‘main program. a ar ning..
Q9. Write short notes on counter.
Ans. Counters are mainly used to keep tack of events. It can be designed by loading an
appropriate number into any one register of microprocessor and then using INR or DCR
instruction for counting.
Q10. Define the term interrupt along with Its types.
Ans. Interrupt means diverting the attention of microprocessor while working. There are two
types of interrupt:
(a) Hardware interrupt
(©) Software interrupt
Q11. What ts the difference between hardware and software interrupt of 8085
microprocessor?
eiebaern ee
13. Explain SUB M arithmetic
cdi tememmire na from accumulator, This instruction subtract the
‘content of memory location specified by register pair and stores the results into accumulator, This instruction copies the
Ra, Sc Copy fiom the contents of the source register
source the i
MOV M.Sc Load) Hy /aud ler | copies the
ney © contents of thé next memory
location into register H.
Example — LHLD 325K
The contents of the accumulator
are copied into the memory
location specified by the
‘operand.
STA 16-bit address 16-bit address ‘This is a 3-byte instruction, the
second byte specifies the low-
order address and the third byte
specifies the high-order address.
Example ~ STA 325
ENG None. with D and E register D, and the contents of Pop off stack to the
register pair
register (C, E, L, flags) are
copied to that location.
Example — PUSH K
The contents of the memory
location pointed out by the stack
pointer register are copied to the
low-order register (C, E, L, The stack pointer is incremented
j tents of that
enabling RAPER E te cored 0
the high-order register (B, D, H,
A) of the operand.
The stack pointer register is
again incremented by 1.
Example - POPK
Output the data The contents of the accumulator
from the are copied into the VO port
OUT — 8-bit port address accumulator to a specified by the operand.
‘Example — OUTK9L
last count can be observed..To
counts.
Delay Routine/ Time delay
Delay routines are subroutines used for maintaining the timings of various operations in
microprocessor. In control applications, certain equipment needs to be ON/OFF afer a
specified time delay. In some applications, a certain operation has to be repeated after a
specified time interval, In such cases, simple time delay routines can be used to maintain the
timings of the operations system with a 0.5 clock periods. Use register C to set up a one millisecond
delay between each count and dliplay the mumber al one of outpul pert,
Ans. MVIB, 00H
NEXT: DCRB
MVIC, 05
DELAY: DCRC
JNZ DELAY
MOV A,B
OUT PORTI
JMP NEXT
DELAY CALCULATIONS:
The delay loop includes two instruction :
DCR and INZ with 14 T states. Therefore the time delay Ti. in the loop is
Tu: 14T states = T (lock period) = COUNT
i COUNT
COUNT=(1*107-17.5
(140)i0
‘Therefore the delay count
‘between cach count.
Q17. Write an assembly language program based on 8085 to count from 0 to 9 with a
one second delay between each count. At the count of 9, the counter should reset itself to
0 and repeat the sequence continuously. Use register pair HL to set up the delay and
display each count at one of the output ports. Assume the clock frequency of the
Is IMEz.
Ans. START:
DISPLAY: or
oT The 1 second delay between each count is set up by using register pair
Loop delay= 24T states *T «COUNT
1 second=24T *1.0«10°«COUNT
COUNT=1/24% 104
41666
-A2C2H
The delay count A2C2H in register HL would provide approximately a 1 second delay
between two counts.
Q18. Write a program to generate a continuous square wave with period of 200ps. Use
bit De to output the square wave.
‘Count=19.1i0=13H_
Q19. Explaim SIM and RIM instru these instruction can be used to
enable/disable interrupt and for serial 1/0?
Ans. READ INTERRUPT MASK (RIM):
instruction permits the system to examine the interrupt mask by loading into the A
aster a byte which defines the condition of the mask bits for the maskable interrupts, the
condition of the interrupts pending for the maskable inlerrupts, the condition of the Interrupt
Enable flag, and the condition of the Serial Input Data (SED) pin on the MP. ‘SET INTERRUPT MASK (SIM):
This instruction is the reverse of the RIM. While the RIM simply reads the status of various
lines, the SIM sets various bits to form masks or generate output data via the SOD line. The
conditions that the programmer wishes to set up mmst be set into the A register exactly as
desired first, then the SIM Instruction is executed.
‘SIM Instruction
ast 7s
WRITS = 1ST?
not alowed
WRITS ORST?
fs ewet
Q20. Explain the interrupt used in 8085|Bticty. I”
Ans. 8085 supports two types of interrupts. They are
1. Hardware interrupts-
«Peripheral device activates interrupt by activating the respective pin.
In response to the interrupt request, microprocessor completes the current instruction
execution in main program and transfer program control (o interrupt service routine.
« In ISR routine, required task is completed. Task may be to read data, to write data, to
update the status, to update the counter etc. UPTUNOTES.COM
After ting the task, the program) cogtrol is transferred back to the main
. ae ee
t Fee ae tr aa ese
. The engeeesdl SOS ha fre] alsa ai
RST 6.5, RST 5.5 and INTR. €
TRAP:
tis non-mask-able edge and level triggered interrupt.
Itisunaffected by any mask or interrupt enable.
© The TRAP signal must make a LOW to HIGH transition and remain HIGH until
ed. This avoids false triggering due to noise or glitches.
‘© Ithas the highest priority among all interrupts.
This interrupt transfers the microprocessor’ control to location 0024 HL
RST 7.5:
© It is mask-able, edge triggered interrupt request input line. This interrupt is triggered
at the rising edge of the signal.
«It has highest priority among all mask-able interrupts and second priority among all
interrupts.
© The interrupt vector location for this interrupt is 003C H.
RST 65 and RST 5.5:
RST SS: a
«These are level triggered, mask-able interrupt request input lines.
© RST 65 transfers microprocessor's control to location 0034 H while RST 5.5
transfers microprocessor's control to location 002C II.
microg '
INTR: a
= Itis level triggered, mask-able interrupt request input line.
© This interrupt works in conjunction with RST N or CALL instruction.
2, Software interrupts-
+ In case of software interrupts the cause of the interrupt is the execution of the
instruction.
The microprocessor 8085 has eight instructions. These eight instructions are RST 0 to
RST 7. Such interrupts are called as software interrupts.
* They allow the microprocessor to transfer program control from the main program to
the subroutine program i.e. predefined service routine addresses.
+ Predefined service routing is also referred to as ISR.
* After completing the subroutine program, the program control retums back to the
main program.
* The vector locations for RST N instruction are as follows- enabl ing learning.
RSTO G000FT (8x0) - 00001
RST 0008H (8x1) = 0008H
RST2 0010H (8x2) ~ 00101
RST3 0018H (8x3) ~ 0018H
RST4 0020H (8x4) = 0020H
RSTS 0028H (8x5) = 0028H
RST6 0030H (8x6) ~ 00301
RST'7 0038H (8x7) = 0038H.
Q21. Write
Ans. STACK:
The stack is actually ister R13. For this
reason, register RI3 is is an area of memory;
the stack pointer is the stack, Usually, the stack is
used for storing data when subrout is a last-in-first-out, ie., LIFO
structure so the last thing stored in the s| the ing retrieved. A mechanical analogy
will help you leam how the stack operates, One common mechanical stack is the plate rack.
used in some cafeterias,
‘Stack Memory om, tt | ing .
PUSH: - This instniction pushes the register pair opto stack, Thy py yiod je \
pair designated in the operand are copied onto the stack in the following sequence. The \_
stack pointer register is decremented and the contents of the high order register (B, D, H,
A) are copied into that location. The stack pointer register is decremented again and the
contents of the low-order register (C, E, L, flags) are! nates :
Eg: - PUSHB
PUSH A
POP: - This instruction pop off stack to register pair. The contents of the memory
location pointed out by the stack pointer register are copied to the low-order register (C,
E, L, status flags) of the operand. The stack pointer is incremented by 1 and the contents
of that memory location are copied to the high-order register (B, D, H, A) of the operand.
The stack pointer register is again ineremented by 1.
Fg: - POPH
POPA
‘Subroutine -
A set of Instructions which are used repeatedly in a program can be referred to as Subroutine.
Only one copy of this Instruction is stored in the memory. When a Subroutine is required it
can be called many times during the Execution of a Particular program. A call Subroutine
Instruction calls the Subroutine. Care Should be taken while retumning a Subroutine as
‘Subroutine can be called from a different place from the memory.
The content of the PC must be Saved by the call Subroutine Instruction to make a correct
Tetum to the calling program,
Subroutine linkage method is a way in which computer call and return the Subroutine. The
simplest way of Subroutine linkage is saving the retum address in a specific location, such as
register which can be called as link register call Subroutine.
Instruction
Call Subroutine Instruction
Figure — Process of subroutine in a program
Subroutine Nesting-Subroutine nesting is a common Programming practice In which one
subroutine calls another. ao UPTUNOTES.COM
Figure Subroutine calling another subroutine
From the above figure, assume that when Subroutine 1 calls Subroutine 2 the retum address
of Subroutine 2 should be saved somewhere. So if link register stores retum address of
Subroutine 1 this will be (destroyed/overwritten) by retum address of Subroutine 2. As the
last Subroutine called is the first one to be retumed ( Last in first out format). So stack data
structure is the most efficient way to store the retum addresses of the Subroutines.
Q22. Explain the various logical instructions related to rotating the accumulator bits.
‘Ans. These instructions execute on the basis of the content of accumulator, When these
instructions execute, the content of accumulator will shift by 1 bit cither left or right as per
the instruction.
1: RLC NO OPERAND
Instruction word size = 1 Byte
Operation =? When this instruction will execute the content of accumulator will shift (or
rolate) left by 1 bit without carry flag
7 i
RVAURVEUEY) UU
2: RAL NO OPERAND: Fr
Instruction word size = 1 Byte
Operation = When this instruction will execute the content of accumulator will shift (or
rotate) left by 1 bit with carry flag. —————
MICROPROCESSOR (KCS ~403) NAVNEET PAL (ASST. PROFESSOR) Page 39
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Direction of shifting/rotation
3: RRC NO OPERAND:
Instruction word size = 1 Byte
Operation => When this instruction will execute the content of accumulator will shift (or
rotate) right by | bit without carry flag.
OGFEGGEYG
Direction cf shiftina/rotation
len this instruction will execute the content of accumulato! shift (or
lag.
=m =
Accumulator
YU IGCVUY
Direction of shiftina/rotation enabling learning.
Unit-4
. BCD-to-Binary conversion and Binary-to-BCD conversion
. Bieta MICROPROCESSOR (KCS -403) NAVNEET PAL (ASST. PROFESSOR) Page 41
E>
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Short Answer type Questions
Q1. Whatis BCD Code? enabling learning..
‘Ans. Binary Code Decimal (BCD) is one of the early computer codes. The idea of this coding
scheme is to convert each digit of a decimal number into its binary equivalent instead of
converting the entire decimal valves into a binary number.
Q2. Write down the principle behind the conversion of a BCD number into its binary
equivalent?
Ams. The conversion of a BCD number info its binary equivalent implies the principle of
positional weighting in a given number.
Q3. Give the logic behind the conversion of binary to BCD.
Ans. The conversion of binary to BCD is performed by dividing the number by the powers of
ten; the division is performed by the subtraction method.
Ans. The contents of H specify the high 0 contents of L specify the low order
byte. It means copy H & L registers into program counter. repeated x
an inefficient technique for a large multiplier:
Amore efficient technique can be revised by following the model of manual multiplication of
decimal numbers. For example,
108
aS
Step 1: (108x5) = 540
Step 2: Shift left & add (LO8x1)~ +108
1620
‘The multiplier multiplies each digit of the multiplicand, starting from the farthest right, and
adds the product by shifting to the left. The same process can be applied in binary
In case of packed BCD both |, if a carry is generated by
adding 6 to BCD), the carry should
A special instruction called DAA. imal adjust accumulator) performs the function of
adjusting a BCD sum in the 8085 instruction set.
This is a 1-byte instruction. It adjusts an 8-bit number in the accumulator to form two BCD
numbers. It used the AC & the CY flags to perform the adjustment. Alll flags are affected.
DAA does not convert a binary number into BCD numbers. It works only with addition when
BCD numbers are used; does not work with subtraction.
MOVCGA + C06 or 60 enabling learning..
Q11. Explain the function of the following instructions:
osm
(i) PUSH
(a) XC
iv) CALL
Ans.
(@ SIM (Set Interrupt Mask):
This instruction masks the interrupts as desired. It also sends out serial data through the SOD
pin. For the instruction, command byte must be loaded in the accunmlator.
[xX ]RST75_ [MSE [M75 [i
[0 0 a | Leas |
in the following
(@)The stack pointer is order register ( B, D, H, A) are
copied on that location.
(b)The stack pointer is decremented again and the contents of low order register (C, E, I, flag
register) are copied to that location.
Example PUSIT RP :store register pair on stack
Or
PUSH BDIW/PSW
PSW refers to accumulator with flag register. Examples:
XCHG (2070H), AX : This instruction exchange the data between AX & a memory
location (2070H) in the data segment.
XCHG AX, BX : This instruction exchanges data between AX & BX.
fy) CALL:
“The program sequence is transferred to address specified by operand.
“Before the transfer, the address of next instruction to CALL is pushed on the stack.
*The sequence of event is described in example.
MOV BA
ANI OFH
MOVCA
MOV A,B enabling learning.. enabling learning..
ADDC
STA 2300H
ALT
QI4. Write down the assembly language program for the subtraction of two 16-bit
numbers in 8085 MPU.
Ans. LHELD 2000H uly mosareBtinig learning.
Ans.
Labels Mnemonics Operands
HID 2501H
XCHG
LDA 250311
LT Hi, 000
ww C08
Loorp: DAD H
RAL
INC AHEAD
DAD D
AHEAD: DCR c
INEZ Loop
SHLD 2504
ALT
stored at 2146H location from
the result at output port. QI9. Write an
Code is available in number 2050H & store the binary equivalent in memory 20S1H.
Ans,
START
enabling learnin
ASCII (Hex Number) into its binary
LXI SP, STACK
LXT H, 2050H
MOV A, M
INXH
CALL ASCHBIN:
MOV M,A
ASCH ‘OD
ADI 073
ADI 30H Add Base number 30H
RET
enabling learning..
Q21. Write an assembly language program for conversion of BCD to seven- segment
Decoder.
Ans.
START -LX1 SP, STACK
LXTH, 2500H
MVID, 031
‘CALL UNPACK
HLT
‘LX1B, BUFFER
‘MOV AM
ANIPOH
ic Q22. Write an assembly language program for conversion of binary to BCD.
Ans.
START: —LXISP, STACK
LXTH, BINBYT enabling learning.
Unit-5
© 8255 Programmable Peripheral Interface
¢ Interfacing keyboard and seven segment display
© 8254 (8253) Programmable Interval Timer
block ‘Ans : The #255a is a programmable peripheral interface which is used for parallel data
transfer. It is used as a general purpose device for interfacing parallel /O devices to the
system data bus. It has three 8-bit ports: Port A, Port B.& Port C.
Q2. Describe briefly the ports of 8255A.
‘Ams: Port A: This has an 8-bit latched & buffered output & 8-bit input latch.
Port B: This has an $-Bit /O latch /buffer and an 8-bit data input buffer.
Port C: This has one 8-bit unlatched input buffer & an 8-bit output latch/buffer.
Q3. What are the different modes of operation of 255A?
0: Basic 0
Poll Method: The 8259A can be set up to function ina polled environment.
Q6. What Write down the various transfer modes of 8237.
Ans : The various transfer modes of 8237 are:
‘+ Single transfer mode
+ Block wansfer mode ‘Ans : Bus Interface Unit (BTU): Its provides a full 16-bit bi-directional data bus & 20-bit
address bus.
Execution Unit (EU); It tells the BIU from where to fetch instructions or data, decodes
instructions & executes instructions..
Q8. Write Down the advantages of memory segmentation.
‘Ans +: It allows the memory addressing capacity to be IMB even through the address
associated with individual instruction is ouly 6-bits. It facilitates use of separate memory
areas for program, data & stack. Its useful in multiprogramming.
Q9. What is the significance of pipelines in 8086 microprocessor?
Q12. Write the control word format for BSR mode of 8255.
‘Ans. Coutrol word format for BSR mode of 8255 is given as:
fe [x [x [x Bit select [S/R
BSRMODE Not Used generally set =0 ‘Set=I Reset=0 enabling learning..
* Mode 0 (basic 1/0): In this mode, in addition to Port A & Port Bl PC7-PC4 & PC3-PCO of
Part C cam be considered as two individual 4-bit ports. Therefore, four ports, each of which
can be configured either as an iuput or an output ports are available. Here the ports are simple
input & output ports, data is written to or read from the specified port without handshaking.
‘The data send out to the output ports are latched, whereas inputs are not latched.
+ Mode 1 (strobe 1/0): In this mode, input or output data transfer is affected by strobe
(handshaking signals). The two: groups, Group A & Group B, can be configured separately,
with each group consisting of an 8-bit port & a 4-bit port. The 8-bit port can be programmed
for input or output. The 4-bit port is used for handshaking.
+ Mode 2 (strobe bi-directional bus 1/0): This mode allows bi-directional data transfer over a
single 8-bit data bus using handshaking signals. This feature is available only in group A with
Port Aas the 8-bit bi-directional data bus, & PC4-PC7 are used for handshaking purposes. In
+ In this mode, 8237 is.
block of data is transferred.
«The transfer cycle may be terminated due to EOP which forces TC
+The DREQ needs to be activated only till the DACK Signal is activated by DMA controller.
+ Auto initialization may be programmed in this mode. UPTUNOTES.COM
y transfer until a TC is reached or an Extemal EOP is
a “enabling learning.
