A Transient-Enhanced Fully-Integrated LDO

Regulator for SoC Application

Nanqi Liu∗ , Brian Johnson† , Vinay Nadig† , Degang Chen∗
∗ Dept. of Electrical and Computer Engineering, Iowa State University, Ames, IA, 50010
† Texas Instruments Inc., 5411 E Williams Blvd, Tucson, AZ 85711
   
Email: nanqiliu, djchen @iastate.edu , johnson brian, vnadig @ti.com

Abstract—A fully integrated low-dropout regulator (LDO) with Therefore, an LDO with ultra-fast settling after load transients
ultra-fast transient settling is proposed to provide a clean supply is in demand.
for digital circuits in nano-scale technology. A super source Many cap-less LDOs have been proposed in the past years
follower (SSF) is inserted into the cascode flipped voltage follower
(FVF) topology to drive the power transistor for fast turn-on. [6] - [10]. A large quiescent current (6%) was consumed in
The proposed positive transient detection (PTD) circuit drive a [6], which can reduce the battery lifetime. A single-transistor-
NMOS transistor for fast pull-down. The combined effects of control LDO based on flipped voltage follower (FVF) provided
these two techniques significantly attenuate the load transient stable voltage regulation at a wide range of output capaci-
induced voltage spikes. The LDO is designed in a 130 nm CMOS tor/ESR conditions in [7]. However, it was sensitive to process,
process and consumes 100 μA quiescent current with 1.2 V
regulated output and 200 mV dropout voltage. For large load voltage and temperature (PVT) variations and load transient
transient of 100 μA to 20 mA and back to 100 μA, the simulated undershoot was still as large as 160 mV. The FVF topology
undershoot and overshoot is less than 95 mV with 150 ns recovery was also used in [8] and [9] with a gain-enhanced stage to
time, demonstrating a glitch peak reduction of 6 times and a improve load regulation, but only results with 100 ns edge
glitch settling time reduction of 5 times. time are provided. A tri-loop LDO with 82 mV overshoot
within 200 ps edge time was proposed in [10]. However, due
I. I NTRODUCTION to the poor regulation performance and low frequency PSR, the
application was limited to wideband communication systems.
The power management IC (PMIC) plays a critical role Stability is a basic requirement for an LDO. Performance
in portable electronics, such as smartphones, tablets, or other in terms of accuracy, transient response and PSR is usually
digital assistants. Various types of power management units are a more difficult task. This paper is mainly focused on the
required in these system-on-chip (SoC) applications. Switch- improvement of transient response for fully integrated LDOs.
ing regulators are commonly employed as the energy reservoir A buffer impedance attenuation (BIA) technique is first im-
interface because of their high power efficiency. However, plemented by inserting a super source follower (SSF) after
they can generate high levels of switching noise. To filter the folded-cascode FVF stage to improve the power device’s
this noise and provide a clean supply, low-dropout regulators capability to quickly source current. A positive transient de-
(LDO) are usually cascaded after the switching regulators [1], tection (PTD) circuit is added at the LDO’s output to detect
[2]. Therefore, high performance LDOs, in terms of accuracy, the overshoot during heavy/light load transient and quickly
response time, over/undershoot, power efficiency, and off-chip generate a pull down current. These two techniques together
component free feature, are essential to the success of SoC. can significantly attenuate the undershoot/overshoot resulted
Conventional LDOs use an off-chip output capacitor in the from large load transient and lead to significantly shorter
μF range to stabilize the system. A large output capacitor transient settling time.
also helps to reduce voltage ripples due to load transients and The rest of the paper is organized as follows. In Section II,
improve power supply rejection (PSR) [3]. For fully-integrated the proposed buffer is compared with conventional buffers in
or cap-less LDOs in SoCs, the output capacitor value is limited cap-less LDOs. Then the transient performance is analyzed and
due to area budget, which can lead to significant degradation the PTD circuit is presented. Section III discusses the circuit
in transient and PSR performance. Different circuit loads can implementation and stability analyses of this LDO. Simulation
have specific supply requirements. Digital circuits typically results are provided in Section IV. Finally, the conclusion is
require an LDO with good load transient response because drawn in Section V.
the current consumption of digital cells, such as SRAM bank,
can change from near zero to maximum (50 to 100 mA), or II. T RANSIENT ENHANCEMENT TECHNIQUES
back, in very short amount of time [4]. An abrupt change Overshoot or undershoot at the LDO’s output results from
in the microprocessor’s switching activity can result in a the redundant or insufficient energy delivery when a load tran-
sharp supply change [5]. These high frequency supply volt- sient occurs. To achieve good transient performance, a large
age transients degrade the performance and energy efficiency unity gain frequency (UGF) is necessary to drive the power
of microprocessor products across all market segments [5]. device immediately and provide the adequate power. Cap-less

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 A. Flipped Voltage Follower
VREF Buffer
VEA FVF has been used in the designs of a buffer [7] as shown
EA MP in Fig. 2(b) because of its fast speed potential and low voltage
VKhd supply operation [12]. M1 senses the VOU T transient and can
Pole-splitting
quickly send an error voltage to VG to control the MP current.
R1 A FVF with folded-cascoded stage was further used in [8], [9]
VFB
and [13] to improve the loop gain, which is shown in Fig. 2(c).
R2 CL IOUT The buffer’s output impedance is ro ≈ RBIAS2 ||rds2 , which
can be large to make the pole wG located at low frequency.

Fig. 1. Typical structure of a LDO with an intermediate buffer stage.

B. Super Source Follower
As mentioned earlier, all non-dominant poles should be
IBIAS1 VG moved to frequencies that are considerably higher than the
MP UGF to suppress the transient voltage spike. To push the pole
VG sKhd
MP
VEA M1 wG to high frequency, we can use large bias current IBIAS2
sKhd and add an additional buffer. As shown in Fig. 2(d), a super
VEA M1
R1 R1 source follower (SSF) is inserted between the FVF stage and
VFB VFB the power device. The SSF has a very low output resistance:
IBIAS1
R2 R2 1
ro ≈ , (2)
gm3 (gm4 rds3 )
(a) (b) which can push wG higher than the UGF. During light-
to-heavy load transition, VOU T undershoot can be inverted
IBIAS2 RBIAS2 IBIAS3
VG VG amplified to V3 instantly and turn on M4 , which is designed in
MP MP
sKhd V2 subthreshold region, to draw a large current to discharge VG .
M3 sKhd
VBIAS M2 With the SSF, the power device can be fast turn-on to source
VEA M1 VBIAS M2 V3 M4 current and thus the undershoot spike is well attenuated. A
R1 VEA M1 R1 small resistor is used to generate the biasing current IBIAS2
VFB V1 VFB to move the parasitic pole w2 to high frequency.
IBIAS1
R2 RBIAS4 IBIAS1 R2 C. Positive Transient Detection
For all the buffers in Fig. 2, the charging up speed at the
(c) (d)
gate of MP is limited to the biasing current IBIAS3 . When
Fig. 2. Buffer structures: (a) Source follower, (b) Flipped voltage follower, heavy-to-light load transient occurs, MP cannot be turned off
(c) FVF with cascode stage, (d) Proposed buffer with SSF. immediately due to this slew rate limitation and thus slow
overshoot settling is overserved. To overcome this problem, the
LDOs are usually designed as a multi-stage architecture as LDO needs extra pull down circuits like the source follower in
shown in Fig. 1 to extend the bandwidth [11]. Due to the [4]. Because of the speed and stability considerations, the pull
small parasitic capacitance and drain resistance in nano-scale down NMOS in [4] should be small which limits the current
technology, the poles at the LDO’s output, at the gate of MP absorption. A novel positive transient detection (PTD) circuit
and at the output of the error amplifier (EA) are all not at is introduced here, which is shown in Fig. 3. A 100 fF coupling
very low frequency. For stability consideration, pole-splitting cap CF is used to couple the VOU T overshoot to VF B . The
techniques need to be implemented to form the dominant pole. common source amplifier M5 followed by an inverter biased
The buffer needs to provide low impedance to MP to move at its threshold can instantly amplify the overshoot and turn on
non-dominant poles to high frequency to obtain a large UGF. M6 (normally off) to pull down VOU T to the designed value.
Several buffer structures are given in Fig. 2. Let us first For speed considerations, transistors in the FVF, SSF stages
consider the simplest common drain amplifier M1 in Fig. and the PTD circuit are all thin-oxide devices to obtain fast
2(a), which is frequently used as a voltage buffer. The output operation.
resistance is small:
III. P ROPOSED TRANSIENT- ENHANCED LDO
1
ro ≈ . (1) The transistor level schematic of the proposed LDO is given
gm1 + gmb1
in Fig. 3. The error amplifier (EA) is implemented with the
However, the dominant pole at the EA’s output slows down folded-cascode topology to boost the DC gain in nano-scale
the speed of VEA and thus limits the transient response at the technology. The LDO has closed-loop stability issue if no
gate of MP . A fast internal loop excluding the EA is in need compensation strategy is used. Due to the small parasitic
to respond to sharp load transient. capacitance, the pole at the output of EA is not at low

978-1-5386-4881-0/18/$31.00 ©2018 IEEE

 VIN VB2
RB2 IB3
VG VB2
MP
V2 VOUT
M3
VREF VFB VB3 VB5 M2 M4
V0 V3 M6
M1 CF
R1
VB1 VB4 V1 M5
VFB CL IOUT
C0 RB4 IB1
R2
GND
Error Amplifier Buffer Based on FVF and SSF Positive Transient Detection

Fig. 3. Full schematic of the proposed LDO.

v0 v2 vg vout
vin gmEA -GmFVF GmSSF -gmMP

RO0 C0 RO2 C2 RO' C' ROUT CL

Fig. 4. Small-signal modeling of the proposed LDO.

1
frequency. Therefore, a compensation capacitor C0 = 1 pF where ROU T = rdsM P || gm 1
||RL . The power device stage
is added to form the dominant pole at V0 . has the gain as
A. Stability Analyses vout −gmM P ROU T
= . (8)
vg 1 + sROU T CL
Fig. 4 shows the small-signal model of the proposed LDO,
where ROi and Ci are the equivalent output resistance and As mentioned earlier, small RB2 is used to move the pole w2
lumped output parasitic capacitance of each gain stage, re- to high frequency. Then the closed loop transfer function of
spectively. the local loop including the FVF, SSF and MP stages can be
The small signal differential input of the EA is given here: calculated as
vg
v0 −vout ∗ v2 ∗ vg
v2 vout
R2 vout
vin = vREF − βvout = vREF − vout . (3) = v
R1 + R2 v0 1 + v0 −v
v2
∗ vg2 ∗ vvout
out g (9)
Non-dominant poles in the EA, e.g., the pole at the diode ADC local
≈
connection in the cascode stage, are all outside of the UGF. ADC local + (1 + sROG CG )(1 + sROU T CL )
So the voltage gain of this stage is calculated as where ADC local = gm1 (RB2 ||rds2 ) ∗ gmM P ROU T .
v0 gmEA RO0 Multiplied with the EA’s gain, the open loop gain of the LDO
= . (4)
vin 1 + sRO0 C0 is
vout v0 vout
The parasitic pole at V1 is located at high frequency because = ∗ . (10)
1
vin vin v0
of the small resistance (≈ gm2 +gmb ) at the node V1 . Then
2
the voltage gain of the FVF with cascode stage is given by In this design, we have β = 12 for VREF = 600 mV and VOU T
= 1.2 V. The closed loop transfer function of the LDO is given
v2 −GmF V F RO2 −gm1 (RB2 ||rds2 ) in (11), where ADC whole = gmEA RO0 ∗ ADC local .
= ≈ .
v0 − vout 1 + sRO2 C2 1 + sCgs3 (RB2 ||rds2 ) The Routh-Hurwitz criterion is used to derive the stability
(5) conditions, which is widely used in control engineering for
The voltage gain of the SSF stage is also derived here: the stability analysis of closed loop systems. The stability
gm3 condition is fulfilled when
vg GmSSF ROG gm3+gmb3
= ≈ (6) 1 1 1 gmEA
v2 1 + sROG CG 1 + sROG CG + > . (12)
1
ROG CG CL (rdsM P ||RL ) 2 C0
where ROG ≈ gm3(gm4rds3) . The miller cap CG equals to
This is used as the design guideline to meet the stability
CG = CgsM P + (1 + gmM P ROU T )CgdM P (7) requirement.

978-1-5386-4881-0/18/$31.00 ©2018 IEEE

 vout ADC whole
= 1 1 (11)
vREF 2 ∗ ADC whole + (1 + sRO0 C0 ) ∗ (ADC local + (1 + sCgs2 (RB2 ||rds2 )(1 + sCL (rdsM P || gm 1
||RL ))

Undershoot=90 mV,
T^dd>=150 ns

Fig. 5. Simulated bode plots of proposed LDO with different IOU T . (a)

IV. S IMULATION R ESULTS

The proposed LDO is simulated in a 130nm CMOS process Overshoot=95 mV,
T^dd>=100 ns
for 1.4 V input voltage and 1.2 V regulated output voltage.
The maximum load current is 20 mA and the total quiescent
current is 100 μA. The total on-chip capacitors are 1.4 pF
including C0 , CF and decoupling capacitors at biases.

A. Stability
The simulated loop gain and phase margin of the proposed (b)
LDO with CL =100 pF at different IOU T are shown in Fig. 5. Fig. 6. Simulated load transient response with CL = 100 pF .
The low frequency loop gain is 51dB while the phase margins
Table I
in all conditions are more than 85◦ . The proposed transient C OMPARISON OF S TATE - OF -A RT C AP - LESS LDO S
enhancement techniques don’t have negative effects on PSR,
Publication [2] 2012 [9] 2014 [10] 2015 This work
so the results are not shown here. Tech (nm) 90 65 65 130
VOU T (V) 1 1 1 1.2
B. Load Transient Dropout (mV) 200 200 150 200
IQ (μA) 408 23.7 90 100
The load transient response is provided in Fig. 6. The IM AX (mA) 100 50 10 20
load current changes between 100 μA and 20 mA within the On-chip cap (pF) 1.8 9 140 1.4
ΔVOU T (mV) 43 40 82 90
rise/fall time of 10 ns. The glitch energy can be calculated as TEdge (ns) 10 100 0.2 10
 t0 +TR TSET T LE (μs) 0.15 1.65 0.3 0.15
2 PSR (dB) at 1 kHz -56 -52 -22 -60
Eglitch = ΔVOU T dt (13)
t0

where t0 is the starting time of the load transient and V. C ONCLUSION

TSET T LE is the recovery time when VOU T settles back to 1 This paper introduces a 1.2 V fully integrated LDO in a 130
% accuracy. As shown in Fig. 6 (a), during light-to-heavy load nm CMOS process. The super source follower based buffer
transition, undershoot is reduced from 600 mV to 90 mV by and the positive transient detection circuit are implemented to
adding the SSF stage. In Fig. 6 (b), the LDO with only SSF achieve fast transient settling. The voltage spikes are less than
stage still has large overshoot about 300 mV during heavy- 95 mV and can recover to 1% accuracy in 150 ns when load
to-light load transient. While after adding the PTD circuit, current changes from 100 μA to 20 mA, or back, with edge
overshoot is reduced to 95 mV and the recovery time is time of 10 ns. The total on-chip capacitance is 1.4 pF and
reduced significantly. In both cases, the LDO can recover to the LDO consumes 100 μA quiescent current. The achieved
1 % accuracy within 150 ns and the glitch energy are reduced specifications of the proposed LDO are suitable for digital
by 32 and 65 times, respectively. circuits in SoC applications.
The performance summary and comparisons with recent
designs are listed in Table I. Although the reported are ACKNOWLEDGMENT
simulated results, compared to [2], the proposed LDO achieves The authors gratefully acknowledge engineers at Texas
similar transient response with much less quiescent current. Instrument for their suggestions.

978-1-5386-4881-0/18/$31.00 ©2018 IEEE

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