Most most of the base DRC issues or violated because of below reasons

filler gaps sCell overlap.

cell orientation issues

standard cell not on cellssite

cells will you be issues due to absence of tab cells

placing single height cellsin level shifter regions in MV tiles

1)All base DRC will be flagged when there is a fail gaps in the desig

Reasons

This might be due to the heart placement blockages at the locations avoiding filler sale insertion

legalisation issues causing empty area around the location

solutions

need to clear legalisation issues

should not leave filler gaps as there will be no filler cells in the design library need to move cells to make
a room for at least filler cells or bigger filler spellspel

should remove heart blockages in the CoRe area to insert fillers

2)Best RC due to the overlap and wrong orientation in the design

Reasons

There will be overlaps of sales in the design and might be fixed state and will not clear it inflow

Sales placed in wrong orientation will cause based RC issues

Overlaps in N4 can be identified by filler and VC star issues in drcs

Solutions

need to unfix the sales to clear inflow or should be manually by moving the sales and must be kept in
fixed state to avoid further moment

need to check the orientation and should change according to the cells in a row

3) based DRC due to the self placed on wrong in one tracks or of cell site

Reasons

Cells not placed in the side rows or placed of grid can be identified by CPO star TRC issues

Cells place on track but in wrong M1 or M2 track colour confilts with internal M1 or M2 shapes

Solutions
Need to legalise the sales or should place on cell sites

Need to change the self placement so that Mask of the internal shapes should match with respect to
track colour

4) best DRC due to the abutment of tap cells

Reasons

Tap cells place in the design improper abutment partial abutment is not allowed due to the internal
structure

Solutions

Need to play the sales so that they should be abutment completely or no abutment

5)LUp issue in the design

Reasons

L u p issues due to the more tabsal pitch in the violated rows

Some might be false issues due to PG shots and sell overlaps in the design

Solutions

Requires tap cells insertion in the particular violated rows

need to clear root cause issues like PG shots and overlap in the design

6) floating gate issue

Reasons

Input Pins of violating cell is not connected to any net or floating

Solutions

The input prince of the cells should not be floating need to check whether those cells are required or tie
off the floating pins to the tie cells

Issue on t-max sales can be checked with full ship team bet they can be waved or not

7) single height cells in the level shifter region

Reasons

In level shifter reason of MV tiles placing single height cells in LS region will be violated because DRC and
lup issues and LvS issues as well

Solutions

Need to be double height in NW fillerss and double height lvl cells should be placed

Metal drv
Most of the metal DRC issues are violated because of below reasons hotspot reasons and improper area
or length space and enclosure maintenance

B) improper length or area space in enclosure maintenance

M1

Spacing -0.038um for yellow mask – 0.05um for red mask

M2

Spacing - >0.06um

Length -> 0.14um

Some basic metals facing or length or enclosure requirements

Via1/via2

Spacing: requires at least one track between them in horizontal or vertical direction do not require
trackspace if place diagonally

Enclosure by upper or lower metal 0.03uum

Via3

Spacing 0.09 u m (requires at least two tracks between them)

Enclosure by m3/m4 :0.03um

Via45678910

Spacing: 0.094um (requires at least one track between them in horizontal and vertical direction do not
required trackspace if place a diagonally)

C) metal density issues

Metal density issues violating around tile boundary can be ignored need to fix them if violetting in core
area or around any macro

Density rules violet mainly due to absence of metal fill in violating area so check for routing blockages of
there any extended block ages need to need to be removed those blockages to generate metal fills at the
violated region

Common lvs checks

Pg shorts

Signal shorts and opens

Pg deive issues

Basic debug technique

1) Use check_lvs
Check_lvs reports most of the PG shots net shorts or opens PG derive issues and also floating pins

So fixing check LVS issues will clean most of the tile lvs

Syntax

Check_lvs – max_errors0 -open_reporting detailed – report_floating _pins true

2) Fixing hotspot region

LVS

1)PG shorts due to overlapping of one power or ground stripes on other power or grounds strips
Solution: need to remove overlapping of different power or crown stripes this can be identified
in check_lbs

2)There are derive PG issues cells of fundament will be placed in other domain

Solution: need to play sales in the respective power domains along with vsi issues there will be m
zero shots in check_rLvd

3) There are sequence shots might be due to no track available when there is a high pin density

Need to spread the sales in the scenario otherwise routing conjunction will be increased at one area and
difficult in clearing shorts and drcs

4) There will be huge missing connections for a on /o n o power in lvs report due to the tab cell
placed in o n o power rows
Solution: tap cells with naming PT tap cell should be placed in o n o domain where as tapcellop
should be placed in Ain domain to avoid this type of issues

5) There will be opens due to the floating pPins OR the net derived 2 only one cell pin might report
floating or missing connections

Need to remove having floating pins or net derived to only one pin is not required

Need to established connection for missing connections reported in check_railways

6) There will be port shots the same net derived to two or multiple ports or shots are the port
location due to the routing congestion

Need to change derivation of sports having same derivations

For shorts between the different net ports need to remove the nets to route again or change the routing
tracks

7) There will be opened reported in lbs and as well false issues will be reported in lbs report
8) PG clock net short (not reported in check_lvs)

Mpcts r o o t buffers placed under PG mesh will cause PG clock net shots
This type of shorts won’t be reported in check_railways has the short in between cell internal shapes and
tile level shapes

Need to be munh thos violated sales to away from the pg mesh or cut the heagi stripes which has
overlapored with internal shapes on all layers if no Ir concern

9) PG short through boundary cells of macross

PG shorts might occur through boundary cells of macross in o n o tiles

If you see any PG shorts highlight me to boundary cells check the violating follow pins on both sides of
micros. The fall of beings must belong to same power or they should be will be cut sell in the boundary
cells