Rev. 2.

3_00

CMOS SERIAL E2PROM S-93C46A/56A/66A

The S-93C46A/56A/66A is high speed, low power 1K/2K/4K-bit E 2 PROM with

a wide operating voltage range. It is organized as 64-word ×16-bit,
128-word×16-bit, 256-word×16-bit, respectivly. Each is capable of sequential
read, at which time addresses are automatically incremented in 16-bit blocks.
The instruction code is compatible with the NM93CS46/56/66.

„ Features
y Low power consumption y Endurance : 106 cycles/word
Standby : 1.0 µA Max. (VCC=5.5 V) y Data retention : 10 years
Operating : 0.8 mA Max. (VCC=5.5 V)
: 0.4 mA Max. (VCC=2.5 V) y S-93C46A : 1K bits NM93CS46 instruction code compatible
y Wide operating voltage range y S-93C56A : 2K bits NM93CS56 instruction code compatible
Read/Write : 1.8 to 5.5 V y S-93C66A : 4K bits NM93CS66 instruction code compatible
y Sequential read capable

„ Packages
y 8-pin DIP (PKG drawing code : DP008-A)
y 8-pin SOP (PKG drawing code : FJ008-D)
y 8-pin TSSOP (PKG drawing code : FT008-E)
y 8-pin MSOP (PKG drawing code : FN008-A)
„ Pin Assignment
8-pin DIP 8-pin SOP1 8-pin SOP2 8-pin TSSOP
Top view Top view Top view Top view

NC 1 8 TEST CS 1 8 VCC CS 1 8 VCC

CS 1 8 VCC SK NC
2 2 7
VCC 7 GND SK 2 7 NC DI 3 6 TEST
SK 2 7 NC 3 6 DO DI 3 6 TEST
DO 4 5 GND
CS

SK 4 5 DI DO 4 5 GND S-93C46AFT
DI 3 6 TEST S-93C56AFT
S-93C46AFJ S-93C46ADFJ S-93C66AFT
DO 4 5 GND S-93C56AFJ S-93C56ADFJ
8-pin MSOP
S-93C66AFJ S-93C66ADFJ
S-93C46ADP-1A Top view
S-93C56ADP-1A VCC 1 8 CS
S-93C66ADP-1A NC 2 7 SK
TEST 3 6 DI
GND 4 5 DO

S-93C46AMFN
* See „ Dimensions S-93C56AMFN
S-93C66AMFN
Figure 1
„ Pin Functions
Table 1
Pin Number
Name Function
DIP SOP1 SOP2 TSSOP MSOP
CS 1 3 1 1 8 Chip select input
SK 2 4 2 2 7 Serial clock input
DI 3 5 3 3 6 Serial data input
DO 4 6 4 4 5 Serial data output
GND 5 7 5 5 4 Ground
Test pin (normally kept open)
TEST 6 8 6 6 3
(can be connected to GND or Vcc)
NC 7 1 7 7 2 No Connection
VCC 8 2 8 8 1 Power supply

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CMOS SERIAL E2PROM
S-93C46A/56A/66A Rev. 2.3_00

„ Block Diagram

Address VCC
Memory array
decoder GND

Data register Output buffer DO

DI

Mode decode logic

CS

SK Clock generator

Figure 2

„ Instruction Set
Table 2
Start Op Address
Instruction Data
Bit Code
S-93C46A S-93C56A S-93C66A

READ (Read data) 1 10 A5 to A0 XA6 to A0 A7 to A0 D15 to D0 Output*1

WRITE (Write data) 1 01 A5 to A0 XA6 to A0 A7 to A0 D15 to D0 Input
ERASE (Erase data) 1 11 A5 to A0 XA6 to A0 A7 to A0 
WRAL (Write all)*2 1 00 01xxxx 01xxxxxx 01xxxxxx D15 to D0 Input
ERAL (Erase all)*2 1 00 10xxxx 10xxxxxx 10xxxxxx 
EWEN (Program enable) 1 00 11xxxx 11xxxxxx 11xxxxxx 
EWDS (Program disable) 1 00 00xxxx 00xxxxxx 00xxxxxx 
x : Doesn’t matter.
*1 : Addresses are continuously incremented.
*2 : Valid only at Vcc = 2.5 V to 5.5 V.

„ Absolute Maximum Ratings

Table 3
Parameter Symbol Ratings Unit
Power supply voltage VCC -0.3 to +7.0 V
Input voltage VIN -0.3 to VCC+0.3 V
Output voltage VOUT -0.3 to VCC V
Operating ambient temperature Topr -40 to +85 °C
Storage temperature under bias Tbias -50 to +95 °C
Storage temperature Tstg -65 to +150 °C

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 CMOS SERIAL E2PROM
Rev. 2.3_00 S-93C46A/56A/66A

„ Recommended Operating Conditions

Table 4
Parameter Symbol Conditions Min. Typ. Max. Unit

READ/WRITE/ERASE
1.8  5.5 V
Power supply voltage VCC EWEN/EWDS
WRAL/ERAL 2.5  5.5 V
VCC=4.5 to 5.5 V 2.0  Vcc V
High level input voltage VIH VCC=2.7 to 4.5 V 0.8×Vcc  Vcc V
VCC=1.8 to 2.7 V 0.8×Vcc  Vcc V
VCC=4.5 to 5.5 V 0.0  0.8 V
Low level input voltage VIL VCC=2.7 to 4.5 V 0.0  0.2×Vcc V
VCC=1.8 to 2.7 V 0.0  0.15×Vcc V

„ Pin Capacitance
Table 5
(Ta=25 °C, f=1.0 MHz, VCC=5 V)

Parameter Symbol Conditions Min. Typ. Max. Unit

Input Capacitance CIN VIN=0 V   8 pF

Output Capacitance COUT VOUT=0 V   10 pF

„ Endurance
Table 6
Parameter Symbol Min. Typ. Max. Unit

Endurance NW 106   cycles/word

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CMOS SERIAL E2PROM
S-93C46A/56A/66A Rev. 2.3_00

„ DC Electrical Characteristics
Table 7

VCC=4.5 V to 5.5 V VCC=2.5 V to 4.5 V VCC=1.8 to 2.5 V

Parameter Smbl Conditions Unit
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Current
consumption ICC1 DO unloaded   0.8   0.6   0.4 mA
(READ)
Current
consumption ICC2 DO unloaded   2.0   1.5   1.0 mA
(PROGRAM)

Table 8

VCC=4.5 V to 5.5 V VCC=2.5 to 4.5 V VCC=1.8 to 2.5 V

Parameter Smbl Conditions Unit
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Standby current CS=GND DO=Open
ISB   1.0 — — 0.6 — — 0.4 µA
consumption Connected to VCC or GND
Input leakage
ILI VIN=GND to VCC  0.1 1.0 — 0.1 1.0 — 0.1 1.0 µA
current
Output leakage
ILO VOUT=GND to VCC  0.1 1.0 — 0.1 1.0 — 0.1 1.0 µA
current
Low level output VOL IOL=2.1 mA   0.4 V
voltage IOL=100 µA   0.1 — — 0.1 — — 0.1 V
IOH=-400 µA 2.4   V
High level output VOH
voltage IOH=-100 µA VCC-0.7   VCC-0.7 — — V
IOH=-10 µA VCC-0.7   VCC-0.7 — — VCC-0.2 — — V
Write enable latch Only when write disable
VDH 1.5   1.5 — — 1.5 — — V
data hold voltage mode

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 CMOS SERIAL E2PROM
Rev. 2.3_00 S-93C46A/56A/66A

„ AC Electrical Characteristics
Table 9
Input pulse voltage 0.1×VCC to 0.9×VCC
Output reference voltage 0.5×VCC
Output load 100pF

Table 10
VCC=4.5 to 5.5V VCC=2.5 to 4.5 V VCC=1.8 to 2.5V
Parameter Smbl Unit
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
CS setup time tCSS 0.2 — — 0.4 — — 1.0 — — µs
CS hold time tCSH 0 — — 0 — — 0 — — µs
CS deselect time tCDS 0.2 — — 0.2 — — 0.4 — — µs
Data setup time tDS 0.1 — — 0.2 — — 0.4 — — µs
Data hold time tDH 0.1 — — 0.2 — — 0.4 — — µs
Output delay tPD — — 0.4 — — 1.0 — — 2.0 µs
Clock frequency fSK 0 — 2.0 0 — 0.5 — — 0.25 MHz
Clock pulse width tSKH, tSKL 0.25 — — 1.0 — — 2.0 — — µs
Output disable time tHZ1, tHZ2 0 — 0.15 0 — 0.5 0 — 1.0 µs
Output enable time tSV 0 — 0.15 0 — 0.5 0 — 1.0 µs
Programming time tPR — 4.0 10.0 — 4.0 10.0 — 4.0 10.0 ms

tCSS tCDS

CS
tSKH tSKL tCSH

SK
tDS tDH tDS tDH

DI Valid data Valid data

tPD tPD
Hi-Z Hi-Z
DO
tSV
(READ) tHZ1
tHZ2
Hi-Z Hi-Z
DO
(VERIFY)

Figure 3 Read Timing

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CMOS SERIAL E2PROM
S-93C46A/56A/66A Rev. 2.3_00

„ Operation
Instructions (in the order of start-bit, instruction, address, and data) are latched to DI in synchronization with the rising
edge of SK after CS goes high. A start-bit can only be recognized when the high of DI is latched to the rising edge of SK
when CS goes from low to high, it is impossible for it to be recognized as long as DI is low, even if there are SK pulses after
CS goes high. Any SK pulses input while DI is low are called "dummy clocks." Dummy clocks can be used to adjust the
number of clock cycles needed by the serial IC to match those sent out by the CPU. Instruction input finishes when CS goes
low, where it must be low between commands during tCDS.
All input, including DI and SK signals, is ignored while CS is low, which is stand-by mode.

1. Read
The READ instruction reads data from a specified address. After A0 is latched at the rising edge of SK, DO output
changes from a high-impedance state (Hi-Z) to low level output. Data is continuously output in synchronization with the rise
of SK.
When all of the data (D0) in the specified address has been read, the data in the next address can be read with the input
of another SK clock. Thus, it is possible for all of the data addresses to be read through the continuous input of SK clocks as
long as CS is high.
The last address (An yyy A1 A0 = 1 yyy 11) rolls over to the top address (An yyy A1 A0 = 0 yyy 00).

CS

SK 1 2 3 4 5 6 7 8 9 10 11 12 23 24 25 26 27 28 39 40 41 42 43 44

DI 1 1 0 A5 A4 A3 A2 A1 A0

Hi-Z Hi-Z
DO 0 D15 D14 D13 D2 D1 D0 D15 D14 D13 D2 D1 D0 D15 D14 D13

A5A4A3A2A1A0+1 A5A4A3A2A1A0+2

Figure 4 Read Timing (S-93C46A)

CS

SK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 24 25 26 27 28 29 40 41 42 43 44 45

DI 1 1 0 X A6 A5 A4 A3 A2 A1 A0

Hi-Z Hi-Z
DO 0 D15 D14 D13 D2 D1 D0 D15 D14 D13 D2 D1 D0 D15 D14 D13

A6A5A4A3A2A1A0+1 A6A5A4A3A2A1A0+2

Figure 5 Read Timing (S-93C56A)

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 CMOS SERIAL E2PROM
Rev. 2.3_00 S-93C46A/56A/66A

CS

SK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 24 25 26 27 28 29 40 41 42 43 44 45

DI 1 1 0 A7 A6 A5 A4 A3 A2 A1 A0

Hi-Z Hi-Z
DO 0 D15 D14 D13 D2 D1 D0 D15 D14 D13 D2 D1 D0 D15 D14 D13

A7A6A5A4A3A2A1A0+1 A7A6A5A4A3A2A1A0+2

Figure 6 Read Timing (S-93C66A)

2. Write (WRITE, ERASE, WRAL, ERAL)

There are four write instructions, WRITE, ERASE, WRAL, and ERAL. Each automatically begins writing to the
non-volatile memory when CS goes low at the completion of the specified clock input.
The write operation is completed in 10 ms (tPR Max.), and the typical write period is less than 5 ms. In the
S-93C46A/56A/66A, it is easy to VERIFY the completion of the write operation in order to minimize the write cycle by setting
CS to high and checking the DO pin, which is low during the write operation and high after its completion. This VERIFY
procedure can be executed over and over again.

Because all SK and DI inputs are ignored during the write operation, any input of instruction will also be disregarded.
When DO outputs high after completion of the write operation or if it is in the high-impedence state (Hi-Z), the input of
instructions is available. Even if the DO pin remains high, it will enter the high-impedence state upon the recognition of a
high of DI (start-bit) attached to the rising edge of an SK pulse. (see Figure 3).

DI input should be low during the VERIFY procedure.

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CMOS SERIAL E2PROM
S-93C46A/56A/66A Rev. 2.3_00

2.1 WRITE
This instruction writes 16-bit data to a specified address.
After changing CS to high, input a start-bit, op-code (WRITE), address, and 16-bit data. If there is a data overflow of more
than 16 bits, only the last 16 bits of the data is considered valid. Changing CS to low will start the WRITE operation. It is not
necessary to make the data "1" before initiating the WRITE operation.

tCDS
CS VERIFY

SK 1 2 3 4 5 6 7 8 9 10 25

DI 1 0 1 A5 A4 A3 A2 A1 A0 D15 D0
tSV tHZ1
Hi-Z busy
DO ready
Hi-Z
tPR

Figure 7 WRITE Timing (S-93C46A)

tCDS
CS VERIFY

SK 1 2 3 4 5 6 7 8 9 10 11 12 27

DI 1 0 1 X A6 A5 A4 A3 A2 A1 A0 D15 D0
tSV tHZ1
Hi-Z busy
DO ready
Hi-Z
tPR

Figure 8 WRITE Timing (S-93C56A)

tCDS
CS VERIFY

SK 1 2 3 4 5 6 7 8 9 10 11 12 27

DI 1 0 1 A7 A6 A5 A4 A3 A2 A1 A0 D15 D0
tSV tHZ1
Hi-Z busy
DO ready
Hi-Z
tPR

Figure 9 WRITE Timing (S-93C66A)

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 CMOS SERIAL E2PROM
Rev. 2.3_00 S-93C46A/56A/66A

2.2 ERASE
This command erases 16-bit data in a specified address.
After changing CS to high, input a start-bit, op-code (ERASE), and address. It is not necessary to input data. Changing CS
to low will start the ERASE operation, which changes every bit of the 16-bit data to "1."

tCDS
CS VERIFY

SK 1 2 3 4 5 6 7 8 9

DI 1 1 1 A5 A4 A3 A2 A1 A0
tSV tHZ1
Hi-Z busy
DO ready
Hi-Z
tPR

Figure 10 ERASE Timing (S-93C46A)

tCDS
CS VERIFY

SK 1 2 3 4 5 6 7 8 9 10 11

DI 1 1 1 X A6 A5 A4 A3 A2 A1 A0
tSV tHZ1
Hi-Z busy
DO ready
Hi-Z
tPR

Figure 11 ERASE Timing (S-93C56A)

tCDS
CS VERIFY

SK 1 2 3 4 5 6 7 8 9 10 11

DI 1 1 1 A7 A6 A5 A4 A3 A2 A1 A0
tSV tHZ1
Hi-Z busy
DO ready
Hi-Z
tPR

Figure 12 ERASE Timing (S-93C66A)

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CMOS SERIAL E2PROM
S-93C46A/56A/66A Rev. 2.3_00

2.3 WRAL
This instruction writes the same 16-bit data into every address.
After changing CS to high, input a start-bit, op-code (WRAL), address (optional), and 16-bit data. If there is a data overflow
of more than 16 bits, only the last 16 bits of the data is considered valid. Changing CS to low will start the WRAL operation.
It is not necessary to make the data "1" before initiating the WRAL operation.

tCDS
CS VERIFY

SK 1 2 3 4 5 6 7 8 9 10 25

DI 1 0 0 0 1 D15 D0
4Xs tSV tHZ1
Hi-Z busy
DO ready
Hi-Z
tPR

Figure 13 WRAL Timing (S-93C46A)

tCDS
CS VERIFY

SK 1 2 3 4 5 6 7 8 9 10 11 12 27

DI 1 0 0 0 1 D15 D0
6Xs tSV tHZ1
Hi-Z busy
DO ready
Hi-Z
tPR

Figure 14 WRAL Timing (S-93C56A)

tCDS
CS VERIFY

SK 1 2 3 4 5 6 7 8 9 10 11 12 27

DI 1 0 0 0 1 D15 D0
6Xs tSV tHZ1
Hi-Z busy
DO ready
Hi-Z
tPR

Figure 15 WRAL Timing (S-93C66A)

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 CMOS SERIAL E2PROM
Rev. 2.3_00 S-93C46A/56A/66A

2.4 ERAL
This instruction erases the data in every address.
After changing CS to high, input a start-bit, op-code (ERAL), and address (optional). It is not necessary to input data.
Changing CS to low will start the ERAL operation, which changes every bit of data to "1."

CS VERIFY
tCDS

SK 1 2 3 4 5 6 7 8 9

DI 1 0 0 1 0
4Xs tSV tHZ1
DO busy ready
Hi-Z
tPR

Figure 16 ERAL Timing (S-93C46A)

CS VERIFY
tCDS

SK 1 2 3 4 5 6 7 8 9 10 11

DI 1 0 0 1 0
6Xs tHZ1
tSV
DO busy ready
Hi-Z
tPR

Figure 17 ERAL Timing (S-93C56A)

CS VERIFY
tCDS

SK 1 2 3 4 5 6 7 8 9 10 11

DI 1 0 0 1 0
6Xs tHZ1
tSV
DO busy ready
Hi-Z
tPR

Figure 18 ERAL Timing (S-93C66A)

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CMOS SERIAL E2PROM
S-93C46A/56A/66A Rev. 2.3_00

3. Write enable (EWEN) and Write disable (EWDS)

The EWEN instruction puts the S-93C46A/56A/66A into write enable mode, which accepts WRITE, ERASE, WRAL, and
ERAL instructions. The EWDS instruction puts the S-93C46A/56A/66A into write disable mode, which refuses WRITE,
ERASE, WRAL, and ERAL instructions.
The S-93C46A/56A/66A powers on in write disable mode, which protects data against unexpected, erroneous write
operations caused by noise and/or CPU malfunctions. It should be kept in write disable mode except when performing write
operations, after power-on and before shut-down.

CS STANDBY

SK 1 2 3 4 5 6 7 8 9

DI 1 0 0
4Xs
11=EWEN
00=EWDS

Figure 19 EWEN/EWDS Timing (S-93C46A)

CS STANDBY

SK 1 2 3 4 5 6 7 8 9 10 11

DI 1 0 0
6Xs
11=EWEN
00=EWDS

Figure 20 EWEN/EWDS Timing (S-93C56A)

CS STANDBY

SK 1 2 3 4 5 6 7 8 9 10 11

DI 1 0 0
6Xs
11=EWEN
00=EWDS

Figure 21 EWEN/EWDS Timing (S-93C66A)

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 CMOS SERIAL E2PROM
Rev. 2.3_00 S-93C46A/56A/66A

„ Receiving a Start-Bit
Both the recognition of a start-bit and the VERIFY procedure occur when CS is “high”. Therefore, only after a write
operation, in order to accept the next command by having CS go high, the DO pin switch from a state of high-impedence to
a state of data output; but if it recognizes a start-bit, the DO pin returns to a state of high-impedence.
When a 3-wire interface is configured by connecting the DI input pin and DO output pin, a period in which the data output from the CPU
and the serial memory collide may be generated, preventing successful input of the start bit.

„ Three-wire Interface (DI-DO direct connection)

Although the normal configuration of a serial interface is a 4-wire interface to CS, SK, DI, and DO, a 3-wire interface is
also a possibility by connecting DI and DO. However, since there is a possibility that the DO output from the serial memory
IC will interfere with the data output from the CPU with a 3-wire interface, install a resistor between DI and DO in order to give
preference to data output from the CPU to DI (See Figure 22).
CPU S-93C46A/56A/66A

SIO DI
DO
R : 10k ∼ 100kΩ

Figure 22

Please refer Application Note “S-29 & S-93C series EEPROMs Tips, Tricks & Traps” for equivalent circuit of each pin.

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CMOS SERIAL E2PROM
S-93C46A/56A/66A Rev. 2.3_00

„ Chracteristics
1. DC Characteristics
1.1 Current consumption (READ) ICC1— 1.2 Current consumption (READ) ICC1—
Ambient temperature Ta Ambient temperature Ta
VCC=5.5 V VCC=3.3 V
fSK=2 MHz fSK=500 KHz
DATA=0101 DATA=0101
0.4 0.4
ICC1 ICC1
(mA) (mA)
0.2 0.2

0 0
-40 0 85 -40 0 85
Ta (°C) Ta (°C)

1.3 Current consumption (READ) ICC1— 1.4 Current consumption (READ) ICC1—
Ambient temperature Ta Power supply voltage VCC
VCC=1.8 V Ta=25 °C
fSK=10 KHz fSK=1 MHz, 500 KHz
DATA=0101 DATA=0101
0.4 0.4
ICC1 ICC1
(mA) 1MHz
(mA) ∼
0.2 0.2
∼
500KHz
0 0
-40 0 85 2 3 4 5 6 7
Ta (°C) VCC (V)

1.5 Current consumption (READ) ICC1— 1.6 Current consumption (READ) ICC1—
Power supply voltage VCC Clock frequency fSK

Ta=25 °C VCC=5.0 V
fSK=100 KHz, 10 KHz Ta=25 °C
DATA=0101
0.4 0.4
ICC1 ICC1
(mA) (mA)
100KHz
0.2 ∼ 0.2
∼
10KHz
0 0
2 3 4 5 6 7 10K 100K 1M 2M
VCC (V) fSK(Hz)

1.7 Current consumption (WRITE) ICC2— 1.8 Current consumption (WRITE) ICC2—
Ambient temperature Ta Ambient temperature Ta

VCC=5.5 V VCC=3.3 V

1.0 1.0
ICC2 ICC2
(mA) (mA)
0.5 0.5

0 0
-40 0 85 -40 0 85
Ta (°C) Ta (°C)

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 CMOS SERIAL E2PROM
Rev. 2.3_00 S-93C46A/56A/66A

1.9 Current consumption (WRITE) ICC2— 1.10 Current consumption (WRITE) ICC2—
Ambient temperature Ta Power supply voltage VCC

VCC=1.8 V Ta=25°C

1.0 1.0
ICC2 ICC2
(mA) (mA)
0.5 0.5

0 0
-40 0 85 2 3 4 5 6 7
Ta (°C) VCC (V)

1.11 Standby current consumption ISB— 1.12 Input leakage current ILI—
Ambient temperature Ta Ambient temperature Ta
VCC=5.5 V VCC=5.5 V
10-6 CS, SK, DI,
TEST=0 V
10-7
ISB 1.0
(A) 10-8
ILI
10-9 (µA)
10-10 0.5
10-11

-40 0 85 0
-40 0 85
Ta (°C)
Ta (°C)

1.13 Input leakage current ILI— 1.14 Output leakage current ILO—
Ambient temperature Ta Ambient temperature Ta

VCC=5.5 V VCC=5.5 V
CS, SK, DI, DO=0 V
TEST=5.5 V
1.0 1.0
ILI ILO
(µA) (µA)
0.5 0.5

0 0
-40 0 85 -40 0 85
Ta (°C) Ta (°C)

1.15 Output leakage current ILO— 1.16 High level output voltage VOH—
Ambient temperature Ta Ambient temperature Ta
VCC=5.5 V VCC=4.5 V
DO=5.5 V IOH=-400µA
4.6
1.0
ILO VOH 4.4
(µA) (V)
0.5
4.2

0
-40 0 85 -40 0 85
Ta (°C) Ta (°C)

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CMOS SERIAL E2PROM
S-93C46A/56A/66A Rev. 2.3_00

1.17 High level output voltage VOH— 1.18 High level output voltage VOH—
Ambient temperature Ta Ambient temperature Ta
VCC=2.7 V VCC=2.5 V
IOH=-100µA IOH=-100µA
2.7 2.5

VOH 2.6 VOH 2.4

(V) (V)

2.5 2.3

-40 0 85 -40 0 85
Ta (°C) Ta (°C)

1.19 High level output voltage VOH— 1.20 Low level output voltage VOL—
Ambient temperature Ta Ambient temperature Ta
VCC=1.8 V VCC=4.5 V
IOH=-10µA IOL=2.1 mA
1.9 0.3

VOH 1.8 VOL 0.2

(V) (V)

1.7 0.1

-40 0 85 -40 0 85
Ta (°C) Ta (°C)

1.21 Low level output voltage VOL— 1.22 High level output current IOH—
Ambient temperature Ta Ambient temperature Ta
VCC=1.8 V VCC=4.5 V
IOL=100µA VOH=2.4 V
0.03
-20.0
VOL 0.02 IOH
(V) (mA)
-10.0
0.01

0
-40 0 85 -40 0 85
Ta (°C) Ta (°C)

1.23 High level output current IOH— 1.24 High level output current IOH—
Ambient temperature Ta Ambient temperature Ta
VCC=2.7 V VCC=2.5 V
VOH=2.0 V VOH=1.8 V

-4 -4
IOH IOH
(mA) (mA)
-2 -2

0 0
-40 0 85 -40 0 85
Ta (°C) Ta (°C)

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 CMOS SERIAL E2PROM
Rev. 2.3_00 S-93C46A/56A/66A

1.25 High level output current IOH— 1.26 Low level output current IOL—
Ambient temperature Ta Ambient temperature Ta
VCC=1.8 V VCC=4.5 V
VOH=1.6 V VOL=0.4 V

-1.0 20
IOH IOL
(mA) (mA)
-0.5 10

0 0
-40 0 85 -40 0 85
Ta (°C) Ta (°C)

1.27 Low level output current IOL— 1.28 Input voltage VIN(VIL,VIH) —
Ambient temperature Ta Power supply voltage VCC

VCC=1.8 V Ta=25°C
VOL=0.1 V CS, SK, DI

1.0 3.0
IOL VINV
(mA) (V)

0.5 1.5

0 0
-40 0 85 1 2 3 4 5 6 7
Ta (°C) VCC (V)

1.29 Input voltage VIN(VIL,VIH) —

Ambient temperature Ta

VCC=5.0 V
CS, SK, DI

3.0
VINV
(V)
2.0

0
-40 0 85
Ta (°C)

Seiko Instruments Inc.

17
CMOS SERIAL E2PROM
S-93C46A/56A/66A Rev. 2.3_00

2. AC Characteristics
2.1 Maximum operating frequency fmax— 2.2 Program time tPR—
Power supply voltage VCC Power supply voltage VCC

Ta=25°C Ta=25°C

2M 4
1M
fmax tPR
(Hz) (ms)
100K
2
10K

1 2 3 4 5 1 2 3 4 5 6 7
VCC (V) VCC (V)

2.3 Program time tPR— 2.4 Program time tPR—

Ambient temperature Ta Ambient temperature Ta

VCC=5.0 V VCC=3.0 V
6 6
tPR tPR
(ms) (ms)
4 4

2 2

-40 0 85 -40 0 85
Ta (°C) Ta (°C)

2.5 Program time tPR— 2.6 Data output delay time tPD—
Ambient temperature Ta Ambient temperature Ta
VCC=1.8 V VCC=4.5 V
6 0.3
tPR tPD
(ms) (µs)
4 0.2

2 0.1

-40 0 85 -40 0 85
Ta (°C) Ta (°C)

2.7 Data output delay time tPD— 2.8 Data output delay time tPD—
Ambient temperature Ta Ambient temperature Ta
VCC=2.7 V VCC=1.8 V
0.6 1.5
tPD tPD
(µs) (µs)
0.4 1.0

0.2 0.5

-40 0 85 -40 0 85
Ta (°C) Ta (°C)

Seiko Instruments Inc.

18
 CMOS SERIAL E2PROM
Rev. 2.3_00 S-93C46A/56A/66A

„ Ordering Information
S-93CxxA yy - zz - w

P code (Distincion for package process)

Taping specification None (for DIP)

TB (IC direction)
Package code DP : DIP
FJ : SOP1
DFJ : SOP2
FT : TSSOP
MFN : MSOP
Product name S-93C46A : 1k bits
S-93C56A : 2k bits
S-93C66A : 4k bits

Product name Package code Taping specification Package/Tape/Reel drawings

DP None DP008-A
S-93C46A FJ
-TB FJ008-D
S-93C56A DFJ
S-93C66A FT -TB FT008-E
MFN -TB FN008-A
Note
1) Package dimensions of SOPs whose package codes are FJ and DFJ are the same in the range of deviation.
2) Please contact an SII local office or a local representative for details.

Seiko Instruments Inc.

19
 9.3(9.6max.)
8 5

1 4

7.62
1.0 1.5

+0.1
0.3 -0.05
2.54 0.5±0.1
0° to 15°

No. DP008-A-P-SD-1.1

TITLE DIP8-A-PKG Dimensions

No. DP008-A-P-SD-1.1
SCALE
UNIT mm

Seiko Instruments Inc.

 5.02±0.2

8 5

1 4
0.20±0.05

1.27 0.4±0.05

No. FJ008-A-P-SD-2.1

TITLE SOP8J-D-PKG Dimensions

No. FJ008-A-P-SD-2.1
SCALE
UNIT mm

Seiko Instruments Inc.

 2.0±0.05 4.0±0.1(10 pitches:40.0±0.2)

ø1.55±0.05 0.3±0.05

ø2.0±0.05 8.0±0.1 2.1±0.1

5°max.

6.7±0.1

1 8

4 5

Feed direction

No. FJ008-D-C-SD-1.1

TITLE SOP8J-D-Carrier Tape

No. FJ008-D-C-SD-1.1
SCALE
UNIT mm

Seiko Instruments Inc.

 60°

2±0.5
Enlarged drawing in the central part 13.5±0.5

2±0.5
ø21±0.8
ø13±0.2

No. FJ008-D-R-SD-1.1

TITLE SOP8J-D-Reel

No. FJ008-D-R-SD-1.1
SCALE QTY. 2,000
UNIT mm

Seiko Instruments Inc.

 +0.3
3.00 -0.2
8 5

1 4
0.17±0.05

0.2±0.1

0.65

No. FT008-A-P-SD-1.1

TITLE TSSOP8-E-PKG Dimensions

No. FT008-A-P-SD-1.1
SCALE
UNIT mm

Seiko Instruments Inc.

 4.0±0.1
2.0±0.05
ø1.55±0.05 0.3±0.05

8.0±0.1 +0.1
ø1.55 -0.05

(4.4)

+0.4
6.6 -0.2

1 8

4 5

Feed direction

No. FT008-E-C-SD-1.0

TITLE TSSOP8-E-Carrier Tape

No. FT008-E-C-SD-1.0
SCALE
UNIT mm

Seiko Instruments Inc.

 13.4±1.0

Enlarged drawing in the central part 17.5±1.0

2±0.5
ø21±0.8
ø13±0.5

No. FT008-E-R-SD-1.0

TITLE TSSOP8-E-Reel

No. FT008-E-R-SD-1.0
SCALE QTY. 3,000
UNIT mm

Seiko Instruments Inc.

 2.95±0.2

8 5

1 4
0.13±0.1

0.2±0.1
0.65±0.1

No. FN008-A-P-SD-1.1

TITLE MSOP8-A-PKG Dimensions

No. FN008-A-P-SD-1.1
SCALE
UNIT mm

Seiko Instruments Inc.

 2.0±0.05
1.35±0.15
4.0±0.1 4.0±0.1
1.55±0.05

1.05±0.05 0.3±0.05

3.1±0.15

4 1

5 8

Feed direction

No. FN008-A-C-SD-1.1

TITLE MSOP8-A-Carrier Tape

No. FN008-A-C-SD-1.1
SCALE
UNIT mm

Seiko Instruments Inc.

 16.5max.

Enlarged drawing in the central part 13.0±0.3

13±0.2

(60°) (60°)

No. FN008-A-R-SD-1.1

TITLE MSOP8-A-Reel

No. FN008-A-R-SD-1.1
SCALE QTY. 3,000
UNIT mm

Seiko Instruments Inc.

• The information described herein is subject to change without notice.
• Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.
• When the products described herein are regulated products subject to the Wassenaar Arrangement or other
agreements, they may not be exported without authorization from the appropriate governmental authority.
• Use of the information described herein for other purposes and/or reproduction or copying without the
express permission of Seiko Instruments Inc. is strictly prohibited.
• The products described herein cannot be used as part of any device or equipment affecting the human
body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus
installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc.
• Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.