Unit-2

4. Physics of Power BJT and Switching Characteristics

A bipolar transistor is a three-layer, two junction npn or pnp semiconductor device. With one
p-region sandwiched by two n-regions, Fig 4.1 (a ), npn transistor is obtained. With two p-
regions sandwiching one n-region, Fig.4.1 (b), pnp transistor is obtained. The term' bipolar
denotes that the current flow in the device is due to the movement of both holes and electrons.
A BJT h as three terminals named collector (e), emitter (E) and base (B). An emitter is indicated
by an arrowhead indicating the direction of emitter current. No arrow is associated with base
or collector. Power transistors of npn type are easy to manufacture and are cheaper also.
Therefore, use of power npn transistors is very wide in high-voltage and high-current
applications. Hereafter, npn transistors would only be considered.

Fig. 4.1 Bipolar junction transistor (a) npn type and pnp type
Steady-state Characteristics
Out of the three possible circuit configurations for a transistor, common-emitter arrangement
is more common in switching applications. So, a common emitter npn circuit for obtaining its
characteristics is considered as shown in Fig.

Fig. 4.2 (a) non transistor circuit characteristics, (b) input charact eristics and (c) output
characteristics.
Fig. 4.3 (a) Output characteristics and load line for npn transistor and (b) electron flow in an npn
transistor.

For load resistor Rc, Fig. 4.2 (a), the collector current Ic is given by

Here α, called forward current gain, is defined as

As IC < IE, value of α varies from 0.95 to 0.99.

As IB is much smaller, β is much more than unity; its value varies from 50 to 300. In another
system of analysis, called h parameters, hFE is used in place of β.

Use of KCL in Fig. 4.2(a ) gives

IE=IC+IB
Dividing both sides of by IC, we get
Transistor as Switch
Transistor operation as a switch means that transistor operates either in the saturation region or
in the cut-off region and nowhere else on the load line. As an ideal switch, the transistor
operates at point A in the saturated state as closed switch with VCE =0 and at point B in the
cut-off state as an open switch with Ic =0, Fig. 4.3(a). In practice, the large base current will
cause the transistor to work in the saturation region at point A' with small saturation voltage
VCES. Here subscript S is used to denote saturated value. Voltage VCES represents on-state
voltage drop of the transistor which is of the order of about 1 V. When the control, or base,
signal is reduced to zero, the transistor is turned off and its operation shifts to B' in the cut-off
region, Fig. 4.3(a) . A small leakage current ICEO flows in the collector circuit when the
transistor is off.

For Fig. 4.2(a ), KVL for the circuit consisting of VB , RB and emitter gives

Also, from Fig. 4.2 (a),

If VCES is the collector-emitter saturation voltage, then collector current lcs is given by

and the corresponding value of minimum base current, that produces saturation, is

If base current is less than IBS, the transistor operates in the active region, i.e. somewhere
between the saturation and cut-off points. If base current is more than IBS, VCES is almost zero
and collector current Equation is given by ICS =VCC/RC. This shows that collector current at
saturation remains substantially constant even if base current is increased.

With base current more than IBS hard drive of transistor is obtained. With hard saturation,
on-state losses of transistor increase. Normally, the practical circuit is designed for hard-drive
of transistor and therefore, base current IB is greater than IBS . The ratio of IB and IBS is defined
as the overdrive factor (ODF).

ODF may be as high as 4 or 5.

The ratio of ICS to IB is called forced current gain βf where

The total power loss in the two junctions of a transistor is

Under saturated state, VBES is greater than VCES, this means BEJ is forward biased. Further
Eq. (2.13) shows that VEB is negative under saturated conditions, therefore, CBJ is also
forward biased. In other words, under saturated conditions, both junctions in a power transistor
are forward biased.

Question:-A bipolar transistor shown in Fig. 4.2 (a) has current gain β =40. The load
resistance RC = 10 Ω, d c supply voltage Vcc = 130 V and input voltage to base circuit,
VB =10 V. For VCES =1.0 V and VBES = 1.5 V, calculate.
(a) the value of RB for operation in the saturated state,
(b) the value of RB for an over drive factor 5,
(c ) forced- current gain and
(d) power loss in the transistor for both parts (a) and (b) .

BJT Switching Characteristics

 When base current is applied, a transistor does not turn on instantly because of the presence
of internal capacitances. Fig .4.5 shows the various switching waveforms of an npn power
transistor with resistive load between collector and emitter Fig. 4.4. When input voltage VB to
base circuit is made -V2 at to junction EB or EBJ is reverse biased, VBE = -V2, the transistor
is off, iB =Ic =0 and VCE =VCC Fig. 4.5. At time t1, input voltage VB is made +V1 and iB rises
to IB1 as shown in Fig. 4.5. After t1, base-emitter voltage VBE begins to rise gradually from

Fig. 4.4 npn transistor with resistive load.

-V2 and collector current ic begins to rise from zero collector- emitter voltage VCE starts falling
from its initial value VCC. After some time delay td , called delay time, the collector current
rises to 0.1 ICS, VCE falls from VCC to 0.9 VCC and VBE reaches VBES =0.7 V. This delay time is
required to charge the base-emitter capacitance to VBES = 0.7 V. Thus, delay time td is defined
as the time during which the collector current rises from zero to 0.1 ICS and collector-emitter
voltage falls from VCC to 0.9 VCC.

Fig. 4.5 Switching waveforms for npn power transistor

 After delay time td , collector current rises from 0.1 ICS to 0.9 ICS and VCE falls from 0.9 VCC
to 0.1 VCC in time tr . This time tr. is known as rise time which depends upon transistor junction
capacitances. Rise time tr is defined as the time during which collector current rises from 0.l
ICS to 0.9 ICS and collector-emitter voltage falls from 0.9 VCC to 0.1 VCC. This shows that total
turn-on time ton =td + tr. Value of ton is of the order of 30 to 300 nano seconds. The transistor
remains in the on, or saturated, state so long as input voltage stays at V1 Fig. 4.5(a). In case
transistor is to be turned off, then input voltage VB and input base current IB are reversed. At
time t2, input voltage VB to base circuit is reversed from V1 to -V2. At the same time, base
current changes from IBl to -IB2 as shown in Fig. 4.5(b). Negative base current IB2 removes
excess carriers from the base. The time ts required to remove these excess carrier is called
storage time and only after ts , base current IB2 begins to decrease towards zero . Transistor
comes out of saturation only after ts. Storage time ts is usually defined as the time during which
collector current falls from ICS to 0.9 ICS and collector-emitter voltage VCE rises from VCES to
0.1VCC, Fig. 4.5 (d) and (e).
After tS collector current begins to fall and collector-emitter voltage starts building up. Time
tf, called fall time, is defined as the time during which collector current drops from 0.9 ICS to
0.1 ICS and collector-emitter voltage rises from 0.1 VCC to 0.9 VCC, Fig. 4.5(d) and (e). Sum of
storage time and fall time gives the transistor turn-off time torr i.e . toff= ts+ tf The various
waveforms during transistor switching as shown in Fig. 4.5. In this figure, tn = conduction
period of transistor, t0 = off period, T = 1/f is the periodic time and f is the switching frequency.

Question
For a power transistor, typical s witching waveforms are shown in Fig. The various parameters
of the transistor circuit are as under: VCC=220 V, VCES = 2V, ICS= 80A, td = 0.4 µS, tr =1µS,
tn= 50µs, ts=3 µS, tf =n 2µs, to =40 µs, f = 5 kHz. Collector to emitter leakage current ic= 2
mA.
Determine average power loss due to collector current during t and t. Find also the peak on n .
instantaneous power loss due to collector current du ring turn-on time.
 Fig 4.6 switching characteristics of BJT

5. Physics of Power MOSFET and Characteristics

A metal-oxide-semiconductor field-effect transistor (MOSFET) is a recent device developed.
by combining the areas of field-effect concept and MOS technology. A power MOSFET has three
terminals called drain (D), source (S) and gate (G) in place of the corresponding three terminals
collector, emitter and base for BJT. The circuit symbol of power MOSFET is as shown in Fig. 5.1(a).
Here arrow indicates the direction of electron flow. A BJT is a current controlled device whereas a
power MOSFET is a voltage-controlled device. As its operation depends upon the flow of majority
carriers only, MOSFET is a unipolar device. The control signal, or base current in BJT is much larger
than the control signal (or gate current) required in a MOSFET. This is because of the fact that' gate
circuit impedance in MOSFET is extremely high, of the order of 109 ohm. This large impedance
permits the MOSFET gate to be driven directly from microelectronic circuits. BJT suffers from
second breakdown voltage whereas MOSFET is free. from this problem. Power MOSFETs are now
finding increasing applications in low-power high frequency converters. Power MOSFETs are of
two types; n-channel enhancement MOSFET and p-channel enhancement MOSFET. Out of these
two types, n-channel enhancement MOSFET is more common because of higher mobility of
electrons.

A simplified structure of n-channel planar MOSFET of low power rating is shown in Fig. 5.1
(b). On p-substrate (or body), two heavily doped n+ regions are diffused as shown. An
insulating layer of silicon dioxide (SiO2) is grown on the surface. Now this insulating layer is
etched in order to embed metallic source and drain terminals. Note that n+ regions make contact
with source and drain terminals as shown. A layer of metal is also deposited on SiO2 layer so as to
form the gate of MOSFET in between source and drain terminals, Fig. 5.1 (b).

When gate circuit is open, junction between n+ region below drain and p-substrate is reverse biased
by input voltage VDD. Therefore, no current flows from drain to source and load. When gate is
made positive with respect to source, an electric field is established as shown in Fig. 5.1 (b).
Eventually, induced negative charges in the p-substrate below SiO2 layer are formed thus causing
the p layer below gate to become an induced n layer. These negative charges, called electrons, form
n-channel between two n+ regions and current can flow'; from drain to source as shown by the arrow.
If VGS made more positive, induced n-channel becomes more deep an therefore more current flows
from D to S. This shows that drain current ID is enhanced by the gradual increase of gate voltage ,
hence the name enhancement MOSFET.
The main disadvantage of n-channel planar MOSFET of Fig. 5.1 (b) is that conducting n-channel in
between drain and source gives large on-state resistance. This leads to high power dissipation in n-
channel. This shows that planar MOSFET construction of Fig. 5.1 (b) is feasible only for low-power
MOSFETs.

Fig. 5.1:- N-channel enhancement power MOSFET (a) circuit symbol and (b ) its basic structure.

The constructional details of high power MOSFET are illustrated in Fig.5.2. In this figure is shown a
planar diffused metal-oxide-semiconductor (DMOS) structure for n-channel which is quite common for
power MOSFETs. On n+ substrate, high resistivity n- layer is epitaxially grown. The thickness of n-
layer determines the voltage blocking capability of the device. On the other side of n+ substrate, a metal
layer is deposited to form the drain terminal. Now p regions are diffused in the epitaxially grown n-
layer. Further, n+ regions are diffused in p regions as shown. As before, SiO2 layer is added, which is
then etched so as to fit metallic source and gate terminals. A power MOSFET actually consists of a
parallel connection of thousands of basic MOSFET cells on the same single chip of silicon.
 Fig. 5.2 Basic structure of an-channel DMOS power MOSFET.

When gate circuit voltage is zero, and VDD is present, n- - p- junctions are reverse biased and
no current flows from drain to source. When gate terminal is made positive with respect to
source, an electric field is established and electrons form n-channel in the p- regions as shown.
So a current from drain to source is established as indicated by arrows. With gate voltage
increased, current ID also increases as expected. Length of n-channel can be controlled and
therefore on-resistance can be made low if short length is used for the channel.

Fig. 5.3 PMOSFET showing Parasitic BJT and diode

An examination of the basic structure of n-channel DMOS power MOSFET (PMOSFET)
reveals that a parasitic npn bipolar junction transistor exists between the source and drain as
shown in Fig. 5.3. The p body acts as the base, n+ layer as the emitter (or source) and n-layer
as the collector (or drain) of this BJT. Since source is connected to both base and emitter of
parasitic BJT, the source short circuit both base and emitter. As a result, potential difference
between base and emitter of the parasitic BJT is zero and therefore BJT is always in the cut-
off state.
Also, vertical travel from source to drain indicates the existence of a parasitic diode as
shown on the right in Fig. 5.3. The parasitic diode, with source acting as anode and drain Load
as cathode may be used in half-bridge or full-bridge rectifiers. The parasitic diode also npn
shows that reverse voltage blocking capability BJT of PMOSFET is almost zero. This in-built
diode is an advantage in inverter circuits. In Fig.5.2, source is negative and drain is positive.
Therefore, electrons flow from source to n+ layer, then through n-channel of p layer and further
through n- and n+ layers to drain. The current must flow opposite to the flow of electrons as
indicated in Fig.5.2. Since the conduction of current is due to the movement of electrons only,
PMOSFET is a majority carrier device. Hence, time delays caused by removal or
recombination of minority carriers are eliminated during the turn-off process of this device.
PMOSFET with a turn-off time of 100 ns are available. Owing to its low turn-off time,
PMOSFET can be operated in a frequency range of 1 to 10 MHz.

2.6.1. PMOSFET Characteristics

The static characteristics of power MOSFET are now described briefly. The basic circuit
diagram for n-channel PMOSFET is shown in Fig. 5.4 where voltage and currents are as
indicated. The source terminal S is taken as common terminal, as usual, between the input and
output of a MOSFET.

Fig. 5.4 N-channel power MOSFET (a) circuit diagram and (6) its typical transfer
characteristic.

(a.) Transfer Characteristics

This characteristic shows the variation of drain current ID as a function of gate-source voltage
VGS. Fig. 5.4(b) shows typical transfer characteristics for n-channel PMOSFET. Threshold
voltage VGST is an important parameter of MOSFET. VGST is the minimum positive voltage
between gate and source to induce n-channel. Thus, for threshold voltage below VGST device
is in the off-state. Magnitude of VGST is of the order of 2 to 3 V.
(b) Output Characteristics
PMOSFET output characteristics, shown in Fig. 5.5(a ), indicate the variation of drain current
ID as a function of drain-source voltage VDS with gate-soure voltage VGS as a parameter. For
low values of VDS. the graph between ID-VDS is almost linear this indicates a constant value of
on resistance RDS =VDS/ID For given VGS. If VDS is increased, output characteristics is
relatively flat, indicating that drain current is nearly constant. A load line intersects the output
characteristics at A and B. Here A indicates fully on and B fully OFF state. PMOSFET operates
as switch either at A or at B just like BJT.

Fig 5.5(a)Output characteristics And (b) Switching waveforms for PMOSFET.

Switching Characteristics:- The switching characteristics of a power MOSFET are
influenced to a large extent by the- internal capacitance of the device and the internal
impedance of the gate drive circuit. At turn-on, there is an initial delay tdn during which input
capacitance charges to gate threshold voltage VGST. Here tdn is called turn-on delay time.
There is further delay tr, called rise time, during which gate voltage rises to VGSP, a voltage
sufficient to drive the MOSFET into on state. During tr, drain current rises from zero to full-
on current ID. Thus, the total turn-on-time is ton =tdn + tr. The turn-on time can be reduced by
using low-impedance gate-drive source.
As MOSFET is a majority carrier device, turn-off process is initiated soon after removal
of gate voltage at time t1. The turn-off delay time, tdf, is the time during which input
capacitance discharges from overdrive gate voltage V1 to VGSP. The fall time, tf' is the time
during which input capacitance discharges from VGSP to threshold voltage. During tf drain
current falls from ID to zero. So when VGS≤VGST, PMOSFET tum-off is complete. Switching
waveforms for a power MOSFET are shown in Fig. 5.5 (b).