Introduction
Basic Definitions
– Program
• Program
– Instruction – Sequence of instructions to solve a task
– Instruction Set
• Instruction
– ISA
– Is a statement with which avail the services of CPU
• Instruction Set
– Set of instruction
• Instruction Set Architecture
– Set of Instructions and auxiliary storage registers
• Make assumptions about how hardware components
behave.
– The set of these assumptions becomes a specification for the logic
design of the Datapath hardware.
CSE2001 Computer Architecture and Organization ; Dr M Rajasekhara Babu, School of C.S.E, Vellore Institute of Technology (VIT)-Vellore-14; 7-Mar-23 9:45 AM Slide. 1
Datapath
Basic Definitions
– Program
• Is a set of instructions and auxiliary registers needed to
– Instruction accomplish the overall changes an instruction makes in the
– Instruction Set programmer visible objects.
– ISA
Datapath
• The design of Datapath involves design at several levels of
– Definition abstraction.
– Levels – At the highest level
• Highest level
• Low level
• it is micro architecture where the basic registers and interconnections of
implementations are laid out.
– At low level of abstraction
• it is the selection of an implementation domain for registers and buses
• These changes could be presented using a notation
is called as Register Transfer Notations (RTN)
CSE2001 Computer Architecture and Organization ; Dr M Rajasekhara Babu, School of C.S.E, Vellore Institute of Technology (VIT)-Vellore-14; 7-Mar-23 9:45 AM Slide. 2
RTN (Register Transfer Notation)
Basic Definitions
– Program • Provides a formal means of describing machine
– Instruction structure and function
– Instruction Set
– ISA • Is at the “just right” level for machine descriptions
Datapath
– Definition
• Does not replace hardware description languages.
– Levels
• Highest level
• There are two types of RTN’s
• Low level – Abstract RTN
• Can be used to describe what a machine does without
describing how the machine does it.
– Concrete RTN
• Can also be used to describe a particular hardware
implementation
CSE2001 Computer Architecture and Organization ; Dr M Rajasekhara Babu, School of C.S.E, Vellore Institute of Technology (VIT)-Vellore-14; 7-Mar-23 9:45 AM Slide. 3
Design Process
Basic Definitions
–
–
Program
Instruction
Informal description
– Instruction Set
– ISA formal RTN description
Datapath
– Definition block diagram arch.
– Levels
• Highest level concrete RTN steps
• Low level
hardware design of blocks
control sequences
control unit and timing
CSE2001 Computer Architecture and Organization ; Dr M Rajasekhara Babu, School of C.S.E, Vellore Institute of Technology (VIT)-Vellore-14; 7-Mar-23 9:45 AM Slide. 4
RTN (Register Transfer Notation)
Basic Definitions
– Program • Abstract RTN
– Instruction – used to describe what a machine does without describing
– Instruction Set
– ISA
how the machine does it.
Datapath – Example: MC6800
– Definition
Instruction add ra, rb, rc (R[a] = R[b] + R[c])
– Levels
• Highest level Abstract RTN
• Low level
add (:=op=12) → R[ra]← R[rb] +R[rc] :
Instruction addi ra, rb, c2 (R[a] = R[b] + c2)
Abstract RTN
addi (:=op=13)
R[ra] R[rb] +c2 〈16..0〉 {2's comp. sign extend} :
CSE2001 Computer Architecture and Organization ; Dr M Rajasekhara Babu, School of C.S.E, Vellore Institute of Technology (VIT)-Vellore-14; 7-Mar-23 9:45 AM Slide. 5
RTN (Register Transfer Notation)
Basic Definitions
– Program • Concrete RTN
– Instruction – used to describe a particular hardware implementation
– Instruction Set
– ISA
Datapath
– Definition
– Levels
• Highest level
• Low level
CSE2001 Computer Architecture and Organization ; Dr M Rajasekhara Babu, School of C.S.E, Vellore Institute of Technology (VIT)-Vellore-14; 7-Mar-23 9:45 AM Slide. 6
1-Bus Micro Architecture
Basic Definitions 31 0
– Program R0
– Instruction PC
R1
Microarchitecture
– Instruction Set 32 32 –bit
– ISA General IR
Datapath Purpose
– Definition Registers
– Levels R31
• Highest level
• Low level MA
A
1-Bus Micro
Architecture MD
CSE2001 Computer Architecture and Organization ; Dr M Rajasekhara Babu, School of C.S.E, Vellore Institute of Technology (VIT)-Vellore-14; 7-Mar-23 9:45 AM Slide. 7
Constraints Imposed by the Microarchitecture
Basic Definitions
– Program • One bus connecting most registers allows many
– Instruction different RTs, but only one at a time
– Instruction Set
– ISA • Memory address must be copied into MA by CPU
Datapath
– Definition
• Memory data written from or read into MD
– Levels
• Highest level
• First ALU operand always in A, result goes to C
• Low level
• Second ALU operand always comes from bus
1-Bus Micro
Architecture • Information only goes into IR and MA from bus
– Constraints
– A decoder (not shown) interprets contents of IR
– MA supplies address to memory, not to CPU bus
CSE2001 Computer Architecture and Organization ; Dr M Rajasekhara Babu, School of C.S.E, Vellore Institute of Technology (VIT)-Vellore-14; 7-Mar-23 9:45 AM Slide. 8
Abstract and Concrete RTN for SRC add Instruction
Basic Definitions
– Program Abstract RTN:
– Instruction (IR ← M[PC]: PC ← PC + 4; instruction_execution);
– Instruction Set instruction_execution := ( • • •
– ISA add (:= op= 12) R[ra] R[rb] + R[rc]:
Datapath
– Definition Concrete RTN:
– Levels
• Highest level Step Concrete RTN
• Low level T0. MA ← PC: C ← PC + 4;
1-Bus Micro T1. MD ← M[MA]; PC ← C;
Architecture
T2. IR ← MD;
– Constraints
T3. A ← R[rb];
– Abstract & Concrete
RTN T4. C ← A + R[rc];
T5. R[ra] ← C;
CSE2001 Computer Architecture and Organization ; Dr M Rajasekhara Babu, School of C.S.E, Vellore Institute of Technology (VIT)-Vellore-14; 7-Mar-23 9:45 AM Slide. 9
Abstract and Concrete RTN for SRC add Instruction
Basic Definitions
– Program Abstract RTN:
– Instruction (IR ← M[PC]: PC ← PC + 4; instruction_execution);
– Instruction Set instruction_execution := ( • • •
– ISA add (:= op= 12) R[ra] R[rb] + R[rc]:
Datapath
– Definition Concrete RTN:
– Levels Step Concrete RTN Control Sequence
• Highest level
T0. MA ← PC: C ← PC + 4; PCout, MAin, Inc4, Cin
• Low level
1-Bus Micro T1. MD ← M[MA]; PC ← C; Read, Cout, PCin, Wait, MDrd
Architecture T2. IR ← MD; MDout, IRin
– Constraints T3. A ← R[rb]; Grb, Rout, Ain
– Abstract & Concrete T4. C ← A + R[rc]; Grc, Rout, ADD, Cin
RTN
T5. R[ra] ← C; Cout, Gra, Rin, End
CSE2001 Computer Architecture and Organization ; Dr M Rajasekhara Babu, School of C.S.E, Vellore Institute of Technology (VIT)-Vellore-14; 7-Mar-23 9:45 AM Slide. 10
1-Bus Vs. 2-bus Microarchitectures
Basic Definitions
– Program A Bus
31 0
(“in bus”) B Bus
– Instruction R0 t bus”)
32 (“o
– Instruction Set 32 general u
32
– ISA purpose
Datapath registers
– Definition R31
– Levels IR
• Highest level
• Low level PC
1-Bus Micro MA
address
data
Architecture
MD
– Constraints
– Abstract & Concrete A
RTN
A B
1-Bus Vs. 2-Bus ALU
C
Microarchitectures
CSE2001 Computer Architecture and Organization ; Dr M Rajasekhara Babu, School of C.S.E, Vellore Institute of Technology (VIT)-Vellore-14; 7-Mar-23 9:45 AM Slide. 11
Summary
• Basic Definitions – Constraints
– Program – Abstract & Concrete RTN
– Instruction • 1-Bus Vs. 2-Bus
– Instruction Set Microarchitectures
– ISA
• Datapath
– Definition
– Levels
• Highest level
• Low level
• 1-Bus Micro Architecture
CSE2001 Computer Architecture and Organization ; Dr M Rajasekhara Babu, School of C.S.E, Vellore Institute of Technology (VIT)-Vellore-14; 7-Mar-23 9:45 AM Slide. 12
Homework
• You are asked to collect a instruction set of any processor and
categorize them based on operation.
( Note: There are 160+ processors are there. So that no two students
should select same processor. )
CSE2001 Computer Architecture and Organization ; Dr M Rajasekhara Babu, School of C.S.E, Vellore Institute of Technology (VIT)-Vellore-14; 7-Mar-23 9:45 AM Slide. 13
References
Text Book
• William Stallings “Computer Organization and architecture” Prentice
Hall, 7th edition, 2006.
Reference Book
• Vincent .P. Heuring, Harry F. Jordan “ Computer System design and
Architecture” Pearson, 2nd Edition, 2003
CSE2001 Computer Architecture and Organization ; Dr M Rajasekhara Babu, School of C.S.E, Vellore Institute of Technology (VIT)-Vellore-14; 7-Mar-23 9:45 AM Slide. 14
Questions ?
CSE2001 Computer Architecture and Organization ; Dr M Rajasekhara Babu, School of C.S.E, Vellore Institute of Technology (VIT)-Vellore-14; 7-Mar-23 9:45 AM Slide. 15
CSE2001 Computer Architecture and Organization ; Dr M Rajasekhara Babu, School of C.S.E, Vellore Institute of Technology (VIT)-Vellore-14; 7-Mar-23 9:45 AM Slide. 16
