Scribd
Upload
31 views9 pages

DLD Lab 5 by Utw

The document discusses implementing and minimizing logic functions with 4 and 8 variables using K-maps, logic gates, Proteus, and Verilog. It provides the minimized forms and circuit diagrams for a 4 variable function ABCD, and writes Verilog descriptions for an 8 variable function using structural and dataflow models.

Uploaded by

urwa tilwusqa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
31 views9 pages

DLD Lab 5 by Utw

The document discusses implementing and minimizing logic functions with 4 and 8 variables using K-maps, logic gates, Proteus, and Verilog. It provides the minimized forms and circuit diagrams for a 4 variable function ABCD, and writes Verilog descriptions for an 8 variable function using structural and dataflow models.

Uploaded by

urwa tilwusqa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 9

NAME:

Urwa_til_wusqa
CLASS:
BCE_2B
REG NO:
FA22_BCE_091
TASK:
DLD LAB 5
SUBMITTED TO:
Dr. Shafia Hussain
LAB #05:
Logic Minimization of Complex Functions using Automated
Tools:
In-Lab Task 1:
Implement the minimized function given below using logic gate IC(s)

F(A,B,C,D) = ∑ (0,1,3,7)
Function in sum of Min-terms form:

A’B’C’D’+A’B’C’D+A’B’CD+A’BCD.

Function in a simplified form using K-map:

Simplified Answer:

= A’B’C’ +A’CD.

Calculated Answer:

= A’B’C’D’+A’B’C’D+A’B’CD+A’BCD.

= A’B’C’ (D’+D) +A’CD (B’+B).

= A’B’C’ (D+D’) +A’CD (B+B’). (By commutative law)


= A’B’C’ +A’CD.

Circuit Diagram of a min-terms form of the Function:


1. When A,B,C,D all are 0:

2. When A,B,C are 0 and D is 1:


3. When A,B are 0 and C,D are 1:

4. When A is 0 and B,C,D are 1:


Number of gates/ICs used: 4 AND gates, 4 NOT gates, 1 OR gate

Circuit Diagram of a simplified Function:


1. When A,B,C are 0:
2, When A is 0 and C,D are 1:

Nu
mber of gates/ICs used: 3 NOT gate, 2 AND gate and 1 OR gate.
OBSERVED
OUTPUTS
Table 5.1: Observation Table for In-Lab Task:
A B C D F F1 F2

0 0 0 0 1 1 1
0 0 0 1 1 1 1
0 0 1 0 0 0 0
0 0 1 1 1 1 1
0 1 0 0 0 0 0
0 1 0 1 0 0 0:
0 1 1 0 0 0 0
0 1 1 1 1 1 1
1 0 0 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 0 0 0
1 0 1 1 0 0 0
1 1 0 0 0 0 0
1 1 0 1 0 0 0
1 1 1 0 0 0 0
1 1 1 1 0 0 0

F1: Output of min-terms form of circuit.

F2: Output of Simplified form of circuit.


In-Lab Task 2:
Using structural mode, write a Verilog description for the 8-variable function ‘F’:
(𝑨, 𝑩, 𝑪, 𝑫, 𝑬, 𝑭, 𝑮, 𝑯) = ∑(0,1,3,7)

Solution:
Function F using K-Map Minimizer:
Verifying using Xilinx:

Post Lab:
Using data flow model, write a Verilog description for the 8-variable function ‘F’ described
in Lab Task 2:

Solution:
CONCLUSION:
Using Proteus, Xilinx, and the K-map minimizer, we minimized 4 and 8 variable
functions. We take 4 variables and first using k map minimizer we reduced the
equations formed by it. Also with using Proteus we made circuits for actual
and minimized equations. The result was same. Then using Xilinx we to check
the digital validation of our equation.

You might also like