SN74AHC1G04-Q1

SCLS540D – AUGUST 2003 – REVISED JANUARY 2024

SN74AHC1G04-Q1 Automotive Single Inverter Gate

1 Features 3 Description
The SN74AHC1G04-Q1 contains one inverter gate.
• Qualified for automotive applications
The device performs the Boolean function Y = A.
• Operating range 2 V to 5.5 V
• ± 8-mA output drive at 5 V Package Information
• Latch-up performance exceeds 250 mA Per JESD PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)

17 SN74AHC1G04- DBV (SOT-23, 5) 2.90 x 2.8 mm 2.9 mm × 1.6 mm

Q1 DCK (SC70, 5) 2 mm × 2.1 mm 2 mm × 1.25 mm
2 Applications
(1) For all available packages, see the orderable addendum at
• Enable or disable a digital signal the end of the data sheet.
• Controlling an indicator LED (2) The package size (length × width) is a nominal value and
• Translation between communication modules and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does
system controllers not include pins.

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.3 Device Functional Modes............................................7
2 Applications..................................................................... 1 8 Application and Implementation.................................... 8
3 Description.......................................................................1 8.1 Application Information............................................... 8
4 Pin Configuration and Functions...................................3 8.2 Typical Application...................................................... 8
5 Specifications.................................................................. 4 8.3 Power Supply Recommendations.............................10
5.1 Absolute Maximum Ratings........................................ 4 8.4 Layout....................................................................... 10
5.2 ESD Ratings............................................................... 4 9 Device and Documentation Support............................12
5.3 Recommended Operating Conditions.........................4 9.1 Documentation Support............................................ 12
5.4 Thermal Information....................................................5 9.2 Receiving Notification of Documentation Updates....12
5.5 Electrical Characteristics.............................................5 9.3 Support Resources................................................... 12
5.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V...........5 9.4 Trademarks............................................................... 12
5.7 Switching Characteristics, VCC = 5 V ± 0.5 V..............5 9.5 Electrostatic Discharge Caution................................12
5.8 Operating Characteristics........................................... 5 9.6 Glossary....................................................................12
6 Parameter Measurement Information............................ 6 10 Revision History.......................................................... 12
7 Detailed Description........................................................7 11 Mechanical, Packaging, and Orderable
7.1 Overview..................................................................... 7 Information.................................................................... 13
7.2 Functional Block Diagram........................................... 7

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4 Pin Configuration and Functions

Figure 4-1. DBV or DCK Package (Top View)

Table 4-1. Pin Functions

PIN
TYPE DESCRIPTION
NO. NAME
1 NC — No Connection
2 A I Input A
3 GND — Ground Pin
4 Y O Output Y
5 VCC — Power Pin

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
VI Input voltage range(2) –0.5 7 V
VO Output voltage range(2) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –20 mA
IOK Output clamp current VO < 0 or VO > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through each VCC or GND ±50 mA
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

5.2 ESD Ratings

VALUE UNIT
Human-Body Model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22-C101, V
±1000
all pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage 2 5.5 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 3 V 2.1 V
VCC = 5.5 V 3.85
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 3 V 0.9 V
VCC = 5.5 V 1.65
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 2 V –50 µA
IOH High-level output current VCC = 3.3 V ± 0.3 V –4
mA
VCC = 5 V ± 0.5 V –8
VCC = 2 V 50 µA
IOL Low-level output current VCC = 3.3 V ± 0.3 V 4
mA
VCC = 5 V ± 0.5 V 8
VCC = 3.3 V ± 0.3 V 100
Δt/Δv Input transition rise or fall rate ns/V
VCC = 5 V ± 0.5 V 20
TA Operating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).

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5.4 Thermal Information

SN74AHC1G04-Q1
THERMAL METRIC(1) DBV DCK UNIT
5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 278 289.2 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
TA= 25°C
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
MIN TYP MAX
2V 1.9 2 1.9
IOH = –50 µA 3V 2.9 3 2.9
VOH 4.5 V 4.4 4.5 4.4 V
IOH = –4 mA 3V 2.58 2.48
IOH = –8 mA 4.5 V 3.94 3.8
2V 0.1 0.1
IOH = 50 µA 3V 0.1 0.1
VOL 4.5 V 0.1 0.1 V
IOL = 4 mA 3V 0.36 0.5
IOL = 8 mA 4.5 V 0.36 0.5
0 V to
II VI = 5.5 V or GND ±0.1 ±1 µA
5.5 V
ICC VI = VCC or GND, IO = 0 5.5 V 1 20 µA
Ci VI = VCC or GND 5V 2 10 10 pF

5.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V

over recommended operating free-air temperature range (unless otherwise noted) (see Load Circuit And Voltage Waveforms)
FROM TO OUTPUT TA = 25°C
PARAMETER MIN MAX UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX
tPLH 7.5 10.6 1 14.5
A Y CL = 50 pF ns
tPHL 7.5 10.6 1 14.5

5.7 Switching Characteristics, VCC = 5 V ± 0.5 V

over recommended operating free-air temperature range (unless otherwise noted) (see Load Circuit And Voltage Waveforms)
FROM TO LOAD TA = 25°C
PARAMETER MIN MAX UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX
tPLH 5.3 7.5 1 10
A Y CL = 50 pF ns
tPHL 5.3 7.5 1 10

5.8 Operating Characteristics

VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 12 pF

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6 Parameter Measurement Information

Figure 6-1. Load Circuit And Voltage Waveforms

A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

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7 Detailed Description
7.1 Overview
The SN74AHC1G04 device contains one inverter gate. The device performs the Boolean function Y = A.
This single gate inverter has Schmitt-Trigger action on its input, allowing for slower rise and fall times and some
noise rejection. This is not a true Schmitt-Trigger, so there is a limit on rise and fall times.
7.2 Functional Block Diagram

Figure 7-1. Logic Diagram (Positive Logic)

7.3 Device Functional Modes

Table 7-1. Function Table
INPUT (1) OUTPUT(2)
A Y
H L
L H

(1) H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

(2) H = Driving High, L = Driving Low, Z = High Impedance State

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

In this application, three 2-input AND gates are combined to produce a 4-input AND gate function as shown in
Typical Application Block Diagram. The fourth gate can be used for another application in the system, or the
inputs can be grounded and the channel left unused.
The SN74AHC1G04-Q1 is used to directly control the RESET pin of a motor controller. The controller requires
four input signals to all be HIGH before being enabled, and should be disabled in the event that any one signal
goes LOW. The 4-input AND gate function combines the four individual reset signals into a single active-low
reset signal.
8.2 Typical Application

Over Current
Power Sup ply
Detection
Motor Con trol ler

OC

PG

ON/OFF RESET

OT
Over
On/Off Switch Temp
Detection

Figure 8-1. Typical Application Block Diagram

8.2.1 Design Requirements

8.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions.
The supply voltage sets the electrical characteristics of the device as described in the Electrical Characteristics
section.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced
by all outputs of the SN74AHC1G04-Q1 plus the maximum static supply current, ICC, listed in the Electrical
Characteristics, and any transient current required for switching. The logic device can only source as much
current that is provided by the positive supply source. Be sure to not exceed the maximum total current through
VCC listed in the Absolute Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74AHC1G04-Q1 plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any
transient current required for switching. The logic device can only sink as much current that can be sunk into
its ground connection. Be sure to not exceed the maximum total current through GND listed in the Absolute
Maximum Ratings.

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The SN74AHC1G04-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting
all of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to
exceed 50 pF.
The SN74AHC1G04-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage
and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state,
the output voltage in the equation is defined as the difference between the measured output voltage and the
supply voltage at the VCC pin.
Total power consumption can be calculated using the information provided in the CMOS Power Consumption
and Cpd Calculation application note.
Thermal increase can be calculated using the information provided in the Thermal Characteristics of Standard
Linear and Logic (SLL) Packages and Devices application note.

CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.

8.2.1.2 Input Considerations

Input signals must cross VIL(max) Vt-(min) to be considered a logic LOW, and VIH(min) Vt+(max) to be considered a
logic HIGH. Do not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The drive current of the controller, leakage current into the SN74AHC1G04-Q1 (as
specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ
resistor value is often used due to these factors.
The SN74AHC1G04-Q1 has CMOS inputs and thus requires fast input transitions to operate correctly, as
defined in the Recommended Operating Conditions table. Slow input transitions can cause oscillations,
additional power consumption, and reduction in device reliability.
The SN74AHC1G04-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description section for additional information regarding the inputs for this device.
8.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.

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Open-drain outputs can be connected together directly to produce a wired-AND configuration or for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
8.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; it will, however, ensure
optimal performance. This can be accomplished by providing short, appropriately sized traces from the
SN74AHC1G04-Q1 to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω, so that the maximum output current
from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load measured in
MΩ; much larger than the minimum calculated previously.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
8.2.3 Application Curves

OC

PG

ON/OFF

OT

RESET

Figure 8-2. Application Timing Diagram

8.3 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Load
Circuit And Voltage Waveforms table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
8.4 Layout
8.4.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases,
functions or parts of functions of digital logic devices are unused (for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used). Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.

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8.4.1.1 Layout Example

GND VCC

Recommend GND flood fill for

improved signal isolation, noise Bypass capacitor
reduction, and thermal dissipation placed close to
0.1 F the device

1A 1 14 VCC
Unused inputs
1B 2 13 4B tied to VCC
1Y 3 12 4A
Unused output
2A 4 11 4Y
left floating
2B 5 10 3B
2Y 6 9 3A
Avoid 90°
corners for GND 7 8 3Y
signal lines

Figure 8-3. Example Layout for the SN74AHC1G04-Q1

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9 Device and Documentation Support

9.1 Documentation Support
9.1.1 Related Documentation
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 9-1. Related Links
PRODUCT TECHNICAL TOOLS & SUPPORT &
PARTS SAMPLE & BUY
FOLDER DOCUMENTS SOFTWARE COMMUNITY
SN74AHC1G04-Q1 Click here Click here Click here Click here Click here

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Revision History
Changes from Revision C (October 2023) to Revision D (January 2024) Page
• Updated RθJA values: DBV = 206 to 278, all values in °C/W............................................................................ 5

Changes from Revision B (July 2023) to Revision C (October 2023) Page

• Added Applications section................................................................................................................................ 1
• Added package size to Package Information table............................................................................................ 1
• Updated RθJA values: DCK = 252 to 289.2, all values in °C/W ........................................................................5
• Added Application and Implementation section..................................................................................................8

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

1A1G04QDBVRG4Q1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 A04S Samples

CAHC1G04QDCKRG4Q1 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (ACS, ACU) Samples

SN74AHC1G04QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 A04S Samples

SN74AHC1G04QDCKRQ1 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 ACS Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

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continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74AHC1G04-Q1 :

• Catalog : SN74AHC1G04

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
1A1G04QDBVRG4Q1 SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
CAHC1G04QDCKRG4Q1 SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3
SN74AHC1G04QDBVRQ1 SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3

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TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
1A1G04QDBVRG4Q1 SOT-23 DBV 5 3000 202.0 201.0 28.0
CAHC1G04QDCKRG4Q1 SC70 DCK 5 3000 200.0 183.0 25.0
SN74AHC1G04QDBVRQ1 SOT-23 DBV 5 3000 202.0 201.0 28.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 (1.1) TYP
0.00
1.45
0.90

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

ALTERNATIVE PACKAGE SINGULATION VIEW

4214839/J 02/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

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 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/J 02/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/J 02/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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 PACKAGE OUTLINE
DCK0005A SCALE 5.600
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

C
2.4
1.8 0.1 C
1.4
B A 1.1 MAX
PIN 1 1.1
INDEX AREA

1 5

2X 0.65 NOTE 4

2.15
1.3 (0.15) 1.3
2 1.85

(0.1)

4
0.33 3
5X
0.15
0.1
0.1 C A B (0.9) TYP
0.0
NOTE 5

0.15
GAGE PLANE 0.22
TYP
0.08

8 0.46
TYP TYP
0 0.26
SEATING PLANE

4214834/D 07/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
5. Lead width does not comply with JEDEC.

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 EXAMPLE BOARD LAYOUT
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)

1
5
5X (0.4)

SYMM
(1.3)
2
2X (0.65)

3 4

(R0.05) TYP (2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214834/D 07/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)
1
5
5X (0.4)

SYMM
(1.3)
2
2X(0.65)

3 4

(R0.05) TYP
(2.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL
SCALE:18X

4214834/D 07/2023

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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