Memory Organization

Contents
• Basic concept and hierarchy
• semiconductor RAM memories and types,
ROM memories and types.
• Cache memories: concept and design issues (
performance, address mapping and
replacement)
• Virtual memory: concept implementation
 Memory
• The memory unit is an essential component in any digital computer
since it is needed for storing programs and data.
• Not all accumulated information is needed by the processor at the
same time.
• So it is more economical to use low cost storage devices as a
backup for storing the information which is not currently used by
the CPU.
• The execution speed of programs is highly dependant on the speed
with which instruction and data can be transferred between the
processor and memory.
• There are 3 basic parameters of memory:--
• Capacity
• Speed
• Cost per bit
 Capacity
• Memory can be viewed as a storage unit
containing m number of locations (addresses),
each of which stores n number of bits..
• Each word is addressed uniquely by log2m
number of bits.
• The total capacity of a memory is expressed as
mXn bit or m word memory.
• Ex. A 16 bit computer that generates 16-bit
address is capable of addressing up to 216=64K
memory locations.
 Speed
• A useful parameter of the memory is its speed of
operation which is the time that elapses between the
initiation of an operation and the completion of that
operation.
• This is measured in terms of two parameter:
access time tA
cycle time tC
Access time is the time taken by the memory to complete
a read operation.
Cycle time is the min time delay required between the
initiations of two successive memory operation.
 Types of Memory
• Memory is the main component of a computer system. It stores
instructions and data in binary form that is used by the central
processing unit. Memories are divided into 2 types such as
1) Primary memory
2) Secondary memory
• Primary memory is the memory that can be directly accessed by
the CPU which constantly interacts with it, retrieves data stored
therein, goes through instructions and execute them as per the
requirement.
• Secondary memory:The maximum capacity of primary memory is
limited. So to handle more data than allowed by primary memory,
secondary memory is used. And it is non-volatile i.e. data is not lost
due to current failure. Magnetic tape, Floppy disk and Hard disk are
some examples of secondary memory.
 Types of Memory
Memory

Primary
Secondary

Magnetic
RAM ROM tape

PROM Magnetic
SRAM Disk
EPROM
DRAM CD ROM
EEPROM
• RAM( Random access memory/ Read write memory):--
The most familiar form of system memory, Random Access Memory
(RAM) derives its name from the fact that any of its memory cells
can be accessed directly if you are aware of the row and column
that intersect at that cell. The columns are referred to as bit lines
while the rows are referred to as word lines. The intersection of a
word line and bit line is the address of the memory cell onto a
silicon wafer.
This is volatile in nature, it means contents stored in it are not
permanent.
Some common types of RAM are as follows
(1) SRAM: Used primarily to create CPU’s speed-sensitive cache,
Static Random Access memory (SRAM) uses multiple
transistors for each memory cell. It does not have a capacitor
in each cell.
Each bit of memory is held by a flip-flop memory which takes
four to six transistors besides some wiring. SRAM is not
required to be refreshed which makes it significantly fast. As
compared to DRAM, SRAM has more parts and therefore it
consumes a lot more space on a chip.
(2) DRAM: Dynamic Random Access Memory needs to be refreshed
consistently and contains memory cells with a paired transistor. In order to
activate the transistor at each bit in the column, DRAM sends a charge
through the appropriate column .
The level of charge is determined by the sense-amplifier while reading. If
the level of charge exceeds fifty percent, it is read as a 1 whereas if the
charge is below fifty percent it is read as a 0. For dynamic memory to work,
Either the CPU or the memory controller recharges all the capacitors before
they are discharged to zero.
To ensure this the memory is read and written back which if referred to as
refresh operation. DRAM is required to be refreshed dynamically all the
time otherwise it will lose the information. This refreshing operation
consumes a lot of time and causes the memory to slow down.
Memory cells have a support infrastructure of other specialized circuits so
that information can be put in and retrieved from them. These circuits
identify each and column, keep track of the refresh sequence, read and
restore the signal from a cell and tell a cell whether it should take a charge
or not)
 ROM
• Read Only Memory (ROM) is an integrated circuit programmed with
data that holds instructions for starting up the computer. Data
stored in ROM is non volatile and is not lost when powered off.
These data cannot be changed or a special operation is needed to
be performed to change it.
ROM chips also comprise of columns and rows but it is different
from RAM in terms of intersection of these. These chips use diodes
instead of transistors to connect the lines if the value is 1 whereas if
the value is 0 the lines are not connected.
A ROM chip cannot be reprogrammed or rewritten therefore when
the chip is created it requires the programming of perfect and
complete information. ROM chips are cost effective and use very
little power.
(1) PROM
Programmable read only memory (PROM) is a
type of ROM. These chips are non volatile and
cannot be purged to store something else once it
has been used. Blank PROM chips can be coded
with the help of a tool known as a programmer.

Similar to ROM, PROM chips also have a grid of

rows and columns but here fuses connect the
intersections.
• EPROM
Erasable Programmable Read Only Memory can be erased with the help of
ultraviolet light and rewritten many times. These chips are configured by the
EPROM programmer, providing the voltage at the specified levels. The floating gate
is linked to the row through the control gate. The cell has a value of 1 till the link
remains established. A process known as Fowler-Nordheim tunneling is performed
to change the value to zero. The tunneling changes the placement of electrons in
the floating gate. An electrical charge of 10 to 13 volts is passed through the bitline
which drains to a ground after entering the floating gate.
The electrical charge excites the electrons of the transistor at the floating gate and
they are pushed through and trapped on the side of the flimsy oxide layer to give a
negative charge. A call sensor monitors the level of the charge that passes through
the threshold of floating gate. Is shows a value of 1 if the flow is more than fifty
percent. On the other hand if the flow is below fifty percent, the value change to
0. Blank EPROM chips have a value of 1 for each cell as the have all of the gates
opened completely.
•
• EEPROM
Electrically Erasable Programmable Read Only
Memory chips are not required to removed to be
erased or rewritten. These chips do not require to
be erased altogether and specific portion of it can
be easily altered. Additional dedicated equipment
are also not required to change the content the
EEPROM chips. These chips are erased and
rewritten with the help of electric charge.
•
 Memory Hierarchy
• The total memory capacity of a computer can
be visualized as being a hierarchy of
components.
• The memory hierarchy system consists of all
storage devices employed in a computer
system.
 Memory Hierarchy

CPU
Register
Cache
RAM

Access time

capacity
Cost per bit

RAM ROM

Flash Memory

Hard disk

CD and DVD

Magnetic tape
 Bootstrap loader
• The bootstrap loader is a program whose
function is to start the computer software
operating when power is turned on.
• When power is turned on the hardware of
computer sets the program counter to the first
address of bootstrap loader.
• The bootstrap program loads a portion of the
operating system from disk to main memory and
control is then transferred to the operating
system, which prepares the computer for general
use.
RAM chips
 RAM
• The block diagram of a RAM chip has been
shown.
• The capacity of memory is 128 words of eight bits
each.
• This require a 7 bit address and an 8 bit
bidirectional data bus which is constructed with
three state buffer gate.
• The read write inputs specify the memory
operation and the two chip select CS control
inputs are for enabling the chip only when it is
selected by the microprocessor.
 RAM
• The unit is in operation only when CS1=1 and CS2 =0.
• If the chip select inputs are not enabled or if they are
enabled but the read write inputs are not enabled the
memory is inhibited and its data bus is in high
impedance state.
• When CS1=1 and CS2=0 the memory can be read or
write mode.
• When WR input is enabled the memory stores a byte
from the data bus into a location specified by the
address input line
• When RD input is enabled the content of selected
bytes are placed into the bus.
ROM chip
 Memory address map
• The designer of a system must calculate the
amount of memory required for the particular
application and assign it to either RAM or ROM.
• The addressing of the memory can be established
by means of a table that specifies the memory
address assigned to each chip.
• The table called a memory address map is a
pictorial representation of assigned address
space for each chip in the system.
 Example 1
• Assume that a computer system needs 512
bytes of RAM and 512 bytes of ROM.
• RAM chip is of 128 X 8
• And ROM chip is of 512 X 8
 Ex 1Calculation of no. of chips.
•
Size=512 bytes

= 512 X 8

• Size of RAM chip=128 X 8

• No. of chips needed= 512 X 8 = 22=4 RAM chip
• 128 X 8
 Example 1

128 X 8 RAM 1

128 X 8 RAM 2

512 X 8 RAM
128 X 8 RAM 3

128 X 8 RAM 4
• The hexadecimal address assigns a range of
hexadecimal equivalent address for each chip

• Line 8 and 9 represent four distinct binary

combination to specify which RAM we chose

• When line 10 is 0, CPU selects a RAM. And

when it’s 1, it selects the ROM
 Memory connection to CPU
• RAM and ROM chips are connected to a CPU through the
data and address buses.
• The low order lines in the address bus select the byte
within the chips and other lines select the particular chip.
• In the previous example each RAM chip receives 7 low
order bits of address bus to select one of 128 possible
bytes.
• The particular RAM chip selected is determined from lines
8 and 9. This is done through a 2 X 4 decoder. Whose
outputs are connected to the CS1 input in each RAM chip.
• The selection between the RAM and ROM is achieved by
line 10.
 Questions?
• How many 128 X 8 RAM chips are needed to
provide a memory capacity of 2048 bytes?
• How many lines of the address bus must be
used to access 2048 bytes of memory? How
many of these lines will be common to all
chips?
• How many lines must be decoded for chip
select? Specify the size of the decoder.
• No. of chips= 2048 X 8 = 2 / 2 =2 =16 RAM chips
11 7 4

128 X 8
• As there are 2048 addresses
• So log2(2048)= 211
• So 11 bits for addressing
• Common lines will be 7 as RAM is of 128 bytes
• 4 lines for chip select.
• Size of decoder 4 X 16.
•
 RAM 10

RAM 16
RAM 11

RAM 13

RAM 14

RAM 15
RAM 12
RAM 1

RAM 9
RAM 7

RAM 8
RAM 5
RAM 3

RAM 4
RAM 2

RAM 6
CS 1
CS1

CS1

CS1

CS1

CS1

CS1

CS1

CS1

CS1

CS1

CS1

CS1
CS1
CS1

CS1
16 out put lines each will be
connected to CS 1of RAM chip
0 1 2 3 4 --------------16
Decoder
4 X 16 7 address lines to access 128
words.

11 10 9 8 7654321
 Cache memory
• Principle of Locality:-
Programs access a small proportion of their address
space at any time
Temporal locality
– Items accessed recently are likely to be accessed again
soon
– e.g., instructions in a loop, induction variables
Spatial locality
– - Items near those accessed recently are likely
to be accessed soon
– E.g., sequential instruction access, array data
 Cache memory
• If the active portion of the program and data
are placed in a fast memory, the average
access time can be reduced, thus reducing the
total execution time of program. Such a fast
memory is referred to as a cache memory.
 The working of cache
• When the cpu needs to access the memory,
the cache is examined. If the word is found in
the cache, it is read from there. If it is not
found in the cache, the main memory is
accessed to read the word. A block of word
containing the one just accessed is then
transferred from main memory to cache..
 Hit Ratio
The performance of cache memory
When the CPU refers to memory and finds the word in the cache its is
said to produce a hit.
If the word is not found in cache it is in main memory and it counts as
miss.

Hit ratio=Total hits/ total CPU references to memory(hit+miss)

Average access time=h*tc+(1-h)*(tc+tm)

H=hit ratio
Tc=cache access time
Tm=memory access time
EX. In a computer assume
Cache access time= 100ns
Main memory access time =1000ns
Hit ratio=0.9

Average access time=h*tc+(1-h)*(tc+tm)

Then avg. access time= (0.9*100)+(1-0.9)*(100+1000)

= (0.9 x 100 ) + (0.1 X 1100)
=200ns
• The transformation of data from main
memory to cache memory is referred to as
mapping process. Three types of mappings
are under consideration:--
(1) associative mapping
(2) direct mapping
(3) Set associative mapping
 Associative Mapping

CPU
Main Memory Cache
32 K X 12 memory
512 X 12

• For three mapping procedure we will use a specific example of a memory

organization shown in fig.
The main memory can store 32K words of 12 bits each. The cache is capable
of storing 512 of these words at any given time. For every word stored in
cache, there is a duplicate copy in a main memory. The CPU communicates
with both memories. It first send a 15 bit address to cache. If there is a hit,
the CPU accepts the 12 bit data from cache. If there is miss, the CPU reads
the word from main memory.
 MEMORY AND CACHE MAPPING - ASSOCIATIVE MAPPLING -
Mapping Function
Specification of correspondence between main memory blocks and cache blocks

Associative mapping
Direct mapping
Set-associative mapping
Associative Mapping
- Any block location in Cache can store any block in memory
-> Most flexible
- Mapping Table is implemented in an associative memory
-> Fast, very Expensive
- Mapping Table
Stores both address and the content of the memory word
address (15 bits)

Argument register

Address Data
01000 3450
CAM 02777 6710
22235 1234

40
 Associative mapping
• The associative memory stores the address and data of
memory word.
• Here the address is of 15 bits and data is of 12 bits.
• A cpu address of 15 bit is placed in argument register and
the associative memory is searched for the matching
address.
• If the address is found the corresponding 12 bit data is read
from the memory.
• If no match occurs, main memory is accessed for the word.
• The address data pair is than transferred to the associative
cache memory.
• If the cache is full then a pair of address of data is replaced
from the memory.
 Direct mapping
• Associated memories are expansive compared to RAM
because of the address logic associated with each cell.
• In direct mapping address is divided in two fields (1)
index (2) tag
• The number of bits in the index field is equal to the no.
of address bits required to access the cache memory.
• In general if there are 2K words in cache memory and n
words in main memory. The n bit memory address is
divided into two fields
• K bits for index and n-k bits for tag.
 MEMORY AND CACHE MAPPING - DIRECT MAPPING -

- Each memory block has only one place to load in Cache

- Mapping Table is made of RAM instead of CAM
- n-bit memory address consists of 2 parts; k bits of Index field and
n-k bits of Tag field
- n-bit addresses are used to access main memory
and k-bit Index is used to access the Cache
Addressing Relationships Tag(6) Index(9)

00 000 32K x 12 000

512 x 12
Main memory Cache memory
Address = 15 bits Address = 9 bits
Data = 12 bits Data = 12 bits
77 777 777
Direct Mapping Cache Organization
Memory
address Memory data
00000 1220 Cache memory
Index
address Tag Data
00777 2340 000 00 1220
01000 3450

01777 4560
02000 5670

777 02 6710
02777 6710
44
 DIRECT MAPPING
Operation

- CPU generates a memory request with (TAG;INDEX)

- Access Cache using INDEX ; (tag; data)
Compare TAG and tag
- If matches -> Hit
Provide Cache[INDEX](data) to CPU
- If not match -> Miss
M[tag;INDEX] <- Cache[INDEX](data)
Cache[INDEX] <- (TAG;M[TAG; INDEX])
CPU <- Cache[INDEX](data)
Direct Mapping with block size of 8 words
Index tag data 6 6 3
000 01 3450 Tag Block Word
Block 0
007 01 6578
010 INDEX
Block 1
017

Block 63 770 02
777 02 6710
45
Direct mapping
Direct mapping
 Direct Mapping
• Each word in cache consist of the data word and
its associated tag. When a new word is first
brought into the cache the tag bits are stored
alongside the data bits.
• The index field is used to access the cache.
• The tag field is compared.
• If the two tag match, there is a hit and desired
data is in cache.
• If there is a miss the required word is read from
main memory, and stored in the cache together
with the new tag replacing the previous value.
 Direct mapping
CPU address= 02777
777 is the index and 02 is
the tag bits.
As the two tag matches
there is a hit

CPU address= 01777

777 index
01 tag
Its a miss.
So a new word together
00 1220 with its tag will be brought
000
into the cache.

777 01 4560
• The disadvantage of direct mapping is that the
hit ratio can drop if two or more words whose
address have the same index but different
tags are accessed repeatedly.
• Ex 01000, 02000, 03000
• This possibility is minimized by the fact that
they will be far apart in the address range.
 Direct mapping
• If the cache uses block size of 8 words. Then
the index is divided into two fields.
• (1) block (2) word
• 512/ 8 =64 blocks 6 bits for block
• 9-6=3 bits for word
•
Tag Block Word
6 6 3
 Question
• A digital computer has a memory unit of 64K X
16 and a cache memory of 1K words. The
cache can use direct mapping with a block size
of four words.
• (a) how many bits are there in the tag, index,
block and word fields of the address format?
• (b) how many block can the cache
accommodate?
 Solution
• Cache size 1K= 210
• So 10 bits are required to address the cache
memory. Index=10bits
• Total memory capacity=64K= 216
• Tag=16-10=6bits
• No. of blocks=1024/4=256=28
• 8 bits for block
• 2 bits for words
 Set-Associative mapping
• This organization shows an improvement over
the direct mapping technique.
• Each data word is store two or more words of
memory under the same index addresses.
• Each data word is stored together with its tag.
• The number of tag-data items in one word of
cache is said to form a set.
 MEMORY AND CACHE MAPPING - SET ASSOCIATIVE MAPPING -

- Each memory block has a set of locations in the Cache to load

Set Associative Mapping Cache with set size of two

Index Tag Data Tag Data
000 01 3450 02 5670

777 02 6710 00 2340

Operation
- CPU generates a memory address(TAG; INDEX)
- Access Cache with INDEX, (Cache word = (tag 0, data 0); (tag 1, data 1))
- Compare TAG and tag 0 and then tag 1
- If tag i = TAG -> Hit, CPU <- data i
- If tag i  TAG -> Miss,
Replace either (tag 0, data 0) or (tag 1, data 1),
Assume (tag 0, data 0) is selected for replacement,
(Why (tag 0, data 0) instead of (tag 1, data 1) ?)
M[tag 0, INDEX] <- Cache[INDEX](data 0)
Cache[INDEX](tag 0, data 0) <- (TAG, M[TAG,INDEX]),
CPU <- Cache[INDEX](data 0)
56
Set associative mapping
 Set associative mapping
• Here each index address refers to two data
words and their associated tags.
• Each tag require 6 bits and each data word is
of 12 bits.
• So the word length is 2(6+12)=36 bits.
• An index address of 9 bits can accommodate
512 words.
• Thus the size of cache memory is 512X36 bits.
 Set associative mapping
• When the cpu generates a memory request,
the index value of the address is used to
access the cache.
• The tag field of the address is then compared
with both tags in the cache to determine if a
match occurs.
• The comparison logic is done by an associative
search of the tags.
 CACHE WRITE
Write Through
When writing into memory
If Hit, both Cache and memory is written in parallel
If Miss, Memory is written
For a read miss, missing block may be
overloaded onto a cache block
Memory is always updated
-> Important when CPU and DMA I/O are both executing
Slow, due to the memory access time
Write-Back (Copy-Back)
When writing into memory
If Hit, only Cache is written
If Miss, missing block is brought to Cache and write into Cache
For a read miss, candidate block must be
written back to the memory
Memory is not up-to-date, i.e., the same item in
Cache and memory may have different value
60
 Questions

• A two way set associative cache memory uses

blocks of four words. The cache can
accommodate a total of 2048 words from
main memory. The main memory size is
128K X 32.
(a) Formulate all the information required to
construct the cache memory.
(b) What is the size of cache memory?
 Solution
• Address generated by CPU= 128 K X 32
• 17 bits for address
• As it is 2-way set associative
• So if it can store 2048 total words then the total addresses will be
1024
• So 10 bits to address the cache. Tag index
• Tag= 17-10=7 7 10
• And the cache will be like

• Tag Data Tag data

7 32 7 32

Total size of cache will be 1024 X2(7 +32)