Department of Electronics and Communication Engineering ACE ENGINEERING COLLEGE
Experiment - 7
8 bit Parallel Load and Serial Out Shift Register using two 4 bit Shift Register
AIM :
Design an 8 bit parallel load and serial out shift register using two 4 bit shift register.
COMPONENTS REQUIRED :
1. IC 74LS95
2. Bread Board and Connecting Wires
3. Digital IC Trainer Kit
THEORY:
Parallel in Serial out shift register
The input to this register is given in parallel i.e. data is given separately to each flip flop and the
output is collected in serial at the output of the end flip flop.
The clock input is directly connected to all the flip flops but the input data is connected individually
to each flip flop through a mux (multiplexer) at input of every flip flop. Here D1, D2, D3 and D4 are the
individual parallel inputs to the shift register. In this register the output is collected in serial.
The output of the previous flip flop and parallel data input are connected to the input of the MUX and
the output of MUX is connected to the next flip flop. A Parallel in Serial out (PISO) shift register converts
parallel data to serial data. Hence they are used in communication lines where a number of data lines are
multiplexed into single serial data line.
Digital Logic Design Lab Manual Page 1
Department of Electronics and Communication Engineering ACE ENGINEERING COLLEGE
PROCEDURE:
1. Place the IC on the Digital IC Trainer kit bread board as shown in the figure without damaging the legs of
IC.
2. Connect Vcc and GND Connections of the IC from the Digital IC Trainer kit
Digital Logic Design Lab Manual Page 2
Department of Electronics and Communication Engineering ACE ENGINEERING COLLEGE
3. Give connections as per the Circuit Diagram on the Digital IC Trainer kit with the inputs and outputs
required
4. Verify the truth table for all combinations of inputs.
5. By connecting the mode pin to logic HIGH it loads the parallel data and it serially gives the data out if the
Mode pin is logic LOW
Circuit Diagram
0
1
0
1
U1
SI
D0 13
D1 Q0
12
D2 Q1
1
D3 Q2
10
Q3
6
0 9
MODE SL
SR D1 D2 D3D4
U1(SR) 8 LED-BIRG LED-BIRG LED-BIRGLED-BIRG
74LS95
1
0
1
0
U2
1
SI
2 D0 13
Q0
3 D1 12
Q1
4 1
D2 Q2
5 10
D3 Q3
6
MODE SL
9
SR D5 D6 D7D8
8 LED-BIRG LED-BIRG LED-BIRGLED-BIRG
74LS95
RESULT:
Implementation of 8 bit parallel load and serial out shift register using two 4 bit shift register is done
and the timing diagram is verified.
Digital Logic Design Lab Manual Page 3
Department of Electronics and Communication Engineering ACE ENGINEERING COLLEGE
Digital Logic Design Lab Manual Page 4
