ADC0844/ADC0848 8-Bit µP Compatible A/D Converters with Multiplexer Options

March 2006

ADC0844/ADC0848
8-Bit µP Compatible A/D Converters with Multiplexer
Options
General Description Features
The ADC0844 and ADC0848 are CMOS 8-bit successive n Easy interface to all microprocessors
approximation A/D converters with versatile analog input n Operates ratiometrically or with 5 VDC
multiplexers. The 4-channel or 8-channel multiplexers can voltage reference
be software configured for single-ended, differential or n No zero or full-scale adjust required
pseudo-differential modes of operation. n 4-channel or 8-channel multiplexer with address logic
The differential mode provides low frequency input common n Internal clock
mode rejection and allows offsetting the analog range of the n 0V to 5V input range with single 5V power supply
converter. In addition, the A/D’s reference can be adjusted n 0.3" standard width 20-pin or 24-pin DIP
enabling the conversion of reduced analog ranges with 8-bit
n 28 Pin Molded Chip Carrier Package
resolution.
The A/Ds are designed to operate from the control bus of a
wide variety of microprocessors. TRI-STATE output latches
Key Specifications
that directly drive the data bus permit the A/Ds to be config- n Resolution 8 Bits
ured as memory locations or I/O devices to the microproces- n Total Unadjusted Error ± 1⁄2 LSB and ± 1 LSB
sor with no interface logic necessary. n Single Supply 5 VDC
n Low Power 15 mW
n Conversion Time 40 µs

Block Diagram

00501601
* ADC0848 shown in DIP Package CH5-CH8 not included on the ADC0844

© 2006 National Semiconductor Corporation DS005016 [Link]

ADC0844/ADC0848
Connection Diagrams
Molded Chip Carrier Package Dual-In-Line Package

00501602
Top View
00501629
Top View
See Ordering Information
Dual-In-Line Package

00501630
Top View

Ordering Information
Temperature Total Unadjusted Error MUX
Package Outline
Range ± 1⁄2 LSB ± 1 LSB Channels
N20A
0˚C to +70˚C ADC0844CCN 4
Molded Dip
N24C
ADC0848BCN ADC0848CCN 8
Molded Dip
J20A
ADC0844BCJ* ADC0844CCJ* 4
Cerdip
V28A
ADC0848BCV ADC0848CCV 8
−40˚C to +85˚C Molded Chip Carrier
V28A
ADC0848BCVX ADC0848CCVX 8 Molded Chip Carrier
in Tape and Reel
* Product/package combination obsolete; shown for reference only

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 ADC0844/ADC0848
Absolute Maximum Ratings (Notes 1, 2) Dual-In-Line Package (Ceramic) 300˚C
If Military/Aerospace specified devices are required, Molded Chip Carrier Package
please contact the National Semiconductor Sales Office/ Vapor Phase (60 seconds) 215˚C
Distributors for availability and specifications.
Infrared (15 seconds) 220˚C
Supply Voltage (VCC) 6.5V
Voltage
Operating Conditions (Notes 1, 2)
Logic Control Inputs −0.3V to +15V
At Other Inputs and Outputs −0.3V to VCC+0.3V Supply Voltage (VCC) 4.5 VDC to 6.0 VDC

Input Current at Any Pin (Note 3) 5 mA Temperature Range TMIN≤TA≤TMAX

Package Input Current (Note 3) 20 mA ADC0844CCN, 0˚C≤TA≤70˚C

ADC0848BCN,
Storage Temperature −65˚C to +150˚C
ADC0848CCN
Package Dissipation at TA=25˚C 875 mW
ADC0844BCJ *, −40˚C≤TA≤85˚C
ESD Susceptibility (Note 4) 800V
ADC0844CCJ *,
Lead Temperature
ADC0848BCV, ADC0848CCV
(Soldering, 10 seconds)
* Product/package combination obsolete; shown for reference only.
Dual-In-Line Package (Plastic) 260˚C

Electrical Characteristics
The following specifications apply for VCC = 5 VDC unless otherwise [Link] limits apply from TMIN to TMAX; all
other limits TA = Tj = 25˚C.
ADC0844CCN
ADC0844BCJ (Note 12)
ADC0848BCN, ADC0848CCN
ADC0844CCJ (Note 12)
ADC0848BCV, ADC0848CCV Limit
Parameter Conditions
Tested Design Tested Design Units
Typ Typ
Limit Limit Limit Limit
(Note 5) (Note 5)
(Note 6) (Note 7) (Note 6) (Note 7)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Maximum Total VREF=5.00 VDC
Unadjusted Error (Note 8)
ADC0844BCN, ADC0848BCN, BCV ± 1⁄2 ± 1⁄2 LSB
ADC0844CCN, ADC0848CCN, CCV ±1 ±1 LSB
ADC0844CCJ (Note 12) ±1 LSB
Minimum Reference Input Resistance 2.4 1.1 2.4 1.2 1.1 kΩ
Maximum Reference Input Resistance 2.4 5.9 2.4 5.4 5.9 kΩ
Maximum Common-Mode Input Voltage (Note 9) VCC+0.05 VCC+0.05 VCC+0.05 V
Minimum Common-Mode Input Voltage (Note 9) GND−0.05 GND−0.05 GND−0.05 V
DC Common-Mode Error Differential Mode ± 1/16 ± 1⁄4 ± 1/16 ± 1⁄4 ± 1⁄4 LSB
Power Supply Sensitivity VCC=5V ± 5% ± 1/16 ± 1⁄8 ± 1/16 ± 1⁄8 ± 1⁄8 LSB
(Note 10)
On Channel=5V, −1 −0.1 −1 µA
Off Channel Leakage Current Off Channel=0V
On Channel=0V, 1 0.1 1 µA
Off Channel=5V
DIGITAL AND DC CHARACTERISTICS
VIN(1), Logical “1” Input Voltage (Min) VCC=5.25V 2.0 2.0 2.0 V
VIN(0), Logical “0” Input Voltage (Max) VCC=4.75V 0.8 0.8 0.8 V
IIN(1), Logical “1” Input Current (Max) VIN=5.0V 0.005 1 0.005 1 µA
IIN(0), Logical “0” Input Current (Max) VIN=0V −0.005 −1 −0.005 −1 µA
VCC=4.75V,
VOUT(1), Logical “1” Output Voltage
IOUT=−360 µA 2.4 2.8 2.4 V
(Min)
IOUT=−10 µA 4.5 4.6 4.5 V
V

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ADC0844/ADC0848
Electrical Characteristics (Continued)
The following specifications apply for VCC = 5 VDC unless otherwise [Link] limits apply from TMIN to TMAX; all
other limits TA = Tj = 25˚C.
ADC0844CCN
ADC0844BCJ (Note 12)
ADC0848BCN, ADC0848CCN
ADC0844CCJ (Note 12)
ADC0848BCV, ADC0848CCV Limit
Parameter Conditions
Tested Design Tested Design Units
Typ Typ
Limit Limit Limit Limit
(Note 5) (Note 5)
(Note 6) (Note 7) (Note 6) (Note 7)
DIGITAL AND DC CHARACTERISTICS
VOUT(0), Logical “0” Output Voltage VCC=4.75V,
0.4 0.34 0.4 V
(Max) IOUT=1.6 mA
VOUT=0V −0.01 −3 −0.01 −0.3 −3 µA
IOUT, TRI-STATE Output Current (Max)
VOUT=5V 0.01 3 0.01 0.3 3 µA
ISOURCE, Output Source Current (Min) VOUT=0V −14 −6.5 −14 −7.5 −6.5 mA
ISINK, Output Sink Current (Min) VOUT=VCC 16 8.0 16 9.0 8.0 mA
ICC, Supply Current (Max) CS =1, VREF Open 1 2.5 1 2.3 2.5 mA

AC Electrical Characteristics
The following specifications apply for VCC = 5VDC, tr = tf = 10 ns unless otherwise specified. Boldface limits apply from TMIN
to TMAX; all other limits TA = Tj = 25˚C.
Tested Design
Typ
Parameter Conditions Limit Limit Units
(Note 5)
(Note 6) (Note 7)
tC, Maximum Conversion Time (See Graph) 30 40 60 µs
tW(WR), Minimum WR Pulse Width (Note 11) 50 150 ns
tACC, Maximum Access Time (Delay from Falling Edge of RD
CL = 100 pF (Note 11) 145 225 ns
to Output Data Valid)
t1H, t0H, TRI-STATE Control (Maximum Delay from Rising CL = 10 pF, RL = 10k
125 200 ns
Edge of RD to Hi-Z State) (Note 11)
tWI, tRI, Maximum Delay from Falling Edge of WR or RD to ns
(Note 11) 200 400
Reset of INTR
tDS, Minimum Data Set-Up Time (Note 11) 50 100 ns
tDH, Minimum Data Hold Time (Note 11) 0 50 ns
CIN, Capacitance of Logic Inputs 5 pF
COUT, Capacitance of Logic Outputs 5 pF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to the ground pins.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V−or VIN > V+) the absolute value of the current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.
Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 5: Typical figures are at 25˚C and represent most likely parametric norm.
Note 6: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 7: Design limits are guaranteed by not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 8: Total unadjusted error includes offset, full-scale, linearity, and multiplexer error.
Note 9: For VIN (−) ≥ VIN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input, which will forward-conduct for analog input
voltages one diode drop below ground or one diode drop greater than VCC supply. Be careful during testing at low VCC levels (4.5V), as high level analog inputs (5V)
can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias
of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an
absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading.
Note 10: Off channel leakage current is measured after the channel selection.
Note 11: The temperature coefficient is 0.3%/˚C.
Note 12: This product/package combination is obsolete. Shown for reference only.

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 ADC0844/ADC0848
Typical Performance Characteristics
Logic Input Threshold Output Current vs.
Voltage vs. Supply Voltage Temperature

00501632
00501631

Power Supply Current vs.

Temperature Linearity Error vs. VREF

00501633 00501634

Conversion Time vs.

Conversion Time vs. VSUPPLY Temperature

00501635 00501636

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ADC0844/ADC0848
Typical Performance Characteristics (Continued)

Unadjusted Offset Error vs.

VREF Voltage

00501637

TRI-STATE Test Circuits and Waveforms

t1H t1H, CL = 10 pF

00501605
00501604
tr = 20 ns

t0H t0H, CL = 10 pF

00501607
tr = 20 ns
00501606

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 ADC0844/ADC0848
Leakage Current Test Circuit

00501608

Timing Diagrams
Programming New Channel Configuration and Starting a Conversion

00501609
Note 13: Read strobe must occur at least 600 ns after the assertion of interrupt to guarantee reset of INTR .
Note 14: MA stands for MUX address.
Using the Previously Selected Channel Configuration and Starting a Conversion

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ADC0844/ADC0848
Timing Diagrams (Continued)

00501610

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 ADC0848 Functional Block Diagram

9
00501611

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ADC0844/ADC0848
ADC0844/ADC0848
Functional Description The actual voltage converted is always the difference be-
tween an assigned “+” input terminal and a “−” input terminal.
The ADC0844 and ADC0848 contain a 4-channel and The polarity of each input terminal of the pair being con-
8-channel analog input multiplexer (MUX) respectively. Each verted indicates which line the converter expects to be the
MUX can be configured into one of three modes of operation most positive. If the assigned “+” input is less than the “−”
differential, pseudo-differential, and single ended. These input the converter responds with an all zeros output code.
modes are discussed in the Applications Information Sec-
A unique input multiplexing scheme has been utilized to
tion. The specific mode is selected by loading the MUX
provide multiple analog channels. The input channels can be
address latch with the proper address (see Table 1 and
software configured into three modes: differential, single
Table 2). Inputs to the MUX address latch (MA0-MA4) are
ended, or pseudo-differential. Figure 1 shows the three
common with data bus lines (DB0-DB4) and are enabled
modes using the 4-channel MUX ADC0844. The eight inputs
when the RD line is high. A conversion is initiated via the CS
of the ADC0848 can also be configured in any of the three
and WR lines. If the data from a previous conversion is not
modes. In the differential mode, the ADC0844 channel inputs
read, the INTR line will be low. The falling edge of WR will
are grouped in pairs, CH1 with CH2 and CH3 with CH4. The
reset the INTR line high and ready the A/D for a conversion
polarity assignment of each channel in the pair is inter-
cycle. The rising edge of WR, with RD high, strobes the data
changeable. The single-ended mode has CH1–CH4 as-
on the MA0/DB0-MA4/DB4 inputs into the MUX address
signed as the positive input with the negative input being the
latch to select a new input configuration and start a conver-
analog ground (AGND) of the device. Finally, in the pseudo-
sion. If the RD line is held low during the entire low period of
differential mode CH1–CH3 are positive inputs referenced to
WR the previous MUX configuration is retained, and the data
CH4 which is now a pseudo-ground. This pseudo-ground
of the previous conversion is the output on lines DB0-DB7.
input can be set to any potential within the input common-
After the conversion cycle (tC ≤ 40 µs), which is set by the
mode range of the converter. The analog signal conditioning
internal clock frequency, the digital data is transferred to the
required in transducer-based data acquisition systems is
output latch and the INTR is asserted low. Taking CS and RD
significantly simplified with this type of input flexibility. One
low resets INTR output high and outputs the conversion
converter package can now handle ground referenced in-
result on the data lines (DB0-DB7).
puts and true differential inputs as well as signals with some
arbitrary reference voltage.
Applications Information The analog input voltages for each channel can range from
50 mV below ground to 50 mV above VCC (typically 5V)
1.0 MULTIPLEXER CONFIGURATION
without degrading conversion accuracy.
The design of these converters utilizes a sampled-data com-
parator structure which allows a differential analog input to
be converted by a successive approximation routine.

TABLE 1. ADC0844 MUX ADDRESSING

MUX Address Channel#
CS WR RD MUX Mode
MA3 MA2 MA1 MA0 CH1 CH2 CH3 CH4 AGND
X L L L L H + −
X L L H L L H − +
Differential
X L H L L H + −
X L H H L H − +
L H L L L H + −
L H L H L L H + −
Single-Ended
L H H L L H + −
L H H H L H + −
H H L L L H + −
Pseudo-
H H L H L L H + −
Differential
H H H L L H + −
X X X X L L L Previous Channel Configuration
X = don’t care

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 ADC0844/ADC0848
Applications Information (Continued)

4 Single-Ended

00501612

2 Differential

00501613

3 Pseudo-Differential

00501614

Combined

00501615

FIGURE 1. Analog Input Multiplexer Options

2.0 REFERENCE CONSIDERATIONS In a ratiometric system (Figure 2a), the analog input voltage
The voltage applied to the reference input of these convert- is proportional to the voltage used for the A/D reference. This
ers defines the voltage span of the analog input (the differ- voltage is typically the system power supply, so the VREF pin
ence between VIN(MAX) and VIN(MIN)) over which the 256 can be tied to VCC. This technique relaxes the stability
possible output codes apply. The devices can be used in requirements of the system reference as the analog input
either ratiometric applications or in systems requiring abso- and A/D reference move together maintaining the same
lute accuracy. The reference pin must be connected to a output code for a given input condition. For absolute accu-
voltage source capable of driving the minimum reference racy (Figure 2b), where the analog input varies between very
input resistance of 1.1 kΩ. This pin is the top of a resistor specific voltage limits, the reference pin can be biased with a
divider string used for the successive approximation conver- time and temperature stable voltage source. The LM385 and
sion. LM336 reference diodes are good low current devices to use
with these converters.

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ADC0844/ADC0848
Applications Information (Continued) to both selected “+” and “−” inputs for a conversion (60 Hz is
most typical). The time interval between sampling the “+”
The maximum value of the reference is limited to the VCC input and then the “−” inputs is 1⁄2 of a clock period. The
supply voltage. The minimum value, however, can be quite change in the common-mode voltage during this short time
small (see Typical Performance Characteristics) to allow interval can cause conversion errors. For a sinusoidal
direct conversions of transducer outputs providing less than common-mode signal this error is:
a 5V output span. Particular care must be taken with regard
to noise pickup, circuit layout and system error voltage
sources when operating with a reduced span due to the
increased sensitivity of the converter (1 LSB equals VREF/ 00501638

256).
where fCM is the frequency of the common-mode signal,
3.0 THE ANALOG INPUTS Vpeak is its peak voltage value and tC is the conversion time.
For a 60 Hz common-mode signal to generate a 1⁄4 LSB error
3.1 Analog Differential Voltage Inputs and (≈5 mV) with the converter running at 40 µS, its peak value
Common-Mode Rejection would have to be 5.43V. This large a common-mode signal is
The differential input of these converters actually reduces much greater than that generally found in a well designed
the effects of common-mode input noise, a signal common data acquisition system.

TABLE 2. ADC0848 MUX Addressing

MUX Address Channel
CS WR RD MUX Mode
MA4 MA3 MA2 MA1 MA0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 AGND
X L L L L L H + −
X L L L H L H − +
X L L H L L H + −
X L L H H L L H − +
Differential
X L H L L L H + −
X L H L H L H − +
X L H H L L H + −
X L H H H L H − +
L H L L L L H + −
L H L L H L H + −
L H L H L L H + −
L H L H H L L H + −
Single-Ended
L H H L L L H + −
L H H L H L H + −
L H H H L L H + −
L H H H H L H + −
H H L L L L H + −
H H L L H L H + −
H H L H L L H + −
Pseudo-
H H L H H L L H + −
Differential
H H H L L L H + −
H H H L H L H + −
H H H H L L H + −
X X X X X L L L Previous Channel Configuration

3.2 Input Current 3.3 Input Source Resistance

Due to the sampling nature of the analog inputs, short dura- The limitation of the input source resistance due to the DC
tion spikes of current enter the “+” input and exit the “−” input leakage currents of the input multiplexer is important. A
at the clock edges during the actual conversion. These worst-case leakage current of ± 1 µA over temperature will
currents decay rapidly and do not cause errors as the inter- create a 1 mV input error with a 1 kΩ source resistance. An
nal comparator is strobed at the end of a clock period. op amp RC active low pass filter can provide both imped-
Bypass capacitors at the inputs will average these currents ance buffering and noise filtering should a high impedance
and cause an effective DC current to flow through the output signal source be required.
resistance of the analog signal source. Bypass capacitors
should not be used if the source resistance is greater than
1 kΩ.

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 ADC0844/ADC0848
Applications Information (Continued) 4.2 Full-Scale
The full-scale adjustment can be made by applying a differ-
4.0 OPTIONAL ADJUSTMENTS ential input voltage which is 1 1⁄2 LSB down from the desired
analog full-scale voltage range and then adjusting the mag-
4.1 Zero Error nitude of the VREF input for a digital output code changing
The zero of the A/D does not require adjustment. If the from 1111 1110 to 1111 1111.
minimum analog input voltage value, VIN(MIN), is not ground,
a zero offset can be done. The converter can be made to 4.3 Adjusting for an Arbitrary Analog Input Voltage
output 0000 0000 digital code for this minimum input voltage Range
by biasing any VIN (−) input at this VIN(MIN) value. This is If the analog zero voltage of the A/D is shifted away from
useful for either differential or pseudo-differential modes of ground (for example, to accommodate an analog input signal
input channel configuration. which does not go to ground), this new zero reference
The zero error of the A/D converter relates to the location of should be properly adjusted first. A VIN (+) voltage which
the first riser of the transfer function and can be measured by equals this desired zero reference plus 1⁄2 LSB (where the
grounding the V− input and applying a small magnitude LSB is calculated for the desired analog span, 1 LSB =
positive voltage to the V+ input. Zero error is the difference analog span/256) is applied to selected “+” input and the
between actual DC input voltage which is necessary to just zero reference voltage at the corresponding “−” input should
cause an output digital code transition from 0000 0000 to then be adjusted to just obtain the 00HEX to 01HEX code
0000 0001 and the ideal 1⁄2 LSB value (1⁄2 LSB=9.8 mV for transition.
VREF=5.000 VDC).

00501616
a) Ratiometric

00501617
b) Absolute with a Reduced Span

FIGURE 2. Referencing Examples

13 [Link]
ADC0844/ADC0848
Applications Information (Continued) where VMAX=the high end of the analog input range and
VMIN=the low end (the offset zero) of the analog range. (Both
The full-scale adjustment should be made [with the proper are ground referenced.)
VIN (−) voltage applied] by forcing a voltage to the VIN (+) The VREF (or VCC) voltage is then adjusted to provide a code
input which is given by: change from FEHEX to FFHEX. This completes the adjust-
ment procedure.
For an example see the Zero-Shift and Span Adjust circuit
below.

Zero-Shift and Span Adjust (2V≤VIN≤5V)

00501618

Differential Voltage Input 9-Bit A/D

00501619

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 ADC0844/ADC0848
Applications Information (Continued)

Span Adjust (0V≤VIN≤3V)

00501620

Protecting the Input

00501621
Diodes are 1N914

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ADC0844/ADC0848
Applications Information (Continued)

High Accuracy Comparators

00501622
DO = all 1s if VIN(+) > VIN(−)
DO = all 0s if VIN(+) < VIN(−)

Operating with Automotive Ratiometric Transducers

00501623
* VIN(−)=0.15 VCC
15% of VCC≤VXDR≤85% of VCC

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 ADC0844/ADC0848
Applications Information (Continued)

A Stand Alone Circuit

00501625
Note: DUT pin numbers in parentheses are for ADC0844, others are for ADC0848.

Start a Conversion without Updating the Channel Configuration

00501626
CS • WR will update the channel configuration and start a conversion.
CS • RD will read the conversion data and start a new conversion without updating the channel configuration.
Waiting for the end of this conversion is not necessary. A CS • WR can immediately follow the CS • RD .

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ADC0844/ADC0848
Applications Information (Continued)

ADC0844 — INS8039 Interface

00501627

SAMPLE PROGRAM FOR ADC0844 — INS8039 INTERFACE

CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS
ORG 0H
0000 04 10 JMP BEGIN ;START PROGRAM AT ADDR 10
ORG 10H ;MAIN PROGRAM
0010 B9 FF BEGIN: MOV R1,#0FFH ;LOAD R1 WITH A UNUSED ADDR
;LOCATION
0012 B8 20 MOV R0,#20H ;A/D DATA ADDRESS
0014 89 FF ORL P1,#0FFH ;SET PORT 1 OUTPUTS HIGH
0016 23 00 MOV A,00H ;LOAD THE ACC WITH A/D MUX DATA
;CH1 AND CH2 DIFFERENTIAL
0018 14 50 CALL CONV ;CALL THE CONVERSION SUBROUTINE
001A 23 02 MOV A,#02H ;LOAD THE ACC WITH A/D MUX DATA
;CH3 AND CH4 DIFFERENTIAL
001C 18 INC R0 ;INCREMENT THE A/D DATA ADDRESS
001D 14 50 CALL CONV ;CALL THE CONVERSION SUBROUTINE

;CONTINUE MAIN PROGRAM

;CONVERSION SUBROUTINE
;ENTRY:ACC — A/D MUX DATA
;EXIT: ACC — CONVERTED DATA

ORG 50H
0050 99 FE CONV: ANL P1,#0FEH ;CHIP SELECT THE A/D
0052 91 MOVX @ R1,A ;LOAD A/D MUX & START CONVERSION

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 ADC0844/ADC0848
Applications Information (Continued)

SAMPLE PROGRAM FOR ADC0844 — INS8039 INTERFACE

CONVERTING TWO RATIOMETRIC, DIFFERENTIAL SIGNALS (Continued)
0053 09 LOOP: IN A,P1 ;INPUT INTR STATE
0054 32 53 JB1 LOOP ;IF INTR = 1 GOTO LOOP
0056 81 MOVX A,@R1 ;IF INTR = 0 INPUT A/D DATA
0057 89 01 ORL P1,&01H ;CLEAR THE A/D CHIP SELECT
0059 A0 MOV @ R0,A ;STORE THE A/D DATA
005A 83 RET ;RETURN TO MAIN PROGRAM
I/O Interface to NSC800

00501628

SAMPLE PROGRAM FOR ADC0848 — NSC800 INTERFACE

0008 NCONV EQU 16
000F DEL EQU 15 ;DELAY 50 µsec CONVERSION
001F CS EQU 1FH ;THE BOARD ADDRESS
3C00 ADDTA EQU 003CH ;START OF RAM FOR A/D
;DATA
0000' 08 09 0A 0B MUXDTA: DB 08H,09H,0AH,0BH ;MUX DATA
0004' 0C 0D 0E 0F DB 0CH,0DH,0EH,0FH
0008' 0E 1F START: LD C,CS
000A' 06 16 LD B,NCONV
000C' 21 0000' LD HL,MUXDTA
000F' 11 003C LD DE,ADDTA
0012' ED A3 STCONV: OUTI ;LOAD A/D’S MUX DATA
;AND START A CONVERSION
0014' EB EX DE,HL ;HL=RAM ADDRESS FOR THE
;A/D DATA
0015' 3E 0F LD A,DEL
0017' 3D WAIT: DEC A ;WAIT 50 µsec FOR THE
0018' C2 0013' JP NZ,WAIT ;CONVERSION TO FINISH
001B' ED A2 INI ;STORE THE A/D’S DATA
;CONVERTED ALL INPUTS?
001D' EB EX DE,HL
001E' C2 000E' JP NZ,STCONV ;IF NOT GOTO STCONV

END
Note 15: This routine sequentially programs the MUX data latch in the signal-ended mode. For CH1-CH8 a conversion is started, then a 50 µs wait for the A/D to
complete a conversion and the data is stored at address ADDTA for CH1, ADDTA + 1 for CH2, etc.

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ADC0844/ADC0848
Physical Dimensions inches (millimeters) unless otherwise noted

Ceramic Dual-In-Line Package (J) (product obsolete in this package)

NS Package Number J20A

Molded Dual-In-Line Package (N)

NS Package Number N20A

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 ADC0844/ADC0848
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N)

NS Package Number N24C

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ADC0844/ADC0848 8-Bit µP Compatible A/D Converters with Multiplexer Options
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Chip Carrier Package (V)

NS Package Number V28A

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at [Link].

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support
which, (a) are intended for surgical implant into the body, or device or system whose failure to perform can be reasonably
(b) support or sustain life, and whose failure to perform when expected to cause the failure of the life support device or
properly used in accordance with instructions for use system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain
no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
Leadfree products are RoHS compliant.

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