Outline

❖ Designing a Processor: Step-by-Step

Single Cycle Processor Design ❖ Datapath Components and Clocking

❖ Assembling an Adequate Datapath

CSE 333 ❖ Controlling the Execution of Instructions

Computer Architecture and Assembly Language ❖ The Main Controller and ALU Controller

❖ Drawback of the single-cycle processor design

[Adapted from slides of Dr. M. Mudaw ar, ICS 233, KFUPM]

The Performance Perspective Designing a Processor: Step-by-Step

❖ Recall, performance is determined by: ❖ Analyze instruction set => datapath requirements
 Instruction count I-Count  The meaning of each instruction is given by the register transfers
 Clock cycles per instruction (CPI)  Datapath must include storage elements for ISA registers
 Clock cycle time  Datapath must support each register transfer
CPI Cycle
❖ Processor design will affect ❖ Select datapath components and clocking methodology
 Clock cycles per instruction
❖ Assemble datapath meeting the requirements
 Clock cycle time
❖ Analyze implementation of each instruction
❖ Single cycle datapath and control design:
 Determine the setting of control signals for register transfer
 Advantage: One clock cycle per instruction
 Disadvantage: long cycle time ❖ Assemble the control logic
Review of MIPS Instruction Formats MIPS Subset of Instructions
❖ All instructions are 32-bit wide ❖ Only a subset of the MIPS instructions are considered
❖ Three instruction formats: R-type, I-type, and J-type  ALU instructions (R-type): add, sub, and, or, xor, slt
Op6 Rs5 Rt5 Rd5 sa5 funct6  Immediate instructions (I-type): addi, slti, andi, ori, xori

Op6 Rs5 Rt5 immediate16  Load and Store (I-type): lw, sw

 Branch (I-type): beq, bne
Op6 immediate26
 Jump (J-type): j
 Op6: 6-bit opcode of the instruction
 Rs5, Rt5, Rd5: 5-bit source and destination register numbers ❖ This subset does not include all the integer instructions
 sa5: 5-bit shift amount used by shift instructions
❖ But sufficient to illustrate design of datapath and control
 funct6: 6-bit function field for R-type instructions
 immediate16: 16-bit immediate value or address offset ❖ Concepts used to implement the MIPS subset are used
 immediate26: 26-bit target address of the jump instruction to construct a broad spectrum of computers

Details of the MIPS Subset Register Transfer Level (RTL)

Instruction Meaning Format ❖ RTL is a description of data flow between registers
add rd, rs, rt addition op6 = 0 rs5 rt5 rd5 0 0x20
sub rd, rs, rt subtraction op6 = 0 rs5 rt5 rd5 0 0x22 ❖ RTL gives a meaning to the instructions
and rd, rs, rt bitwise and op6 = 0 rs5 rt5 rd5 0 0x24
or rd, rs, rt bitwise or op6 = 0 rs5 rt5 rd5 0 0x25 ❖ All instructions are fetched from memory at address PC
xor rd, rs, rt exclusive or op6 = 0 rs5 rt5 rd5 0 0x26
slt rd, rs, rt set on less than op6 = 0 rs5 rt5 rd5 0 0x2a Instruction RTL Description
addi rt, rs, im16 add immediate 0x08 rs5 rt5 im16
ADD Reg(Rd) ← Reg(Rs) + Reg(Rt); PC ← PC + 4
slti rt, rs, im16 slt immediate 0x0a rs5 rt5 im16
andi rt, rs, im16 and immediate 0x0c rs5 rt5 im16 SUB Reg(Rd) ← Reg(Rs) – Reg(Rt); PC ← PC + 4
ori rt, rs, im16 or immediate 0x0d rs5 rt5 im16 ORI Reg(Rt) ← Reg(Rs) | zero_ext(Im16); PC ← PC + 4
xori rt, im16 xor immediate 0x0e rs5 rt5 im16 LW Reg(Rt) ← MEM[Reg(Rs) + sign_ext(Im16)]; PC ← PC + 4
lw rt, im16(rs) load word 0x23 rs5 rt5 im16
SW MEM[Reg(Rs) + sign_ext(Im16)] ← Reg(Rt); PC ← PC + 4
sw rt, im16(rs) store word 0x2b rs5 rt5 im16
beq rs, rt, im16 branch if equal 0x04 rs5 rt5 im16 BEQ if (Reg(Rs) == Reg(Rt))
bne rs, rt, im16 branch not equal 0x05 rs5 rt5 im16 PC ← PC + 4 + 4 × sign_extend(Im16)
j im26 jump 0x02 im26 else PC ← PC + 4
 Instructions are Executed in Steps Instruction Execution – cont’d
❖ R-type Fetch instruction: Instruction ← MEM[PC] ❖ LW Fetch instruction: Instruction ← MEM[PC]
Fetch operands: data1 ← Reg(Rs), data2 ← Reg(Rt) Fetch base register: base ← Reg(Rs)
Execute operation: ALU_result ← func(data1, data2) Calculate address: address ← base + sign_extend(imm16)
Write ALU result: Reg(Rd) ← ALU_result Read memory: data ← MEM[address]
Next PC address: PC ← PC + 4 Write register Rt: Reg(Rt) ← data
Next PC address: PC ← PC + 4
❖ I-type Fetch instruction: Instruction ← MEM[PC]
Fetch operands: data1 ← Reg(Rs), data2 ← Extend(imm16) ❖ SW Fetch instruction: Instruction ← MEM[PC]
Execute operation: ALU_result ← op(data1, data2)
Fetch registers: base ← Reg(Rs), data ← Reg(Rt)
Write ALU result: Reg(Rt) ← ALU_result
Calculate address: address ← base + sign_extend(imm16)
Next PC address: PC ← PC + 4
Write memory: MEM[address] ← data
❖ BEQ Fetch instruction: Instruction ← MEM[PC] Next PC address: PC ← PC + 4
Fetch operands: data1 ← Reg(Rs), data2 ← Reg(Rt) concatenation
Equality: zero ← subtract(data1, data2) ❖ Jump Fetch instruction: Instruction ← MEM[PC]
Branch: if (zero) PC ← PC + 4 + 4×sign_ext(imm16) Target PC address: target ← PC[31:28] , Imm26 , ‘00’
else PC ← PC + 4 Jump: PC ← target

Requirements of the Instruction Set Components of the Datapath

❖ Memory ❖ Combinational Elements 32

0 zero
A
 Instruction memory where instructions are stored  ALU, Adder 16
Extend
32 m
u L
32
ALU result
x U overflow
 Data memory where data is stored
32
 Immediate extender 1
ExtOp select ALU control

❖ Registers  Multiplexers
 32 × 32-bit general purpose registers, R0 is always zero ❖ Storage Elements Instruction
32
Data
32
Memory
32 32 32
 Read source register Rs

PC
Address Address
 Instruction memory 32 Data_out
32

Instruction
 Read source register Rt  Data memory Memory
Data_in

 Write destination register Rt or Rd  PC register MemRead MemWrite

Registers
❖ Program counter PC register and Adder to increment PC
5 32
 Register file 5
RA BusA
32
RB
❖ Sign and Zero extender for immediate constant
BusB
❖ Clocking methodology 5
RW
BusW

❖ ALU for executing instructions  Timing of reads and writes Clock

RegWrite 32
 MIPS Register File RW RA RB
Instruction and Data Memories
❖ Register File consists of 32 × 32-bit registers ❖ Instruction memory needs only provide read access
 BusA and BusB: 32-bit output busses for reading 2 registers  Because datapath does not write instructions
 BusW: 32-bit input bus for writing a register when RegWrite is 1  Behaves as combinational logic for read 32
Address Instruction
32

 Two registers read and one written in a cycle  Address selects Instruction after access time Instruction
Register Memory
❖ Registers are selected by: 5
RA File BusA 32
❖ Data Memory is used for load and store
5
 RA selects register to be read on BusA 5
RB
32  MemRead: enables output on Data_out Data
BusB
RW
 RB selects register to be read on BusB ▪ Address selects the word to put on Data_out Memory
32 32
Clock
 RW selects the register to be written BusW  MemWrite: enables writing of Data_in 32
Address Data_out

Data_in
▪ Address selects the memory word to be written
❖ Clock input RegWrite
32
Clock
▪ The Clock synchronizes the write operation
 The clock input is used ONLY during write operation
 During read, register file behaves as a combinational logic block ❖ Separate instruction and data memories MemRead MemWrite

▪ RA or RB valid => BusA or BusB valid after register file’s access time  Later, we will replace them with caches

Datapath for R-type Instructions Datapath for I-type ALU Instructions

Op6 Rs5 Rt5 Rd5 sa5 funct6 Op6 Rs5 Rt5 immediate16

RegWrite
RegWrite
ALUCtrl
+1
ALUCtrl
30
+1
30 Instruction Registers 32
Instruction Registers 32
Rs 5
Rs 5 30 Memory RA BusA
Memory 32 A

00
30 RA BusA 32
32 A Instruction
L
00

32 5
Instruction 32
32
Rt 5
RB
L 32 RB
BusB U
U Address 32

PC
Address BusB 32 Rt 5
PC

Rd 5 RW ALU result
RW ALU result BusW
BusW
ExtOp

RA & RB come from the RW now comes from Imm16

Extender
instruction’s Rs & Rt fields Rt, instead of Rd
ALU inputs come from BusA & BusB Second ALU input comes
from the extended immediate
RW comes from the Rd field ALU result is connected to BusW ❖ Control signals
RB and BusB are not used
 ALUCtrl is derived from the Op field
❖ Control signals
 RegWrite is used to enable the writing of the ALU result
 ALUCtrl is derived from the funct field because Op = 0 for R-type
 RegWrite is used to enable the writing of the ALU result  ExtOp is used to control the extension of the 16-bit immediate
Combining R-type & I-type Datapaths Adding Data Memory to Datapath
RegWrite ❖ A data memory is added for load and store instructions
ALUCtrl ExtOp
30
+1 Another mux
ALUCtrl MemRead MemWrite
Instruction Registers 32 Imm16 32 ALUSrc
Memory Rs 5 selects 2nd ALU Extender ALU result
MemtoReg
30 32 RA BusA A input as either +1
00

32
Instruction Rt 5
RB
32 L 30 32
32
Address
BusB 0
m U source register Instruction Rs 5
RA BusA Data
PC

0 Memory
m u Rt data on BusB 30 32 Registers A 32
Memory 0

00
u RW BusW x m 32
Instruction
Rd x 1 or the extended 32
Rt 5
RB
L Address
32
u
x
1 32 BusB 0 U
ExtOp ALUSrc Address Data_out
immediate 1

PC
5 0 m
m u
A mux selects RW RegDst ALU result u RW BusW x Data_in

as either Rt or Rd Extender Rd x 1
32
Imm16 1
5
RegDs
RegWrite
❖ Control signals t

ALU calculates data memory address A 3rd mux selects data on BusW as
 ALUCtrl is derived from either the Op or the funct field
either ALU result or memory data_out
 RegWrite enables the writing of the ALU result ❖ Additional Control signals
 MemRead for load instructions BusB is connected to Data_in of Data
 ExtOp controls the extension of the 16-bit immediate
Memory for store instructions
 RegDst selects the register destination as either Rt or Rd  MemWrite for store instructions
 ALUSrc selects the 2nd ALU source as BusB or extended immediate  MemtoReg selects data on BusW as ALU result or Memory Data_out

Controlling the Execution of Load Adding Jump and Branch to Datapath

30 Jump or Branch Target Address
ExtOp = ‘sign’ to sign-extend
Immmediate16 to 32 bits ExtOp ALUCtrl
MemRead MemWrite
30 30
MemRea
MemWrite
= sign = ADD
=1 =0 Next d
ALUSrc MemtoReg Imm26
Imm16 32 PC MemtoReg
=1
Extender ALU result =1 ALU result

+1
PCSrc +1 Imm16
zero
30 32 Instruction Rs 5
Data
Instruction Rs 5
Data RA BusA
RA BusA Memory Memory 0
30 Memory Memory 0 30 32 Registers A

00
32 A Ext m 32
Registers 32 Instruction
00

m 32 0 Rt 5 L Address u
Instruction
32
Rt 5
RB
L Address
32
u
x m RB BusB 0 U 32 x
BusB 0 U u Address Data_out 1

PC
0 m
Address Data_out 1
PC

0 m x m u
m u 1 u x Data_in
u x Data_in RW BusW
RW BusW Rd x 1
Rd x 1 1
1 32
5
5
RegDst RegWrite RegDst RegWrite
RegDst = ‘0’ selects Rt =0 =1 ALUSrc ALUCtrl J, Beq, Bne
as destination register MemRead = ‘1’ to read data memory
❖ Additional Control Signals Next PC computes
ALUSrc = ‘1’ selects extended immediate as MemtoReg = ‘1’ places the data read jump or branch target
second ALU input from memory on BusW
 J, Beq, Bne for jump and branch instructions
instruction address
 Zero condition of the ALU is examined
ALUCtrl = ‘ADD’ to calculate data memory RegWrite = ‘1’ to write the memory For Branch, ALU does
address as Reg(Rs) + sign-extend(Imm16) data on BusW to register Rt  PCSrc = 1 for Jump & taken Branch a subtraction

LW Reg(Rt) ←MEM[Reg(Rs) + sign_ext(Im16)]; : read from MEM

 Single-Cycle Datapath + Control Drawbacks of Single Cycle Processor
30 Jump or Branch Target Address
❖ Long cycle time
30 30

Next J, Beq, Bne  All instructions take as much time as the slowest
Imm26
PC ALU result
PCSrc +1 Imm16
zero ALU Instruction Fetch Reg Read ALU Reg Write
Instruction Rs 5
BusA Data
RA
30
Memory
32 A Memory 0 longest delay
Registers
00

Ext m 32
Instruction
0 Rt 5
RB
L Address
32
u
x Load Instruction Fetch Reg Read ALU Memory Read Reg Write
m 0
u Address
BusB U Data_out 1
PC

0 m
x m u
1 u x Data_in
RW BusW
Rd x 1
1 Store Instruction Fetch Reg Read ALU Memory Write
5

RegDst RegWrite ExtOp ALUSrc ALUCtrl

Branch Instruction Fetch Reg Read ALU
func
ALU
Op
Ctrl MemRead
Jump Instruction Fetch Decode
ALUOp MemWrite MemtoReg

Main ❖ Alternative Solution: Multicycle implementation

Control
 Break down instruction execution into multiple cycles

Multicycle Implementation Summary

❖ Break instruction execution into five steps ❖ 5 steps to design a processor
 Instruction fetch  Analyze instruction set => datapath requirements
 Select datapath components & establish clocking methodology
 Instruction decode and register read
 Assemble datapath meeting the requirements
 Execution, memory address calculation, or branch completion
 Analyze implementation of each instruction to determine control signals
 Memory access or ALU instruction completion  Assemble the control logic
 Load instruction completion
❖ MIPS makes Control easier
❖ One step = One clock cycle (clock cycle is reduced)  Instructions are of same size

 First 2 steps are the same for all instructions  Source registers always in same place
 Immediates are of same size and same location
Instruction # cycles Instruction # cycles
 Operations are always on registers/immediates
ALU & Store 4 Branch 3
Load 5 Jump 2 ❖ Single cycle datapath => CPI=1, but Long Clock Cycle