Dynamic Voltage (IR) Drop Analysis and Design Closure: Issues and Challenges

Abstract—Dynamic voltage (IR) drop, unlike the static and signoff (timing, IR Drop, EM, reliability etc.) com-
voltage drop depends on the switching activity of the de- sign, prehending Dynamic IR drop effects realistically. On one hand,
and hence it is vector dependent. In this paper we have the factors that introduce pessimism in Dynamic voltage drop
highlighted the pitfalls in the common design closure analysis have to be removed, while on the other we must
methodology that addresses static IR drop well, but of- ten ensure the methodology ensures robust cov- erage of various
fails to bound the impact of dynamic voltage drops robustly. silicon conditions and design operating scenarios. We then
Factors that can affect the accuracy of dynamic IR analysis and discuss power distribution and power grid planning
the related metrics for design closure are discussed. A methodology, and highlight the various as- pects that need to
structured approach to planning the power distribution and be taken care of, from the early stages of design
grid for power managed designs is then presented, with an implementation. We also demonstrate some of the systematic
emphasis to cover realistic application scenarios, and how it power grid enhancements like robust au- tomated switch
can be done early in the design cy- cle. Care-about and placement and switched supply resistance minimization
solutions to avoid and fix the Dynamic voltage drop issues are through DRC-aware power metal fill. All the discussions and
also presented. Results are from in- dustrial designs in 45nm results are based on production im- plementations of low
process are presented related to the said topics. power application processors for mo- bile and hand-held
Keywords—Dynamic voltage Drop, DvD, Dynamic IR, Peak devices. The designs include high fre- quency CPU cores,
power, Power switch, VCD, Power gate, SDF. multimedia subsystems (like imaging and video). The numbers
quoted are from the analysis and/or simulation.
I. Introduction The structure of the paper is as follows. In section II , the
Designing an optimal power grid which is robust across commonly followed Dynamic IR methodology and its pitfalls
multiple operating scenarios of a chip continues to be a ma- are highlighted with design results. In section III the issues
jor challenge.[1][2][3] The problem has magnified with tech- related to analysis accuracy and signoff method- ology are
nology shrinking allowing more performance to be packed in discussed. Section IV then elaborates how we went about
a smaller area, from one node to another [4]. The power planning the power distribution and the tech- niques used to
distribution on a chip needs to ensure circuit robustness ensure silicon robustness in the tolerant to Dynamic IR drop.
catering to not only to the average power / current re-
II. Common Design Closure Methodology and Its Pitfalls
quirements, but also needs to ensure timing or reliability is
not affected due to Dynamic IR drop, caused by localized A. Overview Of Static Vs Dynamic IR Drop
power demand and switching patterns. [5] Static IR drop is average voltage drop for the de-
Further, amongst today’s devices power management sign.[12][13], whereas Dynamic IR drop depends on the
techniques like power gating and switch power supplies are switching activity of the logic[11], hence is vector depen-
the norms [6][7][8]. In the case of switched power sup- plies, dent. Dynamic IR drop depends on the switching time of the
typically, power switch cells are uniformly distributed across logic, and is less dependent on the a clock period. This nature
the standard cell logic (logic gates) area of the floor- plan. is illustrated in Fig 1. The Average current depends totally on
There may be further sub-divisions in the switched power grid the time period, where as the dynamic IR drop depends on
in the form of power domains, depending on the granularity the instantanious current which is higher while the cell is
of power gating [10]. These power switches add an additional switching.
dimension to the power distribution problem as they often Static IR drop was good for signoff analysis in older
limit the response of the power grid to dy- namic power or technology nodes where sufficient natural decoupling ca-
current needs. While the power distribu- tion robustness can pacitance from the power network and non-switching logic
be improved easily by increasing the number of power were available. Where as Dynamic IR drop Evaluates the IR
switches, it has an impact on the off- mode leakage (Iddq) and drop caused when large amounts of circuitry switch si-
hence battery life in handheld applications. So clearly, the multaneously, causing peak current demand[1][14]. This
requirement is also to mini- mize the number of switches used current demand could be highly localized and could be brief
as well as minimize the signal routing resources utilized on within a single clock cycle (a few hundred ps), and
the power grid.
This paper discusses the issues related to design closure
 Fig. 1. Average Current Over A Window Fig. 2. Effect Of Low Switch Density In Notch

could result in an IR drop that causes additional setup or hold-

time violations. Typically, high IR drop impact on clock
networks causes hold-time violations, while IR drop on data
path signal nets causes setup-time violations.

B. Deficiencies Found By Dynamic Analysis On A “Good”

Power Grid
A typical power grid and power switches (count and dis-
tribution) are designed for average power or in other words
they are designed to meet static IR drop targets and not for
Dynamic IR drop. In the initial stage of the design, the grid
robustness is checked only with the Static IR drop result. This
is because of late availability of use case scenar- ios (Voltage
change dump (VCD) files). For the example, the switch and
metal grid densities in the notches region can satisfy the static Fig. 3. Effect Of MET3 Grid On Dyanmic IR drop
IR drop criteria, because the average power density in this
region is not significant.
But when a particular application is run, notch area could
have higher power density because of localized switching in
that area and the switches combined with metal grid
(Switched supply is distributed to cells by lower layers like
MET2 and MET3) may not be enough to sup- port the current
density in the notch area. Because of which there can be very
high dynamic IR drop. Refer to Notch area as shown in Fig. 2,
Here due to less number of switch cells combined with not so
robust power grid is the main cause of high dynamic IR drop.
As described by the figure, Switch Voltage drop and MET3
voltage drop are the dominant factors in the overall voltage
drop. A similar analogy on the power density can be extended
to larger region.
Refer to Fig. 3, With the original MET3 grid, static IR drops
was within the budget. However, to meet the dy- namic IR Fig. 4. Closer View Of Dynamic IR Drop
drop goals, an increase of the MET3 (MET3 Grid is Vertical)
grid density by 3 times, was needed. The drop across the
culated based on the static IR drop requirement. For our
MET3 and related vias reduced by 50%, after the
design, with the switch density that is calculated as per
improvement. This is another example of a robustness issue
average power, and with “calculated” optimal cell density and
which was missed in static analysis.
optimal decap density, our expectation is to have a
As discussed earlier, the number of power switches is cal-
good dynamic voltage drop. Static IR drop and vectorless
dynamic results runs were within the budgets. Vectorless
dynamic IR drop was 70mV, but vector based dynamic IR drop
was 153 mV, which is beyond the budget. The main cause for
such high voltage drop was localized switching. The high
dynamic IR drop region has very high power den- sity and
hence this region has high current requirement, which is not
fulfilled by the existing power switch density in that region,
and as a result there is high Dynamic voltage drop. The High IR
drop region has reasonably good decap density and has low
utilization as shown in the Fig. 4. This indicates that the
affected region is not really a case of a poorly designed power
grid, but more of an exceptionally high power density, due to
the design architecture com- bined with the placement of
cells. In any case, the power grid has to eventually be able to
support the design’s power demands in that region, which
requires a different approach as will be discussed later.
III. Accuracy Of Analysis
A. Comprehending Delays In Gate Simulation Fig. 5. Dynamic IR Drop: SDF Annotated VCD

There are several factors that affect the accuracy of the

dynamic IR analysis, and how closely it represents the na-
ture of actual Silicon behavior. One of the key requisites is to
generate a realistic VCD (a file format that captures the
switching information) which accounts for the real cell and
interconnect delays (typically done by annotating an SDF in
the gate simulation). Such a simulation captures the re- alistic
spread of switching activity in the design. The other common
approach is to use a VCD from a zero-delay simu- lation, along
with the timing windows from STA analysis, which often
results in non-realistic Dynamic IR drop that can be
pessimistic or optimistic. Refer to Fig. 5 (SDF An- notated
VCD) and Fig. 6 (Without SDF annotated VCD). It shows a
drop close to 175 mV with a VCD generated with SDF,
versus Vs 141 mV from analysis using a VCD without SDF
annotation. In this case, 175mV is the more realistic result
for the given application. Also, the analysis needs to be done
for more than 1 cycle because this would expose more weak
spots and allow sufficient pre-simulation time for the decap
effects to be comprehended more accu-
rately. Fig. 6. Dynamic IR Drop: Without SDF Annotated VCD

B. Comprehending Realistic Glitch Propagation

Glitches arising out of combinational logic switching can C. Choice Of Technology Specs For Signoff
cause a large amount of instantaneous switching. It is im- Often, worst case conditions are chosen for timing, elec-
portant to factor the effect of such switching, with con- trical and reliability checks to ensure robust silicon opera-
sideration to which of these glitches would die down or tion. However, it is also critical to strike a balance between
propagate, considering cell and interconnect delays under picking bounding conditions and being overly pessimistic. In
realistic conditions. If the glitches are very narrow, the an effort to get results closer to realistic silicon condi- tions,
chances of them getting filtered out by the inertial delay of and to detect potentially silicon fails, we selectively evaluated
the path stages (cell + interconnect) is very high. We filtered designs under both worst case and non-worst- case
out glitches much smaller than the stage delay, and let those conditions. For example if we compare the effect of the worst
comparable to (or larger than) the stage delay propagate. The via resistance spec against the nominal via specs, the drop
glitches in between were kept as ’x’. We found that the across vias alone reduce by 50%, as show in Fig. 7. With Via
pessimism in the dynamic voltage drop re- duced by 20% by resistance and Metal resistances typically being
using this approach.
 Fig. 7. Via Drop: Worst corner Vs Nom Corner

uncorrelated, it is a pessimistic assumption to consider that all

vias and metal layers would be in the worst case corner. With
sufficient characterization data, we can apply a less
pessimistic analysis condition for dynamic IR analysis.
D. Voltage Annotated Timing Closure
Timing impact has been analyzed with dynamic voltage
annotation in the STA tool. The voltage annotated timing
violations on one particular design before any fixes can be
seen in Table I. It was ensured that the frequency goals were
met by fixing these violations, either addressing the voltage
drop itself, or at least by improving timing slack on those
paths.

Design Worst Slack (ps) Failing End Points

IP1 -251 370
IP2 -347 95
IP3 -30 8
IP4 -37 2 Fig. 8. Average Power Vs Peak Average Power

TABLE I
DYNAMIC IR DrOP ANNOTated TIMING higher average power during the high-power sub-window,
else the device would not function as per design. An exam-
ple of this is shown in Fig. 8, where the application average
IV. Methodology For power Grid Design For Ro- bust power is about 214 mW where as the average power over a
Dynamic IR sub-window is 367mW. This sub window extends over a few
In this section, the care-about in planning the power dis- hundred clock cycles. In this case, the grid has to support 367
tribution (grid, switches) for power managed designs are mW of average power and not 214mW. Hence, choos- ing the
discussed. Knowledge of the design operating scenarios and right average power for designing the grid would help the
architecture play a key role in ensuring the robust- ness across design scale up to not just dynamic voltage drop issues, but
scenarios. Some techniques to improve power grid robustness even to sustain the average cases more robustly.
through simple physical implementation schemes such as
B. Early Dynamic IR Analysis
power metal fill and decap planning are also touched upon.
One of the difficulties in evaluating the dynamic IR im- pact
A. Choosing The Right Average Power on SOCs or complex designs (IPs) is to get vectors for
The choice of the average power value for which the power sufficient scenarios, and to get them in time to detect issues
distribution is designed for is critical. It is common practice to before the design tapes out. Our Early Analysis flow addresses
design for the average power seen in the use case that this issue. In this flow, the switching activity of a sub IP is
consumes the highest power. However, there can be a sub- integrated at the top level, and switching activity at the top
window within the application window, for which the average level is created, for use in dynamic IR analysis. Using this flow,
power is much higher than that of the entire use case time. It we were able to identify certain architec- tural hot-spots for
is obvious that the grid has to support this dynamic IR drop, like cases of crossbar interconnects
interacting with shared memories having very high power
density. The results obtained from this flow
 Fig. 11. Region Based Switch Density

list of IPs/Modules which consume more power than the rest

of the design. This means that these IPs/Modules need higher
current. Which implies that there is a need for more switches
Fig. 9. Dynamic IR Drop Profile Using Early Analysis Flow in these modules. Typically standard cells of sub IPs/Modules
are placed within close proximity. Hence planning a higher
switch density in this area will make the area better in terms
of dynamic IR drop. Covering more scenarios (More VCD) will
excite different parts of design and hence will show any
weakness in the power network. Refer to Fig. 11 for region
based switch density. Covering more scenario will also show
the area where the voltage drop is low (cool area), the regions
which do not have high IR drop region. In the cool area, switch
density can be re- duced by removing some of the switches.
This will help in reducing the leakage power of the design in
standby mode.

D. Switch Placement In Floorplan Channels / Boundaries

Channels (between macro cells) and floorplan edges or
boundaries are often weak spots in a design’s power dis-
tribution scheme. It was highlighted earlier how a channel
with power switches placed a bit far from the high switch- ing
activity logic gave rise to a dynamic IR hot spot (Refer to Fig.
Fig. 10. Dynamic IR Drop Profile From Full Subsystem Simulation 2). To address such issues, we have implemented an
automated bounding scheme where all the standard cell logic
were found to correlate well with the analysis done with the area in the floorplan is surrounded by power switches at the
complete simulation done at the top level of the sub- system boundaries. Refer to Fig. 12. The switch cell bound- ing is
itself. Both cases are shown in Fig. 9 and Fig. 10, where we done over the corners of channel, making it more robust to
can notice both the magnitude and the profile of the dynamic voltage drop variations.
IR results match closely (The first map is based on the sub- E. Using Design Knowledge To Reduce Dynamic IR
design switching ported to the top level while the second map
In one of our design, the architecture of the design was
is with switching information from full design simulation ).
such that, a group of registers banks switching simultane-
This technique can be extended to SOC’s, to do vector based
ously, and these banks would switch in every cycle. Also these
dynamic IR drop analysis accurately.
groups of register banks and associated cells are phys- ically
C. Power Switch Density And Placement placed close to each another. The Clock to some of the flops
were skewed so as to stagger the switching which will reduce
For designs with power switches, in most cases, high the switching activity (These timing paths had high positive
voltage drop is because of lesser number of switches than slacks). This will reduce the peak current requirement and
needed for localized power density in certain regions. From hence reduce the peak drop. Refer to
common power analysis methods, it is possible to get a
 Fig. 12. Switch Density In Notches

Fig. 14. Metal density without Vs with Metal fill

Fig. 13. Staggering Switching Activity To Reduce Dynamic IR Drop

the metal fill is done on 2 layers and 2% improvement when
metal fill was done on all layers.
Fig. 13, the switching activity last for around 200ps, where as
the clock period is higher, Thus we have used the design
knowledge to reduce switching activity. G. Other Methods To Reduce Dynamic IR Drop

F. Power/Ground Metal Fill Load and Slew violation will not only cause crosstalk but
also cause high power. This is because, there will be high
Experiment Drop Improvement current requirement for higher loads/slews. Hence fixing
Without Metal Fill 9.3 - load/slew violation will help in reducing dynamic voltage
drop. Another method to reduce Dynamic IR drop is haloing of
Metal Fill on 2 Layers 8.4 0.9
Clock tree cells, and adding decaps near these cells. This will
Metal Fill on All layers 7.3 2
help in reducing the voltage drop in clock tree cells due to
TABLE II switching.
USING PoWER/GROUND METAL FiLL TO IMProVE PowER griD rOBUSTNESS

V. Conclusion
Another technique we followed was Power/Ground Metal We have highlighted the common issues faced in the de-
fill. After the design is frozen, final step is to add metal fill in sign closure of power managed designs . Key accuracy and
the areas where the free metal tracks are available. These
signoff methodology issues were addressed and im-
inserted metal straps are connected power or ground. Refer to
provements made in replicating actual device operating
Fig. 14. By doing so, the power and ground grid becomes
conditions in analysis. A comprehensive set of techniques
stronger and hence would help in reducing voltage drop. Refer
adopted in our designs to create a robust power grid, and to
to Table.1. We have seen that as much as 0.9% (0.9% of supply
ensure device timing robustness considering dynamic volt-
voltage) improvement in voltage drop when
age drop, was presented. This covered the choice of the
correct power values, power switch planning, using design
knowledge and power routing techniques.
A. Future Work
The main area of our ongoing work is with respect to
comprehending the impact of dynamic IR on timing behav- ior
of the device - path level, and timing yield. Another area of
study is on the coverage of multiple scenarios with- out
having to simulate each of them (which is impossible, and
hence vector based analysis is not complete today). Further,
dynamic IR impact on test modes are presently being studied.
Efforts are on to correlate analysis and sili- con measurements
to establish a close link between analysis and real device
operation.
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