MC14106B

Hex Schmitt Trigger

The MC14106B hex Schmitt Trigger is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14106B
may be used in place of the MC14069UB hex inverter for enhanced [Link]
noise immunity or to “square up” slowly changing waveforms.
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions
must be taken to avoid applications of any voltage higher than
maximum rated voltages to this high−impedance circuit. For proper
operation, Vin and Vout should be constrained to the range VSS ≤ (Vin SOIC−14 NB TSSOP−14
or Vout) ≤ VDD. D SUFFIX DT SUFFIX
Unused inputs must always be tied to an appropriate logic voltage CASE 751A CASE 948G
level (e.g., either VSS or VDD). Unused outputs must be left open.
MARKING DIAGRAMS
Features
• Increased Hysteresis Voltage Over the MC14584B 14

• Supply Voltage Range = 3.0 Vdc to 18 Vdc 14106BG

• Capable of Driving Two Low−power TTL Loads or One AWLYWW

Low−power Schottky TTL Load Over the Rated Temperature 1

Range SOIC−14 NB
• Pin−for−Pin Replacement for CD40106B and MM74C14
• Can Be Used to Replace the MC14584B or MC14069UB 14

• NLV Prefix for Automotive and Other Applications Requiring 14

106B
Unique Site and Control Change Requirements; AEC−Q100 ALYWG
Qualified and PPAP Capable G
• These Devices are Pb−Free and are RoHS Compliant 1
TSSOP−14
MAXIMUM RATINGS (Voltages Referenced to VSS)
A = Assembly Location
Symbol Parameter Value Unit WL, L = Wafer Lot
VDD DC Supply Voltage Range −0.5 to +18.0 V YY, Y = Year
WW, W = Work Week
Vin, Vout Input or Output Voltage Range −0.5 to VDD + 0.5 V G or G = Pb−Free Package
(DC or Transient)
(Note: Microdot may be in either location)
Iin, Iout Input or Output Current ± 10 mA
(DC or Transient) per Pin
ORDERING INFORMATION
PD Power Dissipation, per Package 500 mW See detailed ordering and shipping information in the package
(Note 1) dimensions section on page 2 of this data sheet.

TA Ambient Temperature Range −55 to +125 °C

Tstg Storage Temperature Range −65 to +150 °C
TL Lead Temperature 260 °C
(8−Second Soldering)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/°C From 65°C To 125°C

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

August, 2014 − Rev. 10 MC14106B/D
 MC14106B

1 2

3 4

5 6

9 8

11 10

13 12

VDD = PIN 14
VSS = PIN 7

Figure 1. Logic Diagram Figure 2. Equivalent Circuit Schematic

(1/6 of Circuit Shown)

ORDERING INFORMATION
Device Package Shipping†
MC14106BDG SOIC−14 NB 55 Units / Rail
(Pb−Free)

NLV14106BDG* SOIC−14 NB 55 Units / Rail

(Pb−Free)

MC14106BDR2G SOIC−14 NB 2500 / Tape & Reel

(Pb−Free)

NLV14106BDR2G* SOIC−14 NB 2500 / Tape & Reel

(Pb−Free)

MC14106BDTR2G TSSOP−14 2500 / Tape & Reel

(Pb−Free)

NLV14106BDTR2G* TSSOP−14 2500 / Tape & Reel

(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.

[Link]
2
 MC14106B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

−55°C 25°C 125°C

VDD Typ
Characteristic Symbol Vdc Min Max Min (Note 2) Max Min Max Unit
Output Voltage “0” Level VOL 5.0 − 0.05 − 0 0.05 − 0.05 Vdc
Vin = VDD 10 − 0.05 − 0 0.05 − 0.05
15 − 0.05 − 0 0.05 − 0.05
“1” Level VOH 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc
Vin = 0 10 9.95 − 9.95 10 − 9.95 −
15 14.95 − 14.95 15 − 14.95 −
Hysteresis Voltage VH (5) 5.0 0.3 2.0 0.3 1.1 2.0 0.3 2.0 Vdc
10 1.2 3.4 1.2 1.7 3.4 1.2 3.4
15 1.6 5.0 1.6 2.1 5.0 1.6 5.0
Threshold Voltage
Positive−Going VT+ 5.0 2.2 3.6 2.2 2.9 3.6 2.2 3.6 Vdc
10 4.6 7.1 4.6 5.9 7.1 4.6 7.1
15 6.8 10.8 6.8 8.8 10.8 6.8 10.8
Negative−Going VT– 5.0 0.9 2.8 0.9 1.9 2.8 0.9 2.8 Vdc
10 2.5 5.2 2.5 3.9 5.2 2.5 5.2
15 4.0 7.4 4.0 5.8 7.4 4.0 7.4
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 –3.0 − –2.4 –4.2 − –1.7 −
(VOH = 4.6 Vdc) 5.0 –0.64 − –0.51 –0.88 − –0.36 −
(VOH = 9.5 Vdc) 10 –1.6 − –1.3 –2.25 − –0.9 −
(VOH = 13.5 Vdc) 15 –4.2 − –3.4 –8.8 − –2.4 −
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc
(VOL = 0.5 Vdc) 10 1.6 − 1.3 2.25 − 0.9 −
(VOL = 1.5 Vdc) 15 4.2 − 3.4 8.8 − 2.4 −
Input Current Iin 15 − ±0.1 − ± 0.00001 ±0.1 − ±1.0 mAdc
Input Capacitance Cin − − − − 5.0 7.5 − − pF
(Vin = 0)
Quiescent Current IDD 5.0 − 0.25 − 0.0005 0.25 − 7.5 mAdc
(Per Package) 10 − 0.5 − 0.0010 0.5 − 15
15 − 1.0 − 0.0015 1.0 − 30
Total Supply Current (Notes 3 & 4) IT 5.0 IT = (1.8 mA/kHz) f + IDD mAdc
(Dynamic plus Quiescent, 10 IT = (3.6 mA/kHz) f + IDD
Per Package) 15 IT = (5.4 mA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25°C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk where IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and
k = 0.001.
5. VH = VT+ – VT– (But maximum variation of VH is specified as less that VT+ max – VT– min).

[Link]
3
 MC14106B

SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25°C)

VDD Typ
Characteristic Symbol Vdc Min (Note 6) Max Unit
Output Rise Time tTLH 5.0 − 100 200 ns
10 − 50 100
15 − 40 80
Output Fall Time tTHL 5.0 − 100 200 ns
10 − 50 100
15 − 40 80
Propagation Delay Time tPLH, tPHL 5.0 − 125 250 ns
10 − 50 100
15 − 40 80
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD 20 ns 20 ns
14
INPUT VDD
PULSE OUTPUT 90%
50%
GENERATOR INPUT 10% VSS
7 VSS CL tPHL tPLH
90% VOH
OUTPUT 50%
10%
VOL
tf tr

Figure 1. Switching Time Test Circuit and Waveforms

VDD
Vout , OUTPUT VOLTAGE (Vdc)

0
0 VT- VT+ VDD
VH
Vin, INPUT VOLTAGE (Vdc)

Figure 2. Typical Transfer Characteristics

[Link]
4
 MC14106B

APPLICATIONS

Vin Vout

VH VDD VH VDD

Vin Vin
VSS VSS

VDD VDD

Vout Vout
VSS VSS

(a) Schmitt Triggers will square up (b) A Schmitt trigger offers maximum
inputs with slow rise and fall times. noise immunity in gate applications.

Figure 3.

VDD VDD

R
tw C
tw
Rs Rs
Vout Vout

C R
VDD
tw = RC IN
VT+

Useful as Pushbutton/Keyboard Debounce Circuit.

Figure 4. Monostable Multivibrator

[Link]
5
 MC14106B

t1+t2
R A
Vin Vout
R t1
C
t2 VDD
Vin VT+
VSS
C
VT )
VDD
* t1 [ RCln
VT – VT+
A
VDD–VT – VSS
* t2 [ RCln
VDD–VT )

f
ƪǒVDD–VT )
V
1 [ RCln  VDD–VT –  T )Ǔ ǒ Ǔƫ
VT –
VDD
Vout VT+
VSS

*t1 + t2 & tPHL + tPLH Useful in discriminating against short pulse durations.

Figure 5. Astable Multivibrator Figure 6. Integrator

C
Vin
Vin

R +EDGE

-EDGE
-EDGE +EDGE
VDD
tw
VDD
tw = RC ln
VT+
Useful as an edge detector circuit.

Figure 7. Differentiator

C C C

Vin

R R R

Figure 8. Positive Edge Time Delay Circuit

[Link]
6
 MC14106B

PACKAGE DIMENSIONS

TSSOP−14
CASE 948G
ISSUE B

14X K REF NOTES:

1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE
−U− N DAMBAR PROTRUSION. ALLOWABLE
PIN 1 DAMBAR PROTRUSION SHALL BE 0.08
IDENT. F (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
1 7 CONDITION.
DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
0.15 (0.006) T U S K

ÉÉÉ
ÇÇÇ
DETERMINED AT DATUM PLANE −W−.
A
−V− K1

ÇÇÇ
ÉÉÉ
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200

ÇÇÇ
J J1 B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
SECTION N−N D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
C −W− J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
0.10 (0.004) K1 0.19 0.25 0.007 0.010
−T− SEATING L 6.40 BSC 0.252 BSC
PLANE D G H DETAIL E M 0_ 8_ 0_ 8_

SOLDERING FOOTPRINT*

7.06

0.65
PITCH

14X 14X
0.36
1.26
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

[Link]
7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

SOIC−14 NB
14 CASE 751A−03
1
ISSUE L
DATE 03 FEB 2016
SCALE 1:1

D A NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
0.25 M B M 13X b DIM MIN MAX MIN MAX
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
h
A X 45 _
D 8.55 8.75 0.337 0.344
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
0.10 L 0.40 1.25 0.016 0.049
e A1 M
SEATING M 0_ 7_ 0_ 7_
C PLANE

GENERIC
SOLDERING FOOTPRINT* MARKING DIAGRAM*
6.50 14X 14
1.18
XXXXXXXXXG
1 AWLYWW

XXXXX = Specific Device Code

A = Assembly Location
1.27
WL = Wafer Lot
PITCH
Y = Year
WW = Work Week
G = Pb−Free Package
14X
*This information is generic. Please refer to
0.58
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.

DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42565B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−14 NB PAGE 1 OF 2

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ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 [Link]

 SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016

STYLE 1: STYLE 2: STYLE 3: STYLE 4:

PIN 1. COMMON CATHODE CANCELLED PIN 1. NO CONNECTION PIN 1. NO CONNECTION
2. ANODE/CATHODE 2. ANODE 2. CATHODE
3. ANODE/CATHODE 3. ANODE 3. CATHODE
4. NO CONNECTION 4. NO CONNECTION 4. NO CONNECTION
5. ANODE/CATHODE 5. ANODE 5. CATHODE
6. NO CONNECTION 6. NO CONNECTION 6. NO CONNECTION
7. ANODE/CATHODE 7. ANODE 7. CATHODE
8. ANODE/CATHODE 8. ANODE 8. CATHODE
9. ANODE/CATHODE 9. ANODE 9. CATHODE
10. NO CONNECTION 10. NO CONNECTION 10. NO CONNECTION
11. ANODE/CATHODE 11. ANODE 11. CATHODE
12. ANODE/CATHODE 12. ANODE 12. CATHODE
13. NO CONNECTION 13. NO CONNECTION 13. NO CONNECTION
14. COMMON ANODE 14. COMMON CATHODE 14. COMMON ANODE

STYLE 5: STYLE 6: STYLE 7: STYLE 8:

PIN 1. COMMON CATHODE PIN 1. CATHODE PIN 1. ANODE/CATHODE PIN 1. COMMON CATHODE
2. ANODE/CATHODE 2. CATHODE 2. COMMON ANODE 2. ANODE/CATHODE
3. ANODE/CATHODE 3. CATHODE 3. COMMON CATHODE 3. ANODE/CATHODE
4. ANODE/CATHODE 4. CATHODE 4. ANODE/CATHODE 4. NO CONNECTION
5. ANODE/CATHODE 5. CATHODE 5. ANODE/CATHODE 5. ANODE/CATHODE
6. NO CONNECTION 6. CATHODE 6. ANODE/CATHODE 6. ANODE/CATHODE
7. COMMON ANODE 7. CATHODE 7. ANODE/CATHODE 7. COMMON ANODE
8. COMMON CATHODE 8. ANODE 8. ANODE/CATHODE 8. COMMON ANODE
9. ANODE/CATHODE 9. ANODE 9. ANODE/CATHODE 9. ANODE/CATHODE
10. ANODE/CATHODE 10. ANODE 10. ANODE/CATHODE 10. ANODE/CATHODE
11. ANODE/CATHODE 11. ANODE 11. COMMON CATHODE 11. NO CONNECTION
12. ANODE/CATHODE 12. ANODE 12. COMMON ANODE 12. ANODE/CATHODE
13. NO CONNECTION 13. ANODE 13. ANODE/CATHODE 13. ANODE/CATHODE
14. COMMON ANODE 14. ANODE 14. ANODE/CATHODE 14. COMMON CATHODE

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42565B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−14 NB PAGE 2 OF 2

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the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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rights of others.

© Semiconductor Components Industries, LLC, 2019 [Link]

 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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