Super Sequencer with Margining Control

and Nonvolatile Fault Recording

Data Sheet ADM1166
FEATURES FUNCTIONAL BLOCK DIAGRAM
Complete supervisory and sequencing solution for up to AUX1 AUX2 REFIN REFOUT REFGND SDA SCL A1 A0

10 supplies
ADM1166 VREF SMBus
16 event deep black box nonvolatile fault recording INTERFACE

10 supply fault detectors enable supervision of supplies to

MUX
12-BIT
<0.5% accuracy at all voltages at 25°C SAR ADC EEPROM

<1.0% accuracy across all voltages and temperatures CLOSED-LOOP FAULT RECORDING
MARGINING SYSTEM
5 selectable input attenuators allow supervision of supplies to
VX1 PDO1
14.4 V on VH and 6 V on VP1 to VP4 (VPx) DUAL-
CONFIGURABLE
OUTPUT PDO2
VX2 FUNCTION
5 dual-function inputs, VX1 to VX5 (VXx) VX3
INPUTS DRIVERS PDO3
(LOGIC INPUTS (HV CAPABLE OF PDO4
High impedance input to supply fault detector with VX4 OR DRIVING GATES PDO5
SFDs)
thresholds between 0.573 V and 1.375 V VX5 OF N-FET) PDO6
SEQUENCING
General-purpose logic input ENGINE
VP1 CONFIGURABLE PDO7
10 programmable driver outputs, PDO1 to PDO10 (PDOx) VP2 PROGRAMMABLE OUTPUT
RESET DRIVERS PDO8
Open-collector with external pull-up VP3 GENERATORS
(LV CAPABLE
(SFDs) OF DRIVING PDO9
Push/pull output, driven to VDDCAP or VPx VP4
LOGIC SIGNALS)
VH PDO10
Open collector with weak pull-up to VDDCAP or VPx
AGND PDOGND
Internally charge-pumped high drive for use with external VOUT VOUT VOUT VOUT VOUT VOUT VDD
ARBITRATOR VDDCAP
N-FET (PDO1 to PDO6 only) DAC DAC DAC DAC DAC DAC

SE implements state machine control of PDO outputs

09332-001
State changes conditional on input events DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 VCCP GND
Figure 1.
Enables complex control of boards
Power-up and power-down sequence control APPLICATIONS
Fault event handling Central office systems
Interrupt generation on warnings Servers/routers
Watchdog function can be integrated in SE Multivoltage system line cards
Program software control of sequencing through SMBus DSP/FPGA supply sequencing
Complete voltage-margining solution for 6 voltage rails In-circuit testing of margined supplies
6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage
GENERAL DESCRIPTION
adjustment via dc-to-dc converter trim/feedback node
12-bit ADC for readback of all supervised voltages The ADM1166 Super Sequencer® is a configurable supervisory/
2 auxiliary (single-ended) ADC inputs sequencing device that offers a single-chip solution for supply
Reference input (REFIN) has 2 input options monitoring and sequencing in multiple-supply systems. In addition
Driven directly from 2.048 V (±0.25%) REFOUT pin to these functions, the ADM1166 integrates a 12-bit ADC and
More accurate external reference for improved ADC six 8-bit voltage output DACs. These circuits can be used to
performance implement a closed-loop margining system that enables supply
Device powered by the highest of VPx, VH for improved adjustment by altering either the feedback node or reference of
redundancy a dc-to-dc converter using the DAC outputs.
User EEPROM: 256 bytes Supply margining can be performed with a minimum of external
Industry-standard 2-wire bus interface (SMBus) components. The margining loop can be used for in-circuit testing
Guaranteed PDO low with VH, VPx = 1.2 V of a board during production (for example, to verify board func-
Available in 40-lead, 6 mm × 6 mm LFCSP and tionality at −5% of nominal supplies), or it can be used dynamically
48-lead, 7 mm × 7 mm TQFP packages to accurately control the output voltage of a dc-to-dc converter.
For more information about the ADM1166 register map, refer
to the AN-698 Application Note.

Rev. A Document Feedback

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Trademarks and registered trademarks are the property of their respective owners. Technical Support [Link]
ADM1166 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 SMBus Jump (Unconditional Jump)........................................ 18
Functional Block Diagram .............................................................. 1 Sequencing Engine Application Example ............................... 19
Applications ....................................................................................... 1 Fault and Status Reporting ........................................................ 20
General Description ......................................................................... 1 Nonvolatile Black Box Fault Recording................................... 21
Revision History ............................................................................... 2 Black Box Writes with No External Supply ............................ 21
Detailed Block Diagram .................................................................. 3 Voltage Readback............................................................................ 22
Specifications..................................................................................... 4 Supply Supervision with the ADC ........................................... 22
Absolute Maximum Ratings............................................................ 7 Supply Margining ........................................................................... 23
Thermal Resistance ...................................................................... 7 Overview ..................................................................................... 23
ESD Caution .................................................................................. 7 Open-Loop Supply Margining ................................................. 23
Pin Configurations and Function Descriptions ........................... 8 Closed-Loop Supply Margining ............................................... 23
Typical Performance Characteristics ........................................... 10 Writing to the DACs .................................................................. 24
Powering the ADM1166 ................................................................ 13 Choosing the Size of the Attenuation Resistor ....................... 24
Slew Rate Consideration............................................................ 13 DAC Limiting and Other Safety Features ............................... 24
Inputs................................................................................................ 14 Applications Diagram .................................................................... 25
Supply Supervision ..................................................................... 14 Communicating with the ADM1166 ........................................... 26
Programming the Supply Fault Detectors ............................... 14 Configuration Download at Power-Up ................................... 26
Input Comparator Hysteresis .................................................... 14 Updating the Configuration ..................................................... 26
Input Glitch Filtering ................................................................. 15 Updating the Sequencing Engine ............................................. 27
VP1 Glitch Filtering ................................................................... 15 Internal Registers........................................................................ 27
Supply Supervision with VXx Inputs ....................................... 15 EEPROM ..................................................................................... 27
VXx Pins as Digital Inputs ........................................................ 16 Serial Bus Interface..................................................................... 27
Outputs ............................................................................................ 17 SMBus Protocols for RAM and EEPROM .............................. 29
Supply Sequencing Through Configurable Output Drivers ....... 17 Write Operations ........................................................................ 30
Default Output Configuration .................................................. 17 Read Operations ......................................................................... 31
Sequencing Engine ......................................................................... 18 Outline Dimensions ....................................................................... 33
Overview...................................................................................... 18 Ordering Guide .......................................................................... 33
Warnings ...................................................................................... 18

REVISION HISTORY
3/15—Rev. 0 to Rev. A Changed
Round-Robin Circuit to
ADC Round-Robin ....................................................... Throughout
Changes to Figure 3, Figure 4, and Table 4 ................................... 8
Added Slew Rate Consideration Section ..................................... 13
Added VP1 Glitch Filtering Section............................................. 15
Changes to Ordering Guide .......................................................... 33

12/10—Revision 0: Initial Version

Rev. A | Page 2 of 33
Data Sheet ADM1166
The device also provides up to 10 programmable inputs for A block of nonvolatile EEPROM is available that can be used to
monitoring undervoltage faults, overvoltage faults, or out-of- store user-defined information and may also be used to hold a
window faults on up to 10 supplies. In addition, 10 programmable number of fault records that are written by the sequencing engine
outputs can be used as logic enables. Six of these programmable defined by the user when a particular fault or sequence occurs.
outputs can also provide up to a 12 V output for driving the gate The device is controlled via configuration data that can be
of an N-FET that can be placed in the path of a supply. programmed into an EEPROM. The entire configuration can
The logical core of the device is a sequencing engine (SE). This be programmed using an intuitive GUI-based software package
state-machine-based construction provides up to 63 different provided by Analog Devices, Inc.
states. This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.

DETAILED BLOCK DIAGRAM

REFIN REFOUT

AUX2 AUX1 REFGND SDA SCL A1 A0

ADM1166 VREF SMBus

INTERFACE

OSC
DEVICE
12-BIT CONTROLLER
SAR ADC EEPROM

FAULT RECORDING

GPI SIGNAL CONFIGURABLE

CONDITIONING OUTPUT DRIVER PDO1
(HV)
VX1
SFD PDO2
VX2 PDO3
VX3 PDO4
VX4 PDO5

GPI SIGNAL
CONDITIONING CONFIGURABLE
OUTPUT DRIVER PDO6
SEQUENCING (HV)
VX5 ENGINE
SFD

SELECTABLE CONFIGURABLE
VP1 ATTENUATOR SFD OUTPUT DRIVER PDO7
(LV)
VP2
VP3 PDO8
VP4 PDO9

SELECTABLE CONFIGURABLE
VH SFD OUTPUT DRIVER PDO10
ATTENUATOR
(LV)

AGND PDOGND
REG 5.25V VOUT VOUT
VDDCAP VDD CHARGE PUMP DAC DAC
ARBITRATOR

GND VCCP DAC1 DAC2 DAC3 DAC4 DAC5 DAC6

09332-002

Figure 2.

Rev. A | Page 3 of 33
ADM1166 Data Sheet

SPECIFICATIONS
VH = 3.0 V to 14.4 V1, VPx = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.

Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY ARBITRATION
VH, VPx 3.0 V Minimum supply required on one of VPx, VH
VPx 6.0 V Maximum VDDCAP = 5.1 V, typical
VH 14.4 V VDDCAP = 4.75 V
VDDCAP 2.7 4.75 5.4 V Regulated LDO output
CVDDCAP 10 μF Minimum recommended decoupling capacitance
POWER SUPPLY
Supply Current, IVH, IVPx 4.2 6 mA VDDCAP = 4.75 V, PDO1 to PDO10 off, DACs off, ADC off
Additional Currents
All PDOx FET Drivers On 1 mA VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each,
PDO7 to PDO10 off
Current Available from 2 mA Maximum additional load that can be drawn from all PDO
VDDCAP pull-ups to VDDCAP
DAC Supply Currents 2.2 mA Six DACs on with 100 μA maximum load on each
ADC Supply Current 1 mA Running round-robin loop
EEPROM Erase Current 10 mA 1 ms duration only, VDDCAP = 3 V
SUPPLY FAULT DETECTORS
VH Pin
Input Impedance 52 kΩ
Input Attenuator Error ±0.05 % Midrange and high range
Detection Ranges
High Range 6 14.4 V
Midrange 2.5 6 V
VPx Pins
Input Impedance 52 kΩ
Input Attenuator Error ±0.05 % Low range and midrange
Detection Ranges
Midrange 2.5 6 V
Low Range 1.25 3 V
Ultralow Range 0.573 1.375 V No input attenuation error
VXx Pins
Input Impedance 1 MΩ
Detection Range
Ultralow Range 0.573 1.375 V No input attenuation error
Absolute Accuracy ±1 % VREF error + DAC nonlinearity + comparator offset error +
input attenuation error
Threshold Resolution 8 Bits
Digital Glitch Filter 0 μs Minimum programmable filter length
100 μs Maximum programmable filter length

Rev. A | Page 4 of 33
Data Sheet ADM1166
Parameter Min Typ Max Unit Test Conditions/Comments
ANALOG-TO-DIGITAL CONVERTER
Signal Range 0 VREFIN V The ADC can convert signals presented to the VH, VPx,
and VXx pins; VPx and VH input signals are attenuated
depending on the selected range; a signal at the pin
corresponding to the selected range is from 0.573 V to
1.375 V at the ADC input
Input Reference Voltage on 2.048 V
REFIN Pin, VREFIN
Resolution 12 Bits
INL ±2.5 LSB Endpoint corrected, VREFIN = 2.048 V
Gain Error ±0.05 % VREFIN = 2.048 V
Conversion Time 0.44 ms One conversion on one channel
84 ms All 12 channels selected, 16× averaging enabled
Offset Error ±2 LSB VREFIN = 2.048 V
Input Noise 0.25 LSB rms Direct input (no attenuator)
AUX1, AUX2 Input Impedance 1 MΩ
BUFFERED VOLTAGE OUTPUT DACs
Resolution 8 Bits
Code 0x7F Output Voltage Six DACs are individually selectable for centering on
one of four output voltage ranges
Range 1 0.592 0.6 0.603 V
Range 2 0.796 0.8 0.803 V
Range 3 0.996 1 1.003 V
Range 4 1.246 1.25 1.253 V
Output Voltage Range 601.25 mV Same range, independent of center point
LSB Step Size 2.36 mV
INL ±0.75 LSB Endpoint corrected
DNL ±0.4 LSB
Gain Error 1 %
Maximum Load Current (Source) 100 μA
Maximum Load Current (Sink) 100 μA
Maximum Load Capacitance 50 pF
Settling Time to 50 pF Load 2 μs
Load Regulation 2.5 mV Per mA
PSRR 60 dB DC
40 dB 100 mV step in 20 ns with 50 pF load
REFERENCE OUTPUT
Reference Output Voltage 2.043 2.048 2.053 V No load
Load Regulation −0.25 mV Sourcing current, IDACxMAX = −100 μA
0.25 mV Sinking current, IDACxMAX = 100 μA
Minimum Load Capacitance 1 μF Capacitor required for decoupling, stability
PSRR 60 dB DC
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge-Pump) Mode
(PDO1 to PDO6)
Output Impedance 500 kΩ
VOH 11 12.5 14 V IOH = 0 μA
VOH 10.5 12 13.5 V IOH = 1 μA
VOH2 8 10 13.5 V IOH = 7 μA
IOUTAVG 20 μA 2 V < VOH < 7 V

Rev. A | Page 5 of 33
ADM1166 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments
Standard (Digital Output) Mode
(PDO1 to PDO10)
VOH 2.4 V VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA
4.5 V VPU to VPx = 6.0 V, IOH = 0 mA
VPU − 0.3 V VPU ≤ 2.7 V, IOH = 0.5 mA
VOL 0 0.50 V IOL = 20 mA
IOL2 20 mA Maximum sink current per PDOx pin
ISINK2 60 mA Maximum total sink for all PDOx pins
RPULL-UP 16 20 29 kΩ Internal pull-up
ISOURCE (VPx)2 2 mA Current load on any VPx pull-ups, that is, total source
current available through any number of PDO pull-up
switches configured onto any one VPx pin
Three-State Output Leakage 10 μA VPDO = 14.4 V
Current
Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, VIH 2.0 V Maximum VIN = 5.5 V
Input Low Voltage, VIL 0.8 V Maximum VIN = 5.5 V
Input High Current, IIH −1 μA VIN = 5.5 V
Input Low Current, IIL 1 μA VIN = 0 V
Input Capacitance 5 pF
Programmable Pull-Down Current, 20 μA VDDCAP = 4.75 V, TA = 25°C, if known logic state is required
IPULL-DOWN
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Output Low Voltage, VOL2 0.4 V IOUT = −3.0 mA
SERIAL BUS TIMING3
Clock Frequency, fSCLK 400 kHz
Bus Free Time, tBUF 1.3 μs
Start Setup Time, tSU;STA 0.6 μs
Stop Setup Time, tSU;STO 0.6 μs
Start Hold Time, tHD;STA 0.6 μs
SCL Low Time, tLOW 1.3 μs
SCL High Time, tHIGH 0.6 μs
SCL, SDA Rise Time, tR 300 ns
SCL, SDA Fall Time, tF 300 ns
Data Setup Time, tSU;DAT 100 ns
Data Hold Time, tHD;DAT 250 ns
Input Low Current, IIL 1 μA VIN = 0 V
SEQUENCING ENGINE TIMING
State Change Time 10 μs
1
At least one of the VH and VPx pins must be ≥ 3.0 V to maintain the device supply on VDDCAP.
2
Specification is not production tested but is supported by characterization data at initial product release.
3
Guaranteed by design.

Rev. A | Page 6 of 33
Data Sheet ADM1166

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE
Table 2.
Parameter Rating θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Voltage on VH Pin 16 V
Voltage on VPx Pins 7V Table 3. Thermal Resistance
Voltage on VXx Pins −0.3 V to +6.5 V Package Type θJA Unit
Voltage on AUX1, AUX2 Pins −0.3 V to +5 V 40-Lead LFCSP 26.5 °C/W
Voltage on A0, A1 Pins −0.3 V to +7 V 48-Lead TQFP 50 °C/W
Voltage on REFIN, REFOUT Pins 5V
Voltage on VDDCAP, VCCP Pins 6.5 V
Voltage on DACx Pins 6.5 V ESD CAUTION
Voltage on PDOx Pins 16 V
Voltage on SDA, SCL Pins 7V
Voltage on GND, AGND, PDOGND, REFGND Pins −0.3 V to +0.3 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature
Soldering Vapor Phase, 60 sec 215°C
ESD Rating, All Pins 2000 V

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. A | Page 7 of 33
ADM1166 Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PDOGND
PDOGND

VDDCAP
VDDCAP

VCCP
VCCP

AUX1
AUX2
AUX1
AUX2

GND
GND

SDA
SDA

SCL
SCL

NC

NC
A1
A0
A1
A0
48 47 46 45 44 43 42 41 40 39 38 37

32
31
33
40
39
38
37
36
35
34

NC 1 36 NC
PIN 1
VX1 1 30 PDO1 VX1 2 INDICATOR 35 PDO1
VX2 2 29 PDO2
VX3 3 28 PDO3 VX2 3 34 PDO2
VX4 4 ADM1166 27 PDO4 VX3 4 33 PDO3
VX5 5 TOP VIEW 26 PDO5
VP1 6 25 PDO6 VX4 5 32 PDO4
(Not to Scale)
VP2 7 24 PDO7 ADM1166
VP3 8 23 PDO8 VX5 6 31 PDO5
VP4 9 22 PDO9 TOP VIEW
VP1 7 30 PDO6
VH 10 21 PDO10 (Not to Scale)
VP2 8 29 PDO7
VP3 9 28 PDO8
11
12
13
14
15
16
17
18
19
20

VP4 10 27 PDO9
REFIN
REFGND

REFOUT
AGND

DAC1
DAC2
DAC3
DAC4
DAC5
DAC6

VH 11 26 PDO10
NC 12 25 NC

NOTE 13 14 15 16 17 18 19 20 21 22 23 24
09332-003

1. THIS PAD IS A NO CONNECT (NC).

REFIN
REFGND

REFOUT
NC
AGND

NC
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
IF POSSIBLE, SOLDER THIS PAD TO THE BOARD
FOR IMPROVED MECHANICAL STABILITY.

09332-004
NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

Figure 3. 40-Lead LFCSP Pin Configuration Figure 4. 48-Lead TQFP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.
40-Lead 48-Lead
LFCSP TQFP Mnemonic Description
N/A1 1, 12, 13, 24, NC No Connect. Do not connect to this pin.
25, 36, 37, 48
1 to 5 2 to 6 VX1 to VX5 (VXx) High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to
1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.
6 to 9 7 to 10 VP1 to VP4 (VPx) Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the
input attenuation on a potential divider connected to these pins, the output of which
connects to a supply fault detector. These pins allow thresholds from 2.5 V to 6.0 V, from
1.25 V to 3.00 V, and from 0.573 V to 1.375 V.
10 11 VH High Voltage Input to Supply Fault Detectors. Two input ranges can be set by altering the
input attenuation on a potential divider connected to this pin, the output of which connects
to a supply fault detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0 V.
11 14 AGND2 Ground Return for Input Attenuators.
12 15 REFGND2 Ground Return for On-Chip Reference Circuits.
13 16 REFIN Reference Input for ADC. Nominally, 2.048 V. This pin must be driven by a reference voltage.
The on-board reference can be used by connecting the REFOUT pin to the REFIN pin.
14 17 REFOUT Reference Output, 2.048 V. Typically connected to REFIN. Note that the capacitor must be
connected between this pin and REFGND. A 10 μF capacitor is recommended for this purpose.
15 to 20 18 to 23 DAC1 to DAC6 Voltage Output DACs. These pins default to high impedance at power-up.
21 to 30 26 to 35 PDO10 to PDO1 Programmable Driver Outputs.
31 38 PDOGND2 Ground Return for Driver Outputs.
32 39 VCCP Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between
this pin and GND. A 10 μF capacitor is recommended for this purpose.
33 40 A0 Logic Input. This pin sets the seventh bit of the SMBus interface address.
34 41 A1 Logic Input. This pin sets the sixth bit of the SMBus interface address.
35 42 SCL SMBus Clock Pin. Bidirectional, open-drain pin that requires external resistive pull-up.
36 43 SDA SMBus Data Pin. Bidirectional, open-drain pin that requires external resistive pull-up.
37, 38 44, 45 AUX2, AUX1 Auxiliary, Single-Ended ADC Inputs.

Rev. A | Page 8 of 33
Data Sheet ADM1166
Pin No.
40-Lead 48-Lead
LFCSP TQFP Mnemonic Description
39 46 VDDCAP Device Supply Voltage. Linearly regulated from the highest of the VPx and VH pins to a
typical of 4.75 V. Note that the capacitor must be connected between this pin and GND.
A 10 μF capacitor is recommended for this purpose.
40 47 GND2 Supply Ground.
N/A1 EPAD Exposed Pad. This pad is a no connect (NC). If possible, solder this pad to the board for improved
mechanical stability.
1
N/A means not applicable.
2
In a typical application, all ground pins are connected together.

Rev. A | Page 9 of 33
ADM1166 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

6 180

160
5
140

4 120
VVDDCAP (V)

100

IVP1 (µA)
3
80

2 60

40
1
20

0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
09332-050

09332-053
VVP1 (V) VVP1 (V)

Figure 5. VVDDCAP vs. VVP1 Figure 8. IVP1 vs. VVP1 (VP1 Not as Supply)

6 5.0

4.5
5
4.0

3.5
4
3.0
VVDDCAP (V)

IVH (mA)

3 2.5

2.0
2
1.5

1.0
1
0.5

0 0
0 2 4 6 8 10 12 14 16

09332-054
0 2 4 6 8 10 12 14 16
09332-051

VVH (V) VVH (V)

Figure 6. VVDDCAP vs. VVH Figure 9. IVH vs. VVH (VH as Supply)

5.0 350

4.5
300
4.0

3.5 250

3.0
200
IVP1 (mA)

IVH (µA)

2.5
150
2.0

1.5 100

1.0
50
0.5

0 0
0 1 2 3 4 5 6
09332-055

0 1 2 3 4 5 6
09332-052

VVP1 (V) VVH (V)

Figure 7. IVP1 vs. VVP1 (VP1 as Supply) Figure 10. IVH vs. VVH (VH Not as Supply)

Rev. A | Page 10 of 33
Data Sheet ADM1166
14 1.0

0.8
12
0.6
CHARGE-PUMPED V PDO1 (V)

10 0.4

0.2
8

DNL (LSB)
0
6
–0.2

4 –0.4

–0.6
2
–0.8

0 –1.0

09332-066
0 2.5 5.0 7.5 10.0 12.5 15.0 0 1000 2000 3000 4000

09332-056
ILOAD (µA) CODE

Figure 11. Charge-Pumped VPDO1 (FET Drive Mode) vs. ILOAD Figure 14. DNL for ADC

5.0 1.0

4.5 0.8

4.0 0.6

3.5 0.4

3.0 0.2
INL (LSB)
VPDO1 (V)

VP1 = 5V
2.5 0
VP1 = 3V
2.0 –0.2

1.5 –0.4

1.0 –0.6

0.5 –0.8

0 –1.0

09332-063
0 1 2 3 4 5 6 0 1000 2000 3000 4000
09332-057

ILOAD (mA) CODE

Figure 12. VPDO1 (Strong Pull-Up to VPx) vs. ILOAD Figure 15. INL for ADC

4.5 12000

4.0 9894
10000
3.5
VP1 = 5V
3.0 8000
HITS PER CODE
VPDO1 (V)

2.5
6000
VP1 = 3V
2.0

1.5 4000

1.0
2000
0.5
25 81
0 0
09332-064

0 10 20 30 40 50 60 2047 2048 2049

09332-058

ILOAD (µA) CODE

Figure 13. VPDO1 (Weak Pull-Up to VPx) vs. ILOAD Figure 16. ADC Noise, Midcode Input, 10,000 Reads

Rev. A | Page 11 of 33
ADM1166 Data Sheet
1.005

1.004

1.003

1.002

DAC OUTPUT
1.001
VP1 = 3.0V
DAC 20kΩ 1.000
BUFFER
OUTPUT PROBE VP1 = 4.75V
47pF POINT
0.999

0.998

0.997
1

0.996

09332-059
CH1 200mV M1.00µs CH1 756mV
0.995

09332-065
–40 –20 0 20 40 60 80 100
TEMPERATURE (C)

Figure 17. Transient Response of DAC Code Change into Typical Load Figure 19. DAC Output vs. Temperature

2.058

2.053

VP1 = 3.0V
REFOUT (V)

DAC 100kΩ 2.048

BUFFER 1V
OUTPUT
VP1 = 4.75V
PROBE
POINT
2.043

1
09332-060

CH1 200mV M1.00µs CH1 944mV 2.038

09332-061
–40 –20 0 20 40 60 80 100
TEMPERATURE (C)

Figure 18. Transient Response of DAC to Turn-On from High-Z State Figure 20. REFOUT vs. Temperature

Rev. A | Page 12 of 33
Data Sheet ADM1166

POWERING THE ADM1166

The ADM1166 is powered from the highest voltage input on When two or more supplies are within 100 mV of each other,
either the positive-only supply inputs (VPx) or the high voltage the supply that first takes control of VDD keeps control. For
supply input (VH). This technique offers improved redundancy example, if VP1 is connected to a 3.3 V supply, VDD powers up
because the device is not dependent on any particular voltage rail to approximately 3.1 V through VP1. If VP2 is then connected to
to keep it operational. The same pins are used for supply fault another 3.3 V supply, VP1 still powers the device, unless VP2
detection (see the Supply Supervision section). A VDD arbitrator goes 100 mV higher than VP1.
on the device chooses which supply to use. The arbitrator can VDDCAP
VP1 IN OUT
be considered an OR’ing of five low dropout regulators (LDOs) 4.75V
LDO
together. A supply comparator chooses the highest input to provide EN
the on-chip supply. There is minimal switching loss with this VP2 IN OUT
architecture (~0.2 V), resulting in the ability to power the 4.75V
LDO
ADM1166 from a supply as low as 3.0 V. Note that the supply on EN

the VXx pins cannot be used to power the device. VP3 IN OUT
4.75V
LDO
An external capacitor to GND is required to decouple the on-chip EN
supply from noise. This capacitor should be connected to the VP4 IN OUT
VDDCAP pin, as shown in Figure 21. The capacitor has another 4.75V
LDO
use during brownouts (momentary loss of power). Under these EN
INTERNAL
conditions, when the input supply (VPx or VH) dips transiently VH IN OUT DEVICE
4.75V SUPPLY
below VDD, the synchronous rectifier switch immediately turns LDO
EN
off so that it does not pull VDD down. The VDD capacitor can
then act as a reservoir to keep the device active until the next SUPPLY
highest supply takes over the powering of the device. A 10 μF COMPARATOR

capacitor is recommended for this reservoir/decoupling function.

09332-022
The value of the VDDCAP capacitor may be increased if it is
necessary to guarantee a complete fault record is written into Figure 21. VDD Arbitrator Operation
EEPROM should all supplies fail. The value of capacitor to use
is discussed in the Black Box Writes with No External Supply SLEW RATE CONSIDERATION
section. When the ambient temperature of operation is less than
approximately −20°C, and in the event of a power loss where all
The VH input pin can accommodate supplies up to 14.4 V, which
supply inputs fail for less than a few hundreds of milliseconds
allows the ADM1166 to be powered using a 12 V backplane supply.
(for example, due to a system supply brownout), it is recommended
In cases where this 12 V supply is hot swapped, it is recommended
that the supply voltage recover with a ramp rate of at least
that the ADM1166 not be connected directly to the supply. Suitable
1.5 V/ms or less than 0.5 V/ms.
precautions, such as the use of a hot swap controller or RC filter
network, should be taken to protect the device from transients
that could cause damage during hot swap events.

Rev. A | Page 13 of 33
ADM1166 Data Sheet

INPUTS
SUPPLY SUPERVISION The threshold value required is given by
The ADM1166 has 10 programmable inputs. Five of these are VT = (VR × N)/255 + VB
dedicated supply fault detectors (SFDs). These dedicated inputs
are called VH and VPx (VP1 to VP4) by default. The other five where:
inputs are labeled VXx (VX1 to VX5) and have dual functionality. VT is the desired threshold voltage (undervoltage or overvoltage).
They can be used either as SFDs, with functionality similar to that VR is the voltage range.
of VH and VPx, or as CMOS-/TTL-compatible logic inputs to N is the decimal value of the 8-bit code.
the device. Therefore, the ADM1166 can have up to 10 analog VB is the bottom of the range.
inputs, a minimum of five analog inputs and five digital inputs, Reversing the equation, the code for a desired threshold is given by
or a combination thereof. If an input is used as an analog input, N = 255 × (VT − VB)/VR
it cannot be used as a digital input. Therefore, a configuration
requiring 10 analog inputs has no available digital inputs. Table 6 For example, if the user wants to set a 5 V overvoltage threshold
shows the details of each input. on VP1, the code to be programmed in the PS1OVTH register
(as discussed in the AN-698 Application Note) is given by
PROGRAMMING THE SUPPLY FAULT DETECTORS
N = 255 × (5 − 2.5)/3.5
The ADM1166 can have up to 10 SFDs on its 10 input channels.
Therefore, N = 182 (1011 0110 or 0xB6).
These highly programmable reset generators enable the supervision
of up to 10 supply voltages. The supplies can be as low as 0.573 V INPUT COMPARATOR HYSTERESIS
and as high as 14.4 V. The inputs can be configured to detect an The UV and OV comparators shown in Figure 22 are always
undervoltage fault (the input voltage drops below a prepro- looking at VPx. To avoid chatter (multiple transitions when the
grammed value), an overvoltage fault (the input voltage rises input is very close to the set threshold level), these comparators
above a preprogrammed value), or an out-of-window fault (the have digitally programmable hysteresis. The hysteresis can be
input voltage is outside a preprogrammed range). The thresholds programmed up to the values shown in Table 6.
can be programmed to an 8-bit resolution in registers provided in RANGE
SELECT
the ADM1166. This translates to a voltage resolution that is ULTRA OV
dependent on the range selected. LOW COMPARATOR
VPx +

The resolution is given by VREF – GLITCH FAULT

FILTER OUTPUT

Step Size = Threshold Range/255 +

LOW
Therefore, if the high range is selected on VH, the step size can –
UV FAULT TYPE
MID COMPARATOR SELECT
be calculated as

09332-023
(14.4 V − 6.0 V)/255 = 32.9 mV
Figure 22. Supply Fault Detector Block
Table 5 lists the upper and lower limits of each available range,
the bottom of each range (VB), and the range itself (VR). The hysteresis is added after a supply voltage goes out of
tolerance. Therefore, the user can program the amount above
Table 5. Voltage Range Limits the undervoltage threshold to which the input must rise before
Voltage Range (V) VB (V) VR (V) an undervoltage fault is deasserted. Similarly, the user can program
0.573 to 1.375 0.573 0.802 the amount below the overvoltage threshold to which an input
1.25 to 3.00 1.25 1.75 must fall before an overvoltage fault is deasserted.
2.5 to 6.0 2.5 3.5
6.0 to 14.4 6.0 8.4

Table 6. Input Functions, Thresholds, and Ranges

Input Function Voltage Range (V) Maximum Hysteresis Voltage Resolution (mV) Glitch Filter (μs)
VH High voltage analog input 2.5 to 6.0 425 mV 13.7 0 to 100
6.0 to 14.4 1.02 V 32.9 0 to 100
VPx Positive analog input 0.573 to 1.375 97.5 mV 3.14 0 to 100
1.25 to 3.00 212 mV 6.8 0 to 100
2.5 to 6.0 425 mV 13.7 0 to 100
VXx High-Z analog input 0.573 to 1.375 97.5 mV 3.14 0 to 100
Digital input 0 to 5.0 Not applicable Not applicable 0 to 100

Rev. A | Page 14 of 33
Data Sheet ADM1166
The hysteresis value is given by VP1 GLITCH FILTERING
VHYST = VR × NTHRESH/255 If the ADC round-robin is used, it is recommended to enable
where: glitch filtering on VP1 because the ADC input mux is connected
VHYST is the desired hysteresis voltage. to VP1 when the ADC round-robin stops. When the ADC
NTHRESH is the decimal value of the 5-bit hysteresis code. round-robin stops, a small internal glitch on the VP1 monitor
rail occurs, and if the rail is close to the UV threshold, it may be
Note that NTHRESH has a maximum value of 31. The maximum enough to trip the VP1 UV comparator. Use any value of glitch
hysteresis for the ranges is listed in Table 6. filter greater than 0 μs to avoid false UV triggers. For more
INPUT GLITCH FILTERING information about the ADC round-robin, see the Voltage
The final stage of the SFDs is a glitch filter. This block provides Readback section.
time-domain filtering on the output of the SFD comparators, SUPPLY SUPERVISION WITH VXx INPUTS
which allows the user to remove any spurious transitions such The VXx inputs have two functions. They can be used as either
as supply bounce at turn-on. The glitch filter function is in addition supply fault detectors or digital logic inputs. When selected as
to the digitally programmable hysteresis of the SFD comparators. analog (SFD) inputs, the VXx pins have functionality that is very
The glitch filter timeout is programmable up to 100 μs. similar to the VH and VPx pins. The primary difference is that the
For example, when the glitch filter timeout is 100 μs, any pulse VXx pins have only one input range: 0.573 V to 1.375 V. Therefore,
appearing on the input of the glitch filter block that is less than these inputs can directly supervise only the very low supplies.
100 μs in duration is prevented from appearing on the output of However, the input impedance of the VXx pins is high, allowing
the glitch filter block. Any input pulse that is longer than 100 μs an external resistor divide network to be connected to the pin.
appears on the output of the glitch filter block. The output is Thus, potentially any supply can be divided down into the input
delayed with respect to the input by 100 μs. The filtering process is range of the VXx pin and supervised. This enables the ADM1166
shown in Figure 23. to monitor other supplies, such as +24 V, +48 V, and −5 V.
INPUT PULSE SHORTER INPUT PULSE LONGER An additional supply supervision function is available when the
THAN GLITCH FILTER TIMEOUT THAN GLITCH FILTER TIMEOUT
VXx pins are selected as digital inputs. In this case, the analog
PROGRAMMED PROGRAMMED
TIMEOUT TIMEOUT function is available as a second detector on each of the dedicated
analog inputs, VPx and VH. The analog function of VX1 is
mapped to VP1, VX2 is mapped to VP2, and so on. VX5 is
INPUT INPUT mapped to VH. In this case, these SFDs can be viewed as
secondary or warning SFDs.

t0 tGF t0 tGF
The secondary SFDs are fixed to the same input range as the
primary SFDs. They are used to indicate warning levels rather
than failure levels. This allows faults and warnings to be generated
on a single supply using only one pin. For example, if VP1 is set
to output a fault when a 3.3 V supply drops to 3.0 V, VX1 can be
OUTPUT OUTPUT set to output a warning at 3.1 V. Warning outputs are available for
readback from the status registers. They are also OR’ed together
09332-024

t0 tGF t0 tGF and fed into the SE, allowing warnings to generate interrupts on
Figure 23. Input Glitch Filter Function the PDOs. Therefore, in this example, if the supply drops to 3.1 V,
a warning is generated, and remedial action can be taken before
the supply drops out of tolerance.

Rev. A | Page 15 of 33
ADM1166 Data Sheet
VXx PINS AS DIGITAL INPUTS same glitch filter function that is available on the SFDs. This
As discussed in the Supply Supervision with VXx Inputs section, enables the user to ignore spurious transitions on the inputs. For
the VXx input pins on the ADM1166 have dual functionality. The example, the filter can be used to debounce a manual reset switch.
second function is as a digital logic input to the device. Therefore, When configured as digital inputs, each VXx pin has a weak
the ADM1166 can be configured for up to five digital inputs. (10 μA) pull-down current source available for placing the input
These inputs are TTL-/CMOS-compatible inputs. Standard logic into a known condition, even if left floating. The current source,
signals can be applied to the pins: RESET from reset generators, if selected, weakly pulls the input to GND.
PWRGD signals, fault flags, and manual resets. These signals are
VXx
available as inputs to the SE and, therefore, can be used to control (DIGITAL INPUT) +
TO
GLITCH
the status of the PDOs. The inputs can be configured to detect DETECTOR FILTER
SEQUENCING
ENGINE
either a change in level or an edge. –

When configured for level detection, the output of the digital

09332-027
block is a buffered version of the input. When configured for edge VREF = 1.4V

detection, a pulse of programmable width is output from the Figure 24. VXx Digital Input Function
digital block once the logic transition is detected. The width is
programmable from 0 μs to 100 μs. The digital blocks feature the

Rev. A | Page 16 of 33
Data Sheet ADM1166

OUTPUTS
SUPPLY SEQUENCING THROUGH CONFIGURABLE The data driving each of the PDOs can come from one of three
OUTPUT DRIVERS sources. The source can be enabled in the PDOxCFG configu-
ration register (see the AN-698 Application Note for details).
Supply sequencing is achieved with the ADM1166 using the
programmable driver outputs (PDOs) on the device as control The data sources are as follows:
signals for supplies. The output drivers can be used as logic  Output from the SE.
enables or as FET drivers.  Directly from the SMBus. A PDO can be configured so that
The sequence in which the PDOs are asserted (and, therefore, the SMBus has direct control over it. This enables software
the supplies are turned on) is controlled by the sequencing engine control of the PDOs. Therefore, a microcontroller can be
(SE). The SE determines what action is taken with the PDOs, used to initiate a software power-up/power-down sequence.
based on the condition of the ADM1166 inputs. Therefore, the  On-chip clock. A 100 kHz clock is generated on the device.
PDOs can be set up to assert when the SFDs are in tolerance, the This clock can be made available on any of the PDOs. It
correct input signals are received on the VXx digital pins, and can be used, for example, to clock an external device such
no warnings are received from any of the inputs of the device. as an LED.
The PDOs can be used for a variety of functions. The primary
function is to provide enable signals for LDOs or dc-to-dc DEFAULT OUTPUT CONFIGURATION
converters that generate supplies locally on a board. The PDOs All of the internal registers in an unprogrammed ADM1166
can also be used to provide a PWRGD signal, when all the SFDs device from the factory are set to 0. Because of this, the PDOx pins
are in tolerance, or a RESET output if one of the SFDs goes out are pulled to GND by a weak (20 kΩ), on-chip pull-down resistor.
of specification (this can be used as a status signal for a DSP, As the input supply to the ADM1166 ramps up on VPx or VH,
FPGA, or other microcontroller). all PDOx pins behave as follows:
The PDOs can be programmed to pull up to a number of different  Input supply = 0 V to 1.2 V. The PDOs are high impedance.
options. The outputs can be programmed as follows:
 Input supply = 1.2 V to 2.7 V. The PDOs are pulled to GND
 Open drain (allowing the user to connect an external by a weak (20 kΩ), on-chip pull-down resistor.
pull-up resistor).  Supply > 2.7 V. Factory-programmed devices continue to
 Open drain with weak pull-up to VDD. pull all PDOs to GND by a weak (20 kΩ), on-chip pull-down
 Open drain with strong pull-up to VDD. resistor. Programmed devices download current EEPROM
 Open drain with weak pull-up to VPx. configuration data, and the programmed setup is latched. The
 Open drain with strong pull-up to VPx. PDO then goes to the state demanded by the configuration.
 Strong pull-down to GND. This provides a known condition for the PDOs during
 Internally charge pumped high drive (12 V, PDO1 to power-up.
PDO6 only). The internal pull-down can be overdriven with an external pull-up
of suitable value tied from the PDOx pin to the required pull-up
The last option (available only on PDO1 to PDO6) allows the
voltage. The 20 kΩ resistor must be accounted for in calculating
user to directly drive a voltage high enough to fully enhance an
a suitable value. For example, if PDOx must be pulled up to 3.3 V,
external N-FET, which is used to isolate, for example, a card-
and 5 V is available as an external supply, the pull-up resistor
side voltage from a backplane supply (a PDO can sustain greater
value is given by
than 10.5 V into a 1 μA load). The pull-down switches can also
be used to drive status LEDs directly. 3.3 V = 5 V × 20 kΩ/(RUP + 20 kΩ)
Therefore,
RUP = (100 kΩ − 66 kΩ)/3.3 V = 10 kΩ
VFET (PDO1 TO PDO6 ONLY)
VDD
VP4
SEL VP1
CFG4 CFG5 CFG6
20kΩ

20kΩ

20kΩ
10Ω

10Ω

10Ω

SE DATA

SMBus DATA PDO

CLK DATA
20kΩ

09332-028

Figure 25. Programmable Driver Output

Rev. A | Page 17 of 33
ADM1166 Data Sheet

SEQUENCING ENGINE
OVERVIEW
MONITOR
The ADM1166 sequencing engine (SE) provides the user with FAULT STATE
TIMEOUT
powerful and flexible control of sequencing. The SE implements
state machine control of the PDO outputs, with state changes
conditional on input events. SE programs can enable complex

09332-029
control of boards such as power-up and power-down sequence SEQUENCE

control, fault event handling, and interrupt generation on warnings.

A watchdog function that verifies the continued operation of a Figure 26. State Cell
processor clock can be integrated into the SE program. The SE The ADM1166 offers up to 63 state definitions. The signals
can also be controlled via the SMBus, giving software or firmware monitored to indicate the status of the input pins are the outputs
control of the board sequencing. of the SFDs.
The SE state machine comprises 63 state cells. Each state has the WARNINGS
following attributes:
The SE also monitors warnings. These warnings can be generated
 Monitors signals indicating the status of the 10 input pins, when the ADC readings violate their limit register value or
VP1 to VP4, VH, and VX1 to VX5. when the secondary voltage monitors on VPx or VH are triggered.
 Can be entered from any other state. The warnings are OR’ed together and are available as a single
 Three exit routes move the state machine onto a next state: warning input to each of the three blocks that enable exiting a state.
sequence detection, fault monitoring, and timeout. SMBus JUMP (UNCONDITIONAL JUMP)
 Delay timers for the sequence and timeout blocks can be
The SE can be forced to advance to the next state unconditionally.
programmed independently and changed with each state
This enables the user to force the SE to advance. Examples of
change. The range of timeouts is from 0 ms to 400 ms.
the use of this feature include moving to a margining state or
 Output condition of the 10 PDO pins is defined and fixed
debugging a sequence. The SMBus jump or go-to command
within a state.
can be seen as another input to sequence and timeout blocks to
 Transition from one state to the next is made in less than
provide an exit from each state.
20 μs, which is the time needed to download a state definition
from EEPROM to the SE.
 Can trigger a write of the black box fault and status
registers into the black box section of EEPROM.

Table 7. Sample Sequence State Entries

State Sequence Timeout Monitor
IDLE1 If VX1 is low, go to State IDLE2.
IDLE2 If VP1 is okay, go to State EN3V3.
EN3V3 If VP2 is okay, go to State EN2V5. If VP2 is not okay after 10 ms, If VP1 is not okay, go to State IDLE1.
go to State DIS3V3.
DIS3V3 If VX1 is high, go to State IDLE1.
EN2V5 If VP3 is okay, go to State PWRGD. If VP3 is not okay after 20 ms, If VP1 or VP2 is not okay, go to State FSEL2.
go to State DIS2V5.
DIS2V5 If VX1 is high, go to State IDLE1.
FSEL1 If VP3 is not okay, go to State DIS2V5. If VP1 or VP2 is not okay, go to State FSEL2.
FSEL2 If VP2 is not okay, go to State DIS3V3. If VP1 is not okay, go to State IDLE1.
PWRGD If VX1 is high, go to State DIS2V5. If VP1, VP2, or VP3 is not okay, go to State FSEL1.

Rev. A | Page 18 of 33
Data Sheet ADM1166
SEQUENCING ENGINE APPLICATION EXAMPLE If a timer delay is specified, the input to the sequence detector
The application in this section demonstrates the operation of must remain in the defined state for the duration of the timer
the SE. Figure 28 shows how the simple building block of a delay. If the input changes state during the delay, the timer is reset.
single SE state can be used to build a power-up sequence for a The sequence detector can also help to identify monitoring faults.
three-supply system. In the sample application shown in Figure 28, the FSEL1 and
Table 8 lists the PDO outputs for each state in the same SE FSEL2 states first identify which of the VP1, VP2, or VP3 pins
implementation. In this system, a good 5 V supply on the VP1 pin has faulted, and then they take appropriate action.
SEQUENCE
and the VX1 pin held low are the triggers required to start a STATES
power-up sequence. Next, the sequence turns on the 3.3 V supply,
then the 2.5 V supply (assuming successful turn-on of the 3.3 V
supply). When all three supplies have turned on correctly, the IDLE1

PWRGD state is entered, where the SE remains until a fault occurs

VX1 = 0
on one of the three supplies or until it is instructed to go through a
power-down sequence by VX1 going high.
IDLE2
Faults are dealt with throughout the power-up sequence on a
case-by-case basis. The following three sections (the Sequence
VP1 = 1
Detector section, the Monitoring Fault Detector section, and MONITOR FAULT TIMEOUT
STATES STATES
the Timeout Detector section) describe the individual blocks
and use the sample application shown in Figure 28 to demonstrate EN3V3
VP1 = 0 10ms
the actions of the state machine.
Sequence Detector VP2 = 1

The sequence detector block is used to detect when a step in a EN2V5 DIS3V3
20ms
sequence has been completed. It looks for one of the SE inputs (VP1 + VP2) = 0
VX1 = 1
to change state, and is most often used as the gate for successful
VP3 = 1
progress through a power-up or power-down sequence. A timer
block that is included in this detector can insert delays into a PWRGD DIS2V5
VP2 = 0
power-up or power-down sequence, if required. Timer delays (VP1 + VP2 + VP3) = 0
can be set from 10 μs to 400 ms. Figure 27 is a block diagram of VX1 = 1
VX1 = 1
the sequence detector. (VP1 +
FSEL1
VP2) = 0
SUPPLY FAULT
VP1 DETECTION
VP3 = 0
SEQUENCE
DETECTOR FSEL2
VP1 = 0

LOGIC INPUT CHANGE

VX5 OR FAULT DETECTION VP2 = 0

09332-030
TIMER

WARNINGS
Figure 28. Sample Application Flow Diagram
INVERT
FORCE FLOW
(UNCONDITIONAL JUMP)
09332-032

SELECT

Figure 27. Sequence Detector Block Diagram

Table 8. PDO Outputs for Each State

PDO Outputs IDLE1 IDLE2 EN3V3 EN2V5 DIS3V3 DIS2V5 PWRGD FSEL1 FSEL2
PDO1 = 3V3ON 0 0 1 1 0 1 1 1 1
PDO2 = 2V5ON 0 0 0 1 1 0 1 1 1
PDO3 = FAULT 0 0 0 0 1 1 0 1 1

Rev. A | Page 19 of 33
ADM1166 Data Sheet
Monitoring Fault Detector Timeout Detector
The monitoring fault detector block is used to detect a failure The timeout detector allows the user to trap a failure to ensure
on an input. The logical function implementing this is a wide proper progress through a power-up or power-down sequence.
OR gate that can detect when an input deviates from its expected In the sample application shown in Figure 28, the timeout next-
condition. The clearest demonstration of the use of this block is state transition is from the EN3V3 and EN2V5 states. For the
in the PWRGD state, where the monitor block indicates that a EN3V3 state, the signal 3V3ON is asserted on the PDO1 output
failure on one or more of the VPx, VXx, or VH inputs has pin upon entry to this state to turn on a 3.3 V supply.
occurred.
This supply rail is connected to the VP2 pin, and the sequence
No programmable delay is available in this block because the detector looks for the VP2 pin to go above its undervoltage
triggering of a fault condition is likely to be caused by a supply threshold, which is set in the supply fault detector (SFD)
falling out of tolerance. In this situation, the device must react attached to that pin.
as quickly as possible. Some latency occurs when moving out of
this state because it takes a finite amount of time (~20 μs) for the The power-up sequence progresses when this change is detected. If,
state configuration to download from the EEPROM into the SE. however, the supply fails (perhaps due to a short circuit overloading
Figure 29 is a block diagram of the monitoring fault detector. this supply), the timeout block traps the problem. In this example,
MONITORING FAULT
if the 3.3 V supply fails within 10 ms, the SE moves to the DIS3V3
DETECTOR state and turns off this supply by bringing PDO1 low. It also
1-BIT FAULT indicates that a fault has occurred by taking PDO3 high. Timeout
DETECTOR
delays of 100 μs to 400 ms can be programmed.
SUPPLY FAULT FAULT
VP1 DETECTION
FAULT AND STATUS REPORTING
MASK
SENSE The ADM1166 has a fault latch for recording faults. Two registers,
FSTAT1 and FSTAT2, are set aside for this purpose. A single bit
is assigned to each input of the device, and a fault on that input
1-BIT FAULT
DETECTOR sets the relevant bit. The contents of the fault register can be
LOGIC INPUT CHANGE FAULT read out over the SMBus to determine which input(s) faulted.
VX5 OR FAULT DETECTION
The fault register can be enabled or disabled in each state. To
MASK latch data from one state, ensure that the fault latch is disabled
SENSE
in the following state. This ensures that only real faults are
1-BIT FAULT captured and not, for example, undervoltage conditions that
DETECTOR
may be present during a power-up or power-down sequence.
FAULT
WARNINGS
The ADM1166 also has a number of input status registers. These
include more detailed information, such as whether an under-
09332-033

MASK
voltage or overvoltage fault is present on a particular input. The
status registers also include information on ADC limit faults.
Figure 29. Monitoring Fault Detector Block Diagram
There are two sets of these registers with different behaviors.
The first set of status registers is not latched in any way and,
therefore, can change at any time in response to changes on the
inputs. These registers provide information as the UV and OV
state of the inputs, the digital state of the GPI VXx inputs, and
also the ADC warning limit status.
The second set of registers update each time the sequence engine
changes state and are latched until the next state change. The
second set of registers provides the same information as the first
set, but in a more compact form. The reason for this is that
these registers are used by the black box feature when writing
status information for the previous state into EEPROM.
See the AN-698 Application Note for full details about the
ADM1166 registers.

Rev. A | Page 20 of 33
Data Sheet ADM1166
NONVOLATILE BLACK BOX FAULT RECORDING To avoid the fault recorder filling up and fault records being lost, an
A section of EEPROM, from Address 0xF900 to Address 0xF9FF, is application can periodically poll the ADM1166 to determine if
provided which, by default, can be used to store user-defined there are fault records to be read. Alternatively, one of the PDOx
settings and information. Part of this section of EEPROM, outputs can be used to generate an interrupt for a processor in
Address 0xF980 to Address 0xF9FF, can, instead, be used to the fault record write state to signal the need to come and read
store up to 16 fault records. one or more fault records.

Any sequencing engine state can be designated as a black box After reading fault records during normal operation, the following
write state. Each time the sequence engine enters that state a two things must be done before the fault recorder will be able to
fault record is written into EEPROM. The fault record provides reuse the EEPROM locations:
a snapshot of the entire ADM1166 state at the point in time  The EEPROM section must be erased.
when the last state was exited, just prior to entering the designated  The fault recorder must be reset so that it performs its search
black box write state. A fault record contains the following again for the first unused location of EEPROM that is
information: available to store a fault record.
 A flag bit set to 0 after the fault record has been written BLACK BOX WRITES WITH NO EXTERNAL SUPPLY
 The state number of the previous state prior to the fault
In cases where all the input supplies fail, for example, if the card
record write state
has been removed from a powered backplane, the state machine
 Did a sequence/timeout/monitor condition cause the
can be programmed to trigger a write into the black box EEPROM.
previous state to exit?
The decoupling capacitors on the rail that power the ADM1166
 UVSTATx and OVSTATx input comparator status and other loads on the board form an energy reservoir. Depending
 VXx GPISTAT status on the other loads on the board and their behavior as the supply
 LIMSTATx status rails drop, there may be sufficient energy in the decoupling
 A checksum byte capacitors to allow the ADM1166 to write a complete fault record
Each fault record contains eight bytes, with each byte taking (8 bytes of data).
typically about 250 μs to write to EEPROM, for a total write Typically, it takes 2 ms to write to the eight bytes of a fault record. If
time of about 2 ms. Once the black box begins to write a fault the ADM1166 is powered using a 12 V supply on the VH pin, then
record into EEPROM, the ADM1166 ensures the write is complete a UV threshold at 6 V could be set and used as the state machine
before attempting to write any additional fault records. This trigger to start writing a fault record to EEPROM. The higher the
means that if consecutive sequencing engine states are designated threshold, the earlier the black box write will begin, and the more
as black box write states, then a time delay must be used in the energy available in the decoupling capacitors to ensure it completes
first state to ensure that the fault record is written before moving to successfully.
the next state. Provided the VH supply, or another supply connected to a VPx pin,
When the ADM1166 powers on initially, it performs a search remains above 3.0 V during the time to write, the entire fault record
to find the first fault record that has not been written to. It does would always be written to EEPROM. In many cases, there will be
this by checking the flag bit in each fault record until it finds sufficient decoupling capacitors on a board to power the
one where the flag bit is 1. The first fault record is stored at ADM1166 as it writes into EEPROM.
Address 0xF980 and at multiples of eight bytes after that, In cases where the decoupling capacitors are not able to supply
with the last record stored at Address 0xF9F8. sufficient energy for a complete fault record to be written after the
The fault recorder is only able to write in the EEPROM. It is board is removed, the value of the capacitor on VDDCAP may
not able to erase the EEPROM prior to writing the fault record. be increased. In the worst case, assuming that no energy is
Therefore, to ensure correct operation, it is important that the fault supplied to the ADM1166 by external decoupling capacitors,
record EEPROM be erased prior to use. Once all the EEPROM but that the VDDCAP capacitor has 4.75 V across it at the start
locations for the fault records are used, no more fault records can of the black box write to EEPROM, then a VDDCAP of 68 μF is
be written. This ensures that the first fault in any cascading fault is sufficient to guarantee a single complete black box record can
stored and not overwritten and lost. be written to EEPROM.

Rev. A | Page 21 of 33
ADM1166 Data Sheet

VOLTAGE READBACK
The ADM1166 has an on-board, 12-bit accurate ADC for Table 9. ADC Input Voltage Ranges
voltage readback over the SMBus. The ADC has a 12-channel
Attenuation ADC Input Voltage
analog mux on the front end. The 12 channels consist of the SFD Input Range (V) Factor Range (V)
10 SFD inputs (VH, VPx, and VXx) and two auxiliary (single- 0.573 to 1.375 1 0 to 2.048
ended) ADC inputs (AUX1 and AUX2). Any or all of these inputs 1.25 to 3.00 2.181 0 to 4.46
can be selected to be read, in turn, by the ADC. The circuit 2.5 to 6.0 4.363 0 to 6.01
controlling this operation is called the ADC round-robin. 6.0 to 14.4 10.472 0 to 14.41
This circuit can be selected to run through its loop of conversions 1
The upper limit is the absolute maximum allowed voltage on the VPx and
once or continuously. Averaging is also provided for each channel. VH pins.
In this case, the ADC round-robin runs through its loop of The typical way to supply the reference to the ADC on the REFIN
conversions 16 times before returning a result for each channel. At
pin is to connect the REFOUT pin to the REFIN pin. REFOUT
the end of this cycle, the results are written to the output registers.
provides a 2.048 V reference. As such, the supervising range covers
The ADC samples single-sided inputs with respect to the AGND less than half the normal ADC range. It is possible, however, to
pin. A 0 V input gives out Code 0, and an input equal to the provide the ADC with a more accurate external reference for
voltage on REFIN gives out full code (4095 decimal). improved readback accuracy.
The inputs to the ADC come directly from the VXx pins and Supplies can also be connected to the input pins purely for ADC
from the back of the input attenuators on the VPx and VH pins, readback, even though these pins may go above the expected
as shown in Figure 30 and Figure 31. supervisory range limits (but not above the absolute maximum
DIGITIZED ratings on these pins). For example, a 1.5 V supply connected to
NO ATTENUATION VOLTAGE
READING the VX1 pin can be correctly read out as an ADC code of approxi-
12-BIT
VXx mately 3/4 full scale, but it always sits above any supervisory limits
ADC
that can be set on that pin. The maximum setting for the REFIN
09332-025

2.048V VREF pin is 2.048 V.

Figure 30. ADC Reading on VXx Pins SUPPLY SUPERVISION WITH THE ADC
In addition to the readback capability, another level of supervision
ATTENUATION NETWORK
is provided by the on-chip 12-bit ADC. The ADM1166 has limit
VPx/VH (DEPENDS ON RANGE SELECTED)
registers with which the user can program a maximum or
DIGITIZED
VOLTAGE
READING
minimum allowable threshold. Exceeding the threshold generates a
12-BIT warning that can either be read back from the status registers or
ADC
input into the SE to determine what sequencing action the
ADM1166 should take. Only one register is provided for each
09332-026

2.048V VREF
input channel. Therefore, either an undervoltage threshold or
Figure 31. ADC Reading on VPx/VH Pins overvoltage threshold (but not both) can be set for a given channel.
The ADC round-robin can be enabled via a SMBus write, or it
The voltage at the input pin can be derived from the following
can be programmed to turn on in any state in the SE program.
equation:
For example, it can be set to start after a power-up sequence is
ADC Code complete and all supplies are known to be within expected
V= × Attenuation Factor × VREFIN
4095 tolerance limits.
where VREFIN = 2.048 V when the internal reference is used (that Note that latency is built into this supervision, dictated by the
is, the REFIN pin is connected to the REFOUT pin). conversion time of the ADC. With all 12 channels selected, the
The ADC input voltage ranges for the SFD input ranges are listed total time for the round-robin operation (averaging off) is
in Table 9. approximately 6 ms (500 μs per channel selected). Supervision
using the ADC, therefore, does not provide the same real-time
response as the SFDs.

Rev. A | Page 22 of 33
Data Sheet ADM1166

SUPPLY MARGINING
OVERVIEW feedback node, and the output of the dc-to-dc converter is forced to
fall to compensate for this. The dc-to-dc converter output can
It is often necessary for the system designer to adjust supplies, be forced high by setting the DACx output voltage lower than
either to optimize their level or force them away from nominal the feedback node voltage. The series resistor can be split in two,
values to characterize the system performance under these and the node between them can be decoupled with a capacitor
conditions. This is a function typically performed during an in- to ground. This can help to decouple any noise picked up from
circuit test (ICT), such as when a manufacturer wants to guarantee the board. Decoupling to a ground local to the dc-to-dc converter
that a product under test functions correctly at nominal supplies is recommended.
minus 10%.
The ADM1166 can be commanded to margin a supply up or
OPEN-LOOP SUPPLY MARGINING down over the SMBus by updating the values on the relevant
The simplest method of margining a supply is to implement an DAC output.
open-loop technique (see Figure 32). A popular way to do this
CLOSED-LOOP SUPPLY MARGINING
is to switch extra resistors into the feedback node of a power
module, such as a dc-to-dc converter or LDO. The extra resistor A more accurate and comprehensive method of margining is to
alters the voltage at the feedback or trim node and forces the implement a closed-loop system (see Figure 33). The voltage on
output voltage to margin up or down by a certain amount. the rail to be margined can be read back to accurately margin the
rail to the target voltage. The ADM1166 incorporates all the circuits
The ADM1166 can perform open-loop margining for up to six required to do this, with the 12-bit successive approximation ADC
supplies. The six on-board voltage DACs (DAC1 to DAC6) can used to read back the level of the supervised voltages, and the six
drive into the feedback pins of the power modules to be margined. voltage output DACs, implemented as described in the Open-
The simplest circuit to implement this function is an attenuation Loop Supply Margining section, used to adjust supply levels. These
resistor that connects the DACx pin to the feedback node of a circuits can be used along with other intelligence, such as a
dc-to-dc converter. When the DACx output voltage is set equal microcontroller, to implement a closed-loop margining system
to the feedback voltage, no current flows into the attenuation that allows any dc-to-dc converter or LDO supply to be set to
resistor, and the dc-to-dc converter output voltage does not change. any voltage, accurate to within ±0.5% of the target.
Taking DACx above the feedback voltage forces current into the
VIN
MICROCONTROLLER

VOUT
ADM1166
OUTPUT DEVICE
ATTENUATION CONTROLLER
DC-TO-DC RESISTOR, R3 (SMBus)
CONVERTER
R1
DACx
FEEDBACK DAC

R2
PCB
GND
09332-067

TRACE NOISE
DECOUPLING
CAPACITOR

Figure 32. Open-Loop Margining System Using the ADM1166

MICROCONTROLLER
VIN

ADM1166

DC-TO-DC VH/VPx/VXx
CONVERTER
MUX ADC
OUTPUT ATTENUATION
RESISTOR, R3
R1 DEVICE
DACx CONTROLLER
FEEDBACK DAC (SMBus)
R2
PCB
GND
09332-034

TRACE NOISE
DECOUPLING
CAPACITOR

Figure 33. Closed-Loop Margining System Using the ADM1166

Rev. A | Page 23 of 33
ADM1166 Data Sheet
To implement closed-loop margining, CHOOSING THE SIZE OF THE ATTENUATION
1. Disable the six DACx outputs. RESISTOR
2. Set the DAC output voltage equal to the voltage on the The size of the attenuation resistor, R3, determines how much
feedback node. the DAC voltage swing affects the output voltage of the dc-to-dc
3. Enable the DAC. converter that is being margined (see Figure 33).
4. Read the voltage at the dc-to-dc converter output that is
Because the voltage at the feedback pin remains constant, the
connected to one of the VPx, VH, or VXx pins.
current flowing from the feedback node to GND through R2 is
5. If necessary, modify the DACx output code up or down to
a constant. In addition, the feedback node itself is high impedance.
adjust the dc-to-dc converter output voltage. Otherwise,
This means that the current flowing through R1 is the same as
stop because the target voltage has been reached.
the current flowing through R3.
6. Set the DAC output voltage to a value that alters the supply
output by the required amount (for example, ±5%). Therefore, a direct relationship exists between the extra voltage
7. Repeat Step 4 through Step 6 until the measured supply drop across R1 during margining and the voltage drop across R3.
reaches the target voltage. This relationship is given by the following equation:
Step 1 to Step 3 ensures that when the DACx output buffer is R1
turned on, it has little effect on the dc-to-dc converter output. ΔVOUT = (VFB − VDACOUT)
R3
The DAC output buffer is designed to power up without glitching
by first powering up the buffer to follow the pin voltage. It does not where:
drive out onto the pin at this time. Once the output buffer is ΔVOUT is the change in VOUT.
properly enabled, the buffer input is switched over to the DAC, VFB is the voltage at the feedback node of the dc-to-dc converter.
and the output stage of the buffer is turned on. Output glitching VDACOUT is the voltage output of the margining DAC.
is negligible. This equation demonstrates that if the user wants the output
voltage to change by ±300 mV, then R1 = R3. If the user wants the
WRITING TO THE DACS
output voltage to change by ±600 mV, R1 = 2 × R3, and so on.
Four DAC ranges are offered. They can be placed with midcode
It is best to use the full DAC output range to margin a supply.
(Code 0x7F) at 0.6 V, 0.8 V, 1.0 V, and 1.25 V. These voltages are
Choosing the attenuation resistor in this way provides the most
placed to correspond to the most common feedback voltages.
resolution from the DAC, meaning that with one DAC code
Centering the DAC outputs in this way provides the best use of
change, the smallest effect on the dc-to-dc converter output
the DAC resolution. For most supplies, it is possible to place the
voltage is induced. If the resistor is sized up to use a code such
DAC midcode at the point where the dc-to-dc converter output
as 27 decimal to 227 decimal to move the dc-to-dc converter output
is not modified, thereby giving half of the DAC range to margin
by ±5%, it takes 100 codes to move 5% (each code moves the
up and the other half to margin down.
output by 0.05%). This is beyond the readback accuracy of the
The DAC output voltage is set by the code written to the DACx ADC, but it should not prevent the user from building a circuit
register. The voltage is linear with the unsigned binary number to use the most resolution.
in this register. Code 0x7F is placed at the midcode voltage, as
described previously. The output voltage is given by DAC LIMITING AND OTHER SAFETY FEATURES
DAC Output = (DACx − 0x7F)/255 × 0.6015 + VOFF Limit registers (called DPLIMx and DNLIMx) on the device
offer the user some protection from firmware bugs that can
where VOFF is one of the four offset voltages. cause catastrophic board problems by forcing supplies beyond
There are 256 DAC settings available. The midcode value is their allowable output ranges. Essentially, the DAC code written
located at DAC Code 0x7F as close as possible to the middle into the DACx register is clipped such that the code used to set
of the 256 code range. The full output swing of the DACs is the DAC voltage is given by
+302 mV (+128 codes) and −300 mV (−127 codes) around DAC Code
the selected midcode voltage. The voltage range for each midcode = DACx, DACx ≥ DNLIMx and DACx ≤ DPLIMx
voltage is shown in Table 10. = DNLIMx, DACx < DNLIMx
= DPLIMx, DACx > DPLIMx
Table 10. Ranges for Midcode Voltages
In addition, the DAC output buffer is three-stated if DNLIMx >
Midcode Minimum Voltage Maximum Voltage
Voltage (V) Output (V) Output (V) DPLIMx. By programming the limit registers this way, the user
0.6 0.300 0.902 can make it very difficult for the DAC output buffers to be
0.8 0.500 1.102 turned on during normal system operation. The limit registers
1.0 0.700 1.302 are among the registers downloaded from EEPROM at startup.
1.25 0.950 1.552

Rev. A | Page 24 of 33
Data Sheet ADM1166

APPLICATIONS DIAGRAM
12V IN 12V OUT

5V IN 5V OUT

3V IN 3V OUT

IN
DC-TO-DC1
EN OUT 3.3V OUT
VH
ADM1166
5V OUT VP1 PDO1
3V OUT VP2 PDO2
3.3V OUT VP3
IN
2.5V OUT VP4
1.8V OUT VX1 PDO3 DC-TO-DC2
1.2V OUT VX2 PDO4 EN OUT 2.5V OUT
0.9V OUT VX3 PDO5
POWRON PWRGD
VX4 PDO6
SIGNAL VALID
RESET PDO7 IN
SYSTEM RESET DC-TO-DC3
VX5 PDO8
PDO9 EN OUT 1.8V OUT
PDO10
3.3V OUT
REFOUT DAC1*

REFIN VCCP VDDCAP GND IN

LDO
EN OUT 0.9V OUT
10µF 10µF 10µF
3.3V OUT

*ONLY ONE MARGINING CIRCUIT IN

SHOWN FOR CLARITY. DAC1 TO DAC6 OUT 1.2V OUT
ALLOW MARGINING FOR UP TO SIX
VOLTAGE RAILS. EN TRIM
DC-TO-DC4

09332-068
Figure 34. Applications Diagram

Rev. A | Page 25 of 33
ADM1166 Data Sheet

COMMUNICATING WITH THE ADM1166

CONFIGURATION DOWNLOAD AT POWER-UP Option 1
The configuration of the ADM1166 (undervoltage/overvoltage Update the configuration in real time. The user writes to the RAM
thresholds, glitch filter timeouts, and PDO configurations) is across the SMBus, and the configuration is updated immediately.
dictated by the contents of the RAM. The RAM comprises digital Option 2
latches that are local to each function on the device. The latches are Update the Latch As without updating the Latch Bs. With this
double buffered and have two identical latches, Latch A and Latch B. method, the configuration of the ADM1166 remains unchanged
Therefore, when an update to a function occurs, the contents of and continues to operate in the original setup until the instruction
Latch A are updated first, and then the contents of Latch B are is given to update the Latch Bs.
updated with identical data. The advantages of this architecture are
explained in detail in the Updating the Configuration section.
Option 3
Change the EEPROM register contents without changing the RAM
The two latches are volatile memory and lose their contents at
contents, and then download the revised EEPROM contents to
power-down. Therefore, the configuration in the RAM must be
the RAM registers. With this method, the configuration of the
restored at power-up by downloading the contents of the EEPROM
ADM1166 remains unchanged and continues to operate in the
(nonvolatile memory) to the local latches. This download occurs in
original setup until the instruction is given to update the RAM.
steps, as follows:
The instruction to download from the EEPROM in Option 3 is
1. With no power applied to the device, the PDOs are all high
also a useful way to restore the original EEPROM contents if
impedance.
revisions to the configuration are unsatisfactory. For example, if
2. When 1.2 V appears on any of the inputs connected to the
the user needs to alter an overvoltage threshold, the RAM register
VDD arbitrator (VH or VPx), the PDOs are all weakly
can be updated as described in the Option 1 section. However,
pulled to GND with a 20 kΩ resistor.
if the user is not satisfied with the change and wants to revert to
3. When the supply rises above the undervoltage lockout of
the original programmed value, the device controller can issue a
the device (UVLO is 2.5 V), the EEPROM starts to
command to download the EEPROM contents to the RAM again,
download to the RAM.
as described in the Option 3 section, restoring the ADM1166 to
4. The EEPROM downloads its contents to all Latch As.
its original configuration.
5. When the contents of the EEPROM are completely
downloaded to the Latch As, the device controller signals The topology of the ADM1166 makes this type of operation
all Latch As to download to all Latch Bs simultaneously, possible. The local, volatile registers (RAM) are all double-
completing the configuration download. buffered latches. Setting Bit 0 of the UPDCFG register to 1 leaves
6. At 0.5 ms after the configuration download completes, the first the double-buffered latches open at all times. If Bit 0 is set to 0
state definition is downloaded from the EEPROM into the SE. when a RAM write occurs across the SMBus, only the first side
of the double-buffered latch is written to. The user must then
Note that any attempt to communicate with the device prior to
write a 1 to Bit 1 of the UPDCFG register. This generates a pulse
the completion of the download causes the ADM1166 to issue
to update all the second latches at once. EEPROM writes occur
a no acknowledge (NACK).
in a similar way.
UPDATING THE CONFIGURATION The final bit in this register can enable or disable EEPROM page
After power-up, with all the configuration settings loaded from erasure. If this bit is set high, the contents of an EEPROM page can
the EEPROM into the RAM registers, the user may need to alter all be set to 1. If this bit is set low, the contents of a page cannot be
the configuration of functions on the ADM1166, such as changing erased, even if the command code for page erasure is programmed
the undervoltage or overvoltage limit of an SFD, changing the fault across the SMBus. The bit map for the UPDCFG register is shown
output of an SFD, or adjusting the rise time delay of one of the PDOs. in the AN-698 Application Note. A flow diagram for download at
The ADM1166 provides several options that allow the user to power-up and subsequent configuration updates is shown in
update the configuration over the SMBus interface. The following Figure 35.
three options are controlled in the UPDCFG register.
SMBus

POWER-UP DEVICE
(VCC > 2.5V) E CONTROLLER R U
E A P
P D M D
R A L
O T D
M A
L LATCH A LATCH B
FUNCTION
D (OV THRESHOLD
09332-035

EEPROM ON VP1)

Figure 35. Configuration Update Flow Diagram

Rev. A | Page 26 of 33
Data Sheet ADM1166
UPDATING THE SEQUENCING ENGINE Page 8 to Page 11 are available for customer use to store any
Sequencing engine (SE) functions are not updated in the same information that may be required by the customer in their
way as regular configuration latches. The SE has its own dedicated application. Customers can store information on Page 12 to
512-byte nonvolatile, electrically erasable, programmable, read- Page 15, or these pages can store the fault records written by the
only memory (EEPROM) for storing state definitions, providing sequencing engine if users have decided to enable writing of the
63 individual states each with a 64-bit word (one state is reserved). fault records for different states.
At power-up, the first state is loaded from the SE EEPROM into Data can be downloaded from the EEPROM to the RAM in one
the engine itself. When the conditions of this state are met, the of the following ways:
next state is loaded from the EEPROM into the engine, and so  At power-up, when Page 0 to Page 4 are downloaded.
on. The loading of each new state takes approximately 10 μs.
 By setting Bit 0 of the UDOWNLD register (0xD8), which
To alter a state, the required changes must be made directly to performs a user download of Page 0 to Page 4.
the EEPROM. RAM for each state does not exist. The relevant
When the sequence engine is enabled, it is not possible to access
alterations must be made to the 64-bit word, which is then
the section of EEPROM from Address 0xFA00 to Address 0xFBFF.
uploaded directly to the EEPROM.
The sequence engine must be halted before it is possible to read
INTERNAL REGISTERS or write to this range. Attempting to read or write to this range if
The ADM1166 contains a large number of data registers. The the sequence engine is not halted will generate a no acknowledge,
principal registers are the address pointer register and the or NACK.
configuration registers. Read/write access to the configuration and user EEPROM ranges
Address Pointer Register from Address 0xF800 to Address 0xF89F and Address 0xF900
The address pointer register contains the address that selects to Address 0xF9FF depends on whether the black box fault
one of the other internal registers. When writing to the ADM1166, recorder is enabled. If the fault recorder is enabled and one or
the first byte of data is always a register address that is written to more states have been set as fault record trigger states, then it is
the address pointer register. not possible to access any EEPROM location in this range
without first halting the black box. Attempts to read or write
Configuration Registers this EEPROM range while the fault recorder is operating are
The configuration registers provide control and configuration acknowledged by the device but do not return any useful data
for various operating parameters of the ADM1166. or modify the EEPROM in any way.
EEPROM If none of the states are set as fault record trigger states, then the
The ADM1166 has two 512-byte cells of nonvolatile EEPROM black box is considered disabled, and read/write access is allowed
from Address 0xF800 to Address 0xFBFF. The EEPROM is used without having to halt the black box fault recorder.
for permanent storage of data that is not lost when the ADM1166 is SERIAL BUS INTERFACE
powered down. One EEPROM cell, 0xF800 to 0xF9FF, contains the The ADM1166 is controlled via the serial system management
configuration data, user information and, if enabled, any fault bus (SMBus) and is connected to this bus as a slave device under
records of the device; the other section, 0xFA00 to 0xFBFF, contains the control of a master device. It takes approximately 1 ms after
the state definitions for the SE. Although referred to as read-only power-up for the ADM1166 to download from its EEPROM.
memory, the EEPROM can be written to, as well as read from, Therefore, access to the ADM1166 is restricted until the
using the serial bus in exactly the same way as the other registers. download is complete.
The major differences between the EEPROM and other Identifying the ADM1166 on the SMBus
registers are as follows:
The ADM1166 has a 7-bit serial bus slave address (see Table 11).
 An EEPROM location must be blank before it can be The device is powered up with a default serial bus address. The
written to. If it contains data, the data must first be erased. five MSBs of the address are set to 01101; the two LSBs are
 Writing to the EEPROM is slower than writing to the RAM. determined by the logical states of Pin A1 and Pin A0. This
 Writing to the EEPROM should be restricted because it has allows the connection of four ADM1166 devices to one SMBus.
a limited write/cycle life of typically 10,000 write operations
due to the usual EEPROM wear-out mechanisms. Table 11. Serial Bus Slave Address
A1 Pin A0 Pin Hex Address 7-Bit Address1
The first EEPROM is split into 16 (0 to 15) pages of 32 bytes each.
Low Low 0x68 0110100x
Page 0 to Page 3, from Address 0xF800 to Address 0xF89F, hold
Low High 0x6A 0110101x
the configuration data for the applications on the ADM1166
High Low 0x6C 0110110x
(such as the SFDs and PDOs). These EEPROM addresses are
High High 0x6E 0110111x
the same as the RAM register addresses, prefixed by F8. Page 5
1
to Page 7, from Address 0xF8A0 to Address 0xF8FF, are reserved. x = Read/write bit. The address is shown only as the first seven MSBs.

Rev. A | Page 27 of 33
ADM1166 Data Sheet
The device also has several identification registers (read-only) All other devices on the bus remain idle while the selected
that can be read across the SMBus. Table 12 lists these registers device waits for data to be read from or written to it. If the
with their values and functions. R/W bit is a 0, the master writes to the slave device. If the
R/W bit is a 1, the master reads from the slave device.
Table 12. Identification Register Values and Functions
2. Data is sent over the serial bus in sequences of nine clock
Name Address Value Function
pulses: eight bits of data followed by an acknowledge bit
MANID 0xF4 0x41 Manufacturer ID for Analog
from the slave device. Data transitions on the data line
Devices
must occur during the low period of the clock signal and
REVID 0xF5 0x02 Silicon revision
remain stable during the high period because a low-to-high
MARK1 0xF6 0x00 Software brand
transition when the clock is high could be interpreted as a
MARK2 0xF7 0x00 Software brand
stop signal. If the operation is a write operation, the first
data byte after the slave address is a command byte. This
General SMBus Timing command byte tells the slave device what to expect next. It
Figure 36, Figure 37, and Figure 38 are timing diagrams for may be an instruction telling the slave device to expect a
general read and write operations using the SMBus. The block write, or it may be a register address that tells the
SMBus specification defines specific conditions for different slave where subsequent data is to be written. Because data
types of read and write operations, which are discussed in the can flow in only one direction, as defined by the R/W bit,
Write Operations and the Read Operations sections. sending a command to a slave device during a read operation
The general SMBus protocol operates in the following three steps. is not possible. Before a read operation, it may be necessary
to perform a write operation to tell the slave what sort of
1. The master initiates data transfer by establishing a start
read operation to expect and/or the address from which
condition, defined as a high-to-low transition on the serial
data is to be read.
data line SDA, while the serial clock line SCL remains high.
3. When all data bytes have been read or written, stop conditions
This indicates that a data stream follows. All slave peripherals
are established. In write mode, the master pulls the data line
connected to the serial bus respond to the start condition
high during the 10th clock pulse to assert a stop condition. In
and shift in the next eight bits, consisting of a 7-bit slave
read mode, the master device releases the SDA line during the
address (MSB first) plus an R/W bit. This bit determines
low period before the ninth clock pulse, but the slave device
the direction of the data transfer, that is, whether data is
does not pull it low. This is known as a no acknowledge. The
written to or read from the slave device (0 = write, 1 = read).
master then takes the data line low during the low period
The peripheral whose address corresponds to the transmitted
before the 10th clock pulse and then high during the 10th clock
address responds by pulling the data line low during the
pulse to assert a stop condition.
low period before the ninth clock pulse, known as the
acknowledge bit, and by holding it low during the high period
of this clock pulse.

1 9 1 9
SCL

SDA 0 1 1 0 1 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0
START BY ACK. BY ACK. BY
MASTER SLAVE SLAVE
FRAME 1 FRAME 2
SLAVE ADDRESS COMMAND CODE
1 9 1 9
SCL
(CONTINUED)

SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(CONTINUED)
ACK. BY ACK. BY STOP
SLAVE SLAVE BY
FRAME 3 FRAME N MASTER
09332-036

DATA BYTE DATA BYTE

Figure 36. General SMBus Write Timing Diagram

Rev. A | Page 28 of 33
Data Sheet ADM1166
1 9 1 9
SCL

SDA 0 1 1 0 1 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0
START BY ACK. BY ACK. BY
MASTER SLAVE MASTER
FRAME 1 FRAME 2
SLAVE ADDRESS DATA BYTE
1 9 1 9
SCL
(CONTINUED)

SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(CONTINUED)
ACK. BY STOP
MASTER NO ACK. BY
FRAME 3 FRAME N MASTER

09332-037
DATA BYTE DATA BYTE

Figure 37. General SMBus Read Timing Diagram

tR tF t HD; S TA

SCL t LO W

t HD; S TA t HI G H t SU; S TA t SU; S TO

t HD; D AT t SU; D AT
SDA

09332-038
t BUF
P S S P

Figure 38. Serial Bus Timing Diagram

SMBus PROTOCOLS FOR RAM AND EEPROM EEPROM erasure cannot be done at the byte level. The EEPROM
The ADM1166 contains volatile registers (RAM) and nonvolatile is arranged as 32 pages of 32 bytes each, and an entire page
registers (EEPROM). User RAM occupies Address 0x00 to must be erased.
Address 0xDF, and the EEPROM occupies Address 0xF800 to Page erasure is enabled by setting Bit 2 in the UPDCFG register
Address 0xFBFF. (Address 0x90) to 1. If this bit is not set, page erasure cannot
Data can be written to and read from both the RAM and the occur, even if the command byte (0xFE) is programmed across
EEPROM as single data bytes. Data can be written only to the SMBus.
unprogrammed EEPROM locations. To write new data to a
programmed location, the location contents must first be erased.

Rev. A | Page 29 of 33
ADM1166 Data Sheet
WRITE OPERATIONS The master sends a command code telling the slave device
The SMBus specification defines several protocols for different to erase the page. The ADM1166 command code for a page
types of read and write operations. The following abbreviations erasure is 0xFE (1111 1110). Note that for a page erasure to
are used in Figure 39 to Figure 47: take place, the page address must be given in the previous
write word transaction (see the Write Byte/Word section). In
 S = Start addition, Bit 2 in the UPDCFG register (Address 0x90)
 P = Stop must be set to 1.
 R = Read 1 2 3 4 5 6
 W = Write COMMAND

09332-040
SLAVE
S W A BYTE A P
 A = Acknowledge ADDRESS
(0xFE)
 A = No acknowledge Figure 40. EEPROM Page Erasure
The ADM1166 uses the following SMBus write protocols. As soon as the ADM1166 receives the command byte,
Send Byte page erasure begins. The master device can send a stop
command as soon as it sends the command byte. Page
In a send byte operation, the master device sends a single
erasure takes approximately 20 ms. If the ADM1166 is
command byte to a slave device, as follows:
accessed before erasure is complete, it responds with a
1. The master device asserts a start condition on SDA. no acknowledge (NACK).
2. The master sends the 7-bit slave address followed by the
write bit (low). Write Byte/Word
3. The addressed slave device asserts an acknowledge (ACK) In a write byte/word operation, the master device sends a
on SDA. command byte and one or two data bytes to the slave device,
4. The master sends a command code. as follows:
5. The slave asserts an ACK on SDA. 1. The master device asserts a start condition on SDA.
6. The master asserts a stop condition on SDA, and the 2. The master sends the 7-bit slave address followed by the
transaction ends. write bit (low).
In the ADM1166, the send byte protocol is used for the 3. The addressed slave device asserts an ACK on SDA.
following two purposes: 4. The master sends a command code.
5. The slave asserts an ACK on SDA.
 To write a register address to the RAM for a subsequent 6. The master sends a data byte.
single byte read from the same address, or for a block read 7. The slave asserts an ACK on SDA.
or block write starting at that address, as shown in Figure 39. 8. The master sends a data byte or asserts a stop condition.
1 2 3 4 5 6 9. The slave asserts an ACK on SDA.
RAM 10. The master asserts a stop condition on SDA to end the
09332-039

SLAVE
S W A ADDRESS A P
ADDRESS (0x00 TO 0xDF) transaction.
Figure 39. Setting a RAM Address for Subsequent Read
In the ADM1166, the write byte/word protocol is used for three
 To erase a page of EEPROM memory. EEPROM memory purposes:
can be written to only if it is unprogrammed. Before writing  To write a single byte of data to the RAM. In this case, the
to one or more EEPROM memory locations that are already command byte is RAM Address 0x00 to RAM Address 0xDF,
programmed, the page(s) containing those locations must and the only data byte is the actual data, as shown in Figure 41.
first be erased. EEPROM memory is erased by writing a
1 2 3 4 5 6 7 8
command byte.
RAM
09332-041

SLAVE
S ADDRESS W A ADDRESS A DATA A P
(0x00 TO 0xDF)

Figure 41. Single Byte Write to the RAM

 To set up a 2-byte EEPROM address for a subsequent read,

write, block read, block write, or page erase. In this case, the
command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The only data byte is the low
byte of the EEPROM address, as shown in Figure 42.

Rev. A | Page 30 of 33
Data Sheet ADM1166
1 2 3 4 5 6 7 8
Unlike some EEPROM devices that limit block writes to within
EEPROM EEPROM
SLAVE ADDRESS ADDRESS a page boundary, there is no limitation on the start address

09332-042
S ADDRESS W A HIGH BYTE A A P
LOW BYTE
(0xF8 TO 0xFB) (0x00 TO 0xFF) when performing a block write to EEPROM, except when
Figure 42. Setting an EEPROM Address  There must be at least N locations from the start address to
Because a page consists of 32 bytes, only the three MSBs of the highest EEPROM address (0xFBFF) to avoid writing to
the address low byte are important for page erasure. The invalid addresses.
lower five bits of the EEPROM address low byte specify the  An address crosses a page boundary. In this case, both
addresses within a page and are ignored during an erase pages must be erased before programming.
operation.
Note that the ADM1166 features a clock extend function for writes
 To write a single byte of data to the EEPROM. In this case, to the EEPROM. Programming an EEPROM byte takes approxi-
the command byte is the high byte of EEPROM Address 0xF8 mately 250 μs, which limits the SMBus clock for repeated or block
to EEPROM Address 0xFB. The first data byte is the low write operations. The ADM1166 pulls SCL low and extends the
byte of the EEPROM address, and the second data byte is clock pulse when it cannot accept any more data.
the actual data, as shown in Figure 43.
1 2 3 4 5 6 7 8 9 10
READ OPERATIONS
EEPROM EEPROM The ADM1166 uses the following SMBus read protocols.
S SLAVE W A ADDRESS A ADDRESS A DATA A P 09332-043
ADDRESS HIGH BYTE LOW BYTE
(0xF8 TO 0xFB) (0x00 TO 0xFF) Receive Byte
Figure 43. Single Byte Write to the EEPROM In a receive byte operation, the master device receives a single
Block Write byte from a slave device, as follows:

In a block write operation, the master device writes a block of 1. The master device asserts a start condition on SDA.
data to a slave device. The start address for a block write must 2. The master sends the 7-bit slave address followed by the
have been set previously. In the ADM1166, a send byte opera- read bit (high).
tion sets a RAM address, and a write byte/word operation sets 3. The addressed slave device asserts an ACK on SDA.
an EEPROM address, as follows: 4. The master receives a data byte.
5. The master asserts a NACK on SDA.
1. The master device asserts a start condition on SDA.
6. The master asserts a stop condition on SDA, and the
2. The master sends the 7-bit slave address followed by
transaction ends.
the write bit (low).
3. The addressed slave device asserts an ACK on SDA. In the ADM1166, the receive byte protocol is used to read a
4. The master sends a command code that tells the slave single byte of data from a RAM or EEPROM location whose
device to expect a block write. The ADM1166 command address has previously been set by a send byte or write
code for a block write is 0xFC (1111 1100). byte/word operation, as shown in Figure 44.
5. The slave asserts an ACK on SDA. 1 2 3 4 5 6

6. The master sends a data byte that tells the slave device how

09332-045
S SLAVE R A DATA
ADDRESS A P
many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write. Figure 44. Single Byte Read from the EEPROM or RAM
7. The slave asserts an ACK on SDA.
8. The master sends N data bytes.
9. The slave asserts an ACK on SDA after each data byte.
10. The master asserts a stop condition on SDA to end the
transaction.
1 2 3 4 5 6 7 8 9 10

SLAVE COMMAND 0xFC BYTE DATA DATA DATA

S ADDRESS W A (BLOCK WRITE) A COUNT A A A A P
09332-044

1 2 N

Figure 45. Block Write to the EEPROM or RAM

Rev. A | Page 31 of 33
ADM1166 Data Sheet
Block Read Error Correction
In a block read operation, the master device reads a block of The ADM1166 provides the option of issuing a packet error correc-
data from a slave device. The start address for a block read must tion (PEC) byte after a write to the RAM, a write to the EEPROM,
have been set previously. In the ADM1166, this is done by a a block write to the RAM/EEPROM, or a block read from the
send byte operation to set a RAM address, or a write byte/word RAM/EEPROM. This option enables the user to verify that the data
operation to set an EEPROM address. The block read operation received by or sent from the ADM1166 is correct. The PEC byte
itself consists of a send byte operation that sends a block read is an optional byte sent after the last data byte has been written
command to the slave, immediately followed by a repeated start to or read from the ADM1166. The protocol is the same as a
and a read operation that reads out multiple data bytes, as follows: block read for Step 1 to Step 12 and then proceeds as follows:
1. The master device asserts a start condition on SDA. 13. The ADM1166 issues a PEC byte to the master. The master
2. The master sends the 7-bit slave address followed by the checks the PEC byte and issues another block read, if the
write bit (low). PEC byte is incorrect.
3. The addressed slave device asserts an ACK on SDA. 14. A NACK is generated after the PEC byte to signal the end
4. The master sends a command code that tells the slave of the read.
device to expect a block read. The ADM1166 command 15. The master asserts a stop condition on SDA to end the
code for a block read is 0xFD (1111 1101). transaction.
5. The slave asserts an ACK on SDA. Note that the PEC byte is calculated using CRC-8. The frame
6. The master asserts a repeat start condition on SDA. check sequence (FCS) conforms to CRC-8 by the polynomial
7. The master sends the 7-bit slave address followed by the
read bit (high). C(x) = x8 + x2 + x1 + 1
8. The slave asserts an ACK on SDA. See the SMBus Version 1.1 specification for details. An example
9. The ADM1166 sends a byte-count data byte that tells the of a block read with the optional PEC byte is shown in Figure 47.
master how many data bytes to expect. The ADM1166
always returns 32 data bytes (0x20), which is the maximum
allowed by the SMBus Version 1.1 specification.
10. The master asserts an ACK on SDA.
11. The master receives 32 data bytes.
12. The master asserts an ACK on SDA after each data byte.
13. The master asserts a stop condition on SDA to end the
transaction.

1 2 3 4 5 6 7 8 9 10 11 12

S SLAVE W A COMMAND 0xFD A S SLAVE R A BYTE A DATA A

ADDRESS (BLOCK READ) ADDRESS COUNT 1

13

DATA
09332-046

A P
32

Figure 46. Block Read from the EEPROM or RAM

1 2 3 4 5 6 7 8 9 10 11 12

S SLAVE W A COMMAND 0xFD A S SLAVE R A BYTE A DATA A

ADDRESS (BLOCK READ) ADDRESS COUNT 1

13 14 15

DATA
09332-047

A PEC A P
32

Figure 47. Block Read from the EEPROM or RAM with PEC

Rev. A | Page 32 of 33
Data Sheet ADM1166

OUTLINE DIMENSIONS
6.10 0.30
6.00 SQ 0.25
PIN 1 5.90 0.18
INDICATOR PIN 1
31 40
INDICATOR
30 1

0.50
BSC *4.70
EXPOSED
PAD 4.60 SQ
4.50

21 10
20 11
0.45 0.20 MIN
TOP VIEW 0.40 BOTTOM VIEW
0.35 FOR PROPER CONNECTION OF
0.80 THE EXPOSED PAD, REFER TO
0.75 THE PIN CONFIGURATION AND
0.05 MAX FUNCTION DESCRIPTIONS
0.70 SECTION OF THIS DATA SHEET.
0.02 NOM
COPLANARITY
0.08
SEATING 0.20 REF
PLANE

02-02-2010-A
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.

Figure 48. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

6 mm × 6 mm Body, Very Thin Quad
(CP-40-7)
Dimensions shown in millimeters

1.20 9.00
0.75 MAX BSC SQ
0.60
0.45 48 37
1 36

PIN 1
7.00
TOP VIEW BSC SQ
1.05 0° MIN
0.20 (PINS DOWN)
1.00 0.09
0.95 7°
3.5° 12 25
0.15 0° 13 24
SEATING
0.05 PLANE 0.08 MAX
COPLANARITY VIEW A 0.50 0.27
BSC 0.22
LEAD PITCH
VIEW A 0.17
ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026ABC

Figure 49. 48-Lead Thin Plastic Quad Flat Package [TQFP]

(SU-48)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADM1166ACPZ −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-40-7
ADM1166ACPZ-REEL −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-40-7
ADM1166ASUZ −40°C to +85°C 48-Lead Thin Plastic Quad Flat Package [TQFP] SU-48
ADM1166ASUZ-REEL7 −40°C to +85°C 48-Lead Thin Plastic Quad Flat Package [TQFP] SU-48
EVAL-ADM1166TQEBZ Evaluation Kit [TQFP]
1
Z = RoHS Compliant Part.

©2010–2015 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D09332-0-3/15(A)

Rev. A | Page 33 of 33