VLSI DESIGN FOR TESTABILITY
AN INTERNSHIP REPORT
submitted in partial fulfillment of the requirements
for the award of
BACHELOR OF TECHNOLOGY
in
ELECTRONICS & COMMUNICATION ENGINEERING
by
BHAROVATHU GAYATHRI
(22761A04D7)
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
LAKIREDDY BALI REDDY COLLEGE OF ENGINEERING
(AUTONOMOUS)
[Link] Nagar,Mylavaram – 521 230.
Affiliated to JNTUK, Kakinada & Approved by AICTE, New Delhi
Accredited by NBA (under tier-I) and NAAC
Certified by ISO 21001:2018
2024- 2025
LAKIREDDY BALI REDDY COLLEGE OF
ENGINEERING(AUTONOMOUS)
[Link] Nagar, Mylavaram – 521 230.
Affiliated to JNTUK, Kakinada & Approved by AICTE, New Delhi
Accredited by NBA and NAAC, Certified by ISO 21001:2018
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
CERTIFICATE
This is to certify that the Internship entitled “VLSI DESIGN FOR
TESTABILITY”is a bonafide work done in BIST TECHNOLOGIES
[Link]., in Association with APSCHE and submitted by BHAROVATHU
GAYATHRI (22761A04D7)in partial fulfillment of requirement for the
award of Bachelor of Technology in Electronics and Communication
Engineering in Lakireddy Bali Reddy College of Engineering, Mylavaram
during the academic year 2023-2024.
Dr. G. Srinivasulu
Internship Coordinator Professor & HOD
ACKNOWLEDGEMENT
The Satisfaction that accompanies that the successful completion of
any task would be incomplete without the mention of people whose
ceaseless co-operation made it possible, whose constant guidance and
encouragement crown all efforts with success.
I humbly express our thanks to our Principal Dr. K. Appa Rao for
extending his support and for providing us with an environment to
complete our Internship successfully.
I would also like to thank our Vice Principal, Dr. B. Ramesh Reddy
for encouraging us which certainly helped to complete the internship in
time.
I deeply indebted to our Head of Department Dr. G. Srinivasulu,
who modeled us both technically and morally for achieving greater success
in life.
I would like to express our heart full thanks to our parents for their
unflinching support and constant encouragement throughout the period of
our Internship work for making it a successful one.
I would like to thank all the teaching and non-teaching staff
members of Electronics and Communication Engineering, who have
extended their full co-operation during the course of our Internship.
I thank all our friends who helped us sharing knowledge and by
providing material to complete the Internship in time.
BHAROVATHU GAYATHRI
(22761A04D7)
Table of Contents
1. INTRODUCTION 1
1.1 Introduction To VLSI 1
1.2 VLSI Design Process 2
1.3 Applications and Future Trends 2
2. DESIGN FOR TESTABILITY 3
2.1 Introduction To DesignFor Testability 3
2.2 Design For Testability Flow 3
3. PHASES OF PHYSICAL DESIGN 5
3.1 Design For Testability Steps 5
3.2 Scan chain insertion phase 6
4. CONCLUSION 7
List of Figures
Fig. No. Fig. Name Page. No.
1.1 VLSI Technology 1
2.1 Design For Testability Flow 4
3.2 Scan chain insertion phase 6
