2 to 4 decoder
entity dec is
Port ( i : in STD_LOGIC_VECTOR (1 downto 0);
o : out STD_LOGIC_VECTOR (3 downto 0);
en : in STD_LOGIC);
end dec;
architecture Behavioral of dec is
begin
process (en,i)
begin
if (en = '1') then
if ( i = "00" ) then
o <= "0001";
elsif (i = "01") then
o <= "0010";
elsif (i = "10") then
o <= "0100";
else o <= "1000";
end if;
else o<= "0000";
end if;
end process;
end Behavioral;
4 to 1 MUX
entity mux4to1 is
port ( w0, w1, w2, w3 : in std_logic ; s : in std_logic_vector(1 downto 0) ;
f : out std_logic ) ;
end mux4to1 ;
architecture behavior of mux4to1 is
Begin
Process(s,w0,w1,w2,w3)
begin
case s is
when "00" => f <= w0;
when "01" => f <= w1;
when "10" => f <= w2;
When others => f <= w3;
End case;
End process;
end behavior ;
PARALLEL ADDER
Entity parallel_adder is
port ( a,b : in std_logic_vector (3 downto 0); cin : in std_logic ;
O : out std_logic_vector (4 downto 0)) ;
End parallel_adder ;
architecture behavior of parallel_adder is
Begin
Process(a,b,cin)
Variable c : std_logic;
Begin
C := cin;
For i in 0 to 3 loop
O(i) <= a(i) xor b(i) xor c;
C := (a(i) and b(i)) or (a(i) and c) or ( b(i) and c);
End loop;
O(4) <= c;
End process;
end behavior ;
SR LATCH
entity srlatch is
port(r,s:in std_logic ; q,qbar:out std_logic);
end srlatch;
architecture behav of srlatch is
begin
process (s,r)
variable s1: std_logic:= '0';
variable r1: std_logic:= '1';
begin
s1:= s nand r1;
r1:= r nand s1;
q <= s1;
qbar <= r1;
end process; end behav;
JK FLIPFLOP
entity jk1 is
port (j,k,clk:in std_logic ; q:inout std_logic:= '0';qbar:inout std_logic:= '1');
end jk1;
architecture behav of jk1 is
begin
process (j,k,clk)
variable s1,r1: std_logic;
begin
s1 := '0';
r1 := '1';
if (clk = '1' and clk' event) then
s1:= (j and qbar) or ( not(k) and q);
r1:= not (s1);
q <= s1;
qbar <= r1;
else
q <= q;
qbar <= qbar;
end if;
end process;
SISO REGISTER
Entity siso is
Port (din,clk,clr : in std_logic; q : inout std_logic);
End siso;
Architecture behav of siso is
signal q1:std_logic_vector (3 downto 0) := "0000";
begin
Process(din,clk,clr,q1)
Begin
If (clr = '1') then
q <= '0';
q1 <= "0000";
elsIf (clk = '1' and clk'event) then
q1(0) <= din;
For I in 0 to 2 loop
q1(i+1) <= q1(i) ;
End loop;
q <= q1(3);
Else q <= q;
End if;
End process;
End behav;
SIPO REGISTER
entity sipo is
port(
clk, clear : in std_logic;
Input_Data: in std_logic;
Q: inout std_logic_vector(3 downto 0) );
end sipo;
architecture arch of sipo is
begin
process (clk)
begin
if clear = '1' then
Q <= "0000";
elsif (CLK'event and CLK='1') then
Q(3 downto 1) <= Q(2 downto 0);
Q(0) <= Input_Data;
end if;
end process;
end arch;
PISO REGISTER
Entity piso is
Port (clk,clr,en : in std_logic; pin : in std_logic_vector (3 downto 0);q : inout std_logic);
End piso;
Architecture behav of piso is
signal q1:std_logic_vector (3 downto 0) := "0000";
begin
Process(clk,clr,q1,pin,en)
Begin
If (clr = '1') then
q <= '0';
q1 <= "0000";
elsIf (clk = '1' and clk'event) then
q1(3) <= pin(3);
For I in 2 downto 0 loop
If (en = '0') then
Q1(i) <= q1(i+1);
Else q1(i) <= pin(i);
End if;
End loop ;
q <= q1(0);
Else q <= q;
End if;
End process;
End behav;
UP-DOWN COUNTER
entity updown_count is
Port ( clk,rst,updown : in STD_LOGIC; count : out STD_LOGIC_VECTOR (3 downto 0));
end updown_count;
architecture Behavioral of updown_count is
signal temp:std_logic_vector(3 downto 0):="0000";
begin
process(clk,rst)
begin
if(rst='1')then
temp<="0000";
elsif(rising_edge(clk))then
if(updown='0')then
temp<=temp+1;
else temp<=temp-1;
end if;
end if;
end process;
count<=temp;
end Behavioral;
MOD-10 COUNTER
entity mod10_counter is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR(3 downto 0)
);
end mod10_counter;
architecture behav of mod10_counter is
begin
counter : process (clk,reset) is
variable m : integer range 0 to 15 := 0;
begin
if (reset='1') then
m := 0;
elsif (rising_edge (clk)) then
m := m + 1;
end if;
if (m=10) then
m := 0;
end if;
dout <= conv_std_logic_vector (m,4);
end process counter;
end behav;
