ARM Cortex M3
Implementation Overview
Dr. C. GANESH KUMAR
Pipeline
• Three Stage Pipeline.
• Processor will not fetch instructions in every cycle – Mostly during 16-bit instructions two
instructions are fetched (32-bit) in one time.
• Buffer → Instructions are queued before they are needed.
25-01-2023 Embedded Computing (19CCE211) 2
Pipeline
Normal Pipeline Branch Pipeline
BL
LDR Pipeline
25-01-2023 Embedded Computing (19CCE211) 3
Detailed Block Diagram
• Cortex – M3 core → Contains registers, ALU, data
path, and bus interface.
• BusMatrix → Cortex – M3 internal bus system (AHB).
Supports simultaneous transfer. Supports Bit
Orientation Operations.
• NVIC → Supports Nested Interrupt Handling,
Vectored Interrupt.
• SYSTICK → Countdown Timer . It’s a Part of NVIC.
Reload value should be N-1.
• WIC → Wakeup from interrupt events when
processor is powered down.
• MPU → Protect Memory Unit.
• AHB to APB → Bridge connects APB devices,
debugging components.
25-01-2023 Embedded Computing (19CCE211) 4
Detailed Block Diagram
• ETM → Instruction Trace for debug
• Breakpoint → Run-Stop Debug (Up to 8 breakpoints)
• DWT → Data address or data value match is found (Logic
Analyzer)
• ITM → Interrupt Execution (Interrupts executed Cycle,
Execution Time)
• TPIU → Interface External Trace Hardware.
Example: Trace Port Analysers.
• FPB → Flash Patch and Breakpoint – Instruction access
by the CPU matches a certain address.
• ROM Table → Locate memory addresses of debugging
components.
25-01-2023 Embedded Computing (19CCE211) 5
Memory Map
• 4 GB Memory Space
• Cortex-M3 design has an internal bus
infrastructure optimized for this memory
usage.
• Program code can be located in the
code region, the Static Random Access
Memory (SRAM) region, or the external
RAM region
• In SRAM and Peripheral:
Bit-band operation → applies only to data
accesses
25-01-2023 Embedded Computing (19CCE211) 6
Bus Interface
Main bus Interfaces:
• Code Memory Bus → Code memory access (i) I-Code and (ii) D-Code
• System Bus → System bus is used to access memory and peripherals
• Private Peripheral Bus → Access memory dedicated to private peripherals
25-01-2023 Embedded Computing (19CCE211) 7
Bus Interface on Cortex-M3
• I-Code Bus → 32- bit bus – AHB-Lite Bus →
Instruction fetch in 0x00000000 to 0x1FFFFFFF
• D-Code Bus → 32- bit bus – AHB-Lite Bus → Data
access in 0x00000000 to 0x1FFFFFFF
• System Bus → 32- bit bus – AHB-Lite Bus →
Instruction Fetch and Data access in 0x20000000
to 0xDFFFFFFF and 0xE0100000 to 0xFFFFFFFF
• External PPB Bus → 32- bit bus – APB Bus →
Private Peripheral access in 0xE0042000 to
0xE00FF000
• DAP Bus → 32 – bit bus – APB Bus → Debug
interface block
25-01-2023 Embedded Computing (19CCE211) 8
Operation Modes
• Cortex M3 has two modes and two privilege
levels When running an exception handler
• operation modes (thread mode and handler When running a main program
mode) determine whether the processor is
running a normal program or running an
exception handler like an interrupt handler
• The privilege levels (privileged level and user
level) provide a mechanism for safeguarding
memory accesses
• Resetting processor will return to → Thread
mode, Privileged Level
25-01-2023 Embedded Computing (19CCE211) 9
