Data Acquisition Texas Instruments Incorporated

Clocking high-speed data converters

By Eduardo Bartolome, High-Speed ADC Systems and Applications Manager (Email: [email protected]),
Vineet Mishra, High-Speed ADC Design Engineer (Email: [email protected]),
Goutam Dutta, High-Speed ADC Test Engineer (Email: [email protected]),
and David Smith, High-Speed ADC Test Engineer (Email: [email protected])
Introduction Figure 1. Simplified model of clock circuit in high-speed ADC
In circuit design that involves the use of a
high-performance, high-speed analog-to- S&H
digital converter (ADC) such as the ADC
ADS5500, one of the main careabouts is Input Quantizer
the clocking scheme. Questions about the
N1
type of clock to be used (sinusoidal or
square), the voltage levels, or the jitter are N3
Clk+
common. The purpose of this article is to A
explain the general theory to support the Clk – Delay
circuit designer in making the right choices. Locked
Figure 1 shows a simplified model of the N2 Loop
clock circuit inside a high-speed ADC like (DLL)
the ADS5500. Although not all ADCs have
exactly the same internal blocks in their
clock distribution, this diagram can be
modified to fit your particular ADC. Since nowadays most A mathematical estimation of the best-case signal-to-
of the circuits sold as ADCs include a front sample-and-hold noise ratio (SNR) (without other noise sources), given a
(S&H), for the purpose of this article we will differentiate certain amount of jitter, can be extracted from Figure 2.
between them. The circuit that takes an instantaneous Given a sinusoidal input of amplitude A and frequency fIN
analog snapshot of the input signal will be called the S&H; (1/T), the uncertainty of the sampled voltage at a given
and the ADC itself, which converts the analog value being point will be proportional to the slope of the input signal
held by the S&H into quantized digital output, will be called at that instant and to the uncertainty of the sampling
the quantizer. Analyzing what parameters of the internal instant (jitter, which is the rms value of that variation,
clock are important for these two circuits will help us
understand the main careabouts in our external clock design.
Figure 2. Voltage error relation to sampling jitter
Errors in the sampling instant
The conversion process starts when a clock signal tells the
S&H to take the sample. Up to that instant, the internal
switch on the S&H circuit has been closed, allowing the
voltage across the capacitor to track the input signal
(which is why other literature more properly calls this ∆V
circuit “track and hold”). One of the edges of the input
clock then indicates when to open this switch, and the
capacitor holds the voltage at that instant in time. This
instant is represented in Figure 2 by a vertical solid line.
Any error in that instant (∆t) will translate as an error in
voltage (∆V) dependent on the input signal slope. The ∆t
error in that instant is what we will call jitter.

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Texas Instruments Incorporated Data Acquisition

uncorrelated with the input level). The total uncertainty is the addition of all the uncertainties at each point of the sinusoid
weighted by the probability of sampling each of the points:
2
  2πτ  
T T  d  A sin T  
∫0 (Slope( τ ) × Jitter )2dτ = T ∫
1 1
σ 2Jitter =  Jitter  dτ
T 0  dτ 
 
 
2
 2πτ 
T  2πA cos
T  dτ = a = 2πτ , da = 2π
∫0 
1
= Jitter 2 
T T T dτ T

 
2 2π 2
T  2πA  T  2πA  2π
∫0
1 11
=
2π  T 
Jitter 2
T
(cos2 a )da =
2π  T 
Jitter 2
T2
(a + sin a × cos a ) |0
2 2
T  2πA  1 1  2πA 
=   Jitter 2 π =  Jitter 2
2π  T  T 2  T 
The theoretical limitation of the SNR due to jitter is given by
 
 A2 
SNR (dBc ) = = 10 log10   = −20 log ( 2π f Jitter ).
S 2 (1)
2  10 IN
 1  2πA  Jitter 2 
N
 2  T  

Figure 3 shows this limitation as a function of the input frequency.

Observe that increasing or decreasing the input amplitude (AIN) has no effect on the SNR component coming from
jitter. In other words, as we decrease the input amplitude, the amount of error due to the jitter also becomes smaller.
Nevertheless, there are other sources of error, like thermal noise, that do not get smaller. Assuming all these sources of
noise are uncorrelated, the total noise is the addition of a noise term independent of input frequency and a noise term
dependent on input frequency (jitter):
  A
2 
   

SNR (dBc ) = 10 log10 
2  (2)
2 
 Thermal + Quantization + 1  2πA 
  Jitter 2 
 2 T  

Figure 3. Limitation of the SNR due to jitter

as a function of input frequency

110
0.1 ps
100 0.2 ps
0.4 ps
90 0.8 ps
SNR (dBc)

1.6 ps
80 3.2 ps
70
60

50

40
10 100 1000
fIN (MHz)

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 Data Acquisition Texas Instruments Incorporated

For a given ADC, below a certain input amplitude, the

Figure 4. ADS5542 typical noise-floor
SNR is dominated by those other sources and jitter measurement
becomes irrelevant. One way of showing this is plotting
the noise floor in dBFS with respect to the AIN. Figure 4
–67
shows a real noise-floor example of the ADS5542 operating
–68 Measured
at 78 MSPS and 230-MHz input. Thermal

Noise Floor (dBFS)

Note that the theoretical trace, computed by adding the –69 Theoretical
effect of 250 fs of jitter and about 1 LSB of thermal noise –70 Jitter
(idle channel noise; i.e., noise floor with no ADC input), –71
very closely follows the measured performance. This effect –72
is especially important when we compute the theoretical –73
effects of jitter in our system and try to choose the right –74
ADC and clocking. Specifically, it shows that for certain –75
systems, ADC data taken at –1 dBFS may give us too pessi-
–76
mistic a result, as the signal may seldom reach those levels. –60 –50 –40 –30 –20 –10 0
Figure 5 (extracted from Reference 1) shows the SNR AIN (dBFS)
versus input and sampling frequencies. This measured
plot correlates with Equation 2. How can we explain the
degradation observed in the SNR as input frequency (fIN)
increases for a fixed sampling frequency (fS)? Assume that fS/fIN ratio? In other words, given a certain amount of
a full-scale sinusoid at low input frequencies is unaffected phase noise in our clock, will its effect be much worse in
by jitter and that, as we increase the frequency of that the case of 65-MSPS/150-MHz input frequency than in
sinusoid, the SNR will be degraded exclusively by clock the case of 125-MSPS/150-MHz input frequency? From
jitter. In that case, for a given fS, we can estimate a value Equation 2 it is obvious that fS has nothing to do with SNR
for clock jitter. Table 1 shows the measured SNR for jitter. Nevertheless, we observe that as we decrease fS
fS = 60 MSPS (see the red horizontal dashed line in (following the blue vertical dashed line in Figure 5), the
Figure 5) versus the estimated SNR using Equation 2 SNR degrades, which seems counterintuitive.
and assuming a jitter of 200 fs. We know that by increasing the input waveform’s number
So Equation 2 seems to model variation in the SNR of hits per cycle, even with the same likelihood of error on
versus fIN very well. What about SNR variation versus fS? each sample, we will “average out” the bigger portion of
Does the jitter effect on the noise floor depend on the the noise. In other words, as we get more samples, each

Table 1. Measured vs. estimated SNR

fIN (MHz) 2.00 10.01 15.51 30.00 60.04 70.04 80.01 100.00 125.01 150.00 190.04 225.03 300.02
Measured SNR (dBFS) 73.35 72.84 73.13 72.96 72.75 72.54 72.55 71.68 71.50 69.72 69.61 69.22 67.63
Estimated SNR (dBFS) 73.35 73.34 73.32 73.22 72.85 72.68 72.49 72.08 71.49 70.88 69.86 68.99 67.25

Figure 5. SNR with digital phase lock loop off

80
71 69
70
72
Sampling Frequency, fS (MSPS)

73
70
72
73 70
60
SNR (dBFS)

69 68
68
50 71
70
67
66
40 72
73

30 69
68 64
73 67
66
70
20 71 71 66
65 62
69 64
67
72 63
68
62
10 60
0 50 100 150 200 250 300
Input Frequency, fIN (MHz)

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Texas Instruments Incorporated Data Acquisition

one with the same amount of error, the “average” of those

Figure 6. Evaluating the clock rising edge
will be more precise. This is no different than the standard
concept of process gain. Considering the frequency
∆t Clk+
domain, an increase in the sampling frequency will spread
the same amount of noise over a bigger bandwidth, effec- N1
∆V
tively reducing the noise floor. Usually we care about the
in-band noise in our signal. Doubling the frequency of our
A
clock will reduce the noise floor by half (i.e., 3 dB).
Nevertheless, when we compute the SNR, we integrate all
∆V N2
the noise; so this does not explain the SNR degradation
that occurs as we decrease fS. For an explanation we have
Clk–
to introduce a new factor, a new jitter that will not be the
same for different sampling frequencies. A further look at
Figure 1 will help us understand this SNR degradation.
Note that so far we have been talking about jitter gener- • “Squares” the input clock signal (if sinusoidal) to gener-
ically as a total jitter budget allocated to our system. The ate the internal digital clocks. The amplifier is usually
sources for jitter can be external (such as a clock provided followed by logic circuits to distribute the clock to the
by the user) or internal in the ADC. Jitter is a form of internal blocks of the ADC.
simplification (“integration”) of a more specific parameter Although ADC designers optimize this circuit to minimize
called phase noise. The relationship between jitter and jitter, there are always limitations set by the process,
phase noise is explained in References 2 and 3. Disregard- power, and other trade-offs. ADC users can model this
ing those details, ADC users should at least be aware that circuit knowing that it adds a certain noise voltage to the
not all phase noise in the clock will affect the system input clock before amplification takes place.
equally. Phase noise very close to the carrier reflects slow In Figure 6 we represent only the rising edge of the
variation in the sampling instant, which may not be relevant clock, assuming that this is the edge used to open the
in systems with a “short” observation time. Phase noise for switch on the S&H circuit (i.e., the edge indicating when
larger offsets away from the carrier may be more important to hold the sample). Note that the jitter on the other edge
but at the same time easier to filter out. It is important to theoretically has no effect on the SNR. For simplicity we
note that currently ADCs do not provide any mechanism are also assuming that the slopes of the edge on the posi-
to reject any incoming jitter. On the contrary, the clock tive (Clk+) and negative (Clk–) lines of the clock are the
chain inside the ADC adds to the jitter degradation. There same (which may not be true, but this has no effect on the
will always be a delay between initiation of the clock signal following reasoning).
and the time when the S&H goes into the hold mode. While Although the sources of noise are internal (N1, N2),
the mean of that delay, commonly referred to as “aperture their final effect on performance can be minimized by the
delay,” does not produce a nondeterministic error, the user. Specifically, if the input clock has infinite slope, the
variation in that delay will create an error. Some of that addition of any (voltage) noise to that edge will not affect
variation will come from noise sources inside the ADC the time position of the edge. As the edge becomes slower,
(represented as N3 in Figure 1), which the user cannot the effect of adding any voltage noise will produce a bigger
influence except by modifying some of the external condi- variation in time. In the case where the clock is a sinusoidal
tions such as temperature or supply. Nevertheless, there signal, increasing the amplitude or the sampling frequency
are some techniques the user can apply to minimize the will increase the slope of the edge. We should have the
influence of other internal sources of noise (N1 and N2). same jitter when we double the sampling frequency as
We will center the discussion around this topic. when we double the clock amplitude. All this can be
As shown in Figure 1, the first stage in the internal expressed in the following equation:
clock chain is an amplifier. Texas Instruments usually
includes such a circuit to present a more clock-friendly ( JitterTotal )2 = ( JitterExternal )2 + ( JitterN 3 )2 + ( JitterN1,N 2 )2
interface to the user, with the following features: 2
 K( N1, N 2)  (3)
• High input impedance to reduce clock driver load. = ( JitterExternal )2 + ( JitterN 3 )2 +   ,
 Clk _ slope 
• Differential amplifier that supports either differential or
single-ended inputs. where K(N1, N2) represents the input amplifier jitter
• Amplifier to support smaller clock swings. contribution and is constant for each ADC.

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 Data Acquisition Texas Instruments Incorporated

Let’s take a look at Figure 7 (adapted from Figure 17 in

Figure 7. AC performance vs. clock level
Reference 4). This figure really shows how to squeeze the
last dB from the SNR at high input frequency. In line with
SFDR SE 3.3
the previous discussion, one of the first things that catches 77 SFDR Diff 3.3
our attention is that as we increase the clock amplitude, 75 fS = 65 MSPS SFDR SE 1.8
fIN = 190 MHz SFDR Diff 1.8

AC Performance (dB)
the SNR improves. We are just minimizing the effect of the 73
71 (See Note)
third term of Equation 3, improving the SNR to a point
69
where the jitter coming from external sources and from
67
N3 will be dominant and any further improvement in the 65
third term will be irrelevant. Fitting the results from this 63 SNR SE 1.8
model to the measured data (in this case, for differential SNR Diff 1.8
61
SNR SE 3.3
clocking with 3.3-V OVDD, using the curve labeled “SNR 59 SNR Diff 3.3
Diff 3.3”), we can obtain the constants for Equation 3: 57 (See Note)
55
• Adding terms 1 and 2 (we cannot distinguish between 0 1 2 3 4 5 6
them unless other measuring techniques are applied) Clock Level, VPP* (VPP)
will give us a total jitter of 300 fs. Given the purity of *Measured from CLK to CLKC
our sources in the lab, we can assume that all this jitter Note: SE = Single-ended clock with OVDD = 1.8 V or 3.3 V
Diff = Differential clock with OVDD = 1.8 V or 3.3 V
is coming from the ADS5413 and thus from N3.
• K(N1,N2) will be 160 µV.
The final equation will be Figure 8. Measured SNR vs. SNR estimated
2
 160 µV  with Equation 4
( JitterTotal )2 = (300 fs)2 + 
 Clk_slope 
. (4)
66
Figure 8 and Table 2 compare the result of Equation 4 65
with the real data. 64
Note that a clock slope of about 1 V/ns—i.e., a CMOS 63
SNR (dBFS)

edge of 3.3 ns—will be sufficient to obtain the maximum 62

performance from our ADC. If the clock is sinusoidal, we 61
will require a peak-to-peak differential clock of about 4 V. 60
Measured SNR
59
With a single-ended clock, 3.3 VPP will be about the maxi- Estimated SNR
58
mum we can provide without exceeding the supply rails
57
and turning on the internal protections. Using a differential
56
clock will let us increase the clock amplitude to double 0 1000 2000 3000 4000 5000 6000 7000
that amount. This is one of the advantages of using differ- Differential Clock Amplitude (mVPP)
ential clocking. The other is the rejection of common-mode
noise signals. Nevertheless, observe that in Figure 7 the
performance of the single-ended clock for small amplitudes Table 2. Measured SNR vs. SNR estimated with Equation 4
is actually slightly better than that of the differential clock. MEASURED ESTIMATED ESTIMATED
Besides a possible repeatability error between measure- CLOCK SNR JITTER SNR SLOPE
ments, this could also be due to an imbalance between (mVPP) (dBFS) (ps) (dBFS) (V/ns)
the two clock lines (a different N1 versus N2), so that the 820 56.79 1 58.00 0.17
differential clock performance is actually an average of the 1180 59.95 0.73 60.44 0.24
independent single-ended performances. Another trend to
1380 60.97 0.64 61.35 0.28
observe is that when the digital output voltage is increased,
1700 62.44 0.55 62.40 0.35
in this case from 1.8 V to 3.3 V, more switching noise is pro-
duced that seems to couple to the clock circuit, as the degra- 2070 63.47 0.48 63.23 0.42
dation seems to be smaller at lower input frequencies (see 2400 63.96 0.44 63.74 0.49
Figure 9, which was adapted from Figure 19 in Reference 4). 2720 64.34 0.41 64.10 0.56
Finally, note that the clock amplitude has little or no effect 3000 64.59 0.4 64.35 0.61
on the distortion spurious-free dynamic range. 3420 65 0.38 64.62 0.70
3970 65.21 0.36 64.87 0.81
4570 65.28 0.34 65.06 0.93
5050 65.24 0.34 65.17 1.03
5390 65.39 0.33 65.23 1.10
5680 65.26 0.33 65.27 1.16
6020 65.26 0.33 65.32 1.23

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Texas Instruments Incorporated Data Acquisition

With this new piece of information, we can now go back

Figure 9. SNR vs. input frequency
to Figure 5 and see if we can estimate the SNR degradation
as we decrease the sample rate. Using a process similar to
the one we used before, we can estimate the coefficients 70
DCA Off
DCA* Off
for Equation 3 that will predict the SNR across sampling BP Filter
BP** Filter OV = 1.8 V
68 DD
and input frequencies with less than 1 dB of error:
2 66
 40 µV 

SNR (dBFS)
( JitterTotal )2 = ( 250 fs)2 + 
 Clk_slope 
(5)
64
DCA On
BP Filter
The result of applying this model can be seen in Figure 62
10a. Figure 10b shows the original data from Figure 5 for DCA On
60 fS = 65 MSPS No Filter DCA Off
easy comparison.
No Filter
Following are some implications from this model: 58
• The SNR degradation at lower fS seen in Figure 5 0 50 100 150 200 250
occurred because the plot was taken with a fixed 3-VPP Input Frequency, fIN (MHz)
sinusoidal clock that reduced the slope on its edges as *DCA = duty cycle adjuster
we decreased its frequency. **BP = bandpass

• A direct implication of this is that the data sheet actually

shows worse performance than what a user could obtain
with a different clocking scheme.

Figure 10. Measured SNR vs. SNR estimated with Equation 5

SNR (dBFS)
300 300
73-74
225 225
72-73
190 190
Input Frequency, fIN (MHz) (Nonlinear)

Input Frequency, fIN (MHz) (Nonlinear) 71-72

150 150

125 125 70-71

100 100 69-70

80 80
68-69

70 70
67-68
60 60
66-67
30 30
65-66
15 15
64-65
10 10

2 2 63-64
10 20 30 50 60 80 10 20 30 50 60 80
Sampling Frequency, fS (MSPS) Sampling Frequency, fS (MSPS) 62-63
(Nonlinear) (Nonlinear)

(a) Estimated SNR from Equation 5 (b) Measured SNR

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 Data Acquisition Texas Instruments Incorporated

• A first possible approach is to use a step-up transformer Another problem, as ADCs become faster and faster, is
to increase the slope of the sinusoidal clock signal. A pair to squeeze the maximum performance from the timing
of clipping diodes (for example, MAX3X71600LCT-ND) design. Open-loop designs of the internal clock circuit
can be used to limit the amplitude and avoid exceeding tend to leave some margin for supply and temperature
the supply rails of the ADC. This is a clean way of gen- variations, which at high clock rates means that time that
erating a square-like clock signal. could be used to settle the stage is being left just for a
• Another method to square the sinusoidal clock signal is margin. To optimize the timing, closed-loop designs, like
to use an external gate (like a PECL device) acting as a delay locked loop (DLL)-based clocks, can be employed.
comparator. This minimizes the effect of N1 and N2 but Many users wonder if the jitter of the DLL will affect the
transfers the problem to the equivalent N1 and N2 at performance. Notice in Figure 1 that the DLL is not in the
the input of the comparator. Many of these commercial path of the S&H. Nevertheless, the issue is that basic DLL
circuits have very good jitter numbers, but these num- designs have a range of frequencies of operation; so, if they
bers stem from the assumption that the input is square; are designed for the higher clocking rates, they will not be
so important degradation could be seen if a sinusoidal able to operate properly at the lower ones. Also, use of the
clock were used. In many cases the input of the ADC will DLL means that the clock is synchronous—i.e., periodic,
be a much better squaring circuit than the external gate. not burst or pulsed. For applications requiring lower clock
• Ideally we would like to use a very low-jitter clock rates or asynchronous clocking, the ADS5500 includes the
source with square outputs. One good approximation is possibility of bypassing the DLL.
the use of a voltage-controlled crystal oscillator (VCXO) References
with the CDC7005. The use of that circuit will be limited,
For more information related to this article, you can down-
in principle, by the phase noise quality of the VCXO and
load an Acrobat Reader file at www-s.ti.com/sc/techlit/
some degradation that the CDC7005 may add. Also, this
litnumber and replace “litnumber” with the TI Lit. # for
circuit will save a transformer to generate the differen-
the materials listed below.
tial clocking.
• Using an external bandpass filter3,5 will clean up the jitter Document Title TI Lit. #
on the clock. Nevertheless, the insertion loss of the filter 1. “14-Bit, 125MSPS Analog-to-Digital
will attenuate the amplitude of the clock, reducing the Converter,” ADS5500 Data Sheet, p. 17 . . . . . . .sbas303
slope and increasing the effects of N1 and N2. Further 2. A. Zanchi, A. Bonfanti, S. Levantino, and
amplification (prior to filtering) or a step-up transformer C. Samori, “General SSCR vs. cycle-to-cycle
can be used to minimize this attenuation. jitter relationship with application to the phase
• So far we have been estimating jitter indirectly from the noise in PLL,” Proceedings of the 2001 IEEE
SNR degradation, but there could be other reasons for Southwest Symposium on Mixed-Signal
SNR degradation. A method to measure jitter directly on Design (Austin, TX, Feb. 25–27, 2001),
an ADC is described in Reference 5. pp. 32–37. —
3. Alfio Zanchi, “How to Calculate the Period
Errors in the quantizer Jitter σT from the SSCR L(fn) with
The quantizer will, after the sample-and-hold, take the Application to Clock Sources for High-Speed
voltage across the capacitor and convert it into a digital ADCs,” Application Note . . . . . . . . . . . . . . . . . . .slwa028
code. As the S&H is holding the signal steady, the exact 4. “Single 12-Bit, 65-MSPS IF Sampling
time to clock the quantizer is not critical. Nevertheless, Analog-to-Digital Converter,” ADS5413
other problems arise that are related not to jitter but just Data Sheet, p. 9 . . . . . . . . . . . . . . . . . . . . . . . . . .slws153
to pure timing. 5. A. Zanchi, I. Papantonopoulos, and F. Tsay,
One problem is that in a pipeline ADC, usually both “Measurement and Spice prediction of
phases of the clock (clock high and clock low) are used. sub-picosecond clock jitter in A/D converters,”
Each stage performs a task during half of the clock and Proceedings of the 2003 IEEE International
another task during the other half. Both tasks are equally Symposium on Circuits and Systems
important and require at least a minimum time for accurate (Bangkok, Thailand, May 25–28, 2003), Vol. 5,
execution; so the user has to provide a minimum clock pp. V-557–V-560. —
duty cycle. Duty-cycle specifications are usually included
on the data sheet of the device. Also, some ADCs (such as Related Web sites
the ADS5413) have an internal duty-cycle stabilizer that, analog.ti.com
when enabled, creates the right internal duty cycle from www.ti.com/sc/device/partnumber
any external clock duty cycle within a certain range. Replace partnumber with ADS5413, ADS5500, ADS5542,
or CDC7005

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