MC14013B

Dual Type D Flip-Flop

The MC14013B dual type D flip−flop is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each flip−flop has independent Data, (D), Direct
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary
outputs (Q and Q). These devices may be used as shift register [Link]
elements or as type T flip−flops for counter and toggle applications.

Features
• Static Operation
• Diode Protection on All Inputs SOIC−14 SOEIAJ−14 TSSOP−14
• Supply Voltage Range = 3.0 Vdc to 18 Vdc D SUFFIX F SUFFIX DT SUFFIX
CASE 751A CASE 965 CASE 948G
• Logic Edge−Clocked Flip−Flop Design
• Logic State is Retained Indefinitely with Clock Level either High or PIN ASSIGNMENT
Low; Information is Transferred to the Output only on the
Positive−going Edge of the Clock Pulse QA 1 14 VDD
• Capable of Driving Two Low−power TTL Loads or One Low−power QA 2 13 QB
Schottky TTL Load Over the Rated Temperature Range
CA 3 12 QB
• Pin−for−Pin Replacement for CD4013B
RA 4 11 CB
• NLV Prefix for Automotive and Other Applications Requiring
DA 5 10 RB
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable SA 6 9 DB
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant VSS 7 8 SB

MAXIMUM RATINGS (Voltages Referenced to VSS)

MARKING DIAGRAMS
Symbol Parameter Value Unit
14 14
VDD DC Supply Voltage Range −0.5 to +18.0 V
Vin, Vout Input or Output Voltage Range −0.5 to VDD + 0.5 V 14013BG MC14013B
(DC or Transient) AWLYWW ALYWG
Iin, Iout Input or Output Current ±10 mA 1 1
(DC or Transient) per Pin
SOIC−14 SOEIAJ−14
PD Power Dissipation, per Package 500 mW
(Note 1)
14
TA Ambient Temperature Range −55 to +125 °C 14
Tstg Storage Temperature Range −65 to +150 °C 013B
ALYW G
TL Lead Temperature 260 °C G
(8−Second Soldering)
1
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be TSSOP−14
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C A = Assembly Location
WL, L = Wafer Lot
This device contains protection circuitry to guard against damage due to high
YY, Y = Year
static voltages or electric fields. However, precautions must be taken to avoid
WW, W = Work Week
applications of any voltage higher than maximum rated voltages to this
G or G = Pb−Free Package
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD. (Note: Microdot may be in either location)
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

July, 2014 − Rev. 10 MC14013B/D
 MC14013B

TRUTH TABLE
Inputs Outputs
Clock† Data Reset Set Q Q
0 0 0 0 1
1 0 0 1 0
X 0 0 Q Q No
Change
X X 1 0 0 1
X X 0 1 1 0
X X 1 1 1 1
X = Don’t Care
† = Level Change

BLOCK DIAGRAM

S
5 D Q 1

3 C Q 2
R

S
9 D Q 13

11 C Q 12
R
VDD = PIN 14
10
VSS = PIN 7

ORDERING INFORMATION
Device Package Shipping†
MC14013BDG SOIC−14 55 Units / Rail
(Pb−Free)
NLV14013BDG* SOIC−14 55 Units / Rail
(Pb−Free)
MC14013BDR2G SOIC−14 2500 Units / Tape & Reel
(Pb−Free)
NLV14013BDR2G* SOIC−14 2500 Units / Tape & Reel
(Pb−Free)
MC14013BDTR2G TSSOP−14 2500 Units / Tape & Reel
(Pb−Free)

NLV14013BDTR2G* TSSOP−14 2500 Units / Tape & Reel

(Pb−Free)

MC14013BFG SOEIAJ−14 50 Units / Rail

(Pb−Free)

MC14013BFELG SOEIAJ−14 2000 Units / Tape & Reel

(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.

[Link]
2
 MC14013B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

−55_C 25_C 125_C
VDD
Characteristic Symbol Vdc Min Max Min Typ (2) Max Min Max Unit
Output Voltage “0” Level VOL 5.0 − 0.05 − 0 0.05 − 0.05 Vdc
Vin = VDD or 0 10 − 0.05 − 0 0.05 − 0.05
15 − 0.05 − 0 0.05 − 0.05
Vin = 0 or VDD “1” Level VOH 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc
10 9.95 − 9.95 10 − 9.95 −
15 14.95 − 14.95 15 − 14.95 −
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 − 1.5 − 2.25 1.5 − 1.5
(VO = 9.0 or 1.0 Vdc) 10 − 3.0 − 4.50 3.0 − 3.0
(VO = 13.5 or 1.5 Vdc) 15 − 4.0 − 6.75 4.0 − 4.0
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 − 3.5 2.75 − 3.5 − Vdc
(VO = 1.0 or 9.0 Vdc) 10 7.0 − 7.0 5.50 − 7.0 −
(VO = 1.5 or 13.5 Vdc) 15 11 − 11 8.25 − 11 −
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 –3.0 − –2.4 –4.2 − –1.7 −
(VOH = 4.6 Vdc) 5.0 –0.64 − –0.51 –0.88 − −0.36 −
(VOH = 9.5 Vdc) 10 –1.6 − −1.3 –2.25 − –0.9 −
(VOH = 13.5 Vdc) 15 –4.2 − −3.4 −8.8 − −2.4 −
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc
(VOL = 0.5 Vdc) 10 1.6 − 1.3 2.25 − 0.9 −
(VOL = 1.5 Vdc) 15 4.2 − 3.4 8.8 − 2.4 −
Input Current Iin 15 − ±0.1 — ± 0.00001 ±0.1 − ±1.0 mAdc
Input Capacitance Cin − − − − 5.0 7.5 − − pF
(Vin = 0)
Quiescent Current IDD 5.0 − 1.0 − 0.002 1.0 − 30 mAdc
(Per Package) 10 − 2.0 − 0.004 2.0 − 60
15 − 4.0 − 0.006 4.0 − 120
Total Supply Current (3) (4) IT 5.0 IT = (0.75 mA/kHz) f + IDD mAdc
(Dynamic plus Quiescent, 10 IT = (1.5 mA/kHz) f + IDD
Per Package) 15 IT = (2.3 mA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL − 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.002.

[Link]
3
 MC14013B

SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)

Characteristic Symbol VDD Min Typ (Note 6) Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 − 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 − 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 − 40 80
Propagation Delay Time tPLH ns
Clock to Q, Q tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns 5.0 − 175 350
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns 10 − 75 150
15 − 50 100
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns
Set to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns 5.0 − 175 350
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns 10 − 75 150
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns 15 − 50 100
Reset to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 265 ns 5.0 − 225 450
tPLH, tPHL = (0.66 ns/pF) CL + 67 ns 10 − 100 200
tPLH, tPHL = (0.5 ns/pF) CL + 50 ns 15 − 75 150
Setup Times (Note 7) tsu 5.0 40 20 − ns
10 20 10 −
15 15 7.5 −
Hold Times (Note 7) th 5.0 40 20 − ns
10 20 10 −
15 15 7.5 −
Clock Pulse Width tWL, tWH 5.0 250 125 − ns
10 100 50 −
15 70 35 −
Clock Pulse Frequency fcl 5.0 − 4.0 2.0 MHz
10 − 10 5.0
15 − 14 7.0
Clock Pulse Rise and Fall Time tTLH 5.0 − − 15 ms
tTHL 10 − − 5.0
15 − − 4.0
Set and Reset Pulse Width tWL, tWH 5.0 250 125 − ns
10 100 50 −
15 70 35 −

Removal Times trem ns

Set 5 80 0 −
10 45 5 −
15 35 5 −
Reset 5 50 –35 −
10 30 –10 −
15 25 –5 −
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
7. Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.

LOGIC DIAGRAM (1/2 of Device Shown)

S
C C Q

C C Q
C C

C C
C C
C
R

[Link]
4
 MC14013B

20 ns 20 ns
VDD
90%
D 50% 20 ns 20 ns
10% VSS VDD
tsu (H) tsu (L) 90%
20 ns SET OR 50%
th VDD RESET 10%
90% VSS
C 50% tw trem
10% 20 ns 20 ns
VSS 90% VDD
tWH tWL 50%
CLOCK 10%
1 VSS
fcl tPLH tw
tPLH tPHL
VOH tPHL
90% VOH
Q 50% Q OR Q 50%
10% VOL
VOL
tTLH tTHL
Inputs R and S low.

Figure 1. Dynamic Signal Waveforms Figure 2. Dynamic Signal Waveforms

(Data, Clock, and Output) (Set, Reset, Clock, and Output)

TYPICAL APPLICATIONS

n−STAGE SHIFT REGISTER

1 2 nth
D D Q D Q D Q Q

C Q C Q C Q

CLOCK

BINARY RIPPLE UP−COUNTER (Divide−by−2n)

1 2 nth
D Q D Q D Q Q

CLOCK C Q C Q C Q

T FLIP-FLOP

MODIFIED RING COUNTER (Divide−by−(n+1))

1 2 nth
D Q D Q D Q Q

C Q C Q C Q

CLOCK

[Link]
5
 MC14013B

PACKAGE DIMENSIONS

SOIC−14 NB
CASE 751A−03
ISSUE K

D A NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
b DIM MIN MAX MIN MAX
0.25 M B M 13X
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
h D 8.55 8.75 0.337 0.344
A X 45 _ E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
M L 0.40 1.25 0.016 0.049
e A1
SEATING M 0_ 7_ 0_ 7_
C PLANE

SOLDERING FOOTPRINT*
6.50 14X
1.18
1

1.27
PITCH

14X
0.58

DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

[Link]
6
 MC14013B

PACKAGE DIMENSIONS

TSSOP−14
CASE 948G
ISSUE B

14X K REF NOTES:

1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
B 5. DIMENSION K DOES NOT INCLUDE
L DAMBAR PROTRUSION. ALLOWABLE
PIN 1
−U− N
DAMBAR PROTRUSION SHALL BE 0.08
IDENT. F (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
1 7 CONDITION.
DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
0.15 (0.006) T U S
A K DETERMINED AT DATUM PLANE −W−.
MILLIMETERS INCHES

ÉÉÉ
ÇÇÇ
−V− K1 DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200

ÇÇÇ
ÉÉÉ
B 4.30 4.50 0.169 0.177
J J1 C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N−N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C −W− K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
−T− SEATING D G H DETAIL E
PLANE

SOLDERING FOOTPRINT*

7.06

0.65
PITCH

14X 14X
0.36
1.26
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

[Link]
7
 MC14013B

PACKAGE DIMENSIONS

SOEIAJ−14
CASE 965
ISSUE B

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
14 8 LE MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
Q1 (0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
E HE M_ REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
1 7 L TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DETAIL P DAMBAR CANNOT BE LOCATED ON THE LOWER
Z RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
D TO BE 0.46 ( 0.018).

VIEW P MILLIMETERS INCHES

A DIM MIN MAX MIN MAX
e A --- 2.05 --- 0.081
c A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.10 0.20 0.004 0.008
D 9.90 10.50 0.390 0.413
b A1 E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
0.13 (0.005) M 0.10 (0.004) HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
Q1 0.70 0.90 0.028 0.035
Z --- 1.42 --- 0.056

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[Link] MC14013B/D
8