Design of an Integrated Circuit for ATM Password
Verification with Dual-Digit Constraints.
Group 10
Member 1: Md. Abdul Hamid ( ET213022)
Member 2: Md. Ifraz Mahmood ( ET183030R)
Course Code:EEE-4754 Remarks:
Course Title: VLSI Sessional
Course Teacher: Md. Riazul Islam
Lecturer, Department of EEE
International Islamic University Chittagong
Date of Submission: 01-12-2024
Page 1 of 10
Introduction
The goal of this project was to design and implement an Integrated Circuit (IC) for password
verification for an ATM machine. The circuit is required to validate two-digit passwords (ranging
from 0-63) based on specific conditions. These conditions ensure that either both digits are equal
or the last digit is greater than the first. The IC was designed using state-of-the-art logic families
and tools, prioritizing low power consumption, compact area, and high-speed performance. The
work also focused on the detailed implementation of a schematic and simulations using Cadence
tools.
Requirements
Project Objectives:
1. Design a password verification IC with specific logic constraints.
2. Ensure the design complies with the operational requirements of an ATM machine.
Detailed Requirements:
1. Password Input Interface:
The IC accepts two-digit passwords as binary inputs. Binary-coded switches or virtual
pulse generators (e.g., Vpulse) were used for input during simulation.
2. Verification Logic:
Two conditions for password verification:
○ The two digits of the password must be equal (e.g., 11, 22).
○ The second digit must be greater than the first (e.g., 12, 23).
3. Simulation and Validation:
The design was simulated using Cadence to verify correctness under all possible inputs.
4. Low Power Consumption:
Optimized the logic to minimize static and dynamic power consumption.
5. Area Optimization:
Reduced IC overhead by using compact logic designs and optimizing the number of
gates.
6. High-Speed Design:
Ensured the circuit operates efficiently to provide immediate feedback on password
validity.
7. Logic Families Used:
Implemented the design using CMOS and Transmission Gate (TG) logic families for an
optimal trade-off between power, speed, and area.
Page 2 of 10
Working Principle
1. Construction:
Here K-Map used to build up the logic for the circuit.
We don't need to accept inputs that are covered with orange or white color in the following table.
Taking out this number will require us to build up the logic for the chip, which will allow us to
reduce the chip size more and use fewer transistors and NMOs, therefore reducing the cost of the
chip.
In addition, we don't need bcd code since we are using 6 bit binary, which also reduces 2 extra
inputs.
The binary number for 0-63 is indicated by a -f.
a will be counted as msb, and f will be counted as lsb
𝑓(𝑎, 𝑏, 𝑐, 𝑑, 𝑒, 𝑓) = {𝑏`𝑑 + 𝑏𝑐𝑑` + 𝑎`𝑐`𝑑` + 𝑎`𝑐𝑒` + 𝑎`𝑏`𝑒𝑓 + 𝑒𝑐` + 𝑐`𝑑`𝑒` + 𝑏`𝑐`𝑓 + 𝑎𝑏𝑐`𝑑𝑒𝑓 }
ef\cd 00 01 11 10 ef \cd 00 01 11 10
00 0 4 12 8 00 16 20 28 24
01 1 5 13 9 01 17 21 29 25
11 3 7 15 11 11 19 23 31 27
10 2 6 14 10 10 18 22 30 26
a=0;b=0 a=0; b=1
ef\cd 00 01 11 10 ef \cd 00 01 11 10
00 32 36 44 40 00 48 52 60 56
01 33 37 45 41 01 49 53 61 57
11 35 39 47 43 11 51 55 63 59
10 34 38 46 42 10 50 54 62 58
a=1; b=0 a=1; b=1
Page 3 of 10
This expression can be verified from the buildup function.
● 𝑏`𝑑 = {4, 5, 6, 7, 12, 13, 14, 15, 36, 37, 38, 39, 44, 45, 46, 47}
● 𝑏𝑐𝑑` = {24, 25, 26, 27, 56, 57, 58, 59}
● 𝑎`𝑐`𝑑` = {0, 1, 2, 3, 16, 17, 18, 19}
● 𝑎`𝑐𝑒` = {8, 9, 12, 13, 24, 25, 28, 29}
● 𝑒𝑐` = {18, 19, 22, 23, 34, 35, 38, 39}
● 𝑎`𝑏`𝑒𝑓 = {3, 7, 11, 15}
● 𝑐`𝑑`𝑒` = {0, 1, 48, 49}
● 𝑏`𝑐`𝑓 = {1, 3, 5, 7, 33, 35, 37, 39}
● 𝑎𝑏𝑐`𝑑𝑒𝑓 = {55}
●
3. Simulation:
The circuit was designed and simulated in Cadence using schematic capture and verified
through analog simulation tools like ADE-L.
Fig. 1: Output when input is 04, 10, 21, 33, 46, 55
1st column from a-f is the binary representation of 04, (Verified)
Page 4 of 10
Fig. 2: Final Chip Design
Page 5 of 10
Fig. 3: Final Simple Design
Page 6 of 10
Fig. 4->6 input and gate used as Symbol in final design
Fig. 5->3 input and gate used as symbol in final design
Page 7 of 10
Fig. 6: Inverter used as Symbol
Fig. 7->9 input or gate used in final design as symbol.
Page 8 of 10
Fig:8-> 4 Input and gate used as symbol
Combining all this symbol, Final design has been created.
Page 9 of 10
Conclusion
In this project, the following tasks were accomplished:
1. Member 1 Contributions:
○ Designed the schematic for the input interface.
○ Implemented the greater-than comparator logic.
○ Performed the simulation and analysis in Cadence.
2. Member 2 Contributions:
○ Created the schematic for equality verification using k map.
○ Performed the simulation and analysis in Cadence.
This project successfully demonstrated the design and verification of a password validation
IC that meets the requirements of low power, compact area, and high-speed operation.
Appendix
● Software: Cadence Virtuoso
● Simulation Results: (Attach screenshots of schematic, testbench, and waveforms.)
● Challenges: Minor debugging issues during simulation resolved using error logs.
● Learnings: Enhanced understanding of IC design, schematic capture, and binary
comparator logic.
Page 10 of 10
