DepartmentofComput
er
SystemsEngineering
DigitalSystemDesign
Handout#01
Gate-LevelModellingandSimulation
LabLearningObjectives:
Aftercompletingthissession,studentshouldbeableto:
UnderstandbasicsofVerilogprogramming.
Getfamiliarwithstructuraldescription(moduleinstantiation).
Simulatebasiccombinationalcircuitsusinggate-levelmodelling.
Note:Submitthelabreport(solvedactivitiesandexercises)beforethenextlab.
LabHardwareandSoftwareRequired:
[Link]/LaptopComputer with internet connection.
BackgroundTheory:
Gate-levelModelling:
Verilog is both a structural and behavioral language. Internals of each module can
bedefinedatfourlevelsofabstraction,[Link]
of abstraction which include switch-level, gate-level, data flow, and behavioral
oralgorithmlevel.
Theswitch-
levelisthelowestabstractionlevel,wheremodulecanbeimplementedintermsofswitch
es,storagenodes,andinterconnectionsbetweenthem.
Thegate-levelmodellingisimplementedintermsoflogicgatesandinterconnections
between these gates. This design method is like describing adesignintermsof
agate-levellogicdiagram.
Verilog allows the designer to mix and match all four levels of design methodologies
indesign. The modules behave identically to the external world identically irrespective
ofthe level of abstraction at which module is [Link], internals of the
modulecanbe changedwithout any changein theenvironment.
In the digital design community, the term register transfer level (RTL) is used for
[Link],the
higher level of abstraction, design will be more flexible and technology
[Link], the lower-level description provides high performance therefore
as the designmatures,highlevelmodules arereplacedwith thegate-levelmodelling.
LabActivity:
Wearegoingtousetestbenchlisting1.7(2-
bitcomparatordesignanditstestvector)youhavecovered inchapter#1of the textbook.
Steps:
1. Open[Link]
2. Write yourtestbenchcode atthe left and required moduleson theright.
3. Addthesetwolinesafterinitialbegin
$dumpfile("eq2_tb.vcd"); //simulatorgeneratesoutputfileforthewaveformsdata
$dumpvars;
Also,replace$stopwith$finish.
4. SelectIcarusVerilogasyoursimulator.
5. Enable“OpenEPWaveafterrun”.
6. Runthecoding.
7. Aftersuccessfulrun,selectsignalstoshowwaveforms.
Fig#1:EDAplaygroundtestbenchprogrammingandinitialsettings
Exercise:
[Link](fromthetable)
inthetestbench andobservetheoutputfrom waveforms.
a b c_in sum c_out
1 0 0 1
2 1 1 0
3 1 0 1
4 1 1 1
Additionally,youarerequiredtoattachtheinputandoutputwaveformsinyourlabreport.
SOLUTION:
Design code:
module full_adder (
input a, // First input
input b, // Second input
input c_in, // Carry input
output sum, // Sum output
output c_out // Carry output );
assign sum = a ^ b ^ c_in; // XOR operation for sum
assign c_out = (a & b) | (c_in & (a ^ b)); // Carry out logic
endmodule
Testbench:
module testbench;
reg a, b, c_in; // Inputs to the full adder
wire sum, c_out; // Outputs from the full adder
// Instantiate the full adder module
full_adder fa ( .a(a), .b(b), .c_in(c_in), .sum(sum), .c_out(c_out) );
initial begin
// Open VCD file for waveform
$dumpfile("full_adder_tb.vcd");
$dumpvars;
// Display the headers
$display("Time\t a b c_in | sum c_out");
$monitor("%g\t %b %b %b | %b %b", $time, a, b, c_in, sum, c_out);
// Test vector 1
a = 1; b = 0; c_in = 0;
#10;
// Test vector 2
a = 1; b = 1; c_in = 0;
#10;
// Test vector 3
a = 1; b = 0; c_in = 1;
#10;
// Test vector 4
a = 1; b = 1; c_in = 1;
#10;
$finish; // Terminate simulation
end
endmodule
