Analog IC Design with

Low-Dropout Regulators
About the Author
Gabriel Alfonso Rincón-Mora (B.S., M.S., Ph.D.)
worked for Texas Instruments from 1994 to 2003, was
appointed an adjunct professor at Georgia Tech in 1999,
and became a full-time faculty member in 2001. His
scholarly products include five books and one book
chapter, 26 patents, over 100 scientific publications, and
26 commercial power management chip designs. He is
a Distinguished Lecturer for IEEE CASS, an Associate
Editor for IEEE TCAS II, Chair of IEEE’s SSCS-CASS
chapter, and the recipient of several awards.
 Analog IC Design with
Low-Dropout Regulators
Gabriel Alfonso Rincón-Mora, Ph.D.
Georgia Institute of Technology
Atlanta, Georgia

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 To my parents Gladys Maria Mora de Rincón and
Gilberto Rincón Belzares and my brother
Gilberto Alexei Rincón Mora, without whom I would not be
This page intentionally left blank
 Contents
Preface ...................................... xiii
1 System Considerations . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Regulators in Power Management . . . . . . . . . . 1
1.2 Linear versus Switching Regulators . . . . . . . . . 2
1.2.1 Speed Tradeoffs . . . . . . . . . . . . . . . . . . . . 4
1.2.2 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.3 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Market Demand . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.1 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.2 Integration . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.3 Operational Life . . . . . . . . . . . . . . . . . . . . 8
1.3.4 Supply Headroom . . . . . . . . . . . . . . . . . . 9
1.4 Batteries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4.1 Early Batteries . . . . . . . . . . . . . . . . . . . . . 10
1.4.2 Li Ion Batteries . . . . . . . . . . . . . . . . . . . . . 12
1.4.3 Fuel Cells . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4.4 Nuclear Batteries . . . . . . . . . . . . . . . . . . . 13
1.4.5 Harvesters . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5 Circuit Operation . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.1 Categories . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.2 Block-Level Composition . . . . . . . . . . . . 19
1.5.3 Load Environment . . . . . . . . . . . . . . . . . . 20
1.5.4 Steady-State and Transient
Response . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.6 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6.1 Regulating Performance . . . . . . . . . . . . . 26
1.6.2 Power Characteristics . . . . . . . . . . . . . . . 37
1.6.3 Operating Environment . . . . . . . . . . . . . 40
1.7 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.7.1 Functionality . . . . . . . . . . . . . . . . . . . . . . . 41
1.7.2 Parametric Limits . . . . . . . . . . . . . . . . . . . 42
1.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2 Microelectronic Devices . . . . . . . . . . . . . . . . . . . . . . . 45
2.1 Passives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.1.1 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.1.2 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.1.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

vii
viii Contents

2.2 PN-Junction Diodes . . . . . . . . . . . . . . . . . . . . . . . 51

2.2.1 Large-Signal Operation . . . . . . . . . . . . . . 51
2.2.2 Small-Signal Response . . . . . . . . . . . . . . 57
2.2.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.3 Bipolar-Junction Transistors . . . . . . . . . . . . . . . . 58
2.3.1 Large-Signal Operation . . . . . . . . . . . . . . 58
2.3.2 Small-Signal Response . . . . . . . . . . . . . . 62
2.3.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.4 Metal-Oxide Semiconductor Field-Effect
Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.4.1 Large-Signal Operation . . . . . . . . . . . . . . 66
2.4.2 Small-Signal Response . . . . . . . . . . . . . . 73
2.4.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.5 Junction Field-Effect Transistors . . . . . . . . . . . . 76
2.5.1 Large-Signal Operation . . . . . . . . . . . . . . 76
2.5.2 Small-Signal Response . . . . . . . . . . . . . . 79
2.5.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3 Analog Building Blocks . . . . . . . . . . . . . . . . . . . . . . . 83

3.1 Single-Transistor Amplifiers . . . . . . . . . . . . . . . 84
3.1.1 Common-Emitter/Source
Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.1.2 Common-Collector/Drain, Emitter/
Source Voltage Followers . . . . . . . . . . . . 96
3.1.3 Common-Base/Gate Current
Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.1.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.2 Differential Pairs . . . . . . . . . . . . . . . . . . . . . . . . . 112
3.2.1 Differential Signals . . . . . . . . . . . . . . . . . 115
3.2.2 Common-Mode Signals . . . . . . . . . . . . . 117
3.3 Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . 121
3.3.1 Basic Mirror . . . . . . . . . . . . . . . . . . . . . . . 121
3.3.2 Cascoded Mirror . . . . . . . . . . . . . . . . . . . 127
3.3.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 134
3.4 Five-Transistor Differential Amplifier . . . . . . . 135
3.4.1 Differential Signals . . . . . . . . . . . . . . . . . 136
3.4.2 Common-Mode Signals . . . . . . . . . . . . . 139
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

4 Negative Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

4.1 Generalities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.1.1 Loop Composition . . . . . . . . . . . . . . . . . . 145
4.1.2 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
 Contents ix

4.2 Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

4.2.1 Series (Voltage) Mixers . . . . . . . . . . . . . . 150
4.2.2 Shunt (Current) Mixers . . . . . . . . . . . . . . 156
4.3 Samplers (Sensors) . . . . . . . . . . . . . . . . . . . . . . . 163
4.3.1 Shunt (Voltage) Samplers . . . . . . . . . . . . 163
4.3.2 Series (Current) Samplers . . . . . . . . . . . . 166
4.4 Application of Negative-Feedback Theory . . . 171
4.5 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
4.6 Frequency Compensation . . . . . . . . . . . . . . . . . . 176
4.6.1 Establish a Dominant Pole . . . . . . . . . . . 177
4.6.2 Right-Half-Plane (RHP)
Miller Zeros . . . . . . . . . . . . . . . . . . . . . . . . 180
4.6.3 Multiplying the Miller Effect . . . . . . . . . 182
4.6.4 Left-Half-Plane (LHP) Zeros . . . . . . . . . 183
4.6.5 Design Objectives . . . . . . . . . . . . . . . . . . 188
4.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

5 AC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
5.1 Frequency Compensation . . . . . . . . . . . . . . . . . . 192
5.1.1 Uncompensated Response . . . . . . . . . . . 192
5.1.2 Externally Compensated
Response . . . . . . . . . . . . . . . . . . . . . . . . . . 197
5.1.3 Internally Compensated
Response . . . . . . . . . . . . . . . . . . . . . . . . . . 200
5.2 Power-Supply Rejection . . . . . . . . . . . . . . . . . . . 203
5.2.1 Shunt-Feedback Model . . . . . . . . . . . . . . 204
5.2.2 Feed-through Components in GP . . . . . . 206
5.2.3 Power-Supply Rejection Analysis . . . . . 213
5.2.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . 224
5.3 External versus Internal Compensation . . . . . . 226
5.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

6 IC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
6.1 Series Power Pass Device . . . . . . . . . . . . . . . . . . 232
6.1.1 Alternatives . . . . . . . . . . . . . . . . . . . . . . . . 233
6.1.2 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
6.2 Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
6.2.1 Driving N-Type Power Switches . . . . . . 246
6.2.2 Driving P-Type Power Switches . . . . . . 249
6.2.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
6.3 Error Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 265
6.3.1 Low Headroom (i.e., Low
Input Supply) . . . . . . . . . . . . . . . . . . . . . . 266
6.3.2 High Power-Supply Rejection . . . . . . . . 270
x Contents

6.3.3 Low Input-Referred Offset . . . . . . . . . . . 272

6.3.4 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
6.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

7 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

7.1 External Compensation . . . . . . . . . . . . . . . . . . . 291
7.1.1 Compensation . . . . . . . . . . . . . . . . . . . . . 293
7.2 Internal Compensation . . . . . . . . . . . . . . . . . . . . 297
7.2.1 High-Dropout Regulator . . . . . . . . . . . . 298
7.2.2 Low-Dropout Regulator . . . . . . . . . . . . . 302
7.3 Self-Referencing . . . . . . . . . . . . . . . . . . . . . . . . . . 308
7.3.1 Zero-Order Approach . . . . . . . . . . . . . . . 309
7.3.2 Temperature Independence . . . . . . . . . . 310
7.4 Current Regulation . . . . . . . . . . . . . . . . . . . . . . . 319
7.4.1 Current Sources . . . . . . . . . . . . . . . . . . . . 320
7.4.2 Current Mirrors . . . . . . . . . . . . . . . . . . . . 322
7.5 Low-Current and Low-Dropout
Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
7.5.1 Power Switch . . . . . . . . . . . . . . . . . . . . . . 326
7.5.2 Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
7.5.3 Error Amplifier . . . . . . . . . . . . . . . . . . . . . 333
7.5.4 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
7.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

8 IC Protection and Characterization . . . . . . . . . . . . . 347

8.1 Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . 347
8.1.1 Overcurrent Protection ............. 348
8.1.2 Thermal Shutdown . . . . . . . . . . . . . . . . . 352
8.1.3 Reverse-Battery Protection . . . . . . . . . . . 354
8.1.4 Electrostatic-Discharge
Protection . . . . . . . . . . . . . . . . . . . . . . . . . 355
8.2 Characterization . . . . . . . . . . . . . . . . . . . . . . . . . 357
8.2.1 Emulating the Load . . . . . . . . . . . . . . . . . 358
8.2.2 Regulating Performance . . . . . . . . . . . . . 360
8.2.3 Power Performance . . . . . . . . . . . . . . . . . 365
8.2.4 Operating Environment . . . . . . . . . . . . . 367
8.2.5 Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
8.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Index ....................................... 373
 Preface

M
y objective with this book is to introduce, discuss, and illustrate
how to design, simulate, build, and test linear low-dropout
(LDO) regulator integrated circuits (ICs). The driving inspi-
ration for this effort is the increasingly important role LDO regulator
ICs play in modern-day and emerging state-of-the-art applications,
as the demand and promise of system-on-chip (SoC) integration con-
tinues to drive old and create new markets. The fact is the ubiquity
of noisy and unpredictable input sources and loads demands
point-of-load (PoL) regulators that draw little to no power yet
generate increasingly accurate and fast-responding supply voltages.
As a result, mixed-signal ICs that traditionally excluded power-
conditioning features must now embed system and PoL power supplies,
of which linear regulators comprise a large fraction because their
switching counterparts alone generate outputs with unacceptably
high noise content.
A pedagogical presentation of linear regulators, however, must
invariably include analog IC theory and design because linear regu-
lator ICs are, as much as operational amplifiers (op amps) are, intrin-
sically analog. As a result, this book, in setting a foundation for linear
regulators, also reviews analog theory, as some popular books in the
industry also do, but from an intuitive, design-oriented perspective,
one that I have found useful and necessary when designing ICs. The
idea is to understand devices, circuits, and systems well enough at
the physical level to predict their individual and combined character-
istics without resorting to equations or books, the by-product of
which is also being able to reproduce and verify the equations and
theory already found in textbooks. As such, this book presents solid-
state semiconductor theory, circuit design and analysis of basic ana-
log building blocks, and feedback concepts, and shows how to apply
them to the ac and IC design of an analog system: a linear regulator.
In other words, this book includes a fairly comprehensive treatment
of analog IC design.
I wrote the book with the intention of introducing and leading a
novice microelectronic engineer through the entire analog IC design

xi
xii Preface

process, through the eyes of a linear regulator, which embodies

numerous aspects of the art. Notwithstanding, the book also aims to
enlighten practiced analog IC designers with little experience in the
field of regulator ICs. The book also targets experienced regulator IC
engineers who wish to not only review some analog and linear regu-
lator principles from an intuitive yet still academic perspective but
also ascertain and expand their understanding of the state of the art
in the field of linear regulator ICs.
The tone, format, and thought process presented in the book
embodies my combined experience in industry as an analog IC
designer and academia as professor and researcher. From industry,
for instance, I discovered the art of design and the value of product
development, so the book places emphasis on intuitive insight, over-
all system objectives, IC development process, and circuit reliability.
As professor and researcher, I continue to learn the art of a pedagogi-
cal presentation and the value of technical depth and outside-the-box
thinking. What the reader sees in this book is therefore my attempt at
drafting a practical yet academically valuable treatment of analog IC
design and linear regulator ICs. I must confess, however, I still have
much to learn, so I hope my devotion to the book and the field at
large ultimately wins enough of the reader’s favor to pardon any
deficiencies, inconsistencies, and inaccuracies the reader may find in
the book.
With respect to organization, I divided the book into eight chapters.
The first chapter is analogous to the product-definition phase (but
with an academic undertone), when a semiconductor company
justifies a design effort by defining the role and operational objectives
of the proposed system. Before attempting to undertake the design,
however, a novice engineer must first train in the art of analog IC
design, which is why the second, third, and fourth chapters discuss
solid-state theory and devices, circuit building blocks, and feedback,
respectively. The fifth chapter focuses on ac system-design issues and
corresponds to the second step in a prototype-development effort;
here the designer applies the circuit and feedback principles discussed
in the previous two chapters. The next two chapters apply and com-
bine the device know-how presented in the second chapter with the
teachings of the next few chapters to design the actual IC, first at the
component level (sixth chapter) and then at the system level (seventh
chapter). The development process, from an IC designer’s perspec-
tive, culminates in these two chapters because all analog training con-
verges here, with IC design. Finally, the eighth chapter incorporates
protection and discusses characterization, the final two steps in a
product-development cycle. As a whole, the book is an example of a
top-down-top design approach because it starts with an abstract view
of the system for context, then dives down to devices for training,
slowly rising through circuits, until finally reaching the system again,
but now the final design, at the transistor level.
 Preface xiii

Novice engineers may use this book to learn about analog IC

design by reviewing the entire design process by traversing through
all eight chapters sequentially. They may also seek to enhance their
understanding of specific analog design principles, in which case
they might target specific chapters such as Chaps. 2 to 4 for devices,
circuits, and feedback and Chap. 5 for important ac design and
stability considerations. Trained analog designers with little regulator
experience who do not wish to review basic analog principles but
wish to design linear regulator ICs may target Chap. 1 for system
perspective and Chaps. 5 to 8 for regulator-specific issues. Experienced
regulator IC designers, on the other hand, may pinpoint specific sec-
tions in Chaps. 1 and 5 to 8 to enhance their understanding of the
state of the art. With all this in mind, I divided each chapter into self-
inclusive sections and sections into what I thought were relevant and
subject-specific subsections, assigning titles I thought were meaning-
ful, so I hope the Contents facilitates the process of targeting chapters,
sections, and subsections.

Gabriel Alfonso Rincón-Mora, Ph.D.

This page intentionally left blank
 CHAPTER 1
System
Considerations

1.1 Regulators in Power Management

Supplying and conditioning power are the most fundamental func-
tions of an electrical system. A loading application, be it a cellular
phone, pager, or wireless sensor node, cannot sustain itself without
energy, and cannot fully perform its functions without a stable sup-
ply. The fact is transformers, generators, batteries, and other off-line
supplies incur substantial voltage and current variations across time
and over a wide range of operating conditions. They are normally
noisy and jittery not only because of their inherent nature but also
because high-power switching circuits like central-processing units
(CPUs) and digital signal-processing (DSP) circuits usually load it.
These rapidly changing loads cause transient excursions in the sup-
posedly noise-free supply, the end results of which are undesired volt-
age droops and frequency spurs where only a dc component should
exist. The role of the voltage regulator is to convert these unpredictable
and noisy supplies to stable, constant, accurate, and load-independent
voltages, attenuating these ill-fated fluctuations to lower and more
acceptable levels.
The regulation function is especially important in high-performance
applications where systems are increasingly more integrated and
complex. A system-on-chip (SoC) solution, for instance, incorporates
numerous functions, many of which switch simultaneously with the
clock, demanding both high-power and fast-response times in short
consecutive bursts. Not responding quickly to one of these load-current
transitions (i.e., load dumps) forces storage capacitors to supply the
full load and subsequently suffer considerable transient fluctuations
in the supply. The bandwidth performance of the regulator, that is, its
ability to respond quickly, determines the magnitude and extent of
these transient variations.
Regulators also protect and filter integrated circuits (ICs) from expo-
sure to voltages exceeding junction-breakdown levels. The requirement

1
2 Chapter One

is more stringent and acute in emergent state-of-the-art technologies

whose susceptibility to breakdown voltages can be less than 2 V. The
growing demand for space-efficient, single-chip solutions, which
include SoC, system-in-package (SiP), and system-on-package (SoP)
implementations, drives process technologies to finer photolitho-
graphic and metal-pitch dimensions. Unfortunately, the maximum
voltage an IC can sustain before the onset of a breakdown failure
declines with decreasing dimensions and pitch because as the compo-
nent density increases, isolation barriers deteriorate.
References, like regulators, generate and regulate accurate and sta-
ble output voltages that are impervious to variations in the input sup-
ply, loading environment, and various operating conditions. Unlike
regulators, however, references do not supply substantial dc currents.
Although a good reference may shunt positive and negative noise cur-
rents, its total load-current reach is still relatively low. In practice, refer-
ences supply up to 1 mA and regulators from 5 mA to several amps.

1.2 Linear versus Switching Regulators

A voltage regulator is normally a buffered reference: a bias voltage
cascaded with a noninverting op-amp capable of driving large load
currents in shunt-feedback configuration. Bearing in mind the broad
range of load currents possible, regulators are, on a basic level, gener-
ally classified as linear or switching. Linear regulators, also called series
regulators, linearly modulate the conductance of a series pass switch
connected between an input dc supply and the regulated output
to ensure the output voltage is a predetermined ratio of its bias ref-
erence voltage, as illustrated in Fig. 1.1a. The term “series” refers to
the pass element (or switch device) that is in series with the unregu-
lated supply and the load. Since the current flow and its control are

NOTE ON TEXT : To complement and augment the verbal explanations

presented in this book, an effort has been made to conform variable
names to standard small-signal and steady-state naming conven-
tions. Signals embodying both small-signal and dc components use
a smaller-case name with uppercase subscripts, like for instance
output voltage vOUT. When referring only to the dc component, all
capitals are used, as in VOUT, and similarly, when only referring to
small-signal values, the entire name, including subscripts, is in lower
case, as in vOUT. As also illustrated by the previous example, the vari-
ables adopt functionally intuitive names. The first letter usually
describes the signal type and its dimensional units such as v for volt-
age, i for current, A or G for amplifying gain, p for power, and so on.
The subscript tends to describe the function or node to which the
variable is attached, such as “out” for the output of the regulator,
“reg” for a regulated parameter, and so on.
 System Considerations 3

Analog AC signal Digital AC signal

Linear vIN
Linear
amp vIN vREF amp
vREF + Energy Transfer
Series
switch –
Pulse-width vOUT
vOUT
modulated (PWM)

Load
A-D converter
Load

Feedback
loop Feedback
loop Low-pass filter cap

(a) (b)
FIGURE 1.1 (a) Basic linear and (b) switching regulator circuits.

continuous in time, the circuit is linear and analog in nature, and

because it can only supply power through a linearly controlled series
switch, its output voltage cannot exceed its unregulated input supply
(i.e., VOUT < VIN).
A switching regulator is the counterpart to the linear solution, and
because of its switching nature, it can accommodate both alternating-
current (ac) and direct-current (dc) input and output voltages, which
is why it can support ac-ac, ac-dc, dc-ac, and dc-dc converter functions.
Within the context of ICs, however, dc-dc converters predominate
because the ICs derive power from available dc batteries and off-line
ac-dc converters, and most loading applications in the IC and outside
of it demand dc supplies to operate. Nevertheless, given its ac-dc con-
verting capabilities, switching regulators are also termed switching con-
verters, even if only dc-dc functions are performed.
From a circuit perspective, the driving difference between linear
and switching regulators is that the latter is mixed-mode with both
analog and digital components in the feedback loop (Fig. 1.1b). The
basic idea in the switching converter is to alternately energize induc-
tors and/or capacitors from the supply and de-energize them into the
load, transferring energy via quasi-lossless energy-storage devices. To
control the network, the circuit feeds back and converts an analog
error signal into a pulse-width-modulated (PWM) digital-pulse train
whose on-off states determine the connectivity of the aforementioned
switching network. From a signal-processing perspective, the func-
tion of the switching network is to low-pass-filter the supply-level
swings of the digital train down to a millivolt analog signal, the aver-
age of which is the regulated output.
The blocks that normally comprise a dc-dc converter include a
PWM controller, which is the combination of an analog linear ampli-
fier and a pulse-width-modulated analog-digital converter, as shown
in Fig. 1.1b, synchronous and/or asynchronous switches (i.e., transis-
tors and/or diodes), capacitors, and, in many cases, inductors. Many
switched-capacitor implementations do not require power inductors,
4 Chapter One

sometimes making total chip integration possible. These integrated,

inductorless converters, however, cannot typically supply the high-
current levels the discrete power inductors can, which is why they
normally satisfy a relatively smaller market niche in low-power
applications.
Switching regulators, unlike their linear counterparts, are capable
of generating a wide range of output voltages, including values below
and above the input supply. Buck converters, for instance, generate
output voltages lower than the input supply (i.e., VOUT < VIN) while
boost converters deliver the opposite (i.e., VOUT > VIN)—charge pump is
the name normally applied to an inductorless buck or boost con-
verter. Buck-boost converters, as the name implies, are a combination
of both buck and boost circuits and they are consequently capable of
regulating output voltages both above and below the input supply. In
spite of the apparent flexibility and advantages of switching supplies,
however, linear regulators remain popular in consumer and high-
performance electronics, as the next subsection will illustrate.

1.2.1 Speed Tradeoffs

Linear regulators tend to be simpler and faster than switching con-
verters. As Fig. 1.1 illustrates, there are fewer components in a linear
regulator, which imply two things: simplicity and less delay through
the feedback loop, in other words, higher bandwidth and therefore
faster response. The PWM controller, and more specifically, the pulse-
width-modulated analog-to-digital converter, is generally a relatively
laborious block to design, often requiring a clock, comparators, non-
overlapping digital drivers, and a saw-tooth triangular-wave genera-
tor. For a stable switching converter in negative feedback, the switch-
ing frequency is often a decade above the bandwidth of the loop,
further limiting its response time to orders of magnitude below the
transitional frequency ( ft) of the transistors available in a given pro-
cess technology. Because of this, and the fact they are relatively com-
plex circuits (i.e., more delays across the loop), dc-dc converters
require more time to respond than linear regulators, 2–8 μs versus
0.25–1 μs. The switching frequencies of these devices are between 20
kHz and 10 MHz. Although higher switching frequencies can reduce
the ripple content of the output voltage and/or relax the LC-filter
requirements, they are often prohibitive because they increase the
switching power losses of the converter beyond acceptable limits—
increasing power losses demands more energy from the battery and
therefore reduces its runtime.

1.2.2 Noise
Switching regulators are noisier than their linear counterparts are, and
Fig. 1.1 illustrates this by the presence of digital signals in the ac-feedback
path of the circuit. Power switches, which are large devices conducting
 System Considerations 5

high currents, must switch at relatively high frequencies, forcing their

driving signals to be fast and abrupt and injecting noise into the
energy-storage devices used to supply the loading circuits. The noise
is especially prevalent in boost configurations where radio-frequency
(RF) noise tends to be worse. Start-stop clock operation, like on-off
sleep-mode transitions, further aggravates noise content with low-
and high-frequency harmonics.

1.2.3 Efficiency
Switching regulators have one redeeming quality when compared to
linear regulators: they are power efficient. The fact is the voltage (and
therefore power) across the power switches in a dc-dc converter are
far lower (e.g., 10–100 mV) than the voltage across the series pass
device of a linear regulator, which is the difference between the
unregulated input and regulated output (e.g., 0.3–2 V). Allowing the
regulator to dissipate (not deliver) a larger proportion of power
results in decreased power efficiency, which is an important metric in
power-conditioning circuits defined as the ratio of output power POUT
to input power PIN, where the latter comprises delivered output
power POUT and consumed power losses PREG:

POUT POUT
η= = (1.1)
PIN PREG + POUT

Switching regulators commonly achieve efficiencies between 80

and 95%. In the case of linear regulators, quiescent-current flow IQ
and the voltage difference between the unregulated supply VIN and
regulated output VOUT limit power-efficiency performance to consid-
erably lower levels,

I LOADVOUT V
ηLin− Reg = < OUT (1.2)
(I LOAD + IQ )VIN VIN

where ILOAD is the load current and quiescent current IQ flows to

ground, not the load. The maximum possible efficiency a series regu-
lator can attain is therefore the ratio of the output and input supply
voltages, even if its quiescent current nears zero. For instance, the
maximum power efficiency a 2.5 V linear regulator can ever achieve
while powered from a 5 V input supply is only 50%.
Power efficiency in a linear regulator increases with lower input-
output voltage differentials. For instance, if in the above-stated exam-
ple the regulator drew power from a 3.3 V input supply, the efficiency
would have been 76%, or from a 2.8 V input supply, 89%. This char-
acteristic holds true only if average load current ILOAD is considerably
6 Chapter One

greater than average quiescent current IQ, which is typical when a full
load is presented, but not when the system is idling or asleep. Conse-
quently, when the voltage drop between the unregulated supply and
the output is relatively low (i.e., VIN – VOUT < 0.3 V), linear regulators
are often preferred over their switching counterparts because effi-
ciencies are on par, and the circuit is simpler, less expensive, less
noisy, and faster. Their only, though significant, drawback is power
efficiency, and if that is not an issue or if equivalent to a switching
converter, a linear regulator is best.
Increasing load currents to the point where heat sinks are
required is costly. A heat sink increases overhead by requiring an
additional on-board component and demanding more real estate on
the printed-circuit-board (PCB). A common technique used to cir-
cumvent this drawback is to utilize several linear regulators
throughout the PCB to split the load and minimize the power dis-
sipated by each regulating IC, or by replacing them with a switch-
ing regulator, if performance specification requirements allow, in
other words, if more noise in the regulated output is permissible.
Another detrimental side effect of high temperature is higher metal-
oxide-semiconductor (MOS) switch-on resistances, the results of
which are higher conduction losses and consequently lower effi-
ciency performance. In all, as Table 1.1 summarizes, linear regula-
tors are simpler and faster and produce lower noise levels, but their
relatively limited efficiency performance, however, constrains them
to lower power applications and dedicated supply systems. Switch-
ing regulators, on the other hand, may enjoy more efficiency but the
loads they sustain must tolerate higher noise levels, which is why
power to high-performance analog subsystems is normally chan-
neled by way of linear regulators.

Linear Regulators Switching Regulators

Output range is limited √ Output range is flexible
(VOUT < VIN) (VOUT ≤ VIN or VOUT ≥ VIN)
√ Simple circuit Complex circuit
√ Low noise content High noise content
√ Fast response Slow response
Limited power efficiency √ High power efficiency
(η < VOUT/VIN) (η ≈ 80–95%)
Good for low-power applications Good for high-power applications

Check mark “√” denotes positive attributes (i.e., advantages).

TABLE 1.1 Comparing Linear Regulators to Their Switching Counterparts

 System Considerations 7

1.3 Market Demand

1.3.1 System
Both linear and switching regulators claim their place in today’s mar-
ket. Systems like desktop and laptop microprocessors not only
demand substantial amounts of clock-synchronized currents but also
low supply voltages. Such systems reap the benefits of power effi-
cient dc-dc converters. Circuit blocks serving purely analog func-
tions, on the other hand, cannot sustain the noisy supplies generated
by switching regulators and therefore exploit the low-noise and cost-
effective advantages of linear regulators. These analog circuits are
inherently more sensitive to noise originated in the supply rails than
digital blocks, which is why they require “cleaner” power supplies.
Today’s growing market demand for portable electronics, like
cellular phones, portable digital assistants (PDAs), MP3 players,
laptops, and the like requires the use and coexistence of both linear
and switching regulators, since both accuracy and power efficiency
are paramount. In these applications, the integrated power manage-
ment circuit drives noise-sensitive circuits from noisy and variable
input-supply voltages. A dc-dc converter, under these conditions,
steps down the input supply to a lower voltage level, generating in
the process a regulated but noisy supply voltage (e.g., vNOISY), as
shown in Fig. 1.2. A linear regulator then draws power from this
noisy supply to generate a low-noise, ripple-rejected output (e.g.,
vCLEAN), which is now compatible with high-performance, noise-sen-
sitive ICs. The voltage across the linear regulator is therefore low
enough to limit its power losses (e.g., 2.4–1.8 V in the figure). The
purpose of the switching regulator is therefore to down-convert as
much of the input voltage as possible to save power, since it is more
power efficient than the linear regulator. The function of the linear
regulator is to filter the noise and generate the noise-free supply
that the system demands.

FIGURE 1.2 vSUPPLY

Sample low-noise 24 V
power
management vNOISY
2.4 V
system.
Ckt.

1.8 V
Load

vCLEAN
Ckt.

Load

Switching
regulator
Digital
load Linear
regulator
Analog
load
8 Chapter One

Similar operating conditions to those just described arise in many

other mixed-signal applications, where active power supply decoupling
is necessary to reduce and suppress noise. Systems demanding high-
output voltages from low input-supply voltages, as is the case for single-
or dual-battery packs (e.g., 0.9–1.5 V), require the use of boosting dc-dc
converters. As in Fig. 1.2, series regulators may still be required to sup-
press the switching noise generated by the switching regulator.

1.3.2 Integration
The mobile market’s impact on the demands of regulators is pro-
nounced. Because of high variations in battery voltage, virtually all
battery-operated applications require regulators. What is more, most
designs find it necessary to include regulators and other power-
supply circuits in situ, on-chip with the system to save printed-
circuit-board (PCB) real estate and improve performance. This trend
is especially prevalent in products that strive to achieve or approach
the fundamental limits of integration in the form of system-on-chip
(SoC), system-in-package (SiP), and system-on-package (SoP) solutions.
Limited energy and power densities are the by-products of such a
market, requiring circuits to yield high power efficiency and demand
low quiescent-current flow to achieve reasonable lifetime performance.

1.3.3 Operational Life

Current efficiency (ηI), which refers to a proportionately lower quies-
cent current when compared against the load current, is also vital. In
particular, quiescent current (IQ) must be as low as possible during
zero-to-low loading conditions because it amounts to a significant
portion of the total drain current of the battery. During heavy loading
events, on the other hand, higher quiescent current is acceptable
because its impact on total drain current and therefore battery life is
miniscule, which is why current efficiency, and not absolute quies-
cent current, is important:
I LOAD I LOAD (1.3)
ηI = =
I TOTAL I LOAD + IQ

Ultimately, the load alone determines the lifetime of the battery dur-
ing high load-current conditions and the regulator’s quiescent cur-
rent during zero-to-low loading events.
The capacity of a battery, defined in amp-hours, and the average
drain current sets the battery life of the electronic system:

Capacity[Ah] Capacity[Ah]
Life[h] = = (1.4)
I DRAIN(ave) IQ(ave) + I LOAD(ave)

This relationship, coupled with the fact that the majority of portable
devices idle most of the time, implies that battery life is a strong function
 System Considerations 9

40

Probability [%] 30 Mostly, RF PA is

in light-to-moderate
20 power region

10

0.2 0.4 0.6 0.8 1

Normalized output current [A/A]

FIGURE 1.3 Probability-density function (PDF) of a typical radio-frequency (RF)

power amplifier (PA) in a portable CDMA handset application.

of low load-current conditions, that is of IQ(ave). A cellular phone, for

instance, mostly idles (i.e., alert but not in talk mode) and consequently
requires only a fraction of its peak power most of the time, as depicted
by the probability-density function (PDF) in Fig. 1.3. As shown, the
region of highest probability is the zero-to-moderate load-current
range, which is where drain current is mostly comprised of quiescent-
current flow IQ:

IDRAIN(ave) = ∫ (I LOAD + IQ ) ⋅ PDF ⋅ dI LOAD ≈ IQ (1.5)

1.3.4 Supply Headroom

Battery power and state-of-the-art process technologies also imply
low-voltage operation. Today’s most popular secondary (i.e.,
rechargeable) battery technologies are lithium ion (Li Ion), nickel cad-
mium (NiCd), and nickel metal hydride (NiMH), the first of which
ranges from 2.7 V when completely discharged to 4.2 V when fully
charged and the latter two from 0.9 to 1.7 V. Microscale fuel cells have
even lower voltages, approximately at 0.4–0.7 V per cell. Ultimately,
the variable nature of these relatively low-voltage technologies super-
imposes stringent requirements on the regulator, limiting their sup-
ply headroom voltage and their available dynamic range to consider-
ably low levels.
Low-voltage operation is also a consequence of advances in pro-
cess technologies. The push for higher packing densities forces tech-
nologies to improve their photolithographic resolution, fabricating
nanometer-scale junctions, which have inherently lower junction
breakdown voltages. A typical 0.18 μm CMOS technology, for
instance, cannot sustain more than roughly 1.8 V. Additionally, since
financial considerations limit the complexity of the process, that is,
the number of masks used to fabricate the chip and therefore the vari-
ety of devices available, only vanilla (standard) CMOS and stripped
10 Chapter One

BiCMOS process technologies are most desirous, which translates to

less flexibility for the designer.
A low-voltage environment is restrictive for an analog IC designer.
Many traditional design techniques are prohibitive under these con-
ditions, limiting flexibility and sometimes system performance.
Cascoding devices, emitter and source followers, and Darlington-
configured bipolar-junction transistors costs, for instance, which are
useful for increasing gain, bandwidth, and current-driving capabili-
ties, require additional voltage headroom, which is a precious com-
modity in battery-operated devices. Low voltages also imply increased
precision, pushing performance down to fundamental limits. A 1%
1.8 V regulator, for example, must have a total variation of less than
18 mV, which includes 5–12 mV of load and line regulation effects,
extended commercial temperature extremes (e.g., −40o–125ºC), pro-
cess variations, noise and variations in the supply, and so on. What is
more, since dynamic range suffers in a low-voltage setting, the
demand for improved percent accuracy increases to sub-1% levels.
These issues typically give rise to more complex and usually more
expensive ICs (i.e., more silicon real estate and/or more exotic circuit
and/or process technologies), encouraging the designer to be more
resourceful and innovative.

1.4 Batteries
It is important to comprehend fully the environment in which many,
if not most, linear regulators find a home. Typical parameters to con-
sider in a battery, from an IC designer’s perspective, are capacity,
cycle life, internal resistance, self-discharge, and physical size and
weight. Cycle life refers to the number of discharge-recharge cycles a
battery will endure before significantly degrading its capacity, that
is, its ability to store energy. There are several types of batteries,
ranging from reusable alkaline and nickel cadmium (NiCd) to lith-
ium ion (Li Ion) and lithium-ion polymers. Unfortunately, however,
in spite of advances in battery technology, there is no one-battery
solution for all possible applications.

1.4.1 Early Batteries

Most portable electronics today use either nickel- or lithium-based
chemistries to power their systems. Reusable alkaline and lead-acid
batteries are not appropriate for high-performance applications
because of cycle-life and integration limits. Alkaline batteries, for
instance, have long shelf lives but suffer from short cycle lives and
low-power densities. They are therefore best suited for a range of
consumer electronics and gadgets that demand reliable operation on
an infrequent basis, like flashlights. Lead-acid batteries are economi-
cal and good for high-power applications, but they are bulky, which
 System Considerations 11

1.8
Cell voltage (V)

Cell voltage (V)

1.5 4.0

0.9 3.0

Time Time
(a) (b)

FIGURE 1.4 (a) NiCd and NiMH and (b) Li Ion discharge curves under a
constant load current.

is why only macroscale applications like the automobile industry

benefit most from their features, unlike the portable, handheld elec-
tronics industry.
Early cellular phones used nickel-based batteries: nickel cadmium
(NiCd) and nickel-metal hydride (NiMH). These nickel-based solu-
tions suffer from a phenomenon known as cyclic memory. To prevent
the negative effects of cyclic memory, which amounts to crystalline
formation and consequently higher self-discharge rates, periodical
discharge-charge cycles are necessary. Figure 1.4a illustrates the typical
discharge curve of these nickel-based devices, showing how most of
the usable energy is in the 1–1.5 V range.
NiCd batteries, which contain toxic metals, are the predecessors
of the NiMH solution, which is more environmentally friendly and
yields slightly higher energy densities and lower memory effects. The
advantages of NiMH, however, come at the cost of other performance
metrics. Figure 1.5, for instance, illustrates how NiCd eventually outper-
forms NiMH in almost every way over its cycle life. Not only is internal

NiCd NiMH
Capacity [%]
120 1000

90 800
[%]

[Ω]

60 Self-discharge 400
RInternal [Ω] rate [%]

30 200

0.2 0.4 0.6 0.8 1

Normalized number of cycles

FIGURE 1.5 Comparative performance of NiCd and NiMH batteries.

12 Chapter One

resistance lower for NiCd batteries but capacity, internal resistance,

and self-discharge remain relatively constant throughout their full
cycle life, roughly 1500 cycles’ worth. NiMH batteries perform well at
first but quickly degrade within 20% of the NiCd’s full life after a
limited number of charge cycles, giving them roughly half the usable
life of a NiCd battery. NiMH devices, nevertheless, continue to appeal
to the electronics industry because it is environmentally friendly, and
perhaps more importantly, from a marketing perspective, because the
life expectancy of most microelectronic products today is relatively
short, on the order of a year, limiting the number of recharge cycles to
within the range of NiMH technologies. Increased volume sales will
therefore spark innovation and advancements in technology and con-
sequently reduce the cost of NiMH batteries to more competitive lev-
els with respect to NiCd technologies.

1.4.2 Li Ion Batteries

Next in the evolutionary chain of rechargeable energy-storage devices
are the lithium-ion (Li-Ion) batteries, which have the highest energy
density levels, when compared to the nickel-based chemistries, and
they do not contain toxic metals or the dreaded memory effects. They
exhibit relatively constant capacity and internal-resistance performance
over most of their entire cycle life, which extends up to approximately
1000 cycles. Their self-discharge rates are miniscule when compared
against nickel-based chemistries. All these advantages come at the cost
of technology, that is, at a higher dollar premium (roughly twice the
cost), which is not to say the price will not decrease in the near future
because it will, as more and more of them are sold, benefiting from
economies of scale. Because of these reasons, most cellular phones, lap-
tops, and other portable consumer electronics use Li Ions.
At a slightly higher cost, Li-Ion polymers offer similar performance,
but with the ability to conform into thinner and smaller packages,
which is especially useful in handheld, wearable, and wireless-sensor
applications. Ultimately, most Li-Ion technologies conform to the dis-
charge curves shown in Fig. 1.4b, where most of its useful energy falls
within the 2.7–4.2 V region. Because of the sensitive nature of the chem-
istry, charging or discharging them beyond maximum- and minimum-
rated limits (4.2–2.7 V, normally) causes irreversible and sometimes
catastrophic effects, which is why the charging circuit for these batter-
ies is often more complex than for other technologies.

1.4.3 Fuel Cells

Li Ions are mainstream, but not ideal. They do not store enough
energy per unit weight or space for moderate-power, microscale sys-
tems, which is why fuel cells (FCs), energy harvesters, and nuclear
batteries are the subject of attention in the world of research. Figure 1.6
illustrates a Ragone plot of various energy-storage devices, depicting
 System Considerations 13

Harvester

ks

0s

1s
1k

10
10

10
Nuclear battery

s
0 m
10
Specific energy [Wh/kg]

Fuel cell

Li
fe
tim

s
Off-chip

m
e

10
capacitor

On-chip

s
1m
capacitor

Off-chip
Li Ion inductor

s
0μ
Specific power [W/kg] α ILOAD VLOAD 10
FIGURE 1.6 Ragone plot: comparative energy-power performance of various
energy-storage technologies.

their respective energy-to-power relationships. FCs, for instance, like

nuclear batteries and microscale energy harvesters, have higher
energy at low-power levels, whereas Li-Ion technology has higher
energy at higher power levels; in other words, given similar volume
constraints, a Li Ion outlives an FC under high-power conditions, and
vice versa. What is more, FCs are inherently slower to respond to
load changes than Li-Ion batteries, and with inherently lower volt-
ages (0.4–0.7 V). Ultimately, none of these technologies are ideal.
Researchers are therefore looking to improve each of these technolo-
gies separately and, at the same time, leveraging their complemen-
tary features in compact hybrid solutions.

1.4.4 Nuclear Batteries

In the battle for maximum energy storage, nuclear batteries over-
whelm the others at lower power levels, except for energy harvesters,
which provide essentially boundless energy. The main drawback is the
radioactive nature of the material used to build it, and its implied safety
and containment requirements. The secondary but equally relevant
disadvantage is its low power. The heat this technology generates,
however, can provide long-term fuel for thermoelectric generators—
for a decade, for instance. Similarly, the electrons emitted by decaying
isotopes can be used to establish electric fields across parallel and
14 Chapter One

mechanically compliant piezoelectric plates whose attractive force

bends the material and therefore generates current flow on contact.
The emitted electrons can also be used to generate electron-hole pairs
in pn-junction devices, much like photons are used in photovoltaic
solar cells; these devices are called β-voltaic batteries and enjoy the
same chip-integration benefits of solar cells. In the end, however,
safety and the cost of these isotopes prevent the penetration of these
batteries into the marketplace, but research certainly continues, as
their energy content is unequally high.

1.4.5 Harvesters
Last, but certainly not least, in the race for long battery life are energy
harvesters. These electric generators extract fuel energy from the
environment, from motion, heat, and pressure, and so on. These gen-
erators are at the forefront of research and solutions have yet to
mature, but they promise to compete with nuclear batteries in the
race for extended, perhaps even perpetual, life. Microscale harvesters
fabricated with microelectromechanical systems (MEMS) technolo-
gies are compatible with ICs and may therefore see the light of day,
but it is still too early to tell.

1.5 Circuit Operation

1.5.1 Categories
Power
There are various types of linear regulators catering to an assort-
ment of different applications. Generally, the most obvious distinc-
tion between them is power level. Low-power regulators, for
instance, normally supply output currents of less than 1 A, which is
typical of many portable and battery-powered electronics, and
high-power regulators source higher currents for automotive,
industrial, and other applications of the ilk. High-power linear reg-
ulators, however, are quickly losing ground to their switching
counterparts because of their power-efficiency performance deficit.
A system will more than likely use a master switching converter
and sprinkle linear regulators at various load points, conforming to
a point-of-load (PoL) regulation strategy. PoL provides better overall
performance in the form of dc and ac (noise content) accuracy at
each individual load. At present, linear regulators find most of
their market in the sub-300-mA region.

Compensation
Within the context of circuit architecture, two other major classifica-
tions exist: externally and internally compensated structures. A capacitor
used to stabilize the negative feedback loop of the regulator (i.e., to
 System Considerations 15

setting the dominant low-frequency pole) that is connected between

any two of the input/output (I/O) pins of the IC (i.e., input supply,
ground, and regulated output) is said to compensate the circuit exter-
nally. When an internal node is used for connecting a compensation
capacitor, the circuit is said to be internally compensated. In this latter
case, the capacitor hanging off the output cannot exceed a specified
maximum value because the output is a parasitic pole and increasing
its capacitance pulls the pole it sets closer to in-band frequencies, pos-
sibly giving rise to unstable conditions. Output capacitors for exter-
nally compensated circuits, on the other hand, set the dominant low-
frequency pole at the output and must therefore be sufficiently large
(i.e., exceed a specified minimum) to guarantee stable conditions.
Circuit applications normally require an output capacitor to sup-
press transient load excursions. Consider a linear regulator incurs
some finite delay before fully responding to quick load dumps, dur-
ing which time the output capacitor sources or sinks the difference. A
larger-output capacitor therefore droops less and yields better tran-
sient-response performance (i.e., less output voltage variation) in the
presence of load-dump events demanding substantial currents:

ΔiLOADtdelay 1
ΔvOUT = α (1.6)
COUT COUT

For instance, in the presence of a 50-ns, 1–11 mA load dump, a regula-

tor with a bandwidth of 100 kHz and a 0.47 μF output capacitor
allows its output voltage to droop approximately 10 mA(3/2π ⋅ 100
kHz · 50 ns)/0.47 μF or 101 mV before responding and sourcing the
full load. Unlike internally compensated regulators, the output capac-
itor’s requirements for an externally compensated circuit align well
with transient-noise suppression, which is why users prefer exter-
nally compensated circuits, in spite of the dollar and printed-circuit-
board (PCB) real-estate costs associated with off-chip capacitors.
The advent of system-on-chip (SoC) and system-in-package (SiP)
integration is slowly changing the trend from externally to internally
compensated schemes, however. As the IC absorbs more circuits and
regulators into its common silicon substrate, external capacitors are
increasingly more difficult to accommodate. Externally compensated
circuits (where the dominant low-frequency pole is at the output) are
therefore appearing under the guise of internally compensated ICs
simply because the output capacitor, although still hanging off the
output node, is in the IC and no off-chip capacitor is required.
Although advertised as internally compensated structures, for the
sake of the discussions in this text, given their technical implications
on the circuit and feedback loop, linear regulators whose dominant
low-frequency pole is at the output are said to be externally compen-
sated, whether the compensation capacitor is on-chip or not.
16 Chapter One

Dropout
Linear regulators are also classified as low or high dropout (LDO or
HDO), which refers to the minimum voltage dropped across the cir-
cuit, in other words, the minimum difference between the unregu-
lated input supply and the regulated output voltage (VDO in Fig. 1.7).
This voltage is important because it represents the minimum power
dissipated by the regulator, since the power lost is dependent on the
product of the load current and this dropout voltage. Low-dropout
(LDO) regulators consequently dissipate less power than their higher
dropout counterparts and have therefore enjoyed increasing popular-
ity in the marketplace, especially in battery-operated environments.
Linear regulators with dropout voltages below 600 mV belong to the
low-dropout class, but typical dropout voltages are between 200 and
300 mV.
Figure 1.7 also illustrates the three regions of operation of a linear
regulator: linear, dropout, and off regions. When the circuit is operating
properly, that is to say, when it regulates the output with some finite
and nonzero loop gain, the regulator is in the linear region. As input
voltage vIN decreases, past a certain point, one of the transistors in the
loop enters the triode region (or low-gain mode) during which time
the circuit still regulates the output, albeit at a lower loop gain and
consequently with some gain error. As vIN decreases further, the loop
gain continues to fall until it becomes, for all practical purposes, zero,
when it reaches its driving limit. At this point, the regulator enters the
dropout region and the power switch, given its limited drive, oper-
ates like a switch because it supplies all the current it can to maintain
the highest possible output voltage. The voltage difference between
vIN and vOUT in this region is dropout voltage VDO, and although VDO is
at first approximately constant, as though it were a resistive ohmic
voltage drop, it tends to increase with decreasing values of vIN—data-
sheets often quote the equivalent resistance during the mostly linear

vIN
(2) Dropout vIN
region
(3) Off (1) Linear
region vOUT
Linear
region
[V]

VDO vOUT
Low loop gain
No loop gain (max. drive)
No headroom

Input voltage - vIN[V]

FIGURE 1.7 Typical input-output voltage characteristics of a linear regulator.

 System Considerations 17

Linear regulators

High power Low power

(ILOAD > 1 A) (ILOAD < 1 A)

Externally Internally
compensated compensated
(PoleDominant @ vout) (PoleDominant = Inside)

Off-chip cap. On-chip cap. Off-chip cap. On-chip cap.

High dropout (HDO) Low Dropout (LDO)

(VDROPOUT > 0.6 V) (VDROPOUT < 0.6 V)

FIGURE 1.8 Linear regulators and their corresponding subclasses.

portion of the dropout region. The off region is where the circuit
reaches its headroom limit, when the input supply voltage is too low
for the transistors to work properly, and more specifically, for the
negative feedback control loop to process that vO is below its target
and keep some drive applied to the power switch.
In summary, linear regulators can be high or low power, exter-
nally or internally compensated, and high or low dropout, as depicted
in Fig. 1.8. Most linear regulators of interest nowadays fall in the low-
power regime. Because of improved efficiency performance, switch-
ing converters now fill a wider high-power market segment, from
which several low-power subsystems derive power directly or via
series linear regulators. Internally compensated linear regulators
with only on-chip capacitors, though not as popular today, are highly
desirable because of their low PCB real-estate and dollar-cost impli-
cations. They respond poorly to quick load-dump events, however,
and therefore suffer from degraded ac accuracy performance. Their
popularity is growing in lower power application-specific ICs (ASICs),
however, where one or several linear regulators share the silicon die
with their respective loading components.
Convolving the general characteristics just described with the
increasing market demand for portable, battery-powered electronics
birth a niche market for low power, internally compensated, (LDO)
regulators. This consumer market segment demands the small-foot-
print and extended-life solutions internally compensated circuits
with low-dropout voltages enable. Decreasing the voltage dropped
across the regulator (i.e., the difference between the unregulated sup-
ply and the regulated output) reduces the power dissipated by the
18 Chapter One

regulator (PLDO) and therefore increases efficiency, which ultimately

translates to extended single-charge operational life:

PLDO = IQUIESCENTVIN + ILOADVDO ≥ ILOADVDO (1.7)

Dropout voltage and load current, as seen in the relation above,

define the minimum power a linear regulator can ever dissipate under
moderate-to-full loading conditions. The dropout voltage specifica-
tion is therefore of paramount importance.
From the viewpoint of battery-supplied systems, LDO regulators
relax the headroom limits and increase the dynamic range and signal-
to-noise ratio (SNR) performance of their loading circuits, which are
normally the first to degrade when the input supply voltage decreases.
For instance, if an almost drained Li Ion (i.e., VIN is roughly 2.7 V)
powers an LDO regulator with a dropout of 0.2 V, which then powers
an operational amplifier whose noise floor is 10 mV, the operational
amplifier would have to operate under a 2.5 V regulated supply,
which is, for all practical purposes, already a low supply voltage. All
processing must therefore fall within a 2.5 V window, which qualita-
tively sets the maximum possible dynamic range of the circuit:

dynamic range 2.5 V

SNR = = = 250 (1.8)
noise floor 10 mV

Had the regulator been a high-dropout (HDO) device with a dropout

of 0.7 V, the operational amplifier would have had to work under a
2.0 V regulated supply, which imposes serious restrictions on the
amplifier circuit, not to mention its ability to process analog informa-
tion, now within a 2.0 V window and a signal-to-noise ratio of less
than 200. Additionally, the output voltage, as depicted in Fig. 1.7,
exhibits less variation over the full span of the unregulated supply
range with an LDO circuit than with an HDO regulator, since the
onset of dropout is lower for LDO regulators.
Low-dropout voltages are necessary in many applications, from
automotive and industrial to medical. The automotive industry, for
instance, exploits the low-dropout characteristics of LDO regulators
during cold-crank conditions, when the car-battery voltage is between
5.5 and 6 V and the regulated output must be around 5 V, requiring a
loaded dropout voltage of less than 0.5 V. The increasing demand is
especially apparent, however, in mobile battery-operated products
such as cellular phones, pagers, camera recorders, and laptops. Such
space-efficient designs only use a few battery cells, thereby necessar-
ily decreasing the available input supply voltage. In these cases, LDO
regulators are capable of supplying relatively high output voltages.
For instance, if two NiCd cells, which have an approximate range of
1.8–3 V, power an HDO regulator, the maximum output voltage
over the life span of the battery is less than 1.2 V. This output voltage
 System Considerations 19

is not sufficiently high to meet the headroom requirements of most

analog circuits. What is more, the restriction is prohibitive for single
battery-cell conditions.

1.5.2 Block-Level Composition

A regulator is mainly comprised of a control loop whose function is
to monitor and control its output to remain within a small window of
a target reference value, irrespective of its environment and its oper-
ating conditions. A regulator circuit must therefore sense the output,
compare it against a reference, and use the difference to modulate the
conductance between the input supply and the regulated output. In
the case of a voltage regulator, a feedback network senses the output,
as shown in Fig. 1.9, and feeds it to an error amplifier, whose function
is to compare it against a reference voltage and generate an error sig-
nal that modulates the conductance of a pass device. The circuit is
essentially a noninverting operational amplifier with a dc reference
voltage at its noninverting input.
There are two major blocks in a voltage regulator: a voltage refer-
ence and the control loop. The latter is comprised of (1) an error
amplifier to sense and generate a correcting signal, (2) a feedback net-
work to sense the output, and (3) a pass device to mediate and con-
duct whatever load current is required from the unregulated input
supply to the regulated output. The control loop, in essence, reacts to
offset and cancel the effects of load current, input voltage, tempera-
ture, and an array of other variations on the output. The reference

vIN

Error amp.
Voltage reference

vREF
+
Pass
device
–

vOUT
Housekeeping

rOUT

Control loop
Feedback network

FIGURE 1.9 General block-level composition of a linear regulator.

20 Chapter One

block provides a stable dc-bias voltage that is impervious to noise,

temperature, and input-supply-voltage variations. The reference’s
current-driving capabilities are for the most part severely limited, as
mentioned earlier in the chapter.
Housekeeping functions are essential to the overall health of the
device. They ensure the system operates safely and reliably, protecting
the regulator from extreme adverse conditions. Plausible destructive
scenarios include exposure to overcurrent, overvoltage, overtemperature,
short-circuit, and electrostatic discharge (ESD) events. Housekeeping
circuits can also have application-specific features like enable-disable
and soft- or slow-start functions for power-moding a system.

1.5.3 Load Environment

Composition
Figure 1.10 illustrates the typical operating environment of a linear
regulator IC. The effective loading elements include the parasitic devices
associated with the package of the IC, filter capacitors, PCB, and loading
circuits. The model presented assumes that the effective load of the
regulator begins at the pin and not at the bond-pad because that is
the regulation point, where the sense-feedback node is connected. If
there is no bond wire allocated to the sense node, the effective load
starts at the bond pad, where both the power device and sense node
converge. In the case the regulation point is at the pin, as in Fig. 1.10,
the parasitic bond wire inductance (LBW) and resistance (RBW) are part
of the regulator, and the feedback loop consequently combats to mitigate
their adverse effects on the output; in other words, the loop regulates
the output against any variations in LBW and RBW.
Output capacitor COUT suppresses the transiently induced voltage
variations on the output, as mentioned earlier, and for the case of
externally compensated regulators, sets the dominant low-frequency
pole of the controlling negative-feedback loop. The output capaci-
tance is normally on the order of several microfarads, as is for input

vREG Effective load

VIN RBW LBW vLOAD
LBW RBW LPCB RPCB iO Load
VI V
RESR O
RESR
CLOAD

Sense
rLOAD
iLOAD

CIN CB
IC: Reg. LBW RBW COUT
Chip

Pin LPCB RPCB

FIGURE 1.10 Typical loading environment of a linear regulator IC.

 System Considerations 21

filter capacitor CIN, which is also used to suppress transient noise in

light of the parasitic effects prevalent in practical batteries, such as
finite output resistances and limited response times. Because of lower
cost, tantalum capacitors are normally used. These devices, as all oth-
ers to various degrees, exhibit a parasitic equivalent-series resistance
(ESR) denoted in the figure as RESR, the value of which can be up to
several ohms.
Ceramic and ceramic multilayer chip (CMC) capacitors have low
ESR values and consequently lend themselves for higher frequency
applications and improved transient-noise suppression, which is
why designers often place them near the load, as bypass capacitors
(CB in Fig. 1.10). These higher cost devices are normally in the nano-
farad region and, in a multiload environment, sum to less than 1 μF.
The inspiration behind placing them at the load is point-of-load (PoL)
performance such that they supply most of the almost instantaneous
load current and ease the drooping effects of the same, supplying the
necessary current at the load. Without these high-frequency capaci-
tors, tantalum output capacitor COUT would have delivered the cur-
rent through the series parasitic resistors and inductors introduced
by Cout and the PCB (RPCB and LPCB).
Capacitors also exhibit an equivalent-series inductance (ESL), the
magnitude of which is typically less than 5 nH. The effects of this para-
sitic inductance are often negligible in low-power and low-bandwidth
applications. A 10 mA load dump, for example, through a 5 nH induc-
tor in 1 μs produces an ESL voltage of 50 μV (LΔi/Δt = 5 nH · 10
mA/1 μs). On the other hand, a 100 mA load dump that happens in
50 ns across a 5 nH inductor produces an ESL voltage of 10 mV (5 nH ·
100 mA/50 ns), which on a 1 V output constitutes a 1% variation, not
including the effects of load and line regulation, capacitor transient
droop, temperature, and process variations on the output.
In general, all parasitic devices present in the power path of the
regulator cause negative effects on dc, transient, and efficiency per-
formance. Series parasitic bond wire and PCB resistors RBW and RPCB
introduce load-dependent series dc ohmic voltage drops and power
losses, producing a lower-than-anticipated voltage at the load and
higher than expected power losses. Parallel multiple bond wires
appeal to the designer because they produce lower series resistances
and inductances. For similar reasons, loads that are close to the regu-
lator (with short and wide PCB traces) also produce lower voltage
drops and power losses.

Point of Load (PoL)

From the perspective of regulation performance, it is best to sense
and regulate the load voltage at the point of load (PoL), not at the
output of the power-pass device of the regulator, which is why a star
connection at the load with a dedicated sense pin yields the best
results. The objective is to decouple the regulation point from the
22 Chapter One

parasitic voltage drops in the power-conducting path, allowing the

loop to regulate the load against the reference more accurately. Since
the sense node neither sinks nor sources current, no series voltage
drops exist in its path. This star connection, where current- and non-
current-carrying signal paths belonging to the same node converge at
one single point and nowhere else, is also called a Kelvin connection.
Many applications, however, cannot afford to dedicate a pin for this
purpose and resign themselves to a separate sense pad but with a
common output-sense pin, as shown in Fig. 1.10. If the application
also prohibits the use of multiple bond pads, the sense node is con-
nected to the output at the bond pad, and nowhere else inside the IC,
via a dedicated sense path. The objective, in general, is to push the
sensing and regulation point as close to the load as the application
and technology allow.

The Load
The actual “load” is difficult to model because of its unpredictable
nature—the designer is often unaware of what will ultimately load
the regulator, except in application-specific cases. As it applies to the
regulator, however, dc current ILOAD, equivalent load resistance rLOAD,
and equivalent load capacitance CLOAD are the most important param-
eters because they set the biasing condition of the regulator and the
small-signal loading impedance of the same, which affects its stabil-
ity conditions. Load current iLOAD spans the maximum range specified
for the regulator (e.g., 1–50 mA) and incurs the worst-case load dumps
for the system during transient conditions, which amounts to the maxi-
mum possible load step in the shortest time possible (e.g., 1– 25 mA in
100 ns).
Not knowing the exact nature of the load makes it impossible to
predict rLOAD accurately, yet its impact on stability and circuit require-
ments can be profound. If a low-power operational amplifier whose
lowest impedance path to ground may be a diode-connected transis-
tor (with small-signal resistance 1/gm) in series with an active load
(with relatively larger small-signal resistance rds or ro) loads the regu-
lator, the equivalent-load resistance would be on the order of tens to
hundreds of kilo-ohms. High-power amplifiers, on the other hand,
deliver substantial currents to low-impedance outputs, normally sub-
jecting the supply transistor to its triode region (i.e., low-resistance
switch mode) and in series with the low-impedance output. The slew-
ing amplifier therefore establishes a sub-kilo-ohm path from input
supply to ground. In the case of digital circuits, like inverters and
other CMOS gates, both pull-down and push-up transistors simulta-
neously conduct shoot-through current during transitions. Although
these transitions are short, the equivalent resistance from the supply
to ground is the average series combination of two switch-on resis-
tors, both of which are considerably low in value. In the end, rLOAD
may span a wide range of resistances.
 System Considerations 23

The designer, for reliability concerns, must therefore consider all

extreme conditions: (1) load is purely resistive (iLOAD is zero and rLOAD =
VOUT/ILOAD) and (2) load is only a current sink (rLOAD is infinitely large
or altogether removed). For example, the worst-case (extreme) rLOAD
and iLOAD combinations of a 1–50 mA 2.5 V LDO are (1) 2.5 kΩ
(2.5 V/1 mA) and 0 mA, (2) 50 Ω (2.5 V/50 mA) and 0 mA, (3) infi-
nite resistance and 1 mA, and (4) infinite resistance and 50 mA,
respectively. Simply assuming the load is purely resistive may be
unrealistically optimistic or pessimistic. In the case of internally com-
pensated LDOs, for instance, whose output pole is parasitic to the
system, a purely resistive load places the output pole at optimistically
higher frequencies. Subjecting this LDO to a higher impedance load
pulls the output pole to lower frequencies, compromising the stabil-
ity of the system. Similarly, assuming the load is purely active, that is,
only a current sink, may be unrealistically optimistic in the case of
externally compensated LDOs, where the dominant low-frequency
pole is at the output and a high-impedance load optimistically places
this pole at lower frequencies. A lower impedance load pushes the
output pole to higher frequencies, closer to the parasitic poles of the
system, where stability may be compromised.
Equivalent load capacitance CLOAD is often negligible when com-
pared against bypass and output capacitors CB and COUT. This is espe-
cially true for standard commercial-off-the-shelf (COTS) LDO ICs
and moderate power LDOs because their output capacitors are neces-
sarily large. System-on-chip (SoC) applications, however, do not
always enjoy this luxury because COUT is on-chip and therefore con-
siderably smaller than their off-chip counterparts. Some SoC imple-
mentations, in fact, rely entirely on CLOAD for stability and transient
response, altogether eliminating the need for COUT—this is equivalent
to using CLOAD as COUT. As with rLOAD, CLOAD in an SoC environment can
play a pivotal role in establishing the stability conditions of the sys-
tem, which is why the designer must consider all possible values.
However, in the presence of a substantially larger COUT and CB combi-
nation, CLOAD is less important.

1.5.4 Steady-State and Transient Response

Simplified Model
Before subjecting a transient load-dump event the model presented in
Fig. 1.10, it is helpful and convenient, for the sake of design and insight,
to simplify the schematic to those components whose effects domi-
nate the dc, frequency, and transient response of the system. For one,
load and bypass capacitors CLOAD and CB are in parallel and can there-
fore conform to a single equivalent bypass capacitance, as denoted by
CB′ in the now simplified model of Fig. 1.11—given the typical larger
values of CB relative to CLOAD, CB′ normally simplifies to CB. Because
the current flowing through the sense path is negligibly small, the
24 Chapter One

vREG
VIN RBW LBW vLOAD
LBW RBW L′PCB R′PCB iO Load
VI V
RESR O

Sense RESR

rLOAD
iLOAD
CIN CB¢
IC: Reg. COUT
Chip

Pin

FIGURE 1.11 Simplified operating environment of a linear regulator IC.

voltage drops associated with its relevant series parasitic bondwire

resistance and inductance are practically zero, which is why these
components no longer form part of the model. Similarly, when com-
pared with load current iLOAD, LDO’s ground current, which is nor-
mally just the quiescent current of the regulator, is small; as a result,
the adverse effects of iLOAD on the load overwhelm those of this cur-
rent so its parasitic devices are also removed from the simplified
model. Lastly, the series-parasitic elements in the supply and ground-
return paths of the load in the PCB have an aggregate effect on load
voltage vLOAD relative to regulated output VREG—neglecting the effects
of the load’s small-signal output resistance rLOAD:

vLOAD = vREG − iLOAD (RPCB _ SUPPLY + RPCB_GND )

diLOAD
− (LPCB _ SUPPLY + LPCB _ GND ) (1.9)
dt
and can therefore conform and simplify to a single set of lumped
elements,

⎛ di ⎞
vLOAD = vREG − I LOAD RPCB
′ − ⎜⎝ LOAD ⎟⎠ LPCB
′ (1.10)
dt

where R′PCB and L′PCB are the lumped total supply and ground-return
PCB path series parasitic resistance and inductance of the load, as
shown in Fig. 1.11.

DC Variations
Steady-state changes in load current ILOAD , as noted in the previous
equation, decrease dc load voltage VLOAD below its targeted regulated
value VREG. Had the sense node been connected to the output at the
bond pad, the effect would have been increased, adding RBW to the
existing RPCB′. Conversely, dedicating a pin to the sense node and con-
necting it to the load at the load (i.e., Pol) would have eliminated the
 System Considerations 25

adverse effects of both RBW and R′PCB. When the circuit enters the
dropout region, however, the voltages across these parasitic devices
effectively increase the dropout voltage of the LDO, again, degrading
its overall performance, irrespective of where the sense node is
connected.

Transient Variations
In a worst-case transient load-dump event, the load current ramps up
or down to its extreme values in a short time. Considering a positive
load dump, for instance, when load current rises quickly, the LDO is
at first unable to supply the load because it needs time to react and
adjust (i.e., it has limited bandwidth). Filter capacitors COUT, CB, and
CLOAD therefore supply this initial jump in current, most of which is
derived from COUT because it presents a considerably lower imped-
ance path than CB and CLOAD (COUT is larger than CB and CLOAD com-
bined and impedance (1/sCOUT) + RESR is therefore smaller than 1/
sCB′). The net effect is an instantaneous voltage drop across L′PCB (VL =
L′PCB · di LOAD/dt) that lasts as long as iLOAD is changing, another instan-
taneous voltage drop across RESR and R′PCB (ΔiLOAD · (RESR + R′PCB)) and a
voltage-droop response across COUT , the latter two of which last until
the LDO responds and supplies the full load (ΔiLOAD/BW · COUT). All
of these parasitic effects amount to an undesired transient voltage
drop in load voltage vLOAD. Eventually, the IC supplies the full load
and again reaches steady-state operation, at which point COUT, CB, and
CLOAD cease to conduct displacement current and all these parasitic
voltages disappear. For negative load dumps, similar effects occur
and vLOAD temporarily rises above its ideal targeted value.

1.6 Specifications
Three categories aptly describe the operating performance of a linear
regulator: (1) dc- and ac-regulating (accuracy) performance, (2) power
characteristics, and (3) operating requirements. The regulating per-
formance refers to the IC’s ability to regulate its output against varia-
tions in its operating environment. The metrics used to gauge this
performance include load regulation, line regulation, power-supply
rejection, temperature drift, transient load-dump variations, and
dropout voltage. All these parameters essentially portray the behav-
ior of the circuit with respect to load current, input voltage, and junc-
tion temperature. Quiescent-current flow, sleep-mode current, power
efficiency, and current efficiency as well as dropout voltage, indi-
rectly, depict the power characteristics of the regulator. Sleep-mode
current is the current flowing through the IC while disabled, if an
enable-disable function exists, or during low-performance mode (i.e.,
low-bandwidth setting). Current efficiency refers to the ratio of load
to input current, which is especially important during low load-current
conditions (i.e., device is idling and output current is consequently low).
26 Chapter One

The operating limits of the input voltage, output voltage, output

capacitance (and associated ESR), and load current define the envi-
ronment within which the regulator must operate functionally and
within parametric compliance.

1.6.1 Regulating Performance

Load Regulation
Steady-state (dc) voltage variations in the output (ΔVOUT) resulting from
dc changes in load current (ΔILOAD) define load regulation (LDR) perfor-
mance, which ultimately constitutes an ohmic voltage drop, that is, a
linearly load-dependent voltage drop at the output of the regulator:

Δ VOUT ROL
RLDR = ≡RO-REG + RPAR =
Δ I LOAD 1 + AOL βFB
DC

ROL
+ R PCB
′ ≈ + R PCB
′ (1.11)
AOL βFB
DC

where RLDR is the load-regulation resistance, RO-REG the closed-loop out-

put resistance of the regulated loop, ROL the open-loop output resis-
tance from the sense node into the IC, AOL the open-loop gain, β FB the
negative feedback-gain factor, and loop gain AOLβFB is evaluated at dc
because load regulation is a steady-state parameter (all frequency com-
ponents are neglected). Obviously, increasing AOL and decreasing PCB
resistance RPCB′ improves load-regulation performance. Systematic
input-offset voltages, which result from asymmetric currents and volt-
ages in the feedback error amplifier, further degrade load-regulation
performance. Even if the LDO were symmetric, its widely variable
load would cause considerable voltage swings at internal nodes, sub-
jecting some of the devices to asymmetric conditions. Because the
open-loop gain is relatively low (the reason for this is described in a
later chapter), there is a systematic load-dependent input-referred offset
voltage (VOS_S), which should be included in LDR:

⎛ Δ VOS_S ⎞ ⎛ VOUT ⎞
RLDR = RO-REG + RPCB
′ +⎜ ⎟
EFF
⎝ Δ I LOAD ⎠ ⎜⎝ VREF ⎟⎠

⎛ Δ VOS_S ⎞
= RO-REG + RPCB
′ +⎜ ⎟ ACL (1.12)
⎝ Δ I LOAD ⎠

where RLDREFF is the effective LDR, ΔVOS_S the systematic variation of

VOS_S with respect to a dc change in load current ΔILOAD, and VOUT/VREF
and ACL the dc closed-loop gain from reference VREF to output VOUT
(e.g., a 2.4 V LDO referenced with a 1.2 V bandgap has a closed-loop
gain of roughly 2: 2.4 V/1.2 V).
 System Considerations 27

Line Regulation
Line regulation (LNR) performance, like load regulation, is also a dc
parameter and it refers to output voltage variations arising from dc
changes in the input supply, in other words, to the low-frequency sup-
ply gain of the circuit (i.e., LNR is AIN, which refers to ΔvOUT/ΔvIN).
Power-supply rejection PSR (also known as ripple rejection), on the other
hand, is not only the complement of supply gain AIN, in that it refers to
rejection, but it also includes the entire frequency spectrum, not just dc.
Datasheets, as a result, typically quote ripple-rejection values at dc
and other specific frequencies (e.g., 50 dB at dc, 40 dB at 1 kHz, etc.).
Power-supply variations affect the regulator in two ways: directly
through its own supply and indirectly via supply-induced variations
in reference vREF. The reference, as it turns out, is a sensitive node because
the regulator, being that it presents a noninverting feedback amplifier
to vREF (refer to Fig. 1.9 to visualize how vREF and vOUT relate), amplifies
variations in vREF by the regulator’s closed-loop gain (ACL). The overall
supply gain AIN is therefore a function of both the supply gain of the
regulator [Link] and the supply gain of the reference [Link]:

Δ vOUT
AIN ≈ = [Link] + [Link] ACL
Δ vIN
⎛ Δv ⎞ ⎛ Δv ⎞
= ⎜ OUT ⎟ + ⎜ REF ACL⎟ (1.13)
⎝ Δ vIN ⎠ ⎝ Δ vIN ⎠
Δ v REF =0 Δ v [Link] = 0

where superposition is applied and [Link] is evaluated when there is

no variation in the reference and [Link] when there is no variation in
the input supply of the regulator. Because PSR is AIN’s complement,
PSR reduces to

1 1
PSR ≈ ≈ = PSR REG
AIN [Link]

and LNR, since it only applies to the dc portion of supply gain AIN, is

1 1
LNR = AIN = AIN0 = ≈ (1.14)
DC PSR 0 PSR REG0

Normally, vREF’s supply rejection PSRREF is considerably higher than

PSRREG so vREF’s effects are often insignificant and therefore neglected,
but justifying this assumption is critical.

Temperature Drift
In more generalized terms, any variation in the reference propagates
to the output of the regulator through the equivalent closed-loop gain
of the regulator. As such, any temperature effects on the reference, as
28 Chapter One

in the case of ripple-rejection analysis with supply-derived noise, also

have adverse effects on the regulated output. These effects are in
addition to the temperature effects of the regulator, which manifest
themselves through temperature dependence in the input-referred
offset voltage. The metric that gauges the extent of the impact of tem-
perature on the output is fractional temperature coefficient (TC), which
is the percentage variation of the output in response to temperature
changes per degree of temperature change:

⎛V ⎞
(ΔvREF + ΔvOS ) ⎜ OUT ⎟
1 ⎛ dvOUT ⎞ 1 ⎛ ΔvOUT ⎞ ⎝ VREF ⎠
TC ≡ ⎜⎝ ⎟⎠ ≈ ⎜ ⎟=
VOUT dT VOUT ⎝ ΔT ⎠ VOUT ΔT

⎛ Δv + ΔvOS ⎞ 1 (1.15)
= ⎜ REF ⎟⎠ ΔT
⎝ VREF

where ΔvREF and ΔvOS are the temperature-induced variations of refer-

ence voltage vREF and input-referred offset voltage vOS and ΔT the cor-
responding change in temperature. Consequently, accuracy in the
reference and input-offset voltage in the error amplifier are key char-
acteristics for determining the overall temperature-drift performance
of the regulator.

Transient Variations
Noise content (ac accuracy) is another important metric in linear regula-
tors. The principal cause of noise is typically systematic in nature,
either from a switching load or a switching supply. In the case of a
switching load, the output impedance of the regulator, which is com-
prised of the output capacitance COUT and CB and load-regulation out-
put impedance rLDR (ac counterpart of [Link]) determines the extent
to which the noise is suppressed. Similarly, ripple rejection limits the
noise injected from the input supply. Given the mixed-signal nature
of modern systems today, even with reasonable output impedances
and ripple-rejection capabilities, both switching supplies and switch-
ing loads inject substantial noise into the system. Inherent shot, ther-
mal, and 1/f noise are normally not as important and often neglected
in specifications as a result. This is not to say, however, systematic
switching noise always overwhelms inherent noise, especially when
considering extremely sensitive and high-performance applications.
Transiently induced voltage variations also contribute to the
overall ac accuracy of the regulator. The worst-case variation occurs
when the load current suddenly transitions from its lowest rated
value (e.g., zero) to its maximum peak, or vice versa, which comprise
the positive and negative load-dump conditions graphically illustrated
in Fig. 1.12. The response is normally asymmetrical in nature because
 System Considerations 29

Δt1 Δt2

ΔvTR–
vOUT
ΔvLDR

Δt3
ΔvTR+

iLOAD

Time [s]

FIGURE 1.12 Typical transient response to positive and negative load dumps
(i.e., sudden load-current changes).

the error amplifier’s ability to charge and discharge the input of the
pass device is also asymmetrical. To be more specific the output stage
of the error amplifier is a buffer whose purpose is to drive the input
of the pass device, which is highly capacitive, given its large physical
dimensions. For simplicity, the buffer normally conforms to class-A
operation, which is capable of pushing or pulling substantial current,
but not both. As a result, the buffer typically slews into the highly
capacitive node in one direction and not the other, giving rise to dif-
ferent response times and therefore asymmetrical effects on the regu-
lated output. A symmetrical response is possible with class-B and
class-AB buffers but they usually require more silicon real estate,
complexity, and noise, which amount to higher cost.
In the case of a positive load dump, when current suddenly rises,
the additional load current (ΔiLOAD) discharges the output filter capac-
itors until enough time elapses to allow the loop (i.e., the regulator) to
respond (in Δt1). The internal slew-rate conditions of the feedback
loop (i.e., when class-A buffer slews) normally govern the extent of
response time Δt1, which exceeds the corresponding bandwidth time
(1/BWCL). After the circuit has time to react, the pass device responds
by supplying load current iLOAD and additional current to charge and
slew the output filter capacitors back to their targeted regulated volt-
age. The regulated output voltage ultimately settles to the voltage
corresponding to the new load-current value, which is the ideal volt-
age minus the load-regulation effect of the loop (ΔVLDR). When a
negative load dump occurs (i.e., current falls quickly), the extra cur-
rent the pass device initially sources, which cannot decrease until the
30 Chapter One

regulator has time to react, charges the output filter capacitors. When
enough time elapses to allow the loop to respond (Δt2 ≈ 1/BWCL), the
regulator stops sourcing current and allows whatever sinking capa-
bilities it has (i.e., feedback network) to discharge and slew the out-
put capacitor back to its targeted output voltage.
The resulting variation of the regulated output in response to
these load dumps degrades the overall regulating performance of the
regulator and amounts to transient accuracy. As noted in Fig. 1.12, the
regulator ultimately experiences load-regulation effects (ΔVLDR =
Δ[Link]), which, for technical accuracy, should be distinct and
decoupled from the total effects transient-response accuracy has on
the output (ΔvTR). Load-regulation voltage drop ΔVLDR is therefore
subtracted from total load-dump-induced variations ΔvTR+ and ΔvTR–.
During a positive load dump, when load current suddenly
increases, referring to the effective load model shown in Fig. 1.11, out-
put capacitor COUT and total bypass capacitor CB′ supply additional
load current ΔiLOAD. Since COUT is normally more than an order of
magnitude higher than CB′ (impedance 1/sCOUT is much smaller than
1/sCB′), most of ΔiLOAD flows through COUT and ESR resistor RESR, the
result of which is an instantaneous voltage across RESR equivalent to

⎛ COUT ⎞
Δ vESR ≈ ⎜ Δi R (1.16)
⎝ COUT + CB′ ⎟⎠ LOAD ESR

and a droop voltage across COUT and CB′. The aggregate effect on the
output, considering this condition persists until the regulator reacts
(i.e., Δt1 after the onset of the load dump), is

⎛ ΔiLOAD ⎞
ΔvTR + ≈ ⎜ Δt1 + ΔvESR
⎝ COUT + CB′ ⎟⎠

⎛ ΔiLOAD ⎞
≈⎜ (
⎝ COUT + CB′ ⎟⎠
)
Δt1 + COUT R ESR (1.17)

The bypass capacitors have a filtering effect on this total variation,

decreasing its magnitude when more low-ESR capacitance is present.
As already mentioned, the slewing conditions of the class-A buf-
fer against the parasitic capacitance presented by the large series pass
device (CPAR) set response time Δt1. Before the onset of these slew-rate
conditions, however, the loop must have sufficient time to react and
initiate the slew command, producing in the process a bandwidth-
limited delay that is proportional to the reciprocal of the closed-loop
bandwidth (BWCL) of the regulator (approximately 0.37/BWCL—refer
to App. A). After this, the biasing current of the buffer (IBUF) slews
parasitic capacitor CPAR (producing ΔvPAR) until enough drive exists
 System Considerations 31

across the power pass device to fully supply load current iLOAD. Total
response time Δt1 therefore approximates to

0 . 37 ⎛ Δv ⎞ 0 . 37 ⎛ Δi ⎞
Δt1 ≈ + CPAR ⎜ PAR ⎟ ≈ + CPAR ⎜ LOAD ⎟ (1.18)
BWCL ⎝ BUF ⎠
I BW CL g I
⎝ mp BUF ⎠

where gmp is the transconductance of the power pass device. If slew-

rate current IBUF is sufficiently high, response time Δt1 reduces to 0.37/
BWCL. This response-time improvement and independence to CPAR
result at the expense of quiescent-current flow, that is to say, reduced
power efficiency and battery life.
During a negative load dump, when load current suddenly drops,
the regulator continues to source initial load current ILOAD, pushing the
difference (ΔiLOAD) into output filter capacitors COUT and CB′. As a result,
similar to a positive load dump, RESR incurs an instantaneous voltage
across its terminals and output filter capacitors COUT and CB′ slew until
the regulator responds, at which point the pass device shuts off and
allows the output to drop to its steady-state value. Assuming the class-
A buffer slews for positive load dumps and not negative load dumps,
only the closed-loop bandwidth of the loop sets the corresponding
negative load-dump response time to approximately 0.37/BWCL,
giving rise to a full negative load-dump variation (ΔvTR–) of

⎛ ΔiLOAD ⎞ ⎛ ΔiLOAD ⎞ ⎛ 0 . 37 ⎞
ΔvTR − ≈ ⎜ Δt2 + ΔvESR ≈ ⎜ + COUT RESR⎟
⎝ COUT + CB′ ⎟⎠ ⎝ COUT + CB′ ⎟⎠ ⎜⎝ BWCL ⎠
(1.19)
To decouple load regulation from transient-accuracy performance,
LDR voltage ΔVLDR is subtracted from positive and negative transient
variations ΔvTR+ and ΔvTR–. Transient accuracy therefore summarizes to

⎧ ⎡⎛ Δi LOAD ⎞ ⎛ 0 . 37 ⎞ ⎤
⎪ + ⎢⎜ ⎟⎠ ⎜⎝ + C OUT R ESR⎟ − Δ i LOAD R
⎝ + ⎠ LDR ⎥
⎪ ⎣ OUT C B
C ′ BW CL
EFF
⎦
Δ v TR ≈ ⎨ ⎡ ⎤
⎛ Δ i LOAD ⎞ ⎛ 0 . 37 ⎛ Δ ⎞ ⎞
⎪− ⎢⎜ i
+ C PAR
⎜⎝ g I ⎟⎠ + C OUT R ESR⎟⎠ − Δi LOAD R LDR ⎥
LOAD
⎟
⎪⎩ ⎢⎣⎝ C OUT + CB′ ⎠ ⎜⎝ BW CL mp BUF ⎥⎦
EFF

(1.20)

which is often simplified to

Δ VTR(max) ≈ Max (Δ VTR + , Δ VTR − )

⎛ Δ iLOAD ⎞ ⎛ 0 . 37 ⎛ Δi ⎞ ⎞
≈⎜ ⎟ ⎜ + CPAR ⎜ LOAD ⎟ + COUT RESR⎟
⎝ COUT + CB′ ⎠ ⎝ BWCL ⎝ g mpiBUF ⎠ ⎠
− Δi R LDR EFF (1.21)
LOAD
32 Chapter One

Macro3 - Typical LDO Transient Response

Simulation results-stimulus = Full range load-current step
1.56 60E – 3
50E – 3
1.54 Vout

Load-current [A]
40E – 3
1.52
Vout [V]

30E – 3
Mpo - w/l = 50k/2
1.50 20E – 3
Co = 4.7 μF
Cb = 1 μF 10E – 3
1.48 ESR = 1 Ω Load-current
00E + 0
1.46 –10E – 3
0E + 0 1E – 4 2E – 4 3E – 4 4E – 4 5E – 4 6E – 4 7E – 4 8E – 4
Time [s]

FIGURE 1.13 Simulated transient-response performance of an LDO under load-

dump conditions.

where the slew-rate-limited buffer response is worse. Figure 1.13 shows

the simulation results of a 1.53-V LDO under positive and negative
50 mA load dumps and in the presence of a 4.7 μF electrolytic capacitor
with 1 Ω of ESR in combination with an equivalent bypass capacitance
of 1 μF at the output. The LDO is comprised of an ideal voltage refer-
ence and an amplifier macromodel driving a 50 mm/2 μm PMOS
power transistor (Mpo). The results show the output suffers an LDR
voltage drop of 20 mV (ΔvLDR) and a worst-case transient voltage drop
of 55 mV (ΔvTR+), translating to a transient accuracy of 2.3% (or 35
mV/1.53 V) and load-regulation accuracy of 1.3% (or 20 mV/1.53 V).
As the example shows, transient accuracy is a significant portion
of the overall performance of the regulator, which is why a 3–8% mar-
gin is often allocated to this phenomenon. Using high-frequency
capacitors, which have low ESRs and cost more money, considerably
reduces this variation. Increasing the response time of the regulator
has similar benefits, but at the expense of more quiescent current.
Increasing the rise and fall times of the load dumps, in other words,
relaxing them to the point of exceeding the response time of the loop
practically negates all adverse transient effects, and this is how many
data books specify it, when rise and fall times are on the order of
microseconds. However, in state-of-the-art applications, the load is
often synchronized to digital-signal-processing (DSP) and micropro-
cessor (μP) clocks with frequencies ranging from several megahertz
to gigahertz, subjecting the regulator to substantially quick load
dumps (in the nanosecond region), which is where transient accuracy
is worse. It is therefore important to determine and design for a prac-
tical and realistic load; fully understanding the load allows the
designer to better trade accuracy performance for silicon real estate
and power efficiency.
 System Considerations 33
Example 1.1 Determine the load-regulation and transient accuracy of a 100 mA
1.5 V regulator with 500 kHz bandwidth and 300 mΩ equivalent load-regulation
resistance when subjected to 0–100 mA load dumps. Assume the output filter is
comprised of a 10 μF capacitor with an ESR of 0.2 Ω and an equivalent bypass
capacitance of 1 μF. The parasitic input capacitance of the power pass device is
roughly 100 pF and its transconductance 300 mA/V, and it is driven by a class-A
buffer with a constant pull-down current of 5 μA.

ΔVLDR ≈ ΔI LOAD RLDR EFF ≈ 100 mA ⋅ 300 mΩ ≈ 30 mV

ΔVLDR 30 mV
∴ LDR Accuracy = ≈ ≈ 2.0%
VOUT 1.5 V

⎛ ΔiLOAD ⎞ ⎛ 0 . 37 ⎛ ΔiLOAD ⎞ ⎞
ΔVTR ≈ ⎜ ⎟ ⎜ BW + CPAR ⎜ g I ⎟ + COUT RESR⎟ − ΔVLDR
⎝ OUT
C + C ′
B⎠ ⎝ CL ⎝ mp BUF ⎠ ⎠

⎛ ⎞
100 mA ⎜ 0 . 37 ⋅ 2 π 100 mA ⎟
+ 100 pF + 10 μF ⋅ 0 . 2 Ω⎟ − 30 mV ≈ 91 mV
10 μF + 1 μF ⎜ 500 kHz mA
⎜⎝ 300 ⋅ 5 μA ⎟⎠
V

ΔvTR 91 mV
∴ Transient Accuracy = ≈ ≈ 6.1%
VO 1.5 V

Gain Error
The effects of dc and transient loads, line (supply voltage), and
temperature variations on the regulated output amount to dc and
ac accuracy. Gain error GE in the feedback loop, however, which is
worse for lower loop gains, also has a negative impact on accuracy
performance:

ACL − ACL _ I ⎛ AOL 1⎞ −1

GE ≈ =⎜ − β = (1.22)
ACL _ I ⎝ 1 + AOL β FB β FB⎟⎠ FB 1 + AOL β FB

where ACL is the closed-loop forward gain from the reference to the
output, βFB the feedback-gain factor, and ACL_I and 1/βFB the ideal
closed-loop gain (equal to one if vOUT is meant to be regulated to VREF).
Given a gain error from VREF to vOUT, the resulting systematic variation
in the output (ΔVGE) simplifies to the product of reference VREF and
gain error GE and always results in an output voltage that is below its
target (note the negative sign in the GE relationship)

ΔVGE = VREF G E (1.23)

34 Chapter One

Overall Accuracy
Ultimately, accuracy refers to the total output voltage variation, which
includes both systematic (ΔvSystematic) and random (Δv∗Random) compo-
nents. Systematic offsets are consistent, monotonic, and considering
their effects are often in the millivolt region, mostly linear. The com-
bined impact of several systematic offsets on the output is therefore
the linear sum of their individual effects. For instance, if a 1–50 mA
increase in load current pulls vOUT 20 mV below its target under a 5 V
supply and a 5–3 V decrease in supply pulls vOUT 5 mV when loaded
with 1 mA, their combined impact on vOUT is approximately a 25 mV
drop, assuming a linear relationship. Systematic offsets have a polar-
ity and will sometimes cancel one another, depending on the circuit
and its application. Random offsets, on the other hand, are neither
consistent nor monotonic, and their effects must consequently be
treated under probabilistic terms, where the combined effects of sev-
eral components is the root-square sum of its constituent factors:

N
∗
ΔvRandom ≈ ∑ Δv1*2 (1.24)
1

where N denotes the total number of random effects on the output. In

the end, the total variation of the output exhibits combined system-
atic and random components and its accuracy ultimately conforms to
similar terms:

Accuracy ≈
∑ ΔvSystematic ± Δv∗Random (1.25)
VOUT

Load, line, transient, temperature, and gain effects are all system-
atic, monotonic, and for the most part, linear, whereas threshold,
transconductance parameter, and reverse-saturation mismatch off-
sets and process-induced variations in the reference are all random
and probabilistic. The total accuracy performance of a voltage regula-
tor is consequently

⎛V ⎞
ΔVLDR + ΔVLNR + ΔvTR + ΔVTC + ΔvREF ⎜ OUT ⎟ + VREF G E
⎝ VREF ⎠
Accuracy ≈
VOUT

2 2
⎛ ∗ ⎛ VOUT ⎞⎞ ⎛ ∗ ⎛ VOUT ⎞⎞ ∗
⎜ Δv REF ⎜ V ⎟⎟ + ⎜ vOS ⎜ V ⎟⎟ + VREF GE
⎝ ⎝ REF ⎠⎠ ⎝ ⎝ REF ⎠⎠
( ) 2

± (1.26)
VOUT
 System Considerations 35

where ΔVLDR, ΔVLNR, ΔvTR, ΔvTC, and ΔvREF are systematic output voltage
variations resulting from load regulation, line regulation, transient
load dumps, temperature drift, and systematic variations in reference
vREF; VOUT/VREF the ideal closed-loop gain; and ΔvREF∗, vOS∗, and GE∗ the
random process-induced variations in vREF, error amplifier’s input-
referred offset, and gain variations, respectively. Adhering strictly to
a linear summation of all terms, systematic and random, produces
the absolute worst-case performance for all devices at all times, which
is unrealistically pessimistic. A strict probabilistic sum (i.e., root sum
of squares), on the other hand, is unrealistically optimistic because
the consistent and repeatable nature of the systematic components is
underestimated.
In practice, transient load-dump effects dominate accuracy, but
like other effects, though for different reasons, overall accuracy spec-
ifications often exclude them. The fact is these effects depend on how
fast the load can possibly rise or fall (diLOAD/dt); in other words, they
depend strongly on the application. Line- and load-regulation effects
in vREF are also excluded, but unlike their transient counterpart, their
impact on vREF, when compared to other factors, is minimal. Package-
stress effects and other process-induced random variations on vREF are
normally so severe that temperature-drift performance is often diffi-
cult to discern, which is why all systematic variations in the reference
(ΔvREF) are often altogether absorbed by ΔvREF∗. Gain error GE and
process-induced variations in GE are similarly neglected because their
impact is relatively low. The random effects of offset voltage vOS∗ and
reference voltage variation ΔvREF∗ are often combined into one random-
variation parameter (Δ[Link]∗) because they are characterized together—
measuring vOS∗ alone is not as useful and requires more work. Ultimately,
accuracy tends to simplify to

2
⎛ V ⎞
ΔVLDR + ΔVLNR + ΔVTC ± ⎜ Δv∗ [Link] OUT ⎟
⎝ V ⎠ REF
Accuracy ≈ (1.27)
VOUT

Quoted accuracies for linear regulators typically fall in the 1–3%

range, and that excludes transient performance, which can take
another 1–7%, depending on the loading profile presented by the
application at hand.

Example 1.2 Determine the total accuracy performance of the 2.4 V regulator
shown in Fig. 1.14. Assume its forward open-loop gain is 60 dB and output
voltage variations with their corresponding three-sigma variations due to
temperature, load-current, input-supply, full-range transient load-current
changes are 3 ± 30 mV, 20 ± 5 mV, 8 ± 2.5 mV, and 140 ± 5 mV, respectively.
Note the temperature coefficient of the device, which is 3 ± 30 mV divided
by the product of 2.4 V and 125°C, is not consistent across process because
36 Chapter One

FIGURE 1.14 vIN

Three-terminal 2.4-
V linear regulator.

Ref. + vOUT

–
R

R
2.4-V Reg.

random effects overwhelm systematic effects. This is typical in plastic-

packaged, temperature-compensated voltage references, which tend to suffer
from pronounced random-induced offset variations. This randomness results
because the fillers in the package used to increase its reliability have random
shapes and therefore exert random pressure across the die, resulting in random
piezoelectric effects in the reference.

VOUT 1 R+R
Ideal closed-loop gain ACL− I ≈ = = =2
VREF β FB R

2.4 V
∴ Reference VREF = = 1.2 V
2

−1 −1
And gain error GE = = = −0 . 0 0 2
1 + AOL β FB 1000
1+
2

Transient variation ΔvTR is the total output variation in response to a transient

load dump minus its load-regulation contribution ΔVLDR:

∴ ΔvTR = 140 mV – 20 mV = 120 mV

∗ 2 ∗ 2 ∗ 2
And ± 5 mV = ΔvTR + ΔVLDR = ΔvTR + (5 mV)2

ΔvTR∗ is negligible

And since the regulation performance of the entire circuit was quoted, with
vREF as part of the system, all systematic and random variations in the reference
 System Considerations 37
(ΔvREF and ΔvREF∗) are already included in load- and line-regulation effects ΔvLDR
and ΔvLNR; in other words, for all practical purposes, ΔvREF = 0 and ΔvREF∗ = 0.

∑ Δ VSystematic ± ∗2
∑ Δ VRandom
Accuracy ≈
VOUT

Δ VLDR + Δ VLNR + Δ vTR + Δ VTC + VREF GE

≈
VOUT

∗2 ∗2 ∗2
Δ VTC + Δ VLDR + Δ VLNR
±
VOUT

20 mV + 8 mV + 120 mV + 3 mV + 1 . 2 V ⋅ 2 m
≈
2.4 V

2 2 2
(30 mV ) + (5 mV ) + (2 . 5 mV )
±
2.4 V

≈ 6.4% ± 1.3% ≤ 7.7%

Or, if transient accuracy is excluded,

Accuracy ≈ 1.4% ± 1.3% ≤ 2.7%.

The regulator is consequently said to have an accuracy performance of 2.7%.

1.6.2 Power Characteristics

The basic functions of a voltage regulator are to condition power and
transfer energy from a source to an electronic load. Accuracy, as a met-
ric for regulation performance, gauges the power-conditioning capa-
bilities of a regulator whereas efficiency relays information about
energy and its ability to transfer it. Ideally, a regulator transfers only
the energy the load demands from the source to the load, but in prac-
tice, energy is always lost in the process of conditioning power, which
is why efficiency, defined as the ratio of delivered energy ELOAD to
stored energy ESOURCE, gauges what fraction of the source energy actu-
ally reaches the load. Since energy is simply power P over the span of
time t (i.e., E = ∫ P · t), assuming power remains constant throughout
time, energy efficiency and power efficiency (η) amount to the same:

ELOAD P ⋅t P I V
η≈ = LOAD = LOAD = LOAD OUT (1.28)
ESOURCE PSOURCE ⋅ t PSOURCEE I INVIN
38 Chapter One

where VIN and IIN are the steady-state input supply voltage and its
associated current. Efficiency is an extremely important parameter in
the world of portable electronics because it determines operational
life, given its source is either charge- and/or fuel-constrained, as in
the case of battery-powered devices.
In transferring energy, a regulator loses power across its power-
conducing series device and through its control loop. The power dis-
sipated by the series pass switch is the product of the voltage across
it (i.e., input-voltage difference VIN – VOUT) and its current (ILOAD). Sim-
ilarly, the power dissipated by the regulating loop is the product of
the quiescent current (IQ) the loop requires to function and the volt-
age across its rails (i.e., PQ = VIN IQ ). As a result, efficiency expands
and simplifies to

VOUT I LOAD
η=
VOUT I LOAD + (VIN − VOUT )I LOAD + VIN IQ

VOUT I LOAD V η
= ≈ OUT I (1.29)
VIN (I LOAD + IQ ) VIN

where ηI is current efficiency, which is the ratio of ILOAD to total input

current IIN (or ILOAD + IQ):

I LOAD I LOAD
ηI ≈ = (1.30)
I IN I LOAD + IQ

A system designer therefore assigns as low a supply voltage a regula-

tor can handle (i.e., low VIN) while meeting its regulation objectives.
The IC designer must design, as a result, a circuit that not only sustains
the lowest possible voltage across its power pass device (without push-
ing it into dropout to continue enjoying the benefits of regulation) but
also achieves the highest possible current efficiency (i.e., lowest IQ
during light loading conditions).
Dropout voltage is often the limiting factor in efficiency perfor-
mance. From a specification standpoint, the minimum voltage sus-
tained across the pass device when the circuit ceases to regulate is the
dropout voltage. The loop, during this condition, drives the pass
device to source maximum current to the output, but has no ac gain
to offer and therefore no regulation capabilities. However, if VDO is
low and the regulator biased slightly above its dropout region, that is,
VOUT is slightly greater than VIN – VDO, optimum efficiency perfor-
mance is achieved:

vOUT ηI (VIN − VDO )ηI ⎛ VDO ⎞

η= ≤ ≤ ⎜1 − (1.31)
vIN VIN ⎝ VIN ⎟⎠
 System Considerations 39

Since the loop is “railed out” and the power pass device is maxi-
mally driven during dropout conditions, VDO is an ohmic drop, which
means VDO and equivalent switch-on resistance RON describe the same
effect and are linked by ILOAD as

VDO = I LOAD RON (1.32)

The total switch-on resistance is comprised of all series resistors from
the regulation node (i.e., sense point) to input supply voltage VIN,
which normally amounts to the on-resistance of the intrinsic power
device (RON_I) and the series parasitic resistances associated with the
input and output bond wires (RBW) and any metallization (RMETAL)
used to link them,

RON = RBW + RON _ I + RMETAL (1.33)

Reasonable dropout voltages for portable applications are on the

order of 200–300 mV.

Example 1.3 Determine the worst- and best-case full- and zero-load efficiency
performance of a 0–100 mA 1.2 V linear regulator with an extrinsic on-resistance
of 500 mΩ and quiescent dc current of 10 μA. The regulator draws its power from
a 0.9–1.6 V NiCd battery.
Worst-case full-load (i.e., ILOAD is at its maximum value) efficiency occurs
when VIN is at its maximum:

VOUT I LOAD _ MAX 1 . 2 ⋅ 1000 m 1.2

η= = ≈ = 75 %
VIN _ MAX ( I LOAD _ MAX + IQ ) 1 . 6 ⋅ (100 m + 10 μ) 1.6

Best-case full-load efficiency occurs when ILOAD is at its maximum point and
the device is operated slightly above its dropout region:

VDO = I LOAD _ MAX RON = 100 m ⋅ 500 m = 50 mV

VOUT I LOAD _ MAX VOUT I LOAD _ MAX

∴ η= ≈
VIN (I LOAD _ MAX + IQ ) (VOUT + VDO ) ⋅ (I LOAD _ MAX + IQ )

1 . 2 ⋅ 100 m 1.2
= ≈ = 96 %
(1 . 2 + 50 m) ⋅ (100 m + 10 μ) 1 . 25

Since the output power is zero during zero-load current conditions, efficiency
is also zero, irrespective of other operating conditions:

VOUT I LOAD _ MIN 0

η= = = 0%
VIN ( I LOAD _ MIN + IQ ) VIN IQ

which is why quiescent current alone is an important parameter in portable

devices, since load current often falls to zero or low-current levels.
40 Chapter One

1.6.3 Operating Environment

Input Supply
The operating range of input voltage VIN, output voltage VOUT, output
capacitor COUT, capacitor ESR RESR, and load current ILOAD describes the
working limits of the regulator. While the application determines the
minimum acceptable range, the circuit sets the outer boundaries. For
instance, while a Li Ion normally spans the range of 2.7–4.2 V, the
breakdown voltages of the process technology used to build the cir-
cuit sets the upper boundary to, say, 6 V and the minimum headroom
requirements of the circuit, the lower limit, to maybe 2.2 V. As a result,
choosing the process in which to build the circuit is one of the first
design tasks, and its primary goal is normally for the breakdown
voltages to exceed the maximum supply-voltage limit of the applica-
tion. After that, for optimum speed and efficiency, one process may
be picked over the others because of its cost and the components it
offers. The designer is then tasked to design the circuit such that its
headroom limits are low enough to sustain the application.
If a switching converter supplies power to the linear regulator,
the system designer sets the optimal dc target value for VIN. In this
case, the specified VIN represents a combination of several factors, the
most important two of which are the headroom limits of the linear
regulator and its voltage drop (VIN – VOUT), which is important for
efficiency. The headroom limits of the load and the overall regulator
efficiency similarly set output voltage VOUT. Another difference in
converter-supplied applications is the need for start-up control. The
switching converter requires time to ramp up and the overall system
must stay in control and within safety limits (e.g., power switches
kept within their rated power limits) throughout the start-up period.
To remain in control, however, certain functions must operate prop-
erly during start-up, before the supplies reach their parametric tar-
gets, which is why low-headroom circuits (i.e., circuits that tolerate
low VIN values) are appealing in power-management applications.

Compensation
Stability is another parameter to consider and, along with transient
accuracy, sets the acceptable range for output capacitance COUT and
resistance RESR. If the dominant low-frequency pole is at the output,
COUT must exceed a certain value to guarantee stability. Similarly,
given load-dump demands, COUT must exceed a minimum target to
prevent the output from drooping below or above its specified accu-
racy limits. If the dominant low-frequency pole is inside the circuit,
on the other hand, COUT must stay below a maximum value to ensure
the frequency location of the output pole is not pulled low enough to
compromise stability conditions. Transient-response and supply-ripple
rejection requirements demand low ESR values. Stability, on the other
 System Considerations 41

hand, may benefit or suffer from the presence of an ESR, which is

why a range is often specified, not just a lower or an upper boundary
limit.

Load Current
Although the application normally sets the load-current range, the
circuit, as in the case of VIN, imposes outer limits. First, the current-
voltage-temperature power-rating limits, otherwise known as the
safe-operating area (SOA), of the series pass device set “hard” upper-
boundary limits. Additionally, a wide load range also implies the ac
operating conditions of the regulator change considerably, making
it difficult to guarantee stability. The output resistance of the series
pass device, for instance, which has a significant impact on fre-
quency response when not in dropout, is strongly dependent on
ILOAD. Twenty to thirty years ago, applications only demanded
maybe two to three decades of change in load current (e.g., 1 mA to
1 A) because wall outlets, which offer virtually boundless energy
when compared to batteries, supplied them. In today’s portable
market, however, battery-drain current, in an effort to maximize
lifetime, cannot remain relatively high indefinitely and must there-
fore conform to power-moded schemes where the load may be com-
pletely (or almost completely) shut off. In such cases, load current
may span eight to nine decades, if not more, and have a consider-
able impact on stability and consequently on load-current range.
System and IC designers must challenge and fully justify the load-
current range a system demands before unnecessarily designing for
impossible conditions.

1.7 Simulations
1.7.1 Functionality
The role of simulations in state-of-the-art designs is increasingly
important. Their general objectives are to (1) verify functionality
and (2) ascertain parametric-compliance limits. As in programming,
however, they are as good as their inputs: "garbage in, garbage out."
Designers should therefore simulate only when they think they
know what to expect so that they may properly evaluate the simula-
tion. If the results do not conform to expectations, there is either a
problem with the simulation itself or the circuit, so the first thing to
do is ensure the operating conditions, models, and so on of the sim-
ulation are correct, and if so, a reevaluation of the circuit (without
the computer) is in order. This process is iterated until the results
match expectations, at which point the designer is in a better posi-
tion to make important design choices and performance tradeoffs.
42 Chapter One

1.7.2 Parametric Limits

The second important objective of simulations is to ascertain the
parametric limits of the circuit when subjected to extreme process-
corner variations and operating conditions, oftentimes referred as
process-voltage-temperature (PVT) corners, even though extreme
load current, output capacitance, and other operating conditions are
also considered. These simulations ascertain systematic and process-
wide variations of all performance parameters by repeating each cir-
cuit test and successively changing models and operating conditions
to include all possible combinations. For instance, weak NMOS,
strong PMOS, and nominal NPN transistors, along with high resistor
and capacitor values, may constitute one model set of many similar
and distinct model combinations. Similarly, high temperature, low
input voltage, low output capacitance, high ESR, and so on also com-
prise a condition set to which the circuit will be exposed while per-
forming worst-case corner simulations.
Process engineers often guarantee parameters that perform better
than what they claim because their intent is to increase die yield (i.e.,
profits for the company), which means process-corner simulations is,
on probabilistic terms, pessimistic: an exhaustive linear combination
of six-sigma variables is unrealistic. The caveat, however, from a
designer’s perspective, is that an analog circuit has an infinite num-
ber of operating conditions (e.g., start-up conditions subject a circuit
to an infinite number of bias points—large-signal behavior—and
therefore an infinite set of ac conditions) and it is impossible to simu-
late them all, one at a time. This is why a linear sum of six-sigma
process variations, in combination with good engineering judgment,
is believed to mitigate the risk associated with analog IC design and
help justify the cost of fabrication. Fast product-development cycles
also rely on these extreme corner scenarios to increase the chances
of building a sufficiently robust prototype to meet all parametric
limits after only one fabrication cycle, achieving the coveted first-pass
success.

1.8 Summary
The purpose of a regulator is to regulate the output voltage against all
possible operating conditions, from load and supply to temperature
variations. They differ from references only in that they supply load
current, but this seemingly insignificant fact adds considerable com-
plexity and challenges to the problem. However, linear regulators,
when compared with switching regulators, are simpler, faster, and
less noisy, but they suffer from limited power efficiency, which is why
low dropout voltages are so appealing in linear regulators for porta-
ble, battery-powered applications where single-charge battery life is
crucial. Consequently, among other categories, like power level and
frequency-compensation strategy, dropout voltage is an important
 System Considerations 43

metric in linear regulators. In the end, however, irrespective of class,

all regulators must ultimately conform to the accuracy, power, and
operating conditions a given application demands, defining in the
process, among others, the load-regulation, line-regulation, tempera-
ture-drift, and ripple-rejection performance requirements of the regu-
lator. In designing for these performance objectives under all possible
conditions, simulations are extremely useful, but only when the
designer knows (or thinks he or she knows) what to expect, as simula-
tions are as misleading as their programming variables. To be able to
anticipate circuit response, the designer must therefore understand
the basics of analog circuit design, especially as it pertains to linear
regulators, which is the focus of the next few chapters.