Adders

8421 BCD code ( Natural BCD code):

Each decimal digit 0 through 9 is coded by a 4 bit binary no. called natural binary codes.
Because of the 8,4,2,1 weights attached to it. It is a weighted code & also sequential . it is useful
for mathematical operations. The advantage of this code is its case of conversion to & from
decimal. It is less efficient than the pure binary, it require more bits.
Ex: 14→1110 in binary

But as 0001 0100 in 8421 ode.

The disadvantage of the BCD code is that , arithmetic operations are more complex than
they are in pure binary . There are 6 illegal combinations 1010,1011,1100,1101,1110,1111 in
these codes, they are not part of the 8421 BCD code system . The disadvantage of 8421 code is,
the rules of binary addition 8421 no, but only to the individual 4 bit groups.

BCD Addition:

It is individually adding the corresponding digits of the decimal no,s expressed in

4 bit binary groups starting from the LSD . If there is no carry & the sum term is not an illegal
code , no correction is needed .If there is a carry out of one group to the next group or if the sum
term is an illegal code then 610(0100) is added to the sum term of that group & the resulting carry
is added to the next group.

Ex: Perform decimal additions in 8421 code

(a)25+13
In BCD 25= 0010 0101
In BCD +13 =+0001 0011

38 0011 1000
No carry , no illegal code .This is the corrected sum

DIGITAL LOGIC DESIGN Page no. 1

 Excess three(xs-3)code:

It is a non-weighted BCD code .Each binary codeword is the corresponding 8421

codeword plus 0011(3).It is a sequential code & therefore , can be used for arithmetic
operations..It is a self-complementing code.s o the subtraction by the method of compliment
addition is more direct in xs-3 code than that in 8421 code. The xs-3 code has six invalid states
0000,0010,1101,1110,1111.. It has interesting properties when used in addition & subtraction.

Excess-3 Addition:

Add the xs-3 no.s by adding the 4 bit groups in each column starting from the LSD. If
there is no carry starting from the addition of any of the 4-bit groups , subtract 0011 from the
sum term of those groups ( because when 2 decimal digits are added in xs-3 & there is no carry ,
result in xs-6). If there is a carry out, add 0011 to the sum term of those groups( because when
there is a carry, the invalid states are skipped and the result is normal binary

Binary Parallel Adder:

A binary parallel adder is a digital circuit that adds two binary numbers in parallel form
and produces the arithmetic sum of those numbers in parallel form. It consists of full adders
connected in a chain , with the output carry from each full-adder connected to the input carry of
the next full-adder in the chain.

The interconnection of four full-adder (FA) circuits to provide a 4-bit parallel adder. The
augends bits of A and addend bits of B are designated by subscript numbers from right to left,
with subscript 1 denoting the lower –order bit. The carries are connected in a chain through the
full-adders. The input carry to the adder is Cin and the output carry is C4. The S output generates
the required sum bits. When the 4-bit full-adder circuit is enclosed within an IC package, it has
four terminals for the augends bits, four terminals for the addend bits, four terminals for the sum
bits, and two terminals for the input and output carries. AN n-bit parallel adder requires n-full
adders. It can be constructed from 4-bit, 2-bit and 1-bit full adder ICs by cascading several
packages. The output carry from one package must be connected to the input carry of the one
with the next higher –order bits. The 4-bit full adder is a typical example of an MSI function.
Ripple carry adder:
In the parallel adder, the carry –out of each stage is connected to the carry-in of
the next stage. The sum and carry-out bits of any stage cannot be produced, until sometime after
the carry-in of that stage occurs. This is due to the propagation delays in the logic circuitry,

which lead to a time delay in the addition process. The carry propagation delay for each full-34
adder is the time between the application of the carry-in and the occurrence of the carry-out.

The 4-bit parallel adder, the sum (S1) and carry-out (C1) bits given by FA1 are not valid, until
after the propagation delay of FA1. Similarly, the sum S2 and carry-out (C2) bits given by FA2 are
not valid until after the cumulative propagation delay of two full adders (FA1 and FA2) , and so
on. At each stage ,the sum bit is not valid until after the carry bits in all the preceding stages are
valid. Carry bits must propagate or ripple through all stages before the most significant sum bit is
valid. Thus, the total sum (the parallel output) is not valid until after the cumulative delay of all
the adders.

The parallel adder in which the carry-out of each full-adder is the carry-in to the next most
significant adder is called a ripple carry adder.. The greater the number of bits that a ripple carry
adder must add, the greater the time required for it to perform a valid addition. If two numbers
are added such that no carries occur between stages, then the add time is simply the propagation
time through a single full-adder.

4- Bit ParallelSubtractor:
The subtraction of binary numbers can be carried out most conveniently by means of
complements , the subtraction A-B can be done by taking the 2‘s complement of B and adding
it to A . The 2‘s complement can be obtained by taking the 1‘s complement and adding 1 tothe
least significant pair of bits. The 1‘s complement can be implemented with inverters as
Binary-Adder Subtractor:

A 4-bit adder-subtractor, the addition and subtraction operations are combined into
one circuit with one common binary adder. This is done by including an X-OR gate with each
full-adder. The mode input M controls the operation. When M=0, the circuit is an adder, and
when M=1, the circuit becomes a subtractor. Each X-OR gate receives input M and one of the
inputs of B. When M=0, .The full-adder receives the value of B , the input carry is 0
and the circuit performs A+B. when and C1=1. The B inputs are complemented and
a 1 is through the input carry. The circuit performs the operation A plus the 2‘s complement of B.35

The Look-Ahead –Carry Adder:

In parallel-adder,the speed with which an addition can be performed is governed by

the time required for the carries to propagate or ripple through all of the stages of the adder. The
look-ahead carry adder speeds up the process by eliminating this ripple carry delay. It examines
all the input bits simultaneously and also generates the carry-in bits for all the stages
simultaneously.

The method of speeding up the addition process is based on the two additional
functions of the full-adder, called the carry generate and carry propagate functions.

Consider one full adder stage; say the nth stage of a parallel adder as shown in fig.
we know that is made by two half adders and that the half adder contains an X-OR gate to
produce the sum and an AND gate to produce the carry. If both the bits An and Bn are 1s, a carry
has to be generated in this stage regardless of whether the input carry Cin is a 0 or a 1. This is
called generated carry, expressed as Gn= An.Bn which has to appear at the output through the OR
gate as shown in fig.
 There is another possibility of producing a carry out. X-OR gate inside the half-adder

at the input produces an intermediary sum bit- call it Pn –which is expressed as .

Next Pn and Cn are added using the X-OR gate inside the second half adder to produce the final

sum bit and and output carryC0= Pn.Cn=( )Cn which

becomes carry for the (n+1) thstage.

Consider the case of both Pn and Cn being 1. The input carry Cn has to be propagated
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to the output only if Pn is 1. If Pn is 0, even if Cn is 1, the and gate in the second half-adder will
inhibit Cn . the carry out of the nth stage is 1 when either Gn=1 or Pn.Cn =1 or both Gn and Pn.Cn
are equal to 1.

For the final sum and carry outputs of the nth stage, we get the following Boolean
expressions.

Observe the recursive nature of the expression for the output carry
at the nth stage which becomes the input carry for the (n+1)st stage .it is possible to express the
output carry of a higher significant stage is the carry-out of the previous stage.

Based on these , the expression for the carry-outs of various full adders are as follows,

Observe that the final output carry is expressed as a function of

the input variables in SOP form. Which is two level AND-OR or equivalent NAND-NAND
form. Observe that the full look-ahead scheme requires the use of OR gate with (n+1) inputs and
AND gates with number of inputs varying from 2 to (n+1).
2’s complement Addition and Subtraction using Parallel Adders:

Most modern computers use the 2‘s complement system to represent negative numbers
and to perform subtraction operations of signed numbers can be performed using only the
addition operation ,if we use the 2‘s complement form to represent negative numbers.

The circuit shown can perform both addition and subtraction in the 2‘s complement. This
adder/subtractor circuit is controlled by the control signal ADD/SUB‘. When the ADD/SUB‘
level is HIGH, the circuit performs the addition of the numbers stored in registers A and B.
When the ADD/Sub‘ level is LOW, the circuit subtract the number in register B from the number
in register A. The operation is:

When ADD/SUB‘ is a 1:

1. AND gates 1,3,5 and 7 are enabled , allowing B0,B1,B2and B3 to pass to the OR gates
9,10,11,12 . AND gates 2,4,6 and 8 are disabled , blocking B0‘,B1‘,B2‘, and B3‘ from
reaching the OR gates 9,10,11 and 12.

2. The two levels B0 to B3 pass through the OR gates to the 4-bit parallel adder, to be added
to the bits A0 to A3. The sum appears at the output S0 to S3

3. Add/SUB‘ =1 causes no carry into theadder.

When ADD/SUB‘ is a 0:

1. AND gates 1,3,5 and 7 are disabled , allowing B0,B1,B2and B3 from reaching the OR gates
9,10,11,12 . AND gates 2,4,6 and 8 are enabled , blocking B0‘,B1‘,B2‘, and B3‘ from
reaching the OR gates.
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 2. The two levels B0‘ to B3‘ pass through the OR gates to the 4-bit parallel adder, to be
added to the bits A0 to A3.The C0 is now 1.thus the number in register B is converted to
its 2‘s complement form.

3. The difference appears at the output S0 toS3.

Adders/Subtractors used for adding and subtracting signed binary numbers. In computers , the
output is transferred into the register A (accumulator) so that the result of the addition or
subtraction always end up stored in the register A This is accomplished by applying a transfer
pulse to the CLK inputs of register A.
 BCD Adder:

The BCD addition process:

1. Add the 4-bit BCD code groups for each decimal digit position using ordinary binary
addition.

2. For those positions where the sum is 9 or less, the sum is in proper BCD form and no
correction is needed.

3. When the sum of two digits is greater than 9, a correction of 0110 should be added
to that sum, to produce the proper BCD result. This will produce a carry to be added
to the next decimalposition.

A BCD adder circuit must be able to operate in accordance with the above steps. In other words,
the circuit must be able to do the following:

1. Add two 4-bit BCD code groups, using straight binary addition.
2. Determine, if the sum of this addition is greater than 1101 (decimal 9); if it is , add
0110 (decimal 6) to this sum and generate a carry to the next decimalposition.
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The first requirement is easily met by using a 4- bit binary parallel adder such as the 74LS83
IC .For example , if the two BCD code groups A3A2A1A0and B3B2B1B0 are applied to a 4-bit
parallel adder, the adder will output S4S3S2S1S0 , where S4 is actually C4 , the carry –out of the
MSB bits.

The sum outputs S4S3S2S1S0 can range anywhere from 00000 to 100109when both the
BCD code groups are 1001=9). The circuitry for a BCD adder must include the logic needed to
detect whenever the sum is greater than 01001, so that the correction can be added in. Those
cases , where the sum is greater than 1001 are listed as:

Let us define a logic output X that will go HIGH only when the sum is greater than 01001
(i.e, for the cases in table). If examine these cases ,see that X will be HIGH for either of the
following conditions:

1. Whenever S4 =1(sum greater than15)

2. Whenever S3 =1 and either S2 or S1 or both are 1 (sum 10 to 15)

 This condition can be expressedas

X=S4+S3(S2+S1)
Whenever X=1, it is necessary to add the correction factor 0110 to the sum bits, and to
generate a carry. The circuit consists of three basic parts. The two BCD code groups A3A2A1A0
and B3B2B1B0 are added together in the upper 4-bit adder, to produce the sum S4S3S2S1S0. The
logic gates shown implement the expression for X. The lower 4-bit adder will add the correction
0110 to the sum bits, only when X=1, producing the final BCD sum output represented by
∑3∑2∑1∑0. The X is also the carry-out that is produced when the sum is greater than 01001.
When X=0, there is no carry and no addition of 0110. In such cases, ∑3∑2∑1∑0= S3S2S1S0.

Two or more BCD adders can be connected in cascade when two or more digit decimal
numbers are to be added. The carry-out of the first BCD adder is connected as the carry-in of the
second BCD adder, the carry-out of the second BCD adder is connected as the carry-in of the41
third BCD adder and so on.

Implementation of xs-3 adder using 4-bit binary adders is shown. The augend (A3
A2A1A0) and addend (B3B2B1B0) in xs-3 are added using the 4-bit parallel adder. If the carry is a
1, then 0011(3) is added to the sum bits S3S2S1S0 of the upper adder in the lower 4-bit parallel
Code converters:

The availability of a large variety of codes for the same discrete elements of
information results in the use of different codes by different digital systems. It is sometimes
necessary to use the output of one system as the input to another. A conversion circuit must be
inserted between the two systems if each uses different codes for the same information. Thus a
code converter is a logic circuit whose inputs are bit patterns representing numbers (or
character) in one cod and whose outputs are the corresponding representation in a different
code. Code converters are usually multiple output circuits.
To convert from binary code A to binary code B, the input lines must supply the bit
combination of elements as specified by code A and the output lines must generate the
corresponding bit combination of code B. A combinational circuit performs this transformation
by means of logic gates.

Design of a 4-bit BCD to XS-3 code converter:

Magnitude Comparator
1. Magnitude
Comparator:

2- bit Magnitude Comparator:

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