ELEMENTS OF COMPUTING-1
MINI PROJECT-BUILDING A SIMPLE
MULTIPLEXER AND DEMULTIPLEXER WITH NAND GATES
NAME: RANJANA.L
BRANCH: AI&DS
SUBJECT CODE :23AID102
ROLLNO :24034
MULTIPLEXER AND DE-MULTIPLEXER USING NAND GATES
AIM:
To construct
i) 4 to 1 Multiplexer using NAND gates
ii) 1 to 4 De-Multiplexer using NAND Gates.
DESCRIPTION:
Multiplexer:
A multiplexer (or MUX) is a device that selects one of several analog or digital
input
signals and forwards the selected input into a single line. It is a Combinational logic
circuit (i.e.
its output depends upon only the present value of inputs) that has multiple inputs and
a single
line output. The select lines determine which input is connected to the output.
Multiplexers are
mainly used to increase the amount of data that can be sent over the network within a
certain
amount of time and bandwidth. It is also called a data selector, many to one circuit,
universal
logic circuit or parallel to serial circuit.
Multiplexers are classified into four types:
a) 2 to 1 multiplexer (2 input, 1 output, 1 select line)
b) 4 to 1 multiplexer (4 input, 1 output, 2 select lines)
c) 8 to 1 multiplexer (8 input, 1 output, 3 select lines)
d) 16 to 1 multiplexer (16 input, 1 output, 4 select lines)
If ‘m’ is the number of Data input and ‘n’ is the number of select (control) input, then
.
4 to 1 MUX:
4x1 Multiplexer has four data inputs I0, I1, I2 & I3, two selection lines S0 & S1 and
one output Y. One of these 4 inputs will be connected to the output (Y) based on the
combination
of inputs present at the two selection lines S0 & S1.
De-Multiplexer:
De-multiplexers perform the opposite function of multiplexers. They transfer
information
from a single source over a larger number of channels under the control of selection
signals. The
general de-multiplexer circuit has 1 input signal, n control/select signals and 2n output
signals.
De-multiplexer circuit can also be realized using a decoder circuit with enable.
De-multiplexer can be visualized as reverse multi-position switch. The select lines
permit
input data from single line to be switched to any one of the many output lines. There
are four
basic types of de-multiplexers: 1 to 2 de-multiplexer, 1 to 4 de-multiplexer, 1 to 8 de-
multiplexer and 1 to 16 multiplexer
1 to 4 DEMUX:
1x4 De-multiplexer has one data input I, two selection lines S0 & S1 and four
outputs Y0, Y1, Y2 & Y3. Based on the combination of inputs present at the two
selection lines S1 & S0, the input will be connected to one of the four output terminals
PROCEDURE:
1) Test all the components using a digital IC tester
2) Verify the pin out of IC and ensure that the ICs have been perfectly plugged into
the
breadboard or sockets before feeding the inputs
3) Write the identification number of ICs and input, output pin numbers of ICs in your
logic diagram.
4) Connect VCC = 5V & GND to the respective pin numbers of each ICs.
5) Complete the connection as per the logic diagram
6) Apply inputs to the logic gates from switches block of the trainer kit.
7) Connect output of the logic gates to the LED indicators of the trainer kit.
8) Switch on VCC and apply various combinations of select inputs S1 & S0 according to
the Truth table and verify the results for 4x1 MUX.
9) After completing the 4x1 MUX circuit disconnect the components and repeat steps
1 to 8 for 1x4 DEMUX.
CODE :
4 to 1 MUX:
module MUX_4x1 (
input wire [3:0] A, // 4 input lines
input wire [1:0] S, // 2 selection lines
output wire Y // 1 output line
);
wire S0_inv, S1_inv;
wire [3:0] Y_temp;
// Inverting the selection lines
nand(S0_inv, S[0], S[0]);
nand(S1_inv, S[1], S[1]);
// Generating intermediate outputs based on selection lines and inputs
nand(Y_temp[0], A[0], S0_inv, S1_inv); // When S = 00
nand(Y_temp[1], A[1], S[0], S1_inv); // When S = 01
nand(Y_temp[2], A[2], S0_inv, S[1]); // When S = 10
nand(Y_temp[3], A[3], S[0], S[1]); // When S = 11
// Final NAND gate to produce the output
nand(Y, Y_temp[0], Y_temp[1], Y_temp[2], Y_temp[3]);
Endmodule
1 to 4 DEMUX:
module DEMUX_1x4 (
input wire D, // 1 input line
input wire [1:0] S, // 2 selection lines
output wire [3:0] Y // 4 output lines
);
wire S0_inv, S1_inv;
// Inverting the selection lines
nand(S0_inv, S[0], S[0]);
nand(S1_inv, S[1], S[1]);
// Generating outputs based on the selection lines and input D
nand(Y[0], D, S0_inv, S1_inv); // When S = 00
nand(Y[1], D, S[0], S1_inv); // When S = 01
nand(Y[2], D, S0_inv, S[1]); // When S = 10
nand(Y[3], D, S[0], S[1]); // When S = 11
Endmodule
DIAGRAM :
4 to 1 MUX:
Logic Symbol
Function Table
Logical Expression:
4 to 1 MUX using NAND Gates:
Circuit:
RESULT:
Designed, setup and verified
i) The operation of a 4 to 1 MUX using NAND gates.
ii) The operation of a 1 to 4 DE-MUX using NAND gates.
