International Journal of Scientific & Innovative Research Studies ISSN : 2347-7660 (Print) | ISSN : 2454-1818 (Online)

IMPLEMENTATION OF WIENER FILTER ON FPGA USING XILINX SYSTEM

GENERATOR FOR SPEECH ENHANCEMENT
Dr Neetu Agrawal,
Associate Professor
AIACT&R, Delhi

ABSTRACT

Implementation of Weiner Filter for Speech Enhancement on FPGA is presented in this paper. We use Xilinx
System Generator as a software tool for design and implementation of Weiner Filter. Then, design is
implemented and analyzed using the same tool. Xilinx Spartan 3E is used for implementation due to its low
cost, and low power consumption. Time-domain analysis and spectrogram of original speech and
enhanced speech are presented for comparison. FPGA resource analysis, and power analysis are also
presented.

INTRODUCTION Programming FPGA using HDL languages

such as VHDL and Verilog is a daunting task.
Sometimes, it takes weeks or months to write a
The aim of speech enhancement is to improve the
synthesizable code. To overcome such difficulties,
quality of speech which includes clarity, intelligence,
FPGA manufacturers have developed high-level tools
and pleasantness. Produced speech signal can be
and languages, so that signal processing applications
used for human hearing, or machine recognition.
can be easily implemented on FPGA. One such tool is
The popular methods for enhancing speech are the
Xilinx System Generator. Xilinx System Generator
removal of background noise, echo suppression and
(XSG) is a state of the art tool which offers high
the process of artificially bringing certain frequencies
performance and requires very small learning and
into the speech signal. Noise reduction is the most
development time. XSG offers block libraries that
important field of speech enhancement.
plugs into Simulink tool (containing bit-true and
Digital Signal Processors or ASICs cycle-accurate models of their FPGA’s particular
(Application Specific Integrated Circuits) are used for math, logic, and DSP functions). No knowledge of
implementing digital filters on hardware [7,8]. HDL languages is required to use this tool. Research
However recent advances in technology have led to papers have been proposed, in which many existing
implementation of digital filter algorithms on digital filter algorithms are implemented on FPGA
FPGA.Experiments have been performed which hardware using XSG [14, 15].
indicates FPGAs can outperform Digital Signal
Spectral subtraction is a popular approach
Processor and ASICs [9, 13]. FPGA has been
for speech enhancement. Implementation of
implemented in areas such as Digital Image
spectral subtraction on FPGA is presented in [1]. But
Processing [10] and Digital Signal Processing [11, 12].

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International Journal of Scientific & Innovative Research Studies ISSN : 2347-7660 (Print) | ISSN : 2454-1818 (Online)

spectral subtraction suffers from the following condition that the signals and are
problems [17]: uncorrelated and stationary, the frequency-domain
solution to this stochastic optimization problem is
 residual noise
given by the suppression filter.
 musicality that results from coming and
going of waves over successive frames (1)
The above mentioned problems are solved by the
use of Wiener filter. Above equation is referred as Wiener filter.

In this paper Wiener filter is implemented For non-stationary and time-varying signal with
on Xilinx Spartan 3E FPGA for the Speech stationary background noise, Wiener filter can be
Enhancement. Results are verified using co- expressed as
simulation. For comparison, time-domain analysis
(2)
and spectrogram of enhanced speech are presented
along with original speech. FPGA resource Where is an estimate of the time-varying
estimation and power analysis are also presented. power spectrum of , , on each frame,
This paper is organized as follows: In section and is an estimate of the power spectrum of a
II, brief introduction to Speech Enhancement using stationary background noise.
Wiener Filter is presented. In section III and section Smoothing
IV, FPGA Hardware tools, and Design Tools are
described, respectively. Hardware Implementation An approach to reduce annoying fluctuations by
of Wiener Filter is presented in Section V. slowing down the rapid frame to frame movement
Experimental Results are presented in Section VI. of the object power spectrum is by application of
The conclusions are drawn in Section VII. temporal smoothing. The estimated smooth power
spectrum is given by the equation,
SPEECH ENHANCEMENT USING
WIENER FILTER (5)

Here, is the smoothing constant which controls

Wiener Filter [2] how fast we adapt to non-stationary signal
To recover speech signal corrupted by additive spectrum. If value of is low then time resolution is
noise , from a sequence ,a improved, but noise in estimated power spectrum
linear filter is to be used such that the and thus musicality is high. When large value of is
sequence minimizes the used, estimated power spectrum improves in
expected value of . Under the regions of stationarity, but smears rapid events.

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International Journal of Scientific & Innovative Research Studies ISSN : 2347-7660 (Print) | ISSN : 2454-1818 (Online)

Fig.1. Traditional Wiener Filter with Smoothing of the Object Spectrum Estimate.

SOFTWARE TOOLS hardware implementation Xilinx Spartan 3E starter

kit development board is used.
The XSG is the primary tool used for development of
the design.System Generator is part of the ISE® IMPLEMENTATION
(Interactive Software Environment) Design Suite.
XSG provides Xilinx DSP Blockset such as adders, Software Perspective
multipliers, registers, filters and memories for
A block diagram of the wiener filter algorithm with
application specific design for Simulink environment
smoothing is provided in Fig. 3. Input signals consist
which can be readily compiled into a hardware
of 16-bit speech waveforms sampled at 8 kHz. For
description language (HDL) and subsequently
this specific implementation, a frame size of 16
synthesized for specific Xilinx FPGAs.These blocks
samples was used. A description of blocks in diagram
leverage the Xilinx IP core generators to deliver
is given below:
optimized results for the selected device. [3].
FFT:
The main advantage of using XSG is that,
knowledge of HDL is not required. Thus, one can For implementation of the DFT, two XSG forward
concentrate on design rather than coding. and inverse FFT block are used. These block provides
Moreover, the development time is greatly reduced. both real and imaginary data outputs. To generate
frequency domain magnitude and phase data from
HARDWARE TOOLS the FFT block output, an XSG cordic arctan block is
used.
Xilinx Spartan 3E FPGA is the tool used for hardware Noise Estimate:
implementation of final design. Xilinx Spartan 3E is a
part of Spartan 3 generation of FPGAs which are The initial noise magnitude estimation is calculated
specifically designed to meet the needs of high using an accumulator, and a XSG cmult block. Each
volume, cost-sensitive, electronic applications, such incoming frequency binary data word is added to the
as consumer products. It is embedded with 90nm previously accumulated value for that frequency. To
technology in its architecture and, can be used to obtain an average, the final sum must be divided by
address a wide range of applications like embedded the number of frames used in the calculation.
processing, digital processing, etc [16]. For initial Restricting the number of frames to a power of two,

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International Journal of Scientific & Innovative Research Studies ISSN : 2347-7660 (Print) | ISSN : 2454-1818 (Online)

greatly simplifies the division operation. Therefore, seem to work fine in Simulink environment, but can
this implementation uses the 64 frames of data to show errors while generation of bit code for
calculate the noise magnitude spectrum estimation. hardware. Two of the most common errors are; used
resources exceed available resources, and timing
Wiener Filter:
errors. Thus, some modifications are to be made to
Next, power spectrum is determined for noise and design to make it suitable for hardware
signal by squaring both using two multiplier blocks. implementation.
Wiener filter is implemented using an adder block,
In case of resources exceed error,
and a cordic divide block. The output of cordic divide
properties of blocks are adjusted so that each block
block is multiplied by DFT of noisy signal to obtain
uses minimal resources. For example, number of
output speech DFT. Final output speech DFT is fed
stages in cordic blocks isreduced, use of 3-multiplier
back, squared to estimated power, then multiplied
structure in IFFT block for resource optimization
by smoothing factor  and added to original speech
instead of CLB logic, and properties some multiplier
spectrum multiplied by (1-) to determine transfer
blocks are set for area optimization instead of
function. Here =0.85 is used.
speed.To resolve timing errors, latency of XSG blocks
IFFT: are adjusted.

Before a time-domain frame can be generated, the Testing using Co-Simulation

new magnitude and previously retained phase
Noise and speech signal are added in Simulink
frames must be combined and converted to real and
environment and then sent to Xilinx Spartan 3E
imaginary cartesian coordinates required for input to
starter kit. Noise signal used is Gaussian with zero
the IFFT process (the XSG inverse FFT block
mean and (0.05)^2 variance. After processing,
discussed earlier). This is performed with an XSG
enhanced speech is sent back to Simulink
cordic sin-cos block and two multipliers.
environment where it can be plotted, played, and
Hardware Perspective further analyzed. Speech signal used is in wav
format, and enhanced speech signal sent by FPGA is
After successful implementation of design in
converted to same wav format.
Simulink, next step is to implement the same on
hardware i.e. Xilinx Spartan 3E FPGA. A design may

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International Journal of Scientific & Innovative Research Studies ISSN : 2347-7660 (Print) | ISSN : 2454-1818 (Online)

Fig.2. Block Diagram of hardware implementation of Wiener Filter with Smoothing

RESULTS AND DISCUSSION Fig. 4 and Fig. 5 shows the frequency spectrum and
spectrogram analysis, respectively. From frequency-
domain analysis it can be seen that higher
Speech used to obtain results is “A quick brown fox
frequencies are suppressed by both Wiener filter
jumps over a lazy dog”. Proposed design is compared
(Fig. 4(c)) and spectral subtraction (Fig. 4(d)), but
with spectral subtraction method using time-domain
results obtained from Wiener filter are better.
analysis and frequency-domain analysis. Resource
usage and power analysis of the design are By the use of pre-emphasis and de-
presented too. emphasis filters better results can be obtained.

Time Domain Analysis Resource Estimation

Fig. 3 shows the time domain analysis of proposed From Table 1 it can be seen that design uses about
approach and spectral subtraction. Comparison of 66% of FPGA resources. Design was optimized to use
clean speech (Fig. 3(b)) with Wiener filter (Fig. 3(c)) minimal resources.
and spectral subtraction (Fig. 3(d)) enhanced speech,
Power Analysis
shows that, Wiener filter performed better than
spectral subtraction approach. Detailed power analysis was obtained by power
analysis tool available in Xilinx ISE 13.1. Results are
Increasing number of stages in cordic blocks
presented in Table 2. It can be seen that design uses
gives even better results, but need more resources.
just 0.14 W power.
Thus, a FPGA chip with higher number of resources
will be needed. Time Delay
Time delay was calculated by sending a pulse at 0
Frequency Domain Analysis sec to the input, and then calculating the time at
which output appears. Time delay was calculated to
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be 25 ms. Thus, proposed design can be used in real- time.

Fig.3. Time-domain analysis (a) Noisy speech (b) Clean speech (c) Wiener filter output (d) Spectral subtraction
output

(a) (b)

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International Journal of Scientific & Innovative Research Studies ISSN : 2347-7660 (Print) | ISSN : 2454-1818 (Online)

(c) (d)

Fig.4. Frequency spectrum of (a) Noisy speech (b) Clean speech (c) Wiener filter output (d) Spectral subtraction
output

(a) (b)

(c) (d)

Fig.4. Spectrogram of (a) Noisy speech (b) Clean speech (c) Wiener filter output (d) Spectral subtraction output

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Table 1

Resource Estimation

Logic Utilization Used Available Utilization

Number of Slice Filp Flops 6186 9312 66%

Number of 4 input LUTs 6368 9312 68%

Number of occupied Slices 3964 4656 85%

Total Number of 4 input LUTs 6721 9312 72%

Number of bonded IOBs 39 232 16%

Number of BUFGMUXs 1 24 4%

Number of MULT 18X 18SIOs 16 20 80%

Table 2
Power Analysis

On-Chip Power (W)

Clocks 0.010
Logic 0.022
Signals 0.021
MULTs 0.004
IOs 0.000
Leakage 0.082
Total 0.140

CONCLUSION REFERENCES
In this paper, Wiener Filteris implemented on Xilinx 1. Whittington, Jim and Deo, Kapeel and
Spartan 3E FPGA for speech enhancement, which is a Kleinschmidt, Tristan and Mason, Michael W.
low cost FPGA device from Xilinx. Results show that (2008) FPGA Implementation of Spectral
design uses minimal resources and minimum power Subtraction for In-Car Speech
consumption. Thus, this device can be usedwhere Enhancementand Recognition. In:
low power consumption is required. Now FPGA chips International Conference on Signal Processing
are available with in-built ADC/DAC, so design can be and Communication Systems 2008, 15-17
implemented using a single chip only. Present results December 2008, Gold Coast, Australia.
are appropriate for machine recognition purposes,
but with further improvement it can be used for 2. Thomas F. Quatieri. Discrete-Time Speech
hearing purposes too. Moreover, design is created Signal Processing Principles and Practice,
using Xilinx System Generator, thus it can be ported Pearson Education.
to a large variety of Xilinx FPGA devices including 3. Xilinx System Generator for DSP Reference
high-end FPGA devices like Vertex series. Guide. Xilinx Inc.

8 | Vol (6), No.3 March, 2018 IJSIRS

International Journal of Scientific & Innovative Research Studies ISSN : 2347-7660 (Print) | ISSN : 2454-1818 (Online)

4. System Generator for DSP Performing 12. S. Mittal, S. Gupta, S. Dasgupta. "System
Hardware-in-the-Loop With the Spartan™-3E generator: The state-ofart FPGA design tool
Starter Kit. Xilinx Inc. for dsp applications." in Third International
Innovative Conference On Embedded Systems,
5. Kiran Kintali and Yongfeng Gu.Model-Based
Mobile Communication And Computing
Design with Simulink, HDL Coder, and Xilinx
(ICEMC2), 2008.
System Generator for DSP. Mathworks Inc.
13. R. Duren, J. Stevenson, M. Thompson. "A
6. Spartan 3E FPGA User Guide. Xilinx Inc.
comparison of FPGA and DSP development
7. C.-C. Cheng, W.-H. Liu, C.-H. Yang, and J.-S. environments and performance for acoustic
Hu, “A robust speech enhancement system array processing." in 50th Midwest
for vehicular applications using H1 adaptive Symposium on Circuits and Systems MWSCAS,
filtering,” in IEEE International Conference on IEEE, pp. 1177-1180, 2007.
Systems, Man andCybernetics, vol. 3, 2006,
14. Sparsh Mittal, Saket Gupta. “FPGA
pp. 2541–2546.
Implementation of MIMO System using Xilinx
8. S. Yu, “Hybrid speech enhancement and System Generator for Efficient
speech recognition system for car telematics Hardware/Software co-design” in Software
platform for hands-free control GPS navigator Engineering : An International Journal (SEIJ),
and voice dialer for handphone,” ASEAN Vol. 3, No. 1, april 2013.
Virtual Instrument Applications Contest
15. Prasit Kumar Bandyopadhyay, Arindam
Submission, 2006.
Biswas, Pramit Kumar Bandyopadhyay,
9. D. Halupka, A. Rabi, P. Aarabi, and A. Durbadal Mandal, Rajib Kar. “FPGA Based
Sheikholeslami, “Low-power dual-microphone High Frequency Noise Elimination System
speech enhancement using field from Speech Signal using Xilinx System
programmable gate arrays,” IEEE Transactions Generator” in International Journal of
on Signal Processing, vol. 55, no. 7, pp. 3526– Scientific Research and Application, ISSN:
3535, 2007. 2334-6051, Section: F, Volume 1 - 2012, Issue
10. A. E. Nelson "Implementation of image 2, pg. 20-25.
processing algorithms on FPGA hardware." 16. Spartan-3 generation FPGA user guide. Xilinx
PhD diss., Vanderbilt University, 2000. Inc.
11. S. Choi, R. Scrofano, V. K. Prasanna, J.W. Jang. 17. J. S. Lim and A. V. Oppenheim: Enhancement
"Energy-efficient signal processing using and band width compression of Noisy speech,
FPGAs." in Proceedings of the 2003 Proc. of the IEEE, vol. 67, No..12, pp. 1586-
ACM/SIGDA eleventh international symposium 1604, Dec. (1979).
on Field programmable gate arrays, ACM, pp.
225-234, 2003.

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