5 4 3 2 1

Page Index

MCP61M-M3
01-COVER PAGE
02-BLOCK DIAGRAM
03-BLOCK DISTRIBUTION
D
04-AM3 CPU HT & OVERCLOCK D

05-AM3 CPU MEMORY

REV: 1.0 A (Support DDR3、EuP) 06-AM3 CPU CONTROL & MISC
07-AM3 CPU PWR & GND
PCB:15-R42-011011、15-R42-011010 08-DDR3 DIMM A/B CH
BOM:81-605-R42110
09-DDR3 DIMM POWER
MCP61P Real S3 10-MCP61 HT
Components :714PCS 11-MCP61 PCI-E X16
12-MCP61 PCI-E X1/RGMII/DAC
13-MCP61 PCI
14-MCP61 SATA/IDE
C
15-MCP61 AUDIO/USB/MISC C

16-MCP61 PWR/GND
17-MCP61 DECOUPLING
18-VGA
19-PCI-E X16 CONN
20-PCI1/PCI2
21-PCI-E X1 / SPI
22-Super I/O (F71862F)/FDD
23-PS2/COM/LPT
24-USB Conn.
25-LAN PHY RTL8201EL&8211CL
B
26-AUDIO VT1705/ALC662(CHIP) B

27-AUDIO VT1705/ALC662(PANEL)
28-PWR CON / FNT PNL
29-CPU VCORE (UP6217)
30-DC-DC
31-Clock & Power Distribution

Signature Date
Designer Eli 08/24/2009

Layout
A A

08/20/2009
Linda/Bing <OrgAddr1> Elitegroup Computer Systems
Check Title
MCP61M-M3
Approval
Size Document Number Rev
B COVER PAGE 1.0A
Date: Wednesday, August 26, 2009 Sheet 1 of 31
5 4 3 2 1
 5 4 3 2 1

BLOCK DIAGRAM
POWER
D D
SUPPLY VREG
CONNECTOR
128-BIT 800/1066/1333MHZ
AM3 SOCKET 941 DDRIII SDRAM CONN 0

THERM MONITOR
DDRIII SDRAM CONN 1

HT 16X16 1GHZ
PCI EXPRESS X16
PEX X16

PCI EXPRESS
PEX X1
C PCI 33MHZ C
PCI SLOT 1
NFORCE
MCP61 PCI SLOT 2

692 BGA
HDA
5.1 AUDIO 1705/662
ATA 133
PRIMARY IDE

X8 USB2
INTEGRATED SATA CONTROLLERS (X2) BACK PANEL CONN
X4 - SATA CONN
USB2 PORTS 0-1
X2/ LAN

B USB2 PORTS 2-3 B

FLOPPY CONN FRONT PANEL HDR

PS2/KBRD CONN USB2 PORTS 4-5

SIO LPC BUS 33MHZ
PARALLEL CONN USB2 PORTS 6-7
F71862
BUF SIO CLK 24MHZ USB2 PORTS 8-9

LPC HDR USB2 PORTS 10-11

SERIAL CONN
MII/RGMII MII
8MB FLASH
A RTL8201EL A

Elitegroup Computer Systems

Title
MCP61M-M3
Size Document Number Rev
B
BLOCK DIAGRAM 1.0A
Date: Wednesday, August 26, 2009 Sheet 2 of 31
5 4 3 2 1
 5 4 3 2 1

AM3 SOCKET 938

CHANNEL A0 0-63
HT_CPU_TXCLK0 MEMORY_A0_CLK[2:0] DIMM 0
D
HT_CPU_TXCLK0* MEMORY_A0_CLK[2:0]* D
HT_CPU_RXCLK0
HT_CPU_RXCLK0* MEMORY_B0_CLK[2:0]
MEMORY_B0_CLK[2:0]*
HT_CPU_TXCLK1
HT_CPU_TXCLK1* DIMM 1
HT_CPU_RXCLK1
HT_CPU_RXCLK1* CHANNEL B0 64-127
MEMORY_A1_CLK[2:0]
MEMORY_A1_CLK[2:0]*
CPUCLK_IN* MEMORY_B1_CLK[2:0]
CPUCLK_IN MEMORY_B1_CLK[2:0]*

CLKOUT_200MHZ PE0_REFCLK
C
CLKOUT_200MHZ* PE0_REFCLK* PE0 X16 C

HT_CPU_RXCLK1*
HT_CPU_RXCLK1 PE1_REFCLK
HT_CPU_TXCLK1* PE1_REFCLK* PE1 X1
HT_CPU_TXCLK1
HT_CPU_RXCLK0*
HT_CPU_RXCLK0
HT_CPU_TXCLK0*
HT_CPU_TXCLK0

14MHZ OR 24MHZ*
BUF_SIO
MCP61 SIO

LPC_CLK0

PCI_CLK0 PCI SLOT 1

B PCI_CLK1 B
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLKIN PCI SLOT 2

LPC_CLK1

HDA_BITCLK HDA FLASH LPC

CODEC HEADER

RTC_XTAL
32.0 KHZ
XTAL_IN RGMII_TXCLK LAN
PHY
A RGMII_RXCLK A
25 MHZ
XTAL_OUT Elitegroup Computer Systems
BUF_25MHZ <OrgAddr1>

Title
MCP61M-M3
Size Document Number Rev
B
CLOCK DISTRIBUTION 1.0A
Date: Wednesday, August 26, 2009 Sheet 3 of 31
5 4 3 2 1
 A B C D E

HyperTransport
Please use 1mm pad size,
CPUA place all ELT test pads
on bottom side only.
HT_CLKIN_H1 N6 AD5 HT_CLKOUT_H1
HT_CLKIN_L1 L0_CLKIN_H1 L0_CLKOUT_H1 HT_CLKOUT_L1
P6 L0_CLKIN_L1 L0_CLKOUT_L1 AD4
CPU_VDDHT HT_CLKIN_H0 HT_CLKOUT_H0
HT_CLKIN_L0
N3
N2
L0_CLKIN_H0 L0_CLKOUT_H0 AD1
AC1 HT_CLKOUT_L0
A1 A31
HT_CLKIN_H[0..1] L0_CLKIN_L0 L0_CLKOUT_L0
4 10 L0_CLKIN_H[0..1] 4
R1 51-04 HT_CTLIN_H1 V4 Y6 HT_CTLOUT_H1 STP41
HT_CLKIN_L[0..1] R2 51-04 HT_CTLIN_L1 L0_CTLIN_H1 L0_CTLOUT_H1 HT_CTLOUT_L1 STP42
10 L0_CLKIN_L[0..1] V5 L0_CTLIN_L1 L0_CTLOUT_L1 W6
HT_CTLIN_H0 U1 W2 HT_CTLOUT_H0
HT_CLKOUT_H[0..1] HT_CTLIN_L0 L0_CTLIN_H0 L0_CTLOUT_H0 HT_CTLOUT_L0
10 L0_CLKOUT_H[0..1] V1 L0_CTLIN_L0 L0_CTLOUT_L0 W3
HT_CLKOUT_L[0..1]
10 L0_CLKOUT_L[0..1]
HT_CADIN_H15 U6 Y5 HT_CADOUT_H15
HT_CTLIN_H0 HT_CADIN_L15 L0_CADIN_H15 L0_CADOUT_H15 HT_CADOUT_L15
10 L0_CTLIN_H0
HT_CADIN_H14
V6
T4
L0_CADIN_L15 L0_CADOUT_L15 Y4
AB6 HT_CADOUT_H14
AM3
HT_CTLIN_L0 HT_CADIN_L14 L0_CADIN_H14 L0_CADOUT_H14 HT_CADOUT_L14
10 L0_CTLIN_L0
HT_CADIN_H13
T5
R6
L0_CADIN_L14 L0_CADOUT_L14 AA6
AB5 HT_CADOUT_H13
Top View
HT_CTLOUT_H0 HT_CADIN_L13 L0_CADIN_H13 L0_CADOUT_H13 HT_CADOUT_L13
10 L0_CTLOUT_H0 T6 L0_CADIN_L13 L0_CADOUT_L13 AB4
HT_CADIN_H12 P4 AD6 HT_CADOUT_H12
HT_CTLOUT_L0 HT_CADIN_L12 L0_CADIN_H12 L0_CADOUT_H12 HT_CADOUT_L12
10 L0_CTLOUT_L0 P5 L0_CADIN_L12 L0_CADOUT_L12 AC6
HT_CADIN_H11 M4 AF6 HT_CADOUT_H11
HT_CADIN_H[0..15] HT_CADIN_L11 L0_CADIN_H11 L0_CADOUT_H11 HT_CADOUT_L11
10 L0_CADIN_H[0..15] M5 L0_CADIN_L11 L0_CADOUT_L11 AE6
HT_CADIN_H10 L6 AF5 HT_CADOUT_H10
HT_CADIN_L[0..15] HT_CADIN_L10 L0_CADIN_H10 L0_CADOUT_H10 HT_CADOUT_L10
10 L0_CADIN_L[0..15] M6 L0_CADIN_L10 L0_CADOUT_L10 AF4
HT_CADIN_H9 K4 AH6 HT_CADOUT_H9
HT_CADOUT_H[0..15] HT_CADIN_L9 L0_CADIN_H9 L0_CADOUT_H9 HT_CADOUT_L9
10 L0_CADOUT_H[0..15]
HT_CADIN_H8
K5
J6
L0_CADIN_L9 L0_CADOUT_L9 AG6
AH5 HT_CADOUT_H8
AL1 AL31
HT_CADOUT_L[0..15] HT_CADIN_L8 L0_CADIN_H8 L0_CADOUT_H8 HT_CADOUT_L8
10 L0_CADOUT_L[0..15] K6 L0_CADIN_L8 L0_CADOUT_L8 AH4

HT LINK
HT_CADIN_H7 U3 Y1 HT_CADOUT_H7
HT_CADIN_L7 L0_CADIN_H7 L0_CADOUT_H7 HT_CADOUT_L7
U2 L0_CADIN_L7 L0_CADOUT_L7 W1
HT_CADIN_H6 R1 AA2 HT_CADOUT_H6
HT_CADIN_L6 L0_CADIN_H6 L0_CADOUT_H6 HT_CADOUT_L6
T1 L0_CADIN_L6 L0_CADOUT_L6 AA3
V_DIMM CPU_VDDIO_SUS HT_CADIN_H5 R3 AB1 HT_CADOUT_H5
HT_CADIN_L5 L0_CADIN_H5 L0_CADOUT_H5 HT_CADOUT_L5
1.5V R2 L0_CADIN_L5 L0_CADOUT_L5 AA1
3 HT_CADIN_H4 N1 AC2 HT_CADOUT_H4 CPU-R1 3

HT_CADIN_L4 L0_CADIN_H4 L0_CADOUT_H4 HT_CADOUT_L4

P1 L0_CADIN_L4 L0_CADOUT_L4 AC3
HT_CADIN_H3 L1 AE2 HT_CADOUT_H3
HT_CADIN_L3 L0_CADIN_H3 L0_CADOUT_H3 HT_CADOUT_L3
M1 L0_CADIN_L3 L0_CADOUT_L3 AE3
HT_CADIN_H2 L3 AF1 HT_CADOUT_H2
HT_CADIN_L2 L0_CADIN_H2 L0_CADOUT_H2 HT_CADOUT_L2
L2 L0_CADIN_L2 L0_CADOUT_L2 AE1
HT_CADIN_H1 J1 AG2 HT_CADOUT_H1
HT_CADIN_L1 L0_CADIN_H1 L0_CADOUT_H1 HT_CADOUT_L1
K1 L0_CADIN_L1 L0_CADOUT_L1 AG3
VCC3 VCC3 HT_CADIN_H0 J3 AH1 HT_CADOUT_H0
HT_CADIN_L0 L0_CADIN_H0 L0_CADOUT_H0 HT_CADOUT_L0
J2 L0_CADIN_L0 L0_CADOUT_L0 AG1

ZIF-941P-S RM-940

2 2

1 1

Elitegroup Computer Systems

Title
MCP61M-M3
Size Document Number Rev
Custom
CPU HT & DEBUG 1.0A
Date: Wednesday, August 26, 2009 Sheet 4 of 31
A B C D E
 A B C D E

V_DIMM
1.5V
CPU_VDDIO_SUS
CPU Memory
8 MEM_MA_DQS_H[8..0]
MEM_MA_DQS_H[8..0] DDR3 Memory Interface A DDR3 Memory Interface B
MEM_MA_DQS_L[8..0]
8 MEM_MA_DQS_L[8..0] CPUB CPUC
MEM_MB_DQS_H[8..0] STP7 AG21 AE14 MEM_MA_DATA63 M_TP1 AJ19 AH13 MEM_MB_DATA63
4 8 MEM_MB_DQS_H[8..0] MA_CLK_H7 MA_DATA63 MEM_MA_DATA[63..0] 8 MB_CLK_H7 MB_DATA63 MEM_MB_DATA[63..0] 8 4
STP1 AG20 AG14 MEM_MA_DATA62 M_TP2 AK19 AL13 MEM_MB_DATA62
MEM_MB_DQS_L[8..0] STP2 MA_CLK_L7 MA_DATA62 MEM_MA_DATA61 M_TP3 MB_CLK_L7 MB_DATA62 MEM_MB_DATA61
8 MEM_MB_DQS_L[8..0] AE20 MA_CLK_H6 MA_DATA61 AG16 AL19 MB_CLK_H6 MB_DATA61 AL15
STP3 AE19 AD17 MEM_MA_DATA60 M_TP4 AL18 AJ15 MEM_MB_DATA60
MA_CLK_L6 MA_DATA60 MEM_MA_DATA59 MB_CLK_L6 MB_DATA60 MEM_MB_DATA59
U27 MA_CLK_H5 MA_DATA59 AD13 U31 MB_CLK_H5 MB_DATA59 AF13
U26 AE13 MEM_MA_DATA58 U30 AG13 MEM_MB_DATA58
MA_CLK_L5 MA_DATA58 MEM_MA_DATA57 MB_CLK_L5 MB_DATA58 MEM_MB_DATA57
8 MEM_MA0_CLK0_P V27 MA_CLK_H4 MA_DATA57 AG15 8 MEM_MB0_CLK0_P W29 MB_CLK_H4 MB_DATA57 AL14
W27 AE16 MEM_MA_DATA56 W28 AK15 MEM_MB_DATA56
8 MEM_MA0_CLK0_N MA_CLK_L4 MA_DATA56 8 MEM_MB0_CLK0_N MB_CLK_L4 MB_DATA56
W26 AG17 MEM_MA_DATA55 Y31 AL16 MEM_MB_DATA55
MA_CLK_H3 MA_DATA55 MEM_MA_DATA54 MB_CLK_H3 MB_DATA55 MEM_MB_DATA54
W25 MA_CLK_L3 MA_DATA54 AE18 Y30 MB_CLK_L3 MB_DATA54 AL17
U24 AD21 MEM_MA_DATA53 V31 AK21 MEM_MB_DATA53
8 MEM_MA0_CLK1_P MA_CLK_H2 MA_DATA53 8 MEM_MB0_CLK1_P MB_CLK_H2 MB_DATA53
V24 AG22 MEM_MA_DATA52 W31 AL21 MEM_MB_DATA52
8 MEM_MA0_CLK1_N MA_CLK_L2 MA_DATA52 8 MEM_MB0_CLK1_N MB_CLK_L2 MB_DATA52
G19 AE17 MEM_MA_DATA51 A18 AH15 MEM_MB_DATA51
STP8 MA_CLK_H1 MA_DATA51 MEM_MA_DATA50 M_TP5 MB_CLK_H1 MB_DATA51 MEM_MB_DATA50
H19 MA_CLK_L1 MA_DATA50 AF17 A19 MB_CLK_L1 MB_DATA50 AJ16
STP4 G20 AF21 MEM_MA_DATA49 M_TP6 C19 AH19 MEM_MB_DATA49
STP5 MA_CLK_H0 MA_DATA49 MEM_MA_DATA48 M_TP7 MB_CLK_H0 MB_DATA49 MEM_MB_DATA48
G21 MA_CLK_L0 MA_DATA48 AE21 D19 MB_CLK_L0 MB_DATA48 AL20
STP6 AF23 MEM_MA_DATA47 M_TP8 AJ22 MEM_MB_DATA47
MA_DATA47 MEM_MA_DATA46 MB_DATA47 MEM_MB_DATA46
MA_DATA46 AE23 MB_DATA46 AL22
AJ26 MEM_MA_DATA45 AL24 MEM_MB_DATA45
MA_DATA45 MEM_MA_DATA44 MB_DATA45 MEM_MB_DATA44
8 MEM_MA0_CS_L1 AC25 MA0_CS_L1 MA_DATA44 AG26 8 MEM_MB0_CS_L1 AE30 MB0_CS_L1 MB_DATA44 AK25
AA24 AE22 MEM_MA_DATA43 AC31 AJ21 MEM_MB_DATA43
8 MEM_MA0_CS_L0 MA0_CS_L0 MA_DATA43 8 MEM_MB0_CS_L0 MB0_CS_L0 MB_DATA43
AG23 MEM_MA_DATA42 AH21 MEM_MB_DATA42
MA_DATA42 MEM_MA_DATA41 MB_DATA42 MEM_MB_DATA41
8 MEM_MA0_ODT1 AE28 MA0_ODT1 MA_DATA41 AH25 8 MEM_MB0_ODT1 AF31 MB0_ODT1 MB_DATA41 AH23
AC28 AF25 MEM_MA_DATA40 AD29 AJ24 MEM_MB_DATA40
8 MEM_MA0_ODT0 MA0_ODT0 MA_DATA40 8 MEM_MB0_ODT0 MB0_ODT0 MB_DATA40
AJ28 MEM_MA_DATA39 AL27 MEM_MB_DATA39
MA_DATA39 MEM_MA_DATA38 MB_DATA39 MEM_MB_DATA38
AD27 MA1_CS_L1 MA_DATA38 AJ29 AE29 MB1_CS_L1 MB_DATA38 AK27
AA25 AF29 MEM_MA_DATA37 AB31 AH31 MEM_MB_DATA37
MA1_CS_L0 MA_DATA37 MEM_MA_DATA36 MB1_CS_L0 MB_DATA37 MEM_MB_DATA36
MA_DATA36 AE26 MB_DATA36 AG30
AE27 AJ27 MEM_MA_DATA35 AG31 AL25 MEM_MB_DATA35
MA1_ODT1 MA_DATA35 MEM_MA_DATA34 MB1_ODT1 MB_DATA35 MEM_MB_DATA34
AC27 MA1_ODT0 MA_DATA34 AH27 AD31 MB1_ODT0 MB_DATA34 AL26
AG29 MEM_MA_DATA33 AJ30 MEM_MB_DATA33
MA_DATA33 MEM_MA_DATA32 MB_DATA33 MEM_MB_DATA32
8 MEM_MA_RESET- E20 MA_RESET_L MA_DATA32 AF27 8 MEM_MB_RESET- B19 MB_RESET_L MB_DATA32 AJ31
E29 MEM_MA_DATA31 E31 MEM_MB_DATA31
MA_DATA31 MEM_MA_DATA30 MB_DATA31 MEM_MB_DATA30
8 MEM_MA_CAS- AB25 MA_CAS_L MA_DATA30 E28 8 MEM_MB_CAS- AC29 MB_CAS_L MB_DATA30 E30
AB27 D27 MEM_MA_DATA29 AC30 B27 MEM_MB_DATA29
8 MEM_MA_WE- MA_WE_L MA_DATA29 8 MEM_MB_WE- MB_WE_L MB_DATA29
AA26 C27 MEM_MA_DATA28 AB29 A27 MEM_MB_DATA28
8 MEM_MA_RAS- MA_RAS_L MA_DATA28 8 MEM_MB_RAS- MB_RAS_L MB_DATA28
G26 MEM_MA_DATA27 F29 MEM_MB_DATA27
MA_DATA27 MEM_MA_DATA26 MB_DATA27 MEM_MB_DATA26
8 MEM_MA_BANK2 N25 MA_BANK2 MA_DATA26 F27 8 MEM_MB_BANK2 N31 MB_BANK2 MB_DATA26 F31
3 Y27 C28 MEM_MA_DATA25 AA31 A29 MEM_MB_DATA25 3
8 MEM_MA_BANK1 MA_BANK1 MA_DATA25 8 MEM_MB_BANK1 MB_BANK1 MB_DATA25
AA27 E27 MEM_MA_DATA24 AA28 A28 MEM_MB_DATA24
8 MEM_MA_BANK0 MA_BANK0 MA_DATA24 8 MEM_MB_BANK0 MB_BANK0 MB_DATA24
F25 MEM_MA_DATA23 A25 MEM_MB_DATA23
MA_DATA23 MEM_MA_DATA22 MB_DATA23 MEM_MB_DATA22
8 MEM_MA_CKE1 L27 MA_CKE1 MA_DATA22 E25 8 MEM_MB_CKE1 M31 MB_CKE1 MB_DATA22 A24
M25 E23 MEM_MA_DATA21 M29 C22 MEM_MB_DATA21
8 MEM_MA_CKE0 MA_CKE0 MA_DATA21 8 MEM_MB_CKE0 MB_CKE0 MB_DATA21
D23 MEM_MA_DATA20 D21 MEM_MB_DATA20

MEM CHA
MA_DATA20 MEM_MA_DATA19 MB_DATA20 MEM_MB_DATA19

MEM CHB
MA_DATA19 E26 MB_DATA19 A26
MEM_MA_ADD15 M27 C26 MEM_MA_DATA18 MEM_MB_ADD15 N28 B25 MEM_MB_DATA18
8 MEM_MA_ADD[15..0] MA_ADD15 MA_DATA18 8 MEM_MB_ADD[15..0] MB_ADD15 MB_DATA18
MEM_MA_ADD14 N24 G23 MEM_MA_DATA17 MEM_MB_ADD14 N29 B23 MEM_MB_DATA17
MEM_MA_ADD13 MA_ADD14 MA_DATA17 MEM_MA_DATA16 MEM_MB_ADD13 MB_ADD14 MB_DATA17 MEM_MB_DATA16
AC26 MA_ADD13 MA_DATA16 F23 AE31 MB_ADD13 MB_DATA16 A22
MEM_MA_ADD12 N26 E22 MEM_MA_DATA15 MEM_MB_ADD12 N30 B21 MEM_MB_DATA15
MEM_MA_ADD11 MA_ADD12 MA_DATA15 MEM_MA_DATA14 MEM_MB_ADD11 MB_ADD12 MB_DATA15 MEM_MB_DATA14
P25 MA_ADD11 MA_DATA14 E21 P29 MB_ADD11 MB_DATA14 A20
MEM_MA_ADD10 Y25 F17 MEM_MA_DATA13 MEM_MB_ADD10 AA29 C16 MEM_MB_DATA13
MEM_MA_ADD9 MA_ADD10 MA_DATA13 MEM_MA_DATA12 MEM_MB_ADD9 MB_ADD10 MB_DATA13 MEM_MB_DATA12
N27 MA_ADD9 MA_DATA12 G17 P31 MB_ADD9 MB_DATA12 D15
MEM_MA_ADD8 R24 G22 MEM_MA_DATA11 MEM_MB_ADD8 R29 C21 MEM_MB_DATA11
MEM_MA_ADD7 MA_ADD8 MA_DATA11 MEM_MA_DATA10 MEM_MB_ADD7 MB_ADD8 MB_DATA11 MEM_MB_DATA10
P27 MA_ADD7 MA_DATA10 F21 R28 MB_ADD7 MB_DATA10 A21
MEM_MA_ADD6 R25 G18 MEM_MA_DATA9 MEM_MB_ADD6 R31 A17 MEM_MB_DATA9
MEM_MA_ADD5 MA_ADD6 MA_DATA9 MEM_MA_DATA8 MEM_MB_ADD5 MB_ADD6 MB_DATA9 MEM_MB_DATA8
R26 MA_ADD5 MA_DATA8 E17 R30 MB_ADD5 MB_DATA8 A16
MEM_MA_ADD4 R27 G16 MEM_MA_DATA7 MEM_MB_ADD4 T31 B15 MEM_MB_DATA7
MEM_MA_ADD3 MA_ADD4 MA_DATA7 MEM_MA_DATA6 MEM_MB_ADD3 MB_ADD4 MB_DATA7 MEM_MB_DATA6
T25 MA_ADD3 MA_DATA6 E15 T29 MB_ADD3 MB_DATA6 A14
MEM_MA_ADD2 U25 G13 MEM_MA_DATA5 MEM_MB_ADD2 U29 E13 MEM_MB_DATA5
MEM_MA_ADD1 MA_ADD2 MA_DATA5 MEM_MA_DATA4 MEM_MB_ADD1 MB_ADD2 MB_DATA5 MEM_MB_DATA4
T27 MA_ADD1 MA_DATA4 H13 U28 MB_ADD1 MB_DATA4 F13
MEM_MA_ADD0 W24 H17 MEM_MA_DATA3 MEM_MB_ADD0 AA30 C15 MEM_MB_DATA3
MA_ADD0 MA_DATA3 MEM_MA_DATA2 MB_ADD0 MB_DATA3 MEM_MB_DATA2
MA_DATA2 E16 MB_DATA2 A15
MEM_MA_DQS_H7 AD15 E14 MEM_MA_DATA1 AK13 A13 MEM_MB_DATA1
8 MEM_MA_DQS_H7 MA_DQS_H7 MA_DATA1 8 MEM_MB_DQS_H7 MB_DQS_H7 MB_DATA1
MEM_MA_DQS_L7 AE15 G14 MEM_MA_DATA0 AJ13 D13 MEM_MB_DATA0
8 MEM_MA_DQS_L7 MA_DQS_L7 MA_DATA0 8 MEM_MB_DQS_L7 MB_DQS_L7 MB_DATA0
MEM_MA_DQS_H6 AG18 AK17
8 MEM_MA_DQS_H6 MA_DQS_H6 8 MEM_MB_DQS_H6 MB_DQS_H6
MEM_MA_DQS_L6 AG19 J28 MEM_MA_DQS_H8 AJ17 J31
8 MEM_MA_DQS_L6 MA_DQS_L6 MA_DQS_H8 MEM_MA_DQS_H8 8 8 MEM_MB_DQS_L6 MB_DQS_L6 MB_DQS_H8 MEM_MB_DQS_H8 8
MEM_MA_DQS_H5 AG24 J27 MEM_MA_DQS_L8 AK23 J30
8 MEM_MA_DQS_H5 MA_DQS_H5 MA_DQS_L8 MEM_MA_DQS_L8 8 8 MEM_MB_DQS_H5 MB_DQS_H5 MB_DQS_L8 MEM_MB_DQS_L8 8
MEM_MA_DQS_L5 AG25 AL23
8 MEM_MA_DQS_L5 MA_DQS_L5 8 MEM_MB_DQS_L5 MB_DQS_L5
MEM_MA_DQS_H4 AG27 J25 AL28 J29
8 MEM_MA_DQS_H4 MA_DQS_H4 MA_DM8 MEM_MA_DM8 8 8 MEM_MB_DQS_H4 MB_DQS_H4 MB_DM8 MEM_MB_DM8 8
MEM_MA_DQS_L4 AG28 AL29
8 MEM_MA_DQS_L4 MA_DQS_L4 8 MEM_MB_DQS_L4 MB_DQS_L4
MEM_MA_DQS_H3 D29 K25 MEM_MA_CHECK7 D31 K29 MEM_MB_CHECK7
8 MEM_MA_DQS_H3 MA_DQS_H3 MA_CHECK7 MEM_MA_CHECK[7..0] 8 8 MEM_MB_DQS_H3 MB_DQS_H3 MB_CHECK7 MEM_MB_CHECK[7..0] 8
MEM_MA_DQS_L3 C29 J26 MEM_MA_CHECK6 C31 K31 MEM_MB_CHECK6
8 MEM_MA_DQS_L3 MA_DQS_L3 MA_CHECK6 8 MEM_MB_DQS_L3 MB_DQS_L3 MB_CHECK6
MEM_MA_DQS_H2 C25 G28 MEM_MA_CHECK5 C24 G30 MEM_MB_CHECK5
8 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MA_DQS_H2 MA_CHECK5 MEM_MA_CHECK4 8 MEM_MB_DQS_H2 MB_DQS_H2 MB_CHECK5 MEM_MB_CHECK4
8 MEM_MA_DQS_L2 D25 MA_DQS_L2 MA_CHECK4 G27 Layout: Route as 60 ohms 8 MEM_MB_DQS_L2 C23 MB_DQS_L2 MB_CHECK4 G29 Layout: Route as 60 ohms
MEM_MA_DQS_H1 E19 L24 MEM_MA_CHECK3 D17 L29 MEM_MB_CHECK3
8 MEM_MA_DQS_H1 MEM_MA_DQS_L1 F19
MA_DQS_H1 MA_CHECK3
K27 MEM_MA_CHECK2 with 5/10 W/S from CPU pins. 8 MEM_MB_DQS_H1
C17
MB_DQS_H1 MB_CHECK3
L28 MEM_MB_CHECK2 with 5/10 W/S from CPU pins.
8 MEM_MA_DQS_L1 MA_DQS_L1 MA_CHECK2 8 MEM_MB_DQS_L1 MB_DQS_L1 MB_CHECK2
2 MEM_MA_DQS_H0 F15 H29 MEM_MA_CHECK1 C14 H31 MEM_MB_CHECK1 2
8 MEM_MA_DQS_H0 MA_DQS_H0 MA_CHECK1 8 MEM_MB_DQS_H0 MB_DQS_H0 MB_CHECK1
MEM_MA_DQS_L0 G15 H27 MEM_MA_CHECK0 C13 G31 MEM_MB_CHECK0
8 MEM_MA_DQS_L0 MA_DQS_L0 MA_CHECK0 8 MEM_MB_DQS_L0 MB_DQS_L0 MB_CHECK0
MEM_MA_DM7 AF15 W30 MEM_MB_DM7 AJ14 V29
8 MEM_MA_DM[7..0] MA_DM7 MA_EVENT_L MEM_MA_EVENT_L 8 8 MEM_MB_DM[7..0] MB_DM7 MB_EVENT_L MEM_MB_EVENT_L 8
MEM_MA_DM6 AF19 MEM_MB_DM6 AH17
MA_DM6 MB_DM6
MEM_MA_DM5 AJ25 MEM_MB_DM5 AJ23
MA_DM5 MB_DM5
MEM_MA_DM4 AH29 MEM_MB_DM4 AK29
MEM_MA_DM3 MA_DM4 MEM_MB_DM3 MB_DM4
B29 1 2 CPU_VDDIO_SUS C30 1 2 CPU_VDDIO_SUS
MEM_MA_DM2 MA_DM3 M_R1 300-04 MEM_MB_DM2 MB_DM3 M_R2 300-04
E24 MA_DM2 A23 MB_DM2
MEM_MA_DM1 E18 MEM_MB_DM1 B17
MEM_MA_DM0 MA_DM1 MEM_MB_DM0 MB_DM1
H15 EVENT pins are for future AM3r2 B13 EVENT pins are for future AM3r2
MA_DM0 MB_DM0

ZIF-941P-S ZIF-941P-S

MEMORY CLOCK TRANSLATION

DIMM DDR2 Memory Signal CPU Signal
MEM CHA DIMM A0 MEM_MA0_CLK1 MA_CLK2 MEM CHB
1 3 2 4
MEM_MA0_CLK0 MA_CLK4

DIMM A1
MEM_MA1_CLK1 MA_CLK5
MEM_MA1_CLK0 MA_CLK3
1 1

DIMM B0
CPU MEM_MB0_CLK1 MB_CLK2 CPU
MEM_MB0_CLK0 MB_CLK4

DIMM B1
MEM_MB1_CLK1 MB_CLK5
TO DIMMA0 & DIMMA1 MEM_MB1_CLK0 MB_CLK3 TO DIMMB0 & DIMMB1 Elitegroup Computer Systems
Title

A0 A1 B0 B1 MCP61M-M3
Size Document Number Rev
C
AM3 CPU MEMORY 1.0A
Date: Wednesday, August 26, 2009 Sheet 5 of 31
A B C D E
 A B C D E

下版改為0603
a,20mil(width):20mil(spacing)
VCC3 VCC3 VCC25A M_FB1 b,reference to GND CPU_VDDA_RUN
FB120-08 [email protected]
+12V +12V 1 2

2.5VREF

1
Layout: Place as close as M_C1 M_C2 M_C3
VREF25 VCCNS_REF 10U-08 .22U-06-06 3300P-04
possible to CPU socket.
CPUD

2
4 4

C10 VDDA_1
M_C5 3900P-04
M_TP10 D10 VDDA_2 MISC. CPU_VDDIO_SUS
CPU_CLKP 1 2 CPU_CLKIN_SC_P A8
CPU_CLKIN_SC_N CLKIN_H CPU_CORE_TYPE_L M_R4
a,Rshunt near CPU pin<600mil B8 CLKIN_L CORE_TYPE G5 1 2 1K-04

1
1.5V b,Cseries as a pair within 25mil
V_DIMM CPU_VDDIO_SUS M_R5 CPU_PWRGD C9 D2 CPU_VID5 SSTP11
c,Cseries to CPU pin trace length<1250mil 169-1-04 LDT_STOP- PWROK VID5 CPU_VID4
1.2V D8 LDTSTOP_L VID4 D1 M_TP12
+1.2V_HT CPU_VDDHT d,12:4:6:4:12(1080 for 93ohm) M_C4 3900P-04 LDT_RST- C7 C1 CPU_SVC M_R6 1 2 1K-04

2
CPU_CLKN RESET_L SVC/VID3 CPU_SVD M_R7 1
1 2 SVD/VID2 E3 2 1K-04
CPU_PRESENT_L_15 AL3 E2 CPU_PVEN
CPU_PRESENT_L PVIEN/VID1 CPU_VID0
VID0 E1 STP33

2
CPU_CLKP
10 CPU_CLK_200_P
CPU_CLKN CPU_SIC AL6 AG9 CPU_THERMDC M_R8
10 CPU_CLK_200_N SIC THERMDC
CPU_SID AK6 AG8 CPU_THERMDA 300-04
CPU_PWRGD M_TP15 CPU_SA0 SID THERMDA CPU_THERMTRIP_L_15
10 HTCPU_PWRGD M_TP14 AK4 AK7

1
LDT_STOP- SSTP9 CPU_ALERT_ SA0 THERMTRIP_L CPU_PROCHOT_L_15
10 HTCPU_STOP- M_TP16 AL4 ALERT_L PROCHOT_L AL7
LDT_RST- M_TP17
10 HTCPU_RST- For AM3 CPU
SSTP18 AL10 AK10 CPU_TDO SSTP19
SSTP20 TDI TDO
AJ10 TRST_L
CPU_PVEN M_TP21 SSTP22 AH10
29 CPU_PVEN TCK
CPU_SVD M_TP23 M_TP24 AL9
29 CPU_SVD TMS
CPU_SVC M_TP25
29 CPU_SVC
SSTP26 A5 B6 CPU_DBRDY SSTP27
DBREQ_L DBRDY
CPU_VDDIO_SUS CPU_VDD_FB_H G2 AK11 CPU_VDDIO_FB_H M_TP28
CPU_THERMDC CPU_VDD_FB_L VDD_FB_H VDDIO_FB_H CPU_VDDIO_FB_L
22 CPU_THERMDC STP9 Layout: Keep trace to resistors G1 VDD_FB_L VDDIO_FB_L AL11 M_TP29 Layout: Keep CPU_HTREF0,1
CPU_THERMDA STP10 G4 CPU_VDDNB_FB_H
22 CPU_THERMDA less than 1" from CPU pins. VDDNB_FB_H less than 1.5" from in length.

1
3 CPU_THERMTRIP_L_15 M_STP11 STP34 CPU_VDDIO_PWRGD F3 G3 CPU_VDDNB_FB_L 3
10 CPU_THERMTRIP- M_VDDIO_PWRGD VDDNB_FB_L
CPU_PROCHOT_L_15 M_R9
10 PROCHOT_L
15-1-06 CPU_M_VREF_SUS CPU_VDDIO_SUS STP12 CPU_VTT_SUS_SENSE E12 F1 CPU_PSI- SSTP30 CPU_VDDHT
VDDR_SENSE PSI_L
0.25W M_STP13
2 CPU_M_VREF F12 M_VREF HTREF1 V8 CPU_HTREF1 1 2
M_R11 1 2 39.2-1-04 CPU_M_ZN AH11 V7 CPU_HTREF0 M_R101 2 44.2-1-04
M_ZN HTREF0
1

M_R13 1 2 39.2-1-04 CPU_M_ZP AJ11 M_TP31 M_R12 44.2-1-04

M_ZP

1
CPU_VDD_FB_H M_STP15 M_R14 M_C6 M_C7
29 CPU_CORE_FB
CPU_VDD_FB_L M_STP14 15-1-06 .1U-04 1000P-04 M_R15 1 2 511-1-04 CPU_TEST25_H_BYPASSCLK_H A10 C11 CPU_TEST29_H_FBCLKOUT_H 1 2
29 CPU_CORE_FB- TEST25_H TEST29_H
M_R17 1 2 511-1-04 CPU_TEST25_H_BYPASSCLK_L B10 D11 CPU_TEST29_L_FBCLKOUT_L M_R16 80.6-1-04
2

2
M_TP32 CPU_TEST19_PLLTEST0 TEST25_L TEST29_L
F10 TEST19
CPU_VDDNB_FB_H M_STP16 M_TP33 CPU_TEST18_PLLTEST1 E9
29 CPU_VDDNB_FB TEST18
CPU_VDDNB_FB_L M_STP17 AJ7
29 CPU_VDDNB_FB- TEST13
Layout: Place within 500 F6 AK8 CPU_TEST24_SCANCLK1 SSTP34 Layout: Route as 80 ohms diff
TEST9 TEST24 CPU_TEST23_TSTUPD
12mil(width):20mil(spacing) mils of the CPU socket. TEST23 AH8 STP18 impedance (4/5mil).Keep trace
CPU_SIC STP19 CPU_TEST17_BP3 D6 AJ9 CPU_TEST22_SCANSHIFTEN SSTP35
15 SB_CPU_SIC CPU_SID STP20 CPU_TEST16_BP2 TEST17 TEST22 CPU_TEST21_SCANEN to resistor < 1" from CPU pins.
15 SB_CPU_SID E7 TEST16 TEST21 AL8 SSTP36
STP21 CPU_TEST15_BP1 F8 AJ8 CPU_TEST20_SCANCLK2 SSTP37
STP22 CPU_TEST14_BP0 TEST15 TEST20
C5 TEST14
STP23 CPU_TEST12_SCANSHIFTENB AH9 J10 CPU_TEST28_H_PLLCHRZ_H STP24
TEST12 TEST28_H CPU_TEST28_L_PLLCHRZ_L
TEST28_L H9 STP32
STP26 CPU_TEST7_ANALOG_T E5 AK9 CPU_TEST27_SINGLECHAIN M_TP38
STP27 CPU_TEST6_DIECRACKMON TEST7 TEST27 CPU_TEST26_BURNIN_L
AJ5 TEST6 TEST26 AK5 M_TP39
STP28 CPU_TEST3_GATE0 AH7 G7 CPU_TEST10_ANALOGOUT STP29
STP30 CPU_TEST2_DRAIN0 TEST3 TEST10 CPU_TEST8_DIG_T
AJ6 TEST2 TEST8 D4 STP31

C18 RSVD1 RSVD9 L30

C20 RSVD2 RSVD10 L31
F2 RSVD3 RSVD11 AD25
2
G24 RSVD4 RSVD12 AE24 2

G25
H25
RSVD5
RSVD6
INT. MISC. RSVD13
RSVD14
AE25
AJ18
L25 RSVD7 RSVD15 AJ20
CPU_VDDIO_SUS L26 AK3
RSVD8 RSVD16
M_RN1 300-8P4R
1 2
LDT_RST- 3 4
LDT_STOP- 5 6 ZIF-941P-S
CPU_PWRGD 7 8
VCC25A for CPU PLL
+12V VCC3 VCC3 CPU_PRESENT_L_15 M_R18 1 2 10K-04
CPU_SIC M_R19 1 2 10K-04
CPU_SID M_R20 1 2 10K-04
1

M_C8
VREF25 4.7U-08
D
4

U30A
2

M_R21 1 2 0-04 3 M_Q1 M_RN2 300-8P4R

+
1 G 2N7002-S CPU_TEST27_SINGLECHAIN 1 2
2 CPU_PROCHOT_L_15 3 4
-
S

CPU_THERMTRIP_L_15 5 6
OP324-S CPU_TEST26_BURNIN_L 7 8
11

VCC25A

M_R22 1 2 0-04
1 1
1

CPU_SA0 M_R24 1 2 0-04

1

M_R23 EC48
10K-04-O 22U-25DE CPU_PWRGD M_C9 1 2 180P-04-O
2

LDT_STOP- M_C10 1 2 180P-04-O

Elitegroup Computer Systems
LDT_RST- M_C11 1 2 180P-04-O
Title
MCP61M-M3
Size Document Number Rev
Custom
AM3 CPU CONTROL&MISC 1.0A
Date: Wednesday, August 26, 2009 Sheet 6 of 31
A B C D E
 A B C D E

CPU_VDD_RUN CPU_VDD_RUN Processor Power and Ground

CPUE CPUF

B3 A3 T15 M12 CPU_VDDNB_RUN CPU_VDDHT

VDD_1 VSS_1 VDD_86 VSS_86
C2 VDD_2 VSS_2 A7 T17 VDD_87 VSS_87 M14 CPUG CPUH
C4 VDD_3 VSS_3 A9 T19 VDD_88 VSS_88 M16
D3 VDD_4 VSS_4 A11 T21 VDD_89 VSS_89 M18
D5 B4 T23 M20 A4 AA11 M_ELT1 AJ1 H1 VLDT_HT3_RUN_B
4
VDD_5 VSS_5 VDD_90 VSS_90 VDDNB_1 VSS_171 VLDT_A_1 VLDT_B_1 4

E4 VDD_6 VSS_6 B9 U8 VDD_91 VSS_91 M22 A6 VDDNB_2 VSS_172 AA13 AJ2 VLDT_A_2 VLDT_B_2 H2

1
M_C12
E6 VDD_7 VSS_7 B11 U10 VDD_92 VSS_92 N4 B5 VDDNB_3 VSS_173 AA15 AJ3 VLDT_A_3 VLDT: [email protected] VLDT_B_3 H5
10U-08
F5 VDD_8 VSS_8 B14 U12 VDD_93 VSS_93 N5 B7 VDDNB_4 VSS_174 AA17 AJ4 VLDT_A_4 VLDT_B_4 H6
VCORE CPU_VDD_RUN F7 B16 U14 N7 C6 AA19

2
VDD_9 VSS_9 VDD_94 VSS_94 VDDNB_5 VSS_175 VDDR_HT3 CPU_VDDR
G6 VDD_10 VSS_10 B18 U16 VDD_95 VSS_95 N9 C8 VDDNB_6 VSS_176 AA21
1.5V G8 VDD_11 VSS_11 B20 U18 VDD_96 VSS_96 N11 D7 VDDNB_7 VSS_177 AA23 A12 VDDR_1 VDDR_5 AG12
V_DIMM CPU_VDDIO_SUS H7 VDD_12 VSS_12 B22 U20 VDD_97 VSS_97 N13 D9 VDDNB_8 VSS_178 AB2 B12 VDDR_2 VDDR_6 AH12
H11 VDD_13 VSS_13 B24 U22 VDD_98 VSS_98 N15 E8 VDDNB_9 VSS_179 AB3 C12 VDDR_3 VDDR: [email protected] VDDR_7 AJ12
H23 VDD_14 VSS_14 B26 V9 VDD_99 VSS_99 N17 E10 VDDNB_10 VSS_180 AB8 D12 VDDR_4 VDDR_8 AK12 Layout: Place as close as
CPU_VDDNB CPU_VDDNB_RUN J8 B28 V11 N19 F9 AB10 AL12
J12
VDD_15 VSS_15
B30 V13
VDD_100 VSS_100
N21 F11
VDDNB_11 VSS_181
AB12 CPU_VDDIO_SUS VDDR_9 possible to CPU socket.
VDD_16 VSS_16 VDD_101 VSS_101 VDDNB_12 VSS_182
J14 VDD_17 VSS_17 C3 V15 VDD_102 VSS_102 N23 G10 VDDNB_13 VSS_183 AB14 M24 VDDIO_1
+1.2V_HT CPU_VDDR J16 VDD_18 VSS_18 D14 V17 VDD_103 VSS_103 P2 G12 VDDNB_14 VSS_184 AB16 M26 VDDIO_2 VSS_215 AF18
J18 VDD_19 VSS_19 D16 V19 VDD_104 VSS_104 P3 MT1 MT1 VSS_185 AB18 M28 VDDIO_3 VSS_216 AF20
1.2V J20 VDD_20 VSS_20 D18 V21 VDD_105 VSS_105 P8 MT2 MT2 VSS_186 AB20 M30 VDDIO_4 VSS_217 AF22

POWER/GND4
+1.2V_HT CPU_VDDHT J22 VDD_21 VSS_21 D20 V23 VDD_106 VSS_106 P10 MT3 MT3 VSS_187 AB22 P24 VDDIO_5 VSS_218 AF24
J24 VDD_22 VSS_22 D22 W4 VDD_107 VSS_107 P12 MT4 MT4 VSS_188 AC7 P26 VDDIO_6 VSS_219 AF26
K7 VDD_23 VSS_23 D24 W5 VDD_108 VSS_108 P14 MT5 MT5 VSS_189 AC9 P28 VDDIO_7 VSS_220 AF28
K9 VDD_24 VSS_24 D26 W8 VDD_109 VSS_109 P16 MT6 MT6 VSS_190 AC11 P30 VDDIO_8 VSS_221 AG10

POWER/GND3
K11 VDD_25 VSS_25 D28 W10 VDD_110 VSS_110 P18 MT7 MT7 VSS_191 AC13 T24 VDDIO_9 VSS_222 AG11
K13 VDD_26 VSS_26 D30 W12 VDD_111 VSS_111 P20 MT8 MT8 VSS_192 AC15 T26 VDDIO_10 VSS_223 AH14
K15 VDD_27 VSS_27 E11 W14 VDD_112 VSS_112 P22 MT9 MT9 VSS_193 AC17 T28 VDDIO_11 VSS_224 AH16
K17 VDD_28 VSS_28 F4 W16 VDD_113 VSS_113 R7 MT10 MT10 VSS_194 AC19 T30 VDDIO_12 VSS_225 AH18
K19 VDD_29 VSS_29 F14 W18 VDD_114 VSS_114 R9 MT11 MT11 VSS_195 AC21 V25 VDDIO_13 VSS_226 AH20
K21 VDD_30 VSS_30 F16 W20 VDD_115 VSS_115 R11 MT12 MT12 VSS_196 AC23 V26 VDDIO_14 VSS_227 AH22
K23 VDD_31 VSS_31 F18 W22 VDD_116 VSS_116 R13 MT13 MT13 VSS_197 AD8 V28 VDDIO_15 VSS_228 AH24
L4 VDD_32 VSS_32 F20 Y2 VDD_117 VSS_117 R15 MT14 MT14 VSS_198 AD10 V30 VDDIO_16 VSS_229 AH26
L5 VDD_33 VSS_33 F22 Y3 VDD_118 VSS_118 R17 MT15 MT15 VSS_199 AD12 Y24 VDDIO_17 VSS_230 AH28
L8 VDD_34 VSS_34 F24 Y7 VDD_119 VSS_119 R19 MT16 MT16 VSS_200 AD14 Y26 VDDIO_18 VSS_231 AH30
L10 VDD_35 VSS_35 F26 Y9 VDD_120 VSS_120 R21 MT17 MT17 VSS_201 AD16 Y28 VDDIO_19 VSS_232 AK2
L12 VDD_36 VSS_36 F28 Y11 VDD_121 VSS_121 R23 VSS_202 AD20 Y29 VDDIO_20 VDDIO: [email protected] VSS_233 AK14
L14 VDD_37 VSS_37 F30 Y13 VDD_122 VSS_122 T8 B2 NP/RSVD VSS_203 AD22 AB24 VDDIO_21 VSS_234 AK16

POWER/GND2
L16 VDD_38 VSS_38 G9 Y15 VDD_123 VSS_123 T10 VSS_204 AD24 AB26 VDDIO_22 VSS_235 AK18

POWER/GND1
L18 VDD_39 VSS_39 G11 Y17 VDD_124 VSS_124 T12 H20 NP/VSS1 VSS_205 AE4 AB28 VDDIO_23 VSS_236 AK20
L20 VDD_40 VSS_40 H8 Y19 VDD_125 VSS_125 T14 AE7 NP/VSS2 VSS_206 AE5 AB30 VDDIO_24 VSS_237 AK22
L22 VDD_41 VSS_41 H10 Y21 VDD_126 VSS_126 T16 VSS_207 AE11 AC24 VDDIO_25 VSS_238 AK24
M2 VDD_42 VSS_42 H12 Y23 VDD_127 VSS_127 T18 MT18 MT18 VSS_208 AF2 AD26 VDDIO_26 VSS_239 AK26
3 M3 VDD_43 VSS_43 H14 AA8 VDD_128 VSS_128 T20 MT19 MT19 VSS_209 AF3 AD28 VDDIO_27 VSS_240 AK28 3

M7 VDD_44 VSS_44 H16 AA10 VDD_129 VSS_129 T22 MT20 MT20 VSS_210 AF8 AD30 VDDIO_28 VSS_241 AK30
M9 VDD_45 VSS_45 H18 AA12 VDD_130 VSS_130 U4 MT21 MT21 VSS_211 AF10 AF30 VDDIO_29 VSS_242 AL5
M11 VDD_46 VSS_46 H24 AA14 VDD_131 VSS_131 U5 MT22 MT22 VSS_212 AF12
M13 VDD_47 VSS_47 H26 AA16 VDD_132 VSS_132 U7 MT23 MT23 VSS_213 AF14

DHOLE1
DHOLE2
DHOLE3
DHOLE4
M15 H28 AA18 U9 MT24 AF16 ZIF-941P-S
VDD_48 VSS_48 VDD_133 VSS_133 MT24 VSS_214

MT27
MT28
MT29
MT30
MT31
MT32
M17 VDD_49 VSS_49 H30 AA20 VDD_134 VSS_134 U11 MT25 MT25
M19 VDD_50 VSS_50 J4 AA22 VDD_135 VSS_135 U13 MT26 MT26
M21 VDD_51 VSS_51 J5 AB7 VDD_136 VSS_136 U15
M23 J7 AB9 U17 ZIF-941P-S

MT27
MT28
MT29
MT30
MT31
MT32

DHOLE1
DHOLE2
DHOLE3
DHOLE4
VDD_52 VSS_52 VDD_137 VSS_137
N8 VDD_53 VSS_53 J9 AB11 VDD_138 VSS_138 U19
N10 VDD_54 VSS_54 J11 AB13 VDD_139 VSS_139 U21
N12 VDD_55 VSS_55 J13 AB15 VDD_140 VSS_140 U23
N14 VDD_56 VSS_56 J15 AB17 VDD_141 VSS_141 V2 Add MTx and DHOLEx to GND for new net-in method
N16 VDD_57 VSS_57 J17 AB19 VDD_142 VSS_142 V3
N18 VDD_58 VSS_58 J19 AB21 VDD_143 VSS_143 V10
N20 VDD_59 VSS_59 J21 AB23 VDD_144 VSS_144 V12
N22 VDD_60 VSS_60 J23 AC4 VDD_145 VSS_145 V14
P7 K2 AC5 V16 CPU_VDDNB_RUN CPU_VDDR
VDD_61 VSS_61 VDD_146 VSS_146
P9 VDD_62 VSS_62 K3 AC8 VDD_147 VSS_147 V18
P11 VDD_63 VSS_63 K8 AC10 VDD_148 VSS_148 V20
P13 VDD_64 VSS_64 K10 AC12 VDD_149 VSS_149 V22

1
P15 K12 AC14 W7 M_C13 M_C14 M_C15 M_C16 M_C17 M_C18 M_C19 M_C20 M_C21 M_C22
VDD_65 VSS_65 VDD_150 VSS_150 10U-X5-08-O 10U-X5-08-O 10U-08 .22U-06-O .22U-06-O .01U-04-O 10U-X5-08-O 10U-08 .22U-06-06 .01U-04-O
P17 VDD_66 VSS_66 K14 AC16 VDD_151 VSS_151 W9
P19 K16 AC18 W11

2
VDD_67 VSS_67 VDD_152 VSS_152
P21 VDD_68 VSS_68 K18 AC20 VDD_153 VSS_153 W13
P23 VDD_69 VSS_69 K20 AC22 VDD_154 VSS_154 W15
R4 VDD_70 VSS_70 K22 AD2 VDD_155 VSS_155 W17
R5 VDD_71 VSS_71 K24 AD3 VDD_156 VSS_156 W19
R8 VDD_72 VSS_72 K26 AD7 VDD_157 VSS_157 W21
R10 K28 AD9 W23 CPU_VDDHT VDDR_HT3
VDD_73 VSS_73 VDD_158 VSS_158 CPU_VDDR
R12 VDD_74 VSS_74 K30 AD11 VDD_159 VSS_159 Y8
R14 VDD_75 VSS_75 L7 AD23 VDD_160 VSS_160 Y10
R16 VDD_76 VSS_76 L9 AE10 VDD_161 VSS_161 Y12

1
R18 L11 AE12 Y14 M_C23 M_C24 M_C25 M_C26 M_C27 M_C28 M_C29
VDD_77 VSS_77 VDD_162 VSS_162 10U-08-X .22U-06-O 180P-04 180P-04 10U-X5-08-O 1U-06 10U-08
R20 VDD_78 VSS_78 L13 AF7 VDD_163 VSS_163 Y16
R22 L15 AF9 Y18

2
VDD_79 VSS_79 VDD_164 VSS_164
T2 VDD_80 VSS_80 L17 AF11 VDD_165 VSS_165 Y20
2
T3 VDD_81 VSS_81 L19 AG4 VDD_166 VSS_166 Y22 2

T7 VDD_82 VSS_82 L21 AG5 VDD_167 VSS_167 AA4

T9 VDD_83 VSS_83 L23 AG7 VDD_168 VSS_168 AA5
T11 VDD_84 VSS_84 M8 AH2 VDD_169 VSS_169 AA7
T13 VDD_85 VSS_85 M10 AH3 VDD_170 VSS_170 AA9
CPU_VDDIO_SUS CPU_VDDIO_SUS

ZIF-941P-S ZIF-941P-S

1
M_C30 M_C31 M_C32 M_C33 M_C34 M_C35
10U-08 10U-08-O 180P-04 10U-08 10U-08-O 180P-04

2
Layout: Place across each
VDDIO-GND plane split.

Bottom Side Decoupling VDDR_HT3

M_C36 .22U-06-O
FOR EMC CPU_VDDNB_RUN

1 2 CPU_VDD_RUN

1
M_C58 .22U-06-06 M_C59
CPU_VDDIO_SUS CPU_VDDNB_RUN M_C39 .22U-06-06 1 2 .1U-04
1 2

2
1

SC2 SC3 SC4 SC5 SC6 SC7 SC8 SC9 SC10 SC13 SC14 SC11 SC12
10U-08-X 10U-08-X .01U-04-X .01U-04-X .22U-06-X 180P-04-X 10U-08 .22U-06-06 .01U-04-X .01U-04-X
10U-08-X 10U-X5-08-X-O .22U-06-X-O
2

1 1

CPU_VDD_RUN
1

1
SC15 SC16 SC17 SC18 SC19 SC20 SC21 SC22 SC23 SC24 SC25 SC26 SC27 SC28 SC29 SC30 SC31 SC32 SC33 SC34 SC35 SC36 SC37
10U-08-X 10U-08-X 10U-08-X 10U-08-X-O 10U-08-X-O 10U-08-X 10U-08-X-O 10U-08-X 10U-08-X 10U-08-X 10U-08-X-O 10U-08-X 10U-08-X-O 10U-08-X-O 10U-08-X 10U-08-X-O .22U-06-X-O .22U-06-X .01U-04-X-O .01U-04-X
10U-08-X 10U-08-X 10U-X5-08-X-O
2

2
Elitegroup Computer Systems
Title
下版背面電容去半
MCP61M-M3
Size Document Number Rev
C
AM3 CPU PWR&GND 1.0A
Date: Wednesday, August 26, 2009 Sheet 7 of 31
A B C D E
 5 4 3 2 1

VCC3 VCC3

SCLK0
15 SMB_MEM_SCL
SDATA0
15 SMB_MEM_SDA
DDR3_1A DDR3_2A
MEM_MA_ADD0 188 3 MEM_MA_DATA0 MEM_MB_ADD0 188 3 MEM_MB_DATA0
MEM_MA_ADD1 A0 DQ0 MEM_MA_DATA1 MEM_MB_ADD1 A0 DQ0 MEM_MB_DATA1
181 A1 DQ1 4 181 A1 DQ1 4
MEM_MA_ADD2 61 9 MEM_MA_DATA2 MEM_MB_ADD2 61 9 MEM_MB_DATA2
MEM_MA_DATA[63..0] MEM_MA_ADD3 A2 DQ2 MEM_MA_DATA3 MEM_MB_ADD3 A2 DQ2 MEM_MB_DATA3
5 MEM_MA_DATA[63..0] 180 A3 DQ3 10 180 A3 DQ3 10
MEM_MA_ADD4 59 122 MEM_MA_DATA4 MEM_MB_ADD4 59 122 MEM_MB_DATA4
MEM_MA_CHECK[7..0] MEM_MA_ADD5 A4 DQ4 MEM_MA_DATA5 MEM_MB_ADD5 A4 DQ4 MEM_MB_DATA5
D 5 MEM_MA_CHECK[7..0] 58 A5 DQ5 123 58 A5 DQ5 123 D
MEM_MA_ADD6 178 128 MEM_MA_DATA6 MEM_MB_ADD6 178 128 MEM_MB_DATA6
MEM_MA_ADD7 A6 DQ6 MEM_MA_DATA7 MEM_MB_ADD7 A6 DQ6 MEM_MB_DATA7
56 A7 DQ7 129 56 A7 DQ7 129
MEM_MA_ADD[15..0] MEM_MA_ADD8 177 MEM_MB_ADD8 177
5 MEM_MA_ADD[15..0] A8 A8
MEM_MA_ADD9 175 12 MEM_MA_DATA8 MEM_MB_ADD9 175 12 MEM_MB_DATA8
MEM_MA_BANK0 MEM_MA_ADD10 A9 DQ8 MEM_MA_DATA9 MEM_MB_ADD10 A9 DQ8 MEM_MB_DATA9
5 MEM_MA_BANK0 70 A10 DQ9 13 70 A10 DQ9 13
MEM_MA_BANK1 MEM_MA_ADD11 55 18 MEM_MA_DATA10 MEM_MB_ADD11 55 18 MEM_MB_DATA10
5 MEM_MA_BANK1 A11 DQ10 A11 DQ10
MEM_MA_BANK2 MEM_MA_ADD12 174 19 MEM_MA_DATA11 MEM_MB_ADD12 174 19 MEM_MB_DATA11
5 MEM_MA_BANK2 A12 DQ11 A12 DQ11
MEM_MA_ADD13 196 131 MEM_MA_DATA12 MEM_MB_ADD13 196 131 MEM_MB_DATA12
MEM_MA_ADD14 A13 DQ12 MEM_MA_DATA13 MEM_MB_ADD14 A13 DQ12 MEM_MB_DATA13
172 A14 DQ13 132 172 A14 DQ13 132
MEM_MA_DM[7..0] MEM_MA_ADD15 171 137 MEM_MA_DATA14 MEM_MB_ADD15 171 137 MEM_MB_DATA14
5 MEM_MA_DM[7..0] A15 DQ14 A15 DQ14
MEM_MA_DM8 138 MEM_MA_DATA15 138 MEM_MB_DATA15
5 MEM_MA_DM8 DQ15 DQ15
MEM_MA_BANK0 71 MEM_MB_BANK0 71
MEM_MA_DQS_H[8..0] MEM_MA_BANK1 BA0 MEM_MA_DATA16 MEM_MB_BANK1 BA0 MEM_MB_DATA16
5 MEM_MA_DQS_H[8..0] 190 BA1 DQ16 21 190 BA1 DQ16 21
MEM_MA_BANK2 52 22 MEM_MA_DATA17 MEM_MB_BANK2 52 22 MEM_MB_DATA17
MEM_MA_DQS_L[8..0] BA2 DQ17 MEM_MA_DATA18 BA2 DQ17 MEM_MB_DATA18
5 MEM_MA_DQS_L[8..0] DQ18 27 DQ18 27
28 MEM_MA_DATA19 28 MEM_MB_DATA19
MEM_MA_RAS- MEM_MA_DM0 DQ19 MEM_MA_DATA20 MEM_MB_DM0 DQ19 MEM_MB_DATA20
5 MEM_MA_RAS- 125 DM0/DQS9 DQ20 140 125 DM0/DQS9 DQ20 140
MEM_MA_CAS- MEM_MA_DM1 134 141 MEM_MA_DATA21 MEM_MB_DM1 134 141 MEM_MB_DATA21
5 MEM_MA_CAS- DM1/DQS10 DQ21 DM1/DQS10 DQ21
MEM_MA_WE- MEM_MA_DM2 143 146 MEM_MA_DATA22 MEM_MB_DM2 143 146 MEM_MB_DATA22
5 MEM_MA_WE- DM2/DQS11 DQ22 DM2/DQS11 DQ22
MEM_MA_DM3 152 147 MEM_MA_DATA23 MEM_MB_DM3 152 147 MEM_MB_DATA23
MEM_MA_CKE0 MEM_MA_DM4 DM3/DQS12 DQ23 MEM_MB_DM4 DM3/DQS12 DQ23
5 MEM_MA_CKE0 203 DM4/DQS13 203 DM4/DQS13
MEM_MA_CKE1 MEM_MA_DM5 212 30 MEM_MA_DATA24 MEM_MB_DM5 212 30 MEM_MB_DATA24
5 MEM_MA_CKE1 DM5/DQS14 DQ24 DM5/DQS14 DQ24
MEM_MA_DM6 221 31 MEM_MA_DATA25 MEM_MB_DM6 221 31 MEM_MB_DATA25
MEM_MA_EVENT_L MEM_MA_DM7 DM6/DQS15 DQ25 MEM_MA_DATA26 MEM_MB_DM7 DM6/DQS15 DQ25 MEM_MB_DATA26
5 MEM_MA_EVENT_L 230 DM7/DQS16 DQ26 36 230 DM7/DQS16 DQ26 36
MEM_MA_DM8 161 37 MEM_MA_DATA27 MEM_MB_DM8 161 37 MEM_MB_DATA27
MEM_MA_RESET- DM8/DQS17 DQ27 MEM_MA_DATA28 DM8/DQS17 DQ27 MEM_MB_DATA28
5 MEM_MA_RESET- DQ28 149 DQ28 149
MEM_MA_DQS_L0 6 150 MEM_MA_DATA29 MEM_MB_DQS_L0 6 150 MEM_MB_DATA29
MEM_MA_DQS_H0 DQS0 DQ29 MEM_MA_DATA30 MEM_MB_DQS_H0 DQS0 DQ29 MEM_MB_DATA30
7 DQS0 DQ30 155 7 DQS0 DQ30 155
MEM_MA0_CS_L0 MEM_MA_DQS_L1 15 156 MEM_MA_DATA31 MEM_MB_DQS_L1 15 156 MEM_MB_DATA31
5 MEM_MA0_CS_L0 DQS1 DQ31 DQS1 DQ31
C MEM_MA0_CS_L1 MEM_MA_DQS_H1 16 MEM_MB_DQS_H1 16 C
5 MEM_MA0_CS_L1 MEM_MA_DQS_L2 DQS1 MEM_MA_DATA32 MEM_MB_DQS_L2 DQS1 MEM_MB_DATA32
24 DQS2 DQ32 81 24 DQS2 DQ32 81
MEM_MA0_ODT0 MEM_MA_DQS_H2 25 82 MEM_MA_DATA33 MEM_MB_DQS_H2 25 82 MEM_MB_DATA33
5 MEM_MA0_ODT0 DQS2 DQ33 DQS2 DQ33
MEM_MA0_ODT1 MEM_MA_DQS_L3 33 87 MEM_MA_DATA34 MEM_MB_DQS_L3 33 87 MEM_MB_DATA34
5 MEM_MA0_ODT1 DQS3 DQ34 DQS3 DQ34
MEM_MA_DQS_H3 34 88 MEM_MA_DATA35 MEM_MB_DQS_H3 34 88 MEM_MB_DATA35
MEM_MA0_CLK0_P MEM_MA_DQS_L4 DQS3 DQ35 MEM_MA_DATA36 MEM_MB_DQS_L4 DQS3 DQ35 MEM_MB_DATA36
5 MEM_MA0_CLK0_P 84 DQS4 DQ36 200 84 DQS4 DQ36 200
5 MEM_MA0_CLK0_N MEM_MA0_CLK0_N MEM_MA_DQS_H4 85 201 MEM_MA_DATA37 MEM_MB_DQS_H4 85 201 MEM_MB_DATA37
MEM_MA_DQS_L5 DQS4 DQ37 MEM_MA_DATA38 MEM_MB_DQS_L5 DQS4 DQ37 MEM_MB_DATA38
93 DQS5 DQ38 206 93 DQS5 DQ38 206
MEM_MA0_CLK1_P MEM_MA_DQS_H5 94 207 MEM_MA_DATA39 MEM_MB_DQS_H5 94 207 MEM_MB_DATA39
5 MEM_MA0_CLK1_P DQS5 DQ39 DQS5 DQ39
MEM_MA0_CLK1_N MEM_MA_DQS_L6 102 MEM_MB_DQS_L6 102
5 MEM_MA0_CLK1_N DQS6 DQS6
MEM_MA_DQS_H6 103 90 MEM_MA_DATA40 MEM_MB_DQS_H6 103 90 MEM_MB_DATA40
MEM_MA_DQS_L7 DQS6 DQ40 MEM_MA_DATA41 MEM_MB_DQS_L7 DQS6 DQ40 MEM_MB_DATA41
111 DQS7 DQ41 91 111 DQS7 DQ41 91
MEM_MB_DATA[63..0] MEM_MA_DQS_H7 112 96 MEM_MA_DATA42 MEM_MB_DQS_H7 112 96 MEM_MB_DATA42
5 MEM_MB_DATA[63..0] DQS7 DQ42 DQS7 DQ42
MEM_MA_DQS_L8 42 97 MEM_MA_DATA43 MEM_MB_DQS_L8 42 97 MEM_MB_DATA43
MEM_MB_CHECK[7..0] MEM_MA_DQS_H8 DQS8 DQ43 MEM_MA_DATA44 MEM_MB_DQS_H8 DQS8 DQ43 MEM_MB_DATA44
5 MEM_MB_CHECK[7..0] 43 DQS8 DQ44 209 43 DQS8 DQ44 209
210 MEM_MA_DATA45 210 MEM_MB_DATA45
MEM_MA_RAS- DQ45 MEM_MA_DATA46 MEM_MB_RAS- DQ45 MEM_MB_DATA46
192 RAS DQ46 215 192 RAS DQ46 215
MEM_MB_ADD[15..0] MEM_MA_CAS- 74 216 MEM_MA_DATA47 MEM_MB_CAS- 74 216 MEM_MB_DATA47
5 MEM_MB_ADD[15..0] CAS DQ47 CAS DQ47
MEM_MA_WE- 73 MEM_MB_WE- 73
MEM_MB_BANK0 WE MEM_MA_DATA48 WE MEM_MB_DATA48
5 MEM_MB_BANK0 DQ48 99 DQ48 99
MEM_MB_BANK1 MEM_MA0_CS_L0 193 100 MEM_MA_DATA49 MEM_MB0_CS_L0 193 100 MEM_MB_DATA49
5 MEM_MB_BANK1 S0 DQ49 S0 DQ49
MEM_MB_BANK2 MEM_MA0_CS_L1 76 105 MEM_MA_DATA50 MEM_MB0_CS_L1 76 105 MEM_MB_DATA50
5 MEM_MB_BANK2 S1 DQ50 S1 DQ50
106 MEM_MA_DATA51 106 MEM_MB_DATA51
MEM_MA_CKE0 DQ51 MEM_MA_DATA52 MEM_MB_CKE0 DQ51 MEM_MB_DATA52
50 CKE0 DQ52 218 50 CKE0 DQ52 218
MEM_MB_DM[7..0] MEM_MA_CKE1 169 219 MEM_MA_DATA53 MEM_MB_CKE1 169 219 MEM_MB_DATA53
5 MEM_MB_DM[7..0] CKE1 DQ53 CKE1 DQ53
MEM_MB_DM8 224 MEM_MA_DATA54 224 MEM_MB_DATA54
5 MEM_MB_DM8 DQ54 DQ54
MEM_MA0_ODT0 195 225 MEM_MA_DATA55 MEM_MB0_ODT0 195 225 MEM_MB_DATA55
MEM_MB_DQS_H[8..0] MEM_MA0_ODT1 ODT DQ55 MEM_MB0_ODT1 ODT DQ55
5 MEM_MB_DQS_H[8..0] 77 RSVD/ODT1 77 RSVD/ODT1
108 MEM_MA_DATA56 108 MEM_MB_DATA56
MEM_MB_DQS_L[8..0] MEM_MA0_CLK0_P DQ56 MEM_MA_DATA57 MEM_MB0_CLK0_P DQ56 MEM_MB_DATA57
B 5 MEM_MB_DQS_L[8..0] 184 CK0 DQ57 109 184 CK0 DQ57 109 B
MEM_MA0_CLK0_N 185 114 MEM_MA_DATA58 MEM_MB0_CLK0_N 185 114 MEM_MB_DATA58
MEM_MB_RAS- CK0 DQ58 MEM_MA_DATA59 CK0 DQ58 MEM_MB_DATA59
5 MEM_MB_RAS- DQ59 115 DQ59 115
MEM_MB_CAS- MEM_MA0_CLK1_P 63 227 MEM_MA_DATA60 MEM_MB0_CLK1_P 63 227 MEM_MB_DATA60
5 MEM_MB_CAS- CK1 DQ60 CK1 DQ60
MEM_MB_WE- MEM_MA0_CLK1_N 64 228 MEM_MA_DATA61 MEM_MB0_CLK1_N 64 228 MEM_MB_DATA61
5 MEM_MB_WE- CK1 DQ61 CK1 DQ61
233 MEM_MA_DATA62 233 MEM_MB_DATA62
MEM_MB_CKE0 DQ62 MEM_MA_DATA63 DQ62 MEM_MB_DATA63
5 MEM_MB_CKE0 117 SA0 DQ63 234 VCC3 117 SA0 DQ63 234
MEM_MB_CKE1 237 237
5 MEM_MB_CKE1 SA1 SA1
39 MEM_MA_CHECK0 39 MEM_MB_CHECK0
MEM_MB_EVENT_L SCLK0 CB0 MEM_MA_CHECK1 SCLK0 CB0 MEM_MB_CHECK1
5 MEM_MB_EVENT_L 118 SCL CB1 40 118 SCL CB1 40
SDATA0 238 45 MEM_MA_CHECK2 SDATA0 238 45 MEM_MB_CHECK2
MEM_MB_RESET- SDA CB2 MEM_MA_CHECK3 SDA CB2 MEM_MB_CHECK3
5 MEM_MB_RESET- CB3 46 CB3 46
VCC3 236 158 MEM_MA_CHECK4 VCC3 236 158 MEM_MB_CHECK4
VDDSPD CB4 MEM_MA_CHECK5 VDDSPD CB4 MEM_MB_CHECK5
CB5 159 CB5 159
167 164 MEM_MA_CHECK6 167 164 MEM_MB_CHECK6
MEM_MB0_CS_L0 TEST CB6 MEM_MA_CHECK7 TEST CB6 MEM_MB_CHECK7
5 MEM_MB0_CS_L0 CB7 165 CB7 165
MEM_MB0_CS_L1 48 48
5 MEM_MB0_CS_L1 FREE1 FREE1
49 FREE2 DQS9 126 49 FREE2 DQS9 126
MEM_MB0_ODT0 MEM_MA_EVENT_L 187 135 MEM_MB_EVENT_L 187 135
5 MEM_MB0_ODT0 FREE3 DQS10 FREE3 DQS10
MEM_MB0_ODT1 198 144 198 144
5 MEM_MB0_ODT1 FREE4 DQS11 FREE4 DQS11
DQS12 153 DQS12 153
MEM_MB0_CLK0_P MEM_MA_RESET- 168 204 MEM_MB_RESET- 168 204
5 MEM_MB0_CLK0_P MEM_MB0_CLK0_N RESET DQS13 RESET DQS13
5 MEM_MB0_CLK0_N 53 ERR_OUT DQS14 213 53 ERR_OUT DQS14 213
68 PAR_IN DQS15 222 68 PAR_IN DQS15 222
5 MEM_MB0_CLK1_P MEM_MB0_CLK1_P 79 231 79 231
MEM_MB0_CLK1_N RSVD/SPD DQS16 RSVD/SPD DQS16
5 MEM_MB0_CLK1_N DQS17 162 DQS17 162
DDR3-240P-OR DDR3-240P-OR

SMBus Addressing V_DIMM V_DIMM

A A

SMBus 0
1

EC3 EC2
Device 8-bit Address (hex)
2

DIMMA0 A0
Elitegroup Computer Systems
1000U-6V3D8H11.5E 1000U-6V3D8H11.5E
Title
DIMMB0 A2
DIMMA1 A4
MCP61M-M3
Size Document Number Rev
Custom
DIMMB1 A6 DDR3 DIMM A/B CH 1.0A
Date: Wednesday, August 26, 2009 Sheet 8 of 31
5 4 3 2 1
 A B C D E

DE-COUPLING CAP FOR DIMMs

MEM_VDDIO_SUS DDR3_VTT
1.5V
V_DIMM MEM_VDDIO_SUS

1
4 4

0.75V M_C43 M_C38 M_C60 M_C53 M_C50 M_C54 M_C52 M_C55 M_C51 M_C57 M_C56
DDR_VTT DDR3_VTT .1U-04 .1U-04-O .1U-04 .1U-04 .1U-04-O .1U-04 .1U-04-O .1U-04 .1U-04 .1U-04 .1U-04-O

2
MEM_VDDIO_SUS MEM_VDDIO_SUS
DDR3_1B DDR3_2B
2 VSS1 VDD1 51 2 VSS1 VDD1 51
5 VSS2 VDD2 54 5 VSS2 VDD2 54
8 VSS3 VDD3 57 8 VSS3 VDD3 57
11 VSS4 VDD4 60 11 VSS4 VDD4 60
14 VSS5 VDD5 62 14 VSS5 VDD5 62
17 VSS6 VDD6 65 17 VSS6 VDD6 65
20 VSS7 VDD7 66 20 VSS7 VDD7 66
23 VSS8 VDD8 69 23 VSS8 VDD8 69
26 VSS9 VDD9 72 26 VSS9 VDD9 72
29 VSS10 VDD10 75 29 VSS10 VDD10 75
32 VSS11 VDD11 78 32 VSS11 VDD11 78
3 35 VSS12 VDD12 170 35 VSS12 VDD12 170 3

38 VSS13 VDD13 173 38 VSS13 VDD13 173

41 VSS14 VDD14 176 41 VSS14 VDD14 176
44 VSS15 VDD15 179 44 VSS15 VDD15 179
47 VSS16 VDD16 182 47 VSS16 VDD16 182
80 VSS17 VDD17 183 80 VSS17 VDD17 183
83 VSS18 VDD18 186 83 VSS18 VDD18 186
86 VSS19 VDD19 189 86 VSS19 VDD19 189
89 VSS20 VDD20 191 89 VSS20 VDD20 191
92 VSS21 VDD21 194 92 VSS21 VDD21 194
95 197 DDR3_VTT 95 197 DDR3_VTT
VSS22 VDD22 VSS22 VDD22
98 VSS23 98 VSS23
101 VSS24 101 VSS24
104 VSS25 VTT1 120 104 VSS25 VTT1 120
107 VSS26 VTT2 240 107 VSS26 VTT2 240
110 VSS27 110 VSS27
113 VSS28 113 VSS28
116 VSS29 VREFDQ 1 MEM_VREFDQ_SUS 116 VSS29 VREFDQ 1 MEM_VREFDQ_SUS
119 VSS30 119 VSS30
121 VSS31 121 VSS31
124 VSS32 124 VSS32
127 VSS33 VREFCA 67 MEM_VREFCA_SUS 127 VSS33 VREFCA 67 MEM_VREFCA_SUS
130 VSS34 130 VSS34
133 VSS35 133 VSS35
136 VSS36 136 VSS36
139 VSS37 VSS49 205 139 VSS37 VSS49 205
142 VSS38 VSS50 208 142 VSS38 VSS50 208
145 VSS39 VSS51 211 145 VSS39 VSS51 211
148 VSS40 VSS52 214 148 VSS40 VSS52 214
151 VSS41 VSS53 217 151 VSS41 VSS53 217
2
154 VSS42 VSS54 220 154 VSS42 VSS54 220 2

157 VSS43 VSS55 223 157 VSS43 VSS55 223

160 VSS44 VSS56 226 160 VSS44 VSS56 226
163 VSS45 VSS57 229 163 VSS45 VSS57 229
199 VSS46 VSS58 232 199 VSS46 VSS58 232
166 VSS47 VSS59 235 166 VSS47 VSS59 235
202 VSS48 VSS60 239 202 VSS48 VSS60 239

DDR3-240P-OR DDR3-240P-OR

MEM_VREFDQ_SUS MEM_VREFCA_SUS
MEM_VDDIO_SUS MEM_VREFDQ_SUS MEM_VDDIO_SUS MEM_VREFCA_SUS
1

M_R45 M_C47 M_R44 M_C46

15-1-06 .1U-04-O 15-1-06 .1U-04-O
2

2
2

M_ELT3 M_ELT2
1

1
1 1

M_R46 M_C49 M_C48 Layout: Place within 500 M_R43 M_C45 M_C44 Layout: Place within 500
15-1-06 .1U-04 1000P-04 15-1-06 .1U-04 1000P-04
mils of the DIMMB1 socket. mils of the DIMMB1 socket.
2

2
2

12mil(width):20mil(spacing) 12mil(width):20mil(spacing)
Elitegroup Computer Systems
Title
MCP61M-M3
Size Document Number Rev
Custom
DDR3 DIMM PWR 1.0A
Date: Wednesday, August 26, 2009 Sheet 9 of 31
A B C D E
 5 4 3 2 1

U3A
SM_IC_BGA692_P8MM_25X25
MCP61 L0_CADIN_H[15..0]
L0_CADOUT_H[15..0] L0_CADIN_H[15..0] 4
4 L0_CADOUT_H[15..0] SEC 1 OF 8
L0_CADOUT_H0 AG8 HT_MCP_RXD0_P HT_MCP_TXD0_P AH23 L0_CADIN_H0
D L0_CADOUT_H1 L0_CADIN_H1 D
AG9 HT_MCP_RXD1_P HT_MCP_TXD1_P AH22
L0_CADOUT_H2 AK9 HT_MCP_RXD2_P HT_MCP_TXD2_P AJ21 L0_CADIN_H2
L0_CADOUT_H3 AJ10 HT_MCP_RXD3_P HT_MCP_TXD3_P AH21 L0_CADIN_H3
L0_CADOUT_H4 AG12 HT_MCP_RXD4_P HT_MCP_TXD4_P AH19 L0_CADIN_H4
L0_CADOUT_H5 AG13 HT_MCP_RXD5_P HT_MCP_TXD5_P AH18 L0_CADIN_H5
L0_CADOUT_H6 AK13 HT_MCP_RXD6_P HT_MCP_TXD6_P AJ17 L0_CADIN_H6
L0_CADOUT_H7 AJ14 HT_MCP_RXD7_P HT_MCP_TXD7_P AH17 L0_CADIN_H7
L0_CADOUT_H8 AB10 HT_MCP_RXD8_P HT_MCP_TXD8_P AF22 L0_CADIN_H8
L0_CADOUT_H9 AD10 HT_MCP_RXD9_P HT_MCP_TXD9_P AB20 L0_CADIN_H9
L0_CADOUT_H10 AF10 HT_MCP_RXD10_P HT_MCP_TXD10_P AC20 L0_CADIN_H10
L0_CADOUT_H11 AC12 HT_MCP_RXD11_P HT_MCP_TXD11_P AE20 L0_CADIN_H11
L0_CADOUT_H12 AB11 HT_MCP_RXD12_P HT_MCP_TXD12_P AD18 L0_CADIN_H12 +1.2V_HT VCORE
L0_CADOUT_H13 AB13 HT_MCP_RXD13_P HT_MCP_TXD13_P AF18 L0_CADIN_H13
L0_CADOUT_H14 AF14 HT_MCP_RXD14_P HT_MCP_TXD14_P AB17 L0_CADIN_H14
L0_CADOUT_H15 AE14 HT_MCP_RXD15_P HT_MCP_TXD15_P AC16 L0_CADIN_H15
L0_CADIN_L[15..0]
L0_CADOUT_L[15..0] L0_CADIN_L[15..0] 4 C169 .01U-04
4 L0_CADOUT_L[15..0]
L0_CADOUT_L0 AH8 HT_MCP_RXD0_N HT_MCP_TXD0_N AJ23 L0_CADIN_L0
L0_CADOUT_L1 AH9 HT_MCP_RXD1_N HT_MCP_TXD1_N AJ22 L0_CADIN_L1
L0_CADOUT_L2 AJ9 HT_MCP_RXD2_N HT_MCP_TXD2_N AK21 L0_CADIN_L2
L0_CADOUT_L3 AH10 HT_MCP_RXD3_N HT_MCP_TXD3_N AG21 L0_CADIN_L3
L0_CADOUT_L4 AH12 HT_MCP_RXD4_N HT_MCP_TXD4_N AJ19 L0_CADIN_L4
L0_CADOUT_L5 AH13 HT_MCP_RXD5_N HT_MCP_TXD5_N AJ18 L0_CADIN_L5
L0_CADOUT_L6 AJ13 HT_MCP_RXD6_N HT_MCP_TXD6_N AK17 L0_CADIN_L6
C C
L0_CADOUT_L7 AH14 HT_MCP_RXD7_N HT_MCP_TXD7_N AG17 L0_CADIN_L7
L0_CADOUT_L8 AC10 HT_MCP_RXD8_N HT_MCP_TXD8_N AG22 L0_CADIN_L8
L0_CADOUT_L9 AE10 HT_MCP_RXD9_N HT_MCP_TXD9_N AB19 L0_CADIN_L9
L0_CADOUT_L10 AG10 HT_MCP_RXD10_N HT_MCP_TXD10_N AD20 L0_CADIN_L10
L0_CADOUT_L11 AD12 HT_MCP_RXD11_N HT_MCP_TXD11_N AF20 L0_CADIN_L11
L0_CADOUT_L12 AC11 HT_MCP_RXD12_N HT_MCP_TXD12_N AE18 L0_CADIN_L12
L0_CADOUT_L13 AB12 HT_MCP_RXD13_N HT_MCP_TXD13_N AG18 L0_CADIN_L13
L0_CADOUT_L14 AG14 HT_MCP_RXD14_N HT_MCP_TXD14_N AB16 L0_CADIN_L14
L0_CADOUT_L15 AD14 HT_MCP_RXD15_N HT_MCP_TXD15_N AD16 L0_CADIN_L15 MCP61 mounted MCP68 mounted
07.03.12 07.03.12
L0_CLKOUT_H0 AJ11 HT_MCP_RX_CLK0_P HT_MCP_TX_CLK0_P AH20 L0_CLKIN_H0
4 L0_CLKOUT_H0 L0_CLKIN_H0 4
L0_CLKOUT_L0 AH11 HT_MCP_RX_CLK0_N HT_MCP_TX_CLK0_N AG20 L0_CLKIN_L0
4 L0_CLKOUT_L0 L0_CLKIN_L0 4
L0_CLKOUT_H1 AE12 HT_MCP_RX_CLK1_P HT_MCP_TX_CLK1_P AC18 L0_CLKIN_H1
4 L0_CLKOUT_H1 L0_CLKIN_H1 4
L0_CLKOUT_L1 AF12 HT_MCP_RX_CLK1_N HT_MCP_TX_CLK1_N AB18 L0_CLKIN_L1 VCC3 VCC3_DUAL
4 L0_CLKOUT_L1 L0_CLKIN_L1 4

L0_CTLOUT_H0 AJ15 HT_MCP_RXCTL0_P HT_MCP_TXCTL0_P AH16 L0_CTLIN_H0

4 L0_CTLOUT_H0 L0_CTLIN_H0 4
L0_CTLOUT_L0 AH15 HT_MCP_RXCTL0_N HT_MCP_TXCTL0_N AG16 L0_CTLIN_L0 R446 R309
4 L0_CTLOUT_L0 L0_CTLIN_L0 4
AB14 RESERVED RESERVED AE16 10K-04 10K-04-O
AC14 RESERVED RESERVED AF16
+1.2V_HT HT_MCP_REQ* AH25 HTCPU_REQ-
B HT_MCP_STOP* AH24 HTCPU_STOP- B
VCC_HT1 SR1 150-1-04-XHTCPUCAL_1P2V HTCPU_RST- HTCPU_STOP- 6
AB9 HT_MCP_COMP_VDD HT_MCP_RST* AG23 HTCPU_RST- 6
HT_MCP_PWRGD AG24 HTCPU_PWRGD
SR2 150-1-04-XHTCPUCAL_GND HTCPU_PWRGD 6
AB8 HT_MCP_COMP_GND

CLKOUT_200MHZ_P AK25 CPU_CLK_200_P

CPU_CLK_200_N
CPU_CLK_200_P 6
CLKOUT_200MHZ_N AJ25 CPU_CLK_200_N 6
PROCHOT_L AD8 PROCHOT*/GPIO20
6 PROCHOT_L
CPU_THERMTRIP- AE8 THERMTRIP*/GPIO58
6 CPU_THERMTRIP-
VCC3 +1.2V_CORE
+1.2V_CORE CLK_25MHZ
SL1 CPU_SBVREF AF24 5MIL TRACE
SL2 1 2 AC15 +1.2V_PLL_CPU_HT
1 2 +3.3_PLL_CPU FB-30-S-X AB15 +3.3V_PLL_CPU CLKOUT_25MHZ AK26 TP_CLKOUT25MHZ C160 1U-06 CRB:4.7uF
FB-30-S-X
CLK200_TERM_GND AJ26 CLK200MHZ_TERMP_GND
SC45 SC38 SC44 SC47
I115
4.7U-08-X .1U-04-X .1U-04-X 4.7U-08-X SC46 R447
07.03.12 2.37K-1-04-O
.1U-04-X

A A

<OrgAddr1> Elitegroup Computer Systems

Title
MCP61M-M3
Size Document Number Rev
B
MCP61 HT 1.0A
Date: Wednesday, August 26, 2009 Sheet 10 of 31
5 4 3 2 1
 5 4 3 2 1

U3B
SM_IC_BGA692_P8MM_25X25
PE0_RX_P[15..0] MCP61 PE0_TX_P[15..0]
19 PE0_RX_P[15..0] PE0_TX_P[15..0] 19
SEC 2 OF 8
PE0_RX_P0 H23 PE0_RX0_P PE0_TX0_P G29 PE0_TX_P0
PE0_RX_P1 H25 PE0_RX1_P PE0_TX1_P H27 PE0_TX_P1
PE0_RX_P2 K22 PE0_RX2_P PE0_TX2_P J27 PE0_TX_P2
PE0_RX_P3 K24 PE0_RX3_P PE0_TX3_P J30 PE0_TX_P3
PE0_RX_P4 K26 PE0_RX4_P PE0_TX4_P K29 PE0_TX_P4
D PE0_RX_P5 PE0_TX_P5 D
M22 PE0_RX5_P PE0_TX5_P L29
PE0_RX_P6 M23 PE0_RX6_P PE0_TX6_P M27 PE0_TX_P6
PE0_RX_P7 M26 PE0_RX7_P PE0_TX7_P N27 PE0_TX_P7
PE0_RX_P8 P22 PE0_RX8_P PE0_TX8_P N30 PE0_TX_P8
PE0_RX_P9 P26 PE0_RX9_P PE0_TX9_P P29 PE0_TX_P9
PE0_RX_P10 P25 PE0_RX10_P PE0_TX10_P R29 PE0_TX_P10
PE0_RX_P11 T23 PE0_RX11_P PE0_TX11_P T27 PE0_TX_P11
PE0_RX_P12 T26 PE0_RX12_P PE0_TX12_P U27 PE0_TX_P12
PE0_RX_P13 U23 PE0_RX13_P PE0_TX13_P U30 PE0_TX_P13
PE0_RX_P14 V24 PE0_RX14_P PE0_TX14_P V29 PE0_TX_P14
PE0_RX_P15 V27 PE0_RX15_P PE0_TX15_P W29 PE0_TX_P15
PE0_RX_N[15..0] PE0_TX_N[15..0]
19 PE0_RX_N[15..0] PE0_TX_N[15..0] 19
PE0_RX_N0 H24 PE0_RX0_N PE0_TX0_N G28 PE0_TX_N0
PE0_RX_N1 H26 PE0_RX1_N PE0_TX1_N H28 PE0_TX_N1
PE0_RX_N2 K23 PE0_RX2_N PE0_TX2_N J28 PE0_TX_N2
PE0_RX_N3 K25 PE0_RX3_N PE0_TX3_N J29 PE0_TX_N3
PE0_RX_N4 K27 PE0_RX4_N PE0_TX4_N K28 PE0_TX_N4
PE0_RX_N5 L22 PE0_RX5_N PE0_TX5_N L28 PE0_TX_N5
PE0_RX_N6 M24 PE0_RX6_N PE0_TX6_N M28 PE0_TX_N6
PE0_RX_N7 M25 PE0_RX7_N PE0_TX7_N N28 PE0_TX_N7
PE0_RX_N8 P23 PE0_RX8_N PE0_TX8_N N29 PE0_TX_N8
PE0_RX_N9 P27 PE0_RX9_N PE0_TX9_N P28 PE0_TX_N9
PE0_RX_N10 P24 PE0_RX10_N PE0_TX10_N R28 PE0_TX_N10
C C
PE0_RX_N11 T24 PE0_RX11_N PE0_TX11_N T28 PE0_TX_N11
PE0_RX_N12 T25 PE0_RX12_N PE0_TX12_N U28 PE0_TX_N12
PE0_RX_N13 V23 PE0_RX13_N PE0_TX13_N U29 PE0_TX_N13
PE0_RX_N14 V25 PE0_RX14_N PE0_TX14_N V28 PE0_TX_N14
PE0_RX_N15 V26 PE0_RX15_N PE0_TX15_N W28 PE0_TX_N15

PE_WAKE- B22 PE_WAKE*/GPIO21 PE0_REFCLK_P Y24 PE0_REFCLK

19,21 PE_WAKE- PE0_REFCLK 19
R448 0-04 AF27
UNNAMED_19_MCP61_I99_PE0PRSNTX1
PE0_PRSNTX1*/SDVO_SCL PE0_REFCLK_N Y23 PE0_REFCLK-
19 PE0_PRSNTX1- PE0_REFCLK- 19
R449 0-04 AF28 PE0_PRSNTX4*/SDVO_SDA
UNNAMED_19_MCP61_I99_PE0PRSNTX4
19 PE0_PRSNTX4-
R450 0-04 AE26 PE0_PRSNTX8*
19 PE0_PRSNTX8- PECLK_A_TEST
AF29 PE0_PRSNTX16* PE_A_TSTCLK_N AC24 SR5 100-04-X-O
19 PE0_PRSNTX16-
PE_A_TSTCLK_P AC25 PECLK_A_TEST*
+1.2V_CORE MCP61:Mounted
MCP68:NC
W22 +1.2V_PLL_PE_SS PE_RESET* AH29 PE_RESET-
PE_RESET- 19,21
Y22 +1.2V_PLL_PE_SS
SC50 SC51

4.7U-08-X .1U-04-X PE_CLK_COMP AJ30 PE_COMP R31 2.37K-1-04

+1.2V_CORE VCC3
5A 1.5A
SL4 U22 +1.2V_PLL_PE +3.3V_PLL_PE_SS R22 SL5
B V22 +1.2V_PLL_PE +3.3V_PLL_PE_SS T22 1 2 B
+3.3V_PLL_PE_SS FB-30-S-X
FB-30-S-08-X I99 SC131
SC132 SC133 SC130
.1U-04-X 4.7U-08-X
4.7U-08-X .1U-04-X

MCP61 Pin Define MCP68 Pin Define

PRSNTX1(AF27) +3.3V_HDMI_PLL_HVDD

PRSNTX4(AF28) HDCP_ROM_SCLK

A PRSNTX8(AE26) +3.3V_HDMI A

GND(AF30) HDCP_ROM_SDATA <OrgAddr1> Elitegroup Computer Systems

Title
MCP61M-M3
Size Document Number Rev
B
MCP61 PCI-E X16 1.0A
Date: Wednesday, August 26, 2009 Sheet 11 of 31
5 4 3 2 1
 5 4 3 2 1

U3C
SM_IC_BGA692_P8MM_25X25
MCP61
SEC 3 OF 8

For enhance AC131 Driving Y28 PE1_RX_P PE1_TX_P AA28

Y27 PE1_RX_N PE1_TX_N AA27
PE2_RX_P AB29 PE2_RX_P PE2_TX_P AA30 PE2_TX_P
21 PE2_RX_P PE2_TX_P 21
PE2_RX_N AB28 PE2_RX_N PE2_TX_N AA29 PE2_TX_N
21 PE2_RX_N PE2_TX_N 21
RN17 4.7K-8P4R
D MII_RXCLK D
1 2
3 4 MII_RXDV AK29 PEA_CLKREQ*/GPIO51 PE1_REFCLK_P Y26
5 6 MII_RXER PE1_REFCLK_N Y25
7 8 AG28 PE1_PRSNT* PE2_REFCLK_P AB23 PE2_REFCLK
PE2_PRSNT- PE2_REFCLK- PE2_REFCLK 21
21 PE2_PRSNT- AG30 PE2_PRSNT* PE2_REFCLK_N AA23 PE2_REFCLK- 21
SR3 PE_B_TSTCLK_P
AC27 PE_B_TSTCLK_P
100-04-X PE_B_TSTCLK_N
AC26 PE_B_TSTCLK_N
RESERVED AC29
AD27 RESERVED RESERVED AC28
AD28 RESERVED RESERVED AE27
AE30 RESERVED RESERVED AE28
AE29 RESERVED RESERVED AB24
R251 1K-04-O HDMI_RSET AJ29 RESERVED RESERVED AB25
AG29 RESERVED RESERVED AB27
MCP68:Mounted AH30 RESERVED RESERVED AB26

MII_RXD0 D26 RGMII_RXD0/MII_RXD0 RGMII_TXD0/MII_TXD0 A28 MII_TXD0

25 MII_RXD0 MII_TXD0 25
MII_RXD1 E26 RGMII_RXD1/MII_RXD1 RGMII_TXD1/MII_TXD1 B28 MII_TXD1
25 MII_RXD1 MII_TXD1 25
MII_RXD2 B26 RGMII_RXD2/MII_RXD2 RGMII_TXD2/MII_TXD2 D28 MII_TXD2
25 MII_RXD2 MII_TXD2 25
MII_RXD3 B27 RGMII_RXD3/MII_RXD3 RGMII_TXD3/MII_TXD3 E27 MII_TXD3
25 MII_RXD3 MII_TXD3 25
MII_RXCLK A26 RGMII_RXC/MII_RXCLK RGMII_TXC/MII_TXCLK D27 MII_TXCLK
C 25 MII_RXCLK MII_TXCLK 25 C
MII_RXDV C26 RGMII_RXCTL/MII_RXDV RGMII_TXCTL/MII_TXEN E28 MII_TXEN
25 MII_RXDV MII_TXEN 25

MII_RXER D24 MII_RXER/GPIO36 RGMII/MII_MDC B25 MII_MDC

25 MII_RXER MII_MDC 25
MII_COL E24 MII_COL/GPIO13/MI2C_DATA RGMII/MII_MDIO A25 MII_MDIO
25 MII_COL MII_MDIO 25
MII_CRS F23 MII_CRS/GPIO14/MI2C_CLK
25 MII_CRS VCC3_DUAL
RGMII/MII_PWRDWN*/GPIO37 F24 R41 1.5K-04
VCC3_DUAL
SINTR G24 RGMII/MII_INTR*/GPIO35 BUF_25MHZ C24
VCC3_DUAL
SL3 MII_RESET*/GPIO12 C25 R42
MII_RST- 25
1 2 +3.3V_PLL_MAC_DUAL M9 +3.3V_PLL_MAC_DUAL 1.47K-1-04
FB-30-S-X R358 4.7K-04
VCC3_DUAL MII_VREF C27
SC40
SC43
4.7U-08-X .1U-04-X R407 49.9-1-04 MII_COMP_3P3V B23 MII_COMP_3P3V C134 R43
MII_COMP_GND C23 MII_COMP_GND 1.47K-1-04
R406 49.9-1-04 .1U-04
route >10mil, place close
chip within 750mil

18 DAC_RED D30 DAC_RED DDC_CLK/GPIO17 B6 DDC_CLK 18

B
18 DAC_GREEN D29 DAC_GREEN DDC_DATA/GPIO19 A6 DDC_DATA 18 B
18 DAC_BLUE C30 DAC_BLUE

18 DAC_HSYNC B30 DAC_HSYNC

C29 DAC_VSYNC JTAG_TCK M7 MCP61_TCK R44 10K-04
R45 R46 R47 18 DAC_VSYNC SJ_TDI
JTAG_TDI M5 TP_MCP61_TDI
150-1-04

150-1-04

150-1-04

JTAG_TDO M6 TP_MCP61_TDO SJ_TDO

JTAG_TMS M8 TP_MCP61_TMS SJ_TMS
R408 DAC_RSET B29 DAC_RSET JTAG_TRST* L9 TP_MCP61_TRST* R48 10K-04-O MCP61:NC MCP68:Mounted
124-1-04 DAC_VREF A29 DAC_VREF
BC36 .01U-04 XTALIN K7 XTALIN
PLACE NEAR MCP61 XTALOUT K8 XTALOUT
X1
VCC3 X-25M
1.5A XTALIN_RTC K6 2 1
L5 XTALOUT_RTC K5

1
1 2 +3.3V_DAC F28 +3.3V_DAC

3
FB-30-S-08 X2 C135 C136
1 2 X-32.768K-20m12.5D 33P-04 33P-04

2
3 4
BC37 BC38 I130

1
10U-X5-08 .1U-04
C137 C138
A 15P-04 15P-04 A

2
<OrgAddr1> Elitegroup Computer Systems
Title
MCP61M-M3
Size Document Number Rev
B
MCP61 PCI-E X1/RGMII/DAC 1.0A
Date: Wednesday, August 26, 2009 Sheet 12 of 31
5 4 3 2 1
 5 4 3 2 1

U3D
SM_IC_BGA692_P8MM_25X25
MCP61
AD[31..0] SEC 4 OF 8
20 AD[31..0]
AD0 D14 PCI_AD0 PCI_REQ0* G12 PCI_REQ0-
D PCI_REQ0- 20 D
AD1 E14 PCI_AD1 PCI_REQ1* A10 PCI_REQ1-
PCI_REQ1- 20
AD2 A13 PCI_AD2 PCI_REQ2*/GPIO40/RS232_DSR* C11 1394REQ-
1394REQ- 20
AD3 C14 PCI_AD3 PCI_REQ3*/GPIO38/RS232_CTS* H14 LANREQ-
LANREQ- 20
AD4 A14 PCI_AD4 PCI_REQ4*/GPIO52/RS232_SIN* D13 PCI_REQ4-
PCI_REQ4- 20
AD5 B14 PCI_AD5
AD6 C15 PCI_AD6
AD7 J16 PCI_AD7
AD8 G16 PCI_AD8 PCI_GNT0* A9 PCI_GNT0-
AD9 PCI_GNT1- PCI_GNT0- 20
F16 PCI_AD9 PCI_GNT1* C10 PCI_GNT1- 20
AD10 E16 PCI_AD10 PCI_GNT2*/GPIO41/RS232_DTR* B10
AD11 B15 PCI_AD11 PCI_GNT3*/GPIO39/RS232_RTS* J14
AD12 D16 PCI_AD12 PCI_GNT4*/GPIO53/RS232_SOUT* C12
AD13 C16 PCI_AD13
AD14 D17 PCI_AD14
AD15 C17 PCI_AD15
AD16 J19 PCI_AD16 PCI_INTW* C22 PCI_INTW-
PCI_INTW- 20
AD17 J20 PCI_AD17 PCI_INTX* D22 PCI_INTX-
PCI_INTX- 20
AD18 H20 PCI_AD18 PCI_INTY* A22 PCI_INTY-
PCI_INTY- 20
AD19 G20 PCI_AD19 PCI_INTZ* A21 PCI_INTZ-
PCI_INTZ- 20
AD20 F20 PCI_AD20
AD21 E20 PCI_AD21
AD22 B18 PCI_AD22
AD23 C19 PCI_AD23 PCI_CLK0 B13 PCICLK0 RI1 22-04 PCI_CLKSLOT1
AD24 PCICLK1 RI2 22-04 PCI_CLKSLOT2 PCI_CLKSLOT1 20
D20 PCI_AD24 PCI_CLK1 F14 PCI_CLKSLOT2 20
AD25 C20 PCI_AD25 PCI_CLK2 D12
C AD26 D21 PCI_AD26 PCI_CLK3 E12 C
AD27 C21 PCI_AD27 PCI_CLK4 H12 PCICLK4 RI5 22-04
AD28 B21 PCI_AD28
AD29 H22 PCI_AD29
AD30 G22 PCI_AD30 PCI_CLKIN J12 PCI_CLKIN
AD31 F22 PCI_AD31

CI67

CI68
2

2
CBE-[3..0]

CI69
20 CBE-[3..0]

2
CBE-0 H16 PCI_CBE0*

10P-04-O

10P-04-O
CBE-1 B17 PCI_CBE1*

10P-04-O
CBE-2 A18 PCI_CBE2*

1
CBE-3 B19 PCI_CBE3*

LPC_AD[3..0]
FRAME- LPC_AD[3..0] 22
20 FRAME- C18 PCI_FRAME*
IRDY- A17 PCI_IRDY*
20 IRDY- TRDY- LPC_AD2
20 TRDY- D18 PCI_TRDY* LPC_AD0 G10
STOP- F18 PCI_STOP* LPC_AD1 F10 LPC_AD3
20 STOP- DEVSEL- LPC_AD1 VCC3_DUAL
20 DEVSEL- E18 PCI_DEVSEL* LPC_AD2 D10
PAR J18 PCI_PAR LPC_AD3 E10 LPC_AD0
20 PAR RJ1
PERR- G18 PCI_PERR*/GPIO43/RS232_DCD*
20 PERR- SERR-
20 SERR- H18 PCI_SERR* 1
PME- E22 PCI_PME*/GPIO30
20 PME- 2 3
LPC_PWRDWN*/GPIO54/EXT_NMI* C8 10K-06(2-3)
B
LPC_FRAME* H10 LPC_FRAME- 22 B
LPC_DRQ0*/GPIO50 C9 LPC_DRQ0-
LPC_DRQ0- 22
LPC_DRQ1*/GPIO15/FANRPM1 B9 R56 8.2K-04-O
PCIRST_SLOT1-
VCC3 LPC_SERIRQ
20 PCIRST_SLOT1- C13 PCI_RESET0* LPC_SERIRQ J10 LPC_SERIRQ 22
PCIRST_SLOT2- G14 PCI_RESET1*
20 PCIRST_SLOT2- STRAP JMPR
B11 PCI_RESET2*
HDA_SDOUT
PCIRST_IDE- F12 PCI_RESET3* LPC_CLK0 E8 LPC_CLK0 RI6 33-04LPCCLK_SIO LPC_FRAME
14 PCIRST_IDE- LPCCLK_SIO 22
PCIRST_SIO- D9 LPC_RESET*
DEFAULT*
22 PCIRST_SIO-
LPC_CLK1 D8
00 = LPC BIOS* 1-2
I134 01 = PCI BIOS 2-3

2
CI6 10 = SPI BIOS 1-2
11 = RESERVED
110P-04-O

A A

<OrgAddr1> Elitegroup Computer Systems

Title
MCP61M-M3
Size Document Number Rev
Custom
MCP61 PCI 1.0A
Date: Wednesday, August 26, 2009 Sheet 13 of 31
5 4 3 2 1
 5 4 3 2 1

U3E
SATA1 SM_IC_BGA692_P8MM_25X25 IDE_PDD[15..0] IDE_PDD[15..0]
8 PLACE CAPS AT CONN MCP61
HOLE
1 SEC 5 OF 8
GND A1+ C143 .01U-04 SATA_A0_TX_P IDE_PDD0 PCIRST_IDE- IDE
A+ 2 V2 SATA_A0_TX_P IDE_DATA_P0 AJ3 13 PCIRST_IDE-
3 A1- C144 .01U-04 SATA_A0_TX_N V1 SATA_A0_TX_N IDE_DATA_P1 AJ2 IDE_PDD1 1 2
A- IDE_PDD2 IDE_PDD7 IDE_PDD8
GND 4 IDE_DATA_P2 AH3 3 4
5 B1+ C140 .01U-04 SATA_A0_RX_N W3 SATA_A0_RX_N IDE_DATA_P3 AH1 IDE_PDD3 IDE_PDD6 5 6 IDE_PDD9
D B- B1- C139 .01U-04 SATA_A0_RX_P IDE_PDD4 IDE_PDD5 IDE_PDD10 D
B+ 6 W2 SATA_A0_RX_P IDE_DATA_P4 AG2 7 8
7 IDE_DATA_P5 AF2 IDE_PDD5 IDE_PDD4 9 10 IDE_PDD11
GND IDE_PDD6 IDE_PDD3 IDE_PDD12
9 HOLE IDE_DATA_P6 AF4 VCC3 11 12
SATA2 IDE_DATA_P7 AE6 IDE_PDD7 R347 4.7K-04 IDE_PDD2 13 14 IDE_PDD13
8 SATA-7P2R-OR IDE_DATA_P8 AE5 IDE_PDD8 IDE_PDD1 15 16 IDE_PDD14
HOLE IDE_PDD9 IDE_PDD0 IDE_PDD15
GND 1 IDE_DATA_P9 AF5 17 18
2 A2+ C145 .01U-04 SATA_A1_TX_P Y8 SATA_A1_TX_P IDE_DATA_P10 AF3 IDE_PDD10 19 20
A+ A2- C141 .01U-04 SATA_A1_TX_N IDE_PDD11 IDE_DREQ_P
A- 3 Y7 SATA_A1_TX_N IDE_DATA_P11 AG1 21 22
4 IDE_DATA_P12 AG3 IDE_PDD12 IDE_IOW_P- 23 24
GND B2+ C142 .01U-04 SATA_A1_RX_N IDE_PDD13 IDE_IOR_P- R346 15K-04
B- 5 Y5 SATA_A1_RX_N IDE_DATA_P13 AH2 25 26
6 B2- C146 .01U-04 SATA_A1_RX_P Y6 SATA_A1_RX_P IDE_DATA_P14 AJ1 IDE_PDD14 IDE_IORDY_P 27 28
B+ IDE_PDD15 IDE_DACK_P-
GND 7 IDE_DATA_P15 AK2 29 30
9 IDE_INTR_P 31 32
HOLE SATA3 IDE_ADDR_P0 IDE_ADDR_P1 CBLE_DET_P
IDE_ADDR_P0 AG6 33 34
SATA-7P2R-OR 8 IDE_ADDR_P1 AJ5 IDE_ADDR_P1 IDE_ADDR_P0 35 36 IDE_ADDR_P2
HOLE IDE_ADDR_P2 IDE_CS1_P- IDE_CS3_P-
GND 1 IDE_ADDR_P2 AH6 37 38
2 A3+ C423 .01U-04 SATA_B0_TX_P Y4 SATA_B0_TX_P P_HDLED- 39 40
A+ A3- C421 .01U-04 SATA_B0_TX_N IDE_CS1_P-
A- 3 Y3 SATA_B0_TX_N IDE_CS1_P* AK6
4 IDE_CS3_P* AJ6 IDE_CS3_P- H20X2-P20E-BL
GND B3- C416 .01U-04 SATA_B0_RX_N IDE_DACK_P- R344 5.6K-1-04
B- 5 AA4 SATA_B0_RX_N IDE_DACK_P* AG5
6 B3+ C419 .01U-04 SATA_B0_RX_P AA3 SATA_B0_RX_P IDE_IOW_P* AH4 IDE_IOW_P-
B+ IDE_INTR_P R345 10K-04
GND 7 IDE_INTR_P AH5
9 HOLE IDE_DREQ_P AK3 IDE_DREQ_P close to connector
SATA4 IDE_IOR_P* AJ4 IDE_IOR_P-
C C
8 SATA-7P2R-OR IDE_RDY_P AK4 IDE_IORDY_P R343 10K-04 IDE_PDD7
HOLE CBLE_DET_P
GND 1 CABLE_DET_P/GPIO63 AF6
2 A4+ C422 .01U-04 SATA_B1_TX_P AA2 SATA_B1_TX_P
A+ A4- C417 .01U-04 SATA_B1_TX_N
A- 3 AA1 SATA_B1_TX_N
GND 4
5 B4- C418 .01U-04 SATA_B1_RX_N AB1 SATA_B1_RX_N
B- B4+ C420 .01U-04 SATA_B1_RX_P
B+ 6 AB2 SATA_B1_RX_P
GND 7
9 HOLE VCC3
SATA-7P2R-OR IDE_COMP_3P3 AD5 IDE_COMP_3P3V R64 121-1-04
IDE_COMP_GND AD6 IDE_COMP_GND R65 121-1-04

D1

SATA_HDLED- 1
AC3 SATA_LED*/GPIO57 A5 SATA_HDLED- 3 HDD_LED-
RESERVED
P_HDLED- HDD_LED- 28
AC2 RESERVED 2
AD4 RESERVED
AD3 RESERVED
BAT54A-S
B AE4 RESERVED B
AE3 AA6 SATA_TSTCLK_P SR4 100-04-O
RESERVED SATA_TSTCLK_P
AE1 AB6 SATA_TSTCLK_N
RESERVED SATA_TSTCLK_N
+1.2V_CORE1.5A AE2 RESERVED
L6
1 2 +1.2V_PLL_SP_VDD Y9 +1.2V_PLL_SP_VDD
FB-30-S-08 SATA_TERMP AB5 SATA_TERMP
+1.2V_CORE
C155 C156 VCC3 3A
SL6 U13 +1.2V_PLL_SP_SS
4.7U-08 .1U-04 1 2 +3.3V_PLL U12 +3.3V_PLL_SP_SS R67
FB-30-S-X V12 +3.3V_PLL_LEG 2.49K-1-04
SC158 M12 +3.3V_PLL_DISP
.1U-04-X

SC157 SC159
4.7U-08-X .1U-04-X
I87

A A

<OrgAddr1> Elitegroup Computer Systems

Title
MCP61M-M3
Size Document Number Rev
B
MCP61 SATA/IDE 1.0A
Date: Wednesday, August 26, 2009 Sheet 14 of 31
5 4 3 2 1
 5 4 3 2 1

REMOVE FOR PRODUCTION USB0~3 --> BACK CONNECTORS

U3F USB4~11 --> ON-BOARD HEADER
C404 10P-04-O SM_IC_BGA692_P8MM_25X25
Location Unimportant.
MCP61
AC_RST* VCC3_DUAL GP_CLK SEC 6 OF 8
1 = *RGMII TP_GP_REFCLKB7 M3 USB_0 USB_0- 1 2
RJ2 GP_REFCLK USB0_P
0 = MII HDA_BITCLK R68 22-04 USB_0- 24 USB_0- USB_0
26 HDA_BITCLK B4 HDA_BCLK USB0_N M4 24 USB_0 3 4

.
1 2 USB_1- 5 6
D AC_SYNC 1 C412 10P-04-O USB_1 24 USB_1- USB_1 D
3 2 USB1_P N3 24 USB_1 7 8
(SIO CLK) HDA_SDOUT A3 HDA_SDATA_OUT0/GPIO45 USB1_N N4 USB_1- RN45 15K-8P4R
26 HDA_SDOUT

..
1 = *24MHZ 10K-06(1-2) HDA_SDIN_0 R70 22-04 A2 HDA_SDATA_IN0/GPIO22
26 HDA_SDIN_0
0 = 14.318MHZ R72 22-04 B1 HDA_SDATA_IN1/GPIO23/MGPIO0 USB2_P N1 USB_2 USB_2 1 2
USB_2- 25 USB_2 USB_2-
RJ3 B2 RESERVED USB2_N N2 25 USB_2- 3 4
* = DEFAULT USB_3 5 6
USB_3 25 USB_3 USB_3-
1 USB3_P P1 25 USB_3- 7 8
C411 10P-04-O USB3_N P2 USB_3- RN46 15K-8P4R
3 2
1 2
10K-06(2-3) USB4_P R2 USB_4 USB_4 1 2
HDA_RST- R172 22-04 USB_4- 24 USB_4 USB_4-
26 HDA_RST- C3 HDA_RESET* USB4_N R3 24 USB_4- 3 4

..
HDA_SYNC R173 22-04 B3 HDA_SYNC/GPIO44 USB_5 5 6
26 HDA_SYNC C410 10P-04-O USB_5 24 USB_5 USB_5-
USB5_P P3 24 USB_5- 7 8
R367 10K-04 1 2 USB5_N P4 USB_5- RN43 15K-8P4R
RJ4 VCC3

.
F2 GPIO_1
F1 GPIO_2/NMI* USB6_P T3 USB_6 USB_6 1 2
1 GPIO5 USB_6- 24 USB_6 USB_6-
3 2 F6 GPIO_3/SMI* USB6_N T4 24 USB_6- 3 4
GPIO4 J8 GPIO_4/SCI_INTR* USB_7 5 6
10K-06(2-3) 28 GPIO4 GPIO5 USB_7 24 USB_7 USB_7-
G3 GPIO_5/INIT* USB7_P U3 24 USB_7- 7 8
GPIO6 G5 GPIO_6/FERR*/SYS_FERR* USB7_N U4 USB_7- RN42 15K-8P4R
RJ5
G6 GPIO_7/NFERR*/SYS_PERR*
USB8_P T6 USB_8 USB_8 1 2
1 GPIO6 SPI_DI_MCP USB_8- 24 USB_8 USB_8-
3 2 21 SPI_DI_MCP D3 GPIO_8/SPI_DI USB8_N T5 24 USB_8- 3 4
SPI_DO_MCP D4 GPIO_9/SPI_DO USB_9 5 6
C 21,22 SPI_DO_MCP 24 USB_9 C
10K-06(2-3) SPI_CS_MCP E4 GPIO_10/SPI_CS USB9_P T8 USB_9 USB_9- 7 8
21 SPI_CS_MCP SPI_CLK_MCP USB_9- 24 USB_9- RN47 15K-8P4R
21 SPI_CLK_MCP E3 GPIO_11/SPI_CLK USB9_N T7
RJ6
D5 RESERVED VCC3_DUAL USB_10 1 2
E5 USB_10- 3 4
1 SPI_CLK_MCP
RESERVED
USB_11
3 2 USB_OC0*/GPIO25 P7 1 2 5 6
USB_OC1*/GPIO26 P8 R71 10K-04 USB_11- 7 8
10K-06(1-2) USB_OC2*/GPIO27 P9 RN48 15K-8P4R
USB_OC3*/GPIO28/MGPIO1 P5
MCP61 SPI CLK STRAP MCP68 SPI CLK STRAP USB_OC4*/GPIO29 P6
SR6
SPI_DO | SPI_CLK SPI_DO | SPI_CLK USB_RBIAS_GND T9 USB_RBIAS_GND 1 2

GPIO6：HI--Pseudo S3 00 = 500KHZ 00 = 31MHZ 1.1K-1-04-X

01 = 1.8MHZ 01 = 42MHZ
GPIO6：LOW--Real S3 RESERVED H9
10 = 2.5MHZ *10 = 25MHZ AE7 VCC3_DUAL
RESERVED
VCC3_DUAL D2 +3.3V_VBAT *11 = 25MHZ 11 = 1MHZ V5 USB_10 VCC3 VCC3_DUAL
RESERVED
BAT54C-S RESERVED V4 USB_10-
1 VCCRTC1 *DEFAULT *DEFAULT V7 USB_11
RESERVED
3 1 2 V6 USB_11- +3.3V_VBAT
RESERVED
VBAT1 2 R73 49.9K-1-04
1

1
3
5
7
A20GATE/GPIO55 F5 A20GATE
R74 R75 1 A20GATE 22
INTRUDER* K2 2 49.9K-1-04 RN15
B 1K-04 EXT_SMI*/GPIO32 F3 EXT_SMI R76 4.7K-04 2.7K-8P4R-04 B
1

.
CLR_CMOS RI*/GPIO33 H4 RING-
P 2

MC1 C161 SPEAKER RING- 23

1 SPKR C7 SPEAKER 28
10U-08 1U-06 PWRBTN* G4 SIO_PWRON-
SIO_PWRON- 22
2

2
4
6
8
2 SIO_PME-
3 SIO_PME*/GPIO31 F4 SIO_PME- 22
KBRDRSTIN*/GPIO56 A4 SIO_KBRST-
SIO_KBRST- 22
BT
N

SK-CR2032-D H3*1-R SMB_CLK0 C2 SMB_MEM_SCL

SMB_MEM_SDA SMB_MEM_SCL 8
K4 RTC_RST* SMB_DATA0 C1 SMB_MEM_SDA 8
SMB_CLK1/MSMB_CLK D2 SMB_SCL
MEM_VLD SMB_SDA SMB_SCL 19,20,21
J3 MEM_VLD SMB_DATA1/MSMB_DATA E2 SMB_SDA 19,20,21
HT_VLD H3 HT_VLD +3.3V_VBAT K3 +3.3V_VBAT +3.3V_VBAT
30 HT_VLD
R352 4.7K-04 HTVDD_EN J4 MCPVDD_EN BUF_SIO_CLK B5 SIOCLK R82 1 2 22-04 BUF_SIO_CLK
.

22,28,30 SLP_S5- 30 HTVDD_EN BUF_SIO_CLK 22

VCC3_DUAL CPU_VLD J1 CPU_VLD SUS_CLK/GPIO34 E1 R83 1 2 10K-1-04-O
29 CPU_VLD

C162

C163
CPUVDD_EN J2 CPUVDD_EN THERM*/GPIO59 C6 CPU_THERM-
29 CPUVDD_EN CPU_THERM- 22
FP_RESET-
5VSB . R84
RSTBTN*
SLP_S5*
H5
H8 SLP_S5-
FP_RESET- 28
SLP_S5- 22,28,30

2
4.7K-04-O SLP_S3* G8 SLP_S3-
PWRGD_SB SLP_S3- 22
. PWRGD_SB H6

10P-04-O

10P-04-O
R85 MEM_VLD PWRGD G2 MCP61_PWRGD
D

MCP61_PWRGD 22

1
4.7K-04-O FANRPM0/GPIO60 E6
V_DIMM Q2 C164 FANCTL0/GPIO61 D6
G 2N7002-S-O FANCTL1/GPIO62 C5
1U-06-O L8 PKG_TEST THERM_SIC/GPIO48 AH7
S

A SB_CPU_SIC 6 A
F8 TEST_MODE_EN THERM_SID/GPIO49 AF8
C

R86 TESTMODE SB_CPU_SID 6

2

B Q3 I168 VCC3_DUAL
Elitegroup Computer Systems
.

2N3904-S-O R87 R88 C403 <OrgAddr1>

4.7K-04-O 1K-04 1 2 PWRGD_SB
E

15K-04-O PWRGD_SB 22,30 .1U-04 Title

1

C165 MCP61M-M3
2.2U-06-O Size Document Number Rev
2

B
MCP61 AUDIO/USB/MISC 1.0A
Date: Wednesday, August 26, 2009 Sheet 15 of 31
5 4 3 2 1
 5 4 3 2 1

U3H
+1.2V_CORE SM_IC_BGA692_P8MM_25X25

+1.2V_HT
P19
H19
GND
GND
MCP61
SEC 8 OF 8
Diagramas.com.br
GND
GND
M15
AK14
U3G
SM_IC_BGA692_P8MM_25X25 AE11 GND GND P15
D7 GND GND W6
+1.2V_CORE MCP61 L8 16-100-301371 G27 GND GND N19
SEC 7 OF 8 FB-30-S-08 16-100-300143 AB7 GND GND AC8
AK27 +1.2V +1.2V_HT W15 16-100-300170 T15 GND GND N12
AH27 +1.2V +1.2V_HT W16 U2 GND GND N14
D D
AJ27 +1.2V +1.2V_HT W17 P13 GND GND P14
AG26 +1.2V 1280mA AC9 GND GND M14
AG25 +1.2V +1.2V_PEA AK28 +1.2V_PEA N25 GND GND M13
+1.2V_PEA 17
U18 +1.2V +1.2V_PEA AJ28 G26 GND GND U1
AE22 +1.2V +1.2V_PEA AH28 F17 GND GND R9
AE23 +1.2V +1.2V_PEA AG27 F15 GND GND N9
V19 +1.2V +1.2V_PEA AF26 F13 GND GND P12
V18 +1.2V +1.2V_PEA AE25 F11 GND GND D23
U19 +1.2V +1.2V_PEA AD24 MCP61:Mounted 0ohm PULL-LOW F9 GND GND AK30
W19 +1.2V +1.2V_PEA AC23 D25 GND GND H7
W18 +1.2V MCP68:Mounted 10K PULL-HIGH H17 GND GND A30
V15 +1.2V D19 GND GND AB3
U16 +1.2V +1.2V_CORE J17 GND GND K9
T14 +1.2V H13 GND GND F30
W14 +1.2V 60mA AH26 GND GND N8
AB21 +1.2V +1.2V_SP_D V13 AA9 GND GND F7
AC21 +1.2V +1.2V_SP_D W13 AE21 GND GND J21
U14 +1.2V +1.2V_SP_D V14 AE19 GND GND K1
T18 +1.2V +1.2V_SP_D W12 L9 VCC3 AE17 GND GND AB30
U15 +1.2V FB-30-S-08 AE15 GND GND V30
RJ12
R15 +1.2V AE13 GND GND P30
V17 +1.2V 320mA 1 AA8 GND GND K30
V16 +1.2V +1.2V_SP_A W9 +1.2V_SP_A HDCP_ROM_SDATA AF30 GND GND H21
+1.2V_SP_A 17 3 2
C R17 +1.2V +1.2V_SP_A W8 AK22 GND GND AD26 C
T16 +1.2V +1.2V_SP_A V8 0-04(2-3) AG19 GND GND AA25
U17 +1.2V +1.2V_SP_A V9 AK18 GND GND W25
R19 +1.2V +1.2V_SP_A U9 AG15 GND GND U25
MCP68: 10K ohm pull-high C4 GND GND R25
E30 GND GND L25
+1.2V_DUAL D15 GND GND J25
D11 GND GND W27
AB22 +1.2V_PED J6 GND GND N13
AE24 +1.2V_PED +1.2V_DUAL F26 L6 GND GND R27
AD22 +1.2V_PED +1.2V_DUAL F27 N6 GND GND L27
AA22 +1.2V_PED R6 GND GND W23
AC22 +1.2V_PED U6 GND GND U8
VCC3_DUAL N22 GND GND J9
R13 GND GND AE9
M19 GND GND AG7
+3.3V_DUAL L4 AK1 GND GND F25
+3.3V_DUAL J22 J23 GND GND P18
VCC3 R23 GND GND F21
+3.3V_USB_DUAL L3 M18 GND GND F19
+3.3V_USB_DUAL L2 N18 GND GND F29
H15 +3.3V P16 GND GND AK5
J15 +3.3V N15 GND GND R4
AC6 +3.3V
PLACE CAPS CLOSE TO 3.3V_USB_DUAL R18 GND GND V3
B AC5 +3.3V
ISSUES IN THE PAST T13 GND GND W4 B
T17 GND GND AC4
I17 M17 GND GND C28
L23 GND GND T19
P17 GND GND AC13
J11 GND GND AK10
R16 GND GND AF1
A1 GND GND AG4
J13 GND GND R8
M16 GND GND A27
N16 GND GND H11
N17 GND GND D1
AG11 GND GND AC19
N23 GND GND AC17
R14 GND GND E29
T12 GND GND AJ7
R12 GND GND AB4
AC7 GND

I18

A A

<OrgAddr1> Elitegroup Computer Systems

Title
MCP61M-M3
Size Document Number Rev
B
MCP61 PWR/GND 1.0A
Date: Wednesday, August 26, 2009 Sheet 16 of 31
5 4 3 2 1
 5 4 3 2 1

MCP61/8 DECOUPLING/EMI Diagramas.com.br

MCP61 INTERNAL PULL-UP/DWN'S

PLACE ON BACK SIDE PE0_PRSNTX16* 10K PU TO 3.3V

CENTER OF MCP61 PE0_PRSNTX8* 10K PU TO 3.3V
+1.2V_CORE VCC3 +1.2V_CORE

D PE1_PRSNT* 10K PU TO 3.3V D

SC42 PE2_PRSNT* 10K PU TO 3.3V
SC39 C166 C167 C168 SC58 SC59 SC60
SC41 .1U-04-X
1U-06-X 4.7U-08-X .1U-04 .1U-04 .1U-04 .1U-04-X .1U-04-X .1U-04-X
PE1_CLKREQ* 10K PU TO 3.3V

PCI_PME*/GPIO_30 8.2K PU TO 3.3V_DUAL

LPC_AD0 8.2K PU TO 3.3V

LPC_AD1 8.2K PU TO 3.3V
LPC_AD2 8.2K PU TO 3.3V
LPC_AD3 8.2K PU TO 3.3V
LPC_DRQ1/LPC_CS* 8.2K PU TO 3.3V
LPC_DRQ0* 8.2K PU TO 3.3V
LPC_SERIRQ 10K PU TO 3.3V
16 +1.2V_PEA
HDA_SDATA_IN1/GPIO_23/MGPIO_0 10K PD TO GND
HDA_SDATA_IN0/GPIO_22 10K PD TO GND
C188 SC69 C191
SC71 SC70 JTAG_TMS 10K PU TO 3.3V
C193 1U-06 .1U-04-O .1U-04 JTAG_TRST* 10K PD TO GND
10U-08 10U-08 .1U-04 JTAG_TDI 10K PU TO 3.3V
C C
A20GATE 10K PU TO 3.3V
PE_WAKE* 10K PU TO 3.3V_DUAL
EXT_SMI*/GPIO32 10K PU TO 3.3V_DUAL
THERM*/GPIO_59 10K PU TO 3.3V
KBRDRSTIN*/GPIO_58 10K PU TO 3.3V
RI*/GPIO_33 10K PU TO 3.3V_DUAL
SIO_PME*/GPIO_31/MGPIO_2 10K PU TO 3.3V_DUAL
VCC3_DUAL +1.2V_DUAL PWRBTN* 10K PU TO 3.3V_DUAL
16 +1.2V_SP_A RSTBTN* 10K PU TO 3.3V_DUAL

C198 C199 SC68 SC65 C204

C200 C201 SC66 SC67 C207
4.7U-08 .1U-04 .1U-04-X .1U-04-X 1U-06
4.7U-08 .1U-04 .1U-04-X .1U-04-X .1U-04

B B

A A
MCP61 SPI CLK STRAP MCP68 SPI CLK STRAP

SPI_DO | SPI_CLK SPI_DO | SPI_CLK <OrgAddr1> Elitegroup Computer Systems

00 = 500KHZ 00 = 31MHZ Title
01 = 1.8MHZ 01 = 42MHZ
10 = 2.5MHZ *10 = 25MHZ MCP61M-M3
*11 = 25MHZ 11 = 1MHZ Size Document Number Rev
B
*DEFAULT *DEFAULT MCP61 SATA / IDE / CONN 1.0A
Date: Wednesday, August 26, 2009 Sheet 17 of 31
5 4 3 2 1
 5 4 3 2 1

Diagramas.com.br
VCC5 VCC5

2A VGA
CONN-15P3R-BL
R89 R90
D D
6 2.2K-04 2.2K-04
DAC_RED L10 1 2 FB30-06-B VGA_RED 1 11
12 DAC_RED
7
DAC_GREEN L11 1 2 FB30-06-B VGA_GREEN 2 12 VGA_DATA R91 DDC_DATA
12 DAC_GREEN DDC_DATA 12
8 33-04
DAC_BLUE L12 1 2 FB30-06-B VGA_BLUE 3 13 VGA_HSYNC HSYNC
12 DAC_BLUE 08-422-688080

6.8P-04-O

6.8P-04-O

6.8P-04-O
9
4 14 VGA_VSYNC VSYNC
10

1
5 15 VGA_CLK R92
DDC_CLK 12

1
C208 C209 C210 33-04
R93 R94 R95 6.8P-04 6.8P-04 6.8P-04

2
150-1-04 150-1-04 150-1-04

16

17
C212

C213

C214

1
C215 C216 C217 C218

470P-04 12P-04 12P-04 470P-04

2
Close to Connector With 600 mils

Close to Connector
C C

VCC5
VCC5
U16
VCC5 VGA_RED 1 4 VGA_BLUE
2 5
U11 VGA_GREEN 3 6 VGA_HSYNC

1
DAC_HSYNC 1 5 C176
12 DAC_HSYNC

1
2 SRVO5-4 C181
3 4 R97 HSYNC .1U-04

2
0-04 .1U-04

2
74HCT32-5-S
VCC5
VCC5
U12 VCC5
DAC_VSYNC 1 5 U17
12 DAC_VSYNC
B 2 VGA_VSYNC 1 4 VGA_CLK B

1
3 4 R99 VSYNC C177 2 5
0-04 VGA_DATA 3 6
74HCT32-5-S .1U-04

2
SRVO5-4

A A

<OrgAddr1> Elitegroup Computer Systems

Title
MCP61M-M3
Size Document Number Rev
B
VGA 1.0A
Date: Wednesday, August 26, 2009 Sheet 18 of 31
5 4 3 2 1
 5 4 3 2 1

PCIEX16
VCC3 +12V CONN_R +12V VCC3
VCC3_DUAL
Diagramas.com.br
B1 +12V
PCI_EXPRESS_X16 PRSNT1* A1
B2 +12V +12V A2
B3 +12V +12V A3 VCC12_PE1
B4 GND GND A4
SMB_SCL B5 SMCLK TCK A5
15,20,21 SMB_SCL
SMB_SDA B6 SMDAT TDI A6
D 15,20,21 SMB_SDA D
B7 GND TDO A7
B8 +3.3V TMS A8 PCIE_RST1
B9 TRST* +3.3V A9
B10 +3.3V_AUX +3.3V A10
PE_WAKE- B11 WAKE* PERST* A11 PE_RESET-
11,21 PE_WAKE- PE_RESET- 11,21
1 2
PE0_TX_P[15..0] R134 10K-04 B12 RSVD GND A12
11 PE0_TX_P[15..0]
B13 GND X1 CONNECTOR REFCLK+ A13 PE0_REFCLK
PE0_TX_N[15..0] PE0_REFCLK 11
PE0_TX_P0 C267 .1U-04 PETP0 B14 PETP0 REFCLK- A14 PE0_REFCLK-
11 PE0_TX_N[15..0] PE0_REFCLK- 11 PE0_RX_P[15..0]
PE0_TX_N0 C266 .1U-04 PETN0 B15 PETN0 GND A15
PE0_RX_P0 PE0_RX_P[15..0] 11
B16 GND PERP0 A16
PE0_PRSNTX1- B17 PRSNT2* PERN0 A17 PE0_RX_N0 PE0_RX_N[15..0]
11 PE0_PRSNTX1- PE0_RX_N[15..0] 11
B18 GND GND A18

PE0_TX_P1 C268 .1U-04 PETP1 B19 PETP1 RSVD A19

PE0_TX_N1 C269 .1U-04 PETN1 B20 PETN1 X4 CONNECTOR GND A20
B21 GND PERP1 A21 PE0_RX_P1
B22 GND PERN1 A22 PE0_RX_N1
PE0_TX_P2 C270 .1U-04 PETP2
R155 PE0_TX_N2 C271 .1U-04 PETN2
B23
B24
PETP2
PETN2
GND
GND
A23
A24
Place close to PCI EXPRESS connector as possible.
0-04-O B25 GND PERP2 A25 PE0_RX_P2
B26 GND PERN2 A26 PE0_RX_N2 +12V for 16X
PE0_TX_P3 C272 .1U-04 PETP3 B27 PETP3 GND A27
PE0_TX_N3 C273 .1U-04 PETN3 B28 PETN3 GND A28
C C
B29 GND PERP3 A29 PE0_RX_P3

1
B30 RSVD PERN3 A30 PE0_RX_N3
B31 PRSNT2* GND A31 EC11 CI16
11 PE0_PRSNTX4-
B32 GND RSVD A32 470u-16D8H11E-O .1U-04

2
VCC3 for 16X
PE0_TX_P4 C274 .1U-04 PETP4 B33 PETP4 RSVD A33
PE0_TX_N4 C275 .1U-04 PETN4 B34 PETN4 X8 CONNECTOR GND A34
B35 GND PERP4 A35 PE0_RX_P4

1
B36 GND PERN4 A36 PE0_RX_N4 VCC3_DUAL
PE0_TX_P5 C276 .1U-04 PETP5 B37 PETP5 GND A37 for 16X EC12 CI17
PE0_TX_N5 C277 .1U-04 PETN5 B38 PETN5 GND A38 1000U-6V3D8H11.5E .1U-04

2
R153 B39 GND PERP5 A39 PE0_RX_P5
0-04-O B40 GND PERN5 A40 PE0_RX_N5

1
PE0_TX_P6 C278 .1U-04 PETP6 B41 PETP6 GND A41
PE0_TX_N6 C279 .1U-04 PETN6 B42 PETN6 GND A42 EC13 CI18
B43 GND PERP6 A43 PE0_RX_P6 100u-16D6.3H11EG-LU-O .1U-04

2
B44 GND PERN6 A44 PE0_RX_N6
PE0_TX_P7 C280 .1U-04 PETP7 B45 PETP7 GND A45
PE0_TX_N7 C281 .1U-04 PETN7 B46 PETN7 GND A46
B47 GND PERP7 A47 PE0_RX_P7
B48 PRSNT2* PERN7 A48 PE0_RX_N7
11 PE0_PRSNTX8-
B49 GND GND A49

B PE0_TX_P8 C282 .1U-04 PETP8 B50 PETP8 RSVD A50 B

PE0_TX_N8 C283 .1U-04 PETN8 B51 PETN8 X16 CONNECTOR GND A51
B52 GND PERP8 A52 PE0_RX_P8
B53 GND PERN8 A53 PE0_RX_N8
PE0_TX_P9 C286 .1U-04 PETP9 B54 PETP9 GND A54
PE0_TX_N9 C287 .1U-04 PETN9 B55 PETN9 GND A55
B56 GND PERP9 A56 PE0_RX_P9
B57 GND PERN9 A57 PE0_RX_N9
PE0_TX_P10 C288 .1U-04 PETP10 B58 PETP10 GND A58
PE0_TX_N10 C289 .1U-04 PETN10 B59 PETN10 GND A59
B60 GND PERP10 A60 PE0_RX_P10
B61 GND PERN10 A61 PE0_RX_N10
PE0_TX_P11 C290 .1U-04 PETP11 B62 PETP11 GND A62
PE0_TX_N11 C291 .1U-04 PETN11 B63 PETN11 GND A63
R152 B64 GND PERP11 A64 PE0_RX_P11
0-04-O B65 GND PERN11 A65 PE0_RX_N11
PE0_TX_P12 C292 .1U-04 PETP12 B66 PETP12 GND A66
PE0_TX_N12 C293 .1U-04 PETN12 B67 PETN12 GND A67
B68 GND PERP12 A68 PE0_RX_P12
B69 GND PERN12 A69 PE0_RX_N12
PE0_TX_P13 C294 .1U-04 PETP13 B70 PETP13 GND A70
PE0_TX_N13 C295 .1U-04 PETN13 B71 PETN13 GND A71
B72 GND PERP13 A72 PE0_RX_P13
B73 GND PERN13 A73 PE0_RX_N13
A PE0_TX_P14 C296 .1U-04 PETP14 B74 PETP14 GND A74 A
PE0_TX_N14 C297 .1U-04 PETN14 B75 PETN14 GND A75
B76 A76 PE0_RX_P14
B77
GND
GND
PERP14
PERN14 A77 PE0_RX_N14 <OrgAddr1> Elitegroup Computer Systems
PE0_TX_P15 C298 .1U-04 PETP15 B78 PETP15 GND A78
PE0_TX_N15 C299 .1U-04 PETN15 B79 PETN15 GND A79 Title
B80 A80 PE0_RX_P15
11 PE0_PRSNTX16- B81
GND
PRSNT2*
PERP15
PERN15 A81 PE0_RX_N15 MCP61M-M3
B82 RSVD GND A82 Size Document Number Rev
B
I1 PCI-E X16 CONN 1.0A
Date: Wednesday, August 26, 2009 Sheet 19 of 31
5 4 3 2 1
 1 2 3 4 5 6 7 8

VCC3 VCC3_DUAL

Diagramas.com.br

1
13 CBE-[0..3]
CBE-[0..3]
AD[0..31]
+ EC14
1000U-6V3D8H11.5E-O
+ EC15
1000U-6V3D8H11.5E
PCI Slot 1 & 2
13 AD[0..31]

2
VCC5 VCC5 VCC5 VCC5

A A
-12V +12V -12V +12V
VCC3 VCC3 VCC3
PCI1 VCC3 PCI2

B1 -12V TRST# A1 B1 -12V TRST# A1

B2 TCK +12V A2 B2 TCK +12V A2
B3 A3 TMS B3 A3 TMS
GROUND TMS TDI GROUND TMS TDI
B4 TDO TDI A4 B4 TDO TDI A4
B5 +5V +5V A5 B5 +5V +5V A5
B6 A6 PCI_INTW- B6 A6 PCI_INTX-
+5V INT#[A] PCI_INTW- 13 +5V INT#[A]
PCI_INTX- B7 A7 PCI_INTY- PCI_INTY- B7 A7 PCI_INTZ-
13 PCI_INTX- INT#[B] INT#[C] PCI_INTY- 13 INT#[B] INT#[C]
PCI_INTZ- B8 A8 PCI_INTW- B8 A8
13 PCI_INTZ- INT#[D] +5V INT#[D] +5V
B9 PRSNT#[1] RESERVED3 A9 B9 PRSNT#[1] RESERVED3 A9
B10 A10 VCC3_DUAL B10 A10 VCC3_DUAL
RESERVED1 +5V(I/O) RESERVED1 +5V(I/O) PCI_CLKSLOT2
B11 PRSNT#[2] RESERVED4 A11 B11 PRSNT#[2] RESERVED4 A11

1
B12 A12 B12 A12 CI19
GROUND GROUND GROUND GROUND
B13 GROUND GROUND A13 B13 GROUND GROUND A13
B14 A14 B14 A14 10P-04

2
RESERVED2 3.3V_AUX RESERVED2 3.3V_AUX
B15 GROUND RST# A15 PCIRST_SLOT1- 13 B15 GROUND RST# A15 PCIRST_SLOT2- 13
PCI_CLKSLOT1 B16 A16 PCI_CLKSLOT2 B16 A16
13 PCI_CLKSLOT1 CLK +5V(I/O) PCI_GNT0- 13 PCI_CLKSLOT2 CLK +5V(I/O) PCI_GNT1-
B17 GROUND GNT# A17 PCI_GNT0- 13 B17 GROUND GNT# A17 PCI_GNT1- 13
PCI_REQ0- B18 A18 PCI_REQ1- B18 A18
13 PCI_REQ0- REQ# GROUND PME- 13 PCI_REQ1- REQ# GROUND PME-
B19 +5V PME# A19 PME- 13 B19 +5V PME# A19
AD31 B20 A20 AD30 AD31 B20 A20 AD30
AD29 AD[31] AD[30] AD29 AD[31] AD[30]
B21 AD[29] +3.3V A21 B21 AD[29] +3.3V A21
B22 A22 AD28 B22 A22 AD28
AD27 GROUND AD[28] AD26 AD27 GROUND AD[28] AD26
B23 AD[27] AD[26] A23 B23 AD[27] AD[26] A23
AD25 B24 A24 AD25 B24 A24
AD[25] GROUND AD24 R140 AD[25] GROUND AD24 R141
B25 +3.3V AD[24] A25 B25 +3.3V AD[24] A25
PCI_CLKSLOT1 CBE-3 B26 A26 1 2 AD21 CBE-3 B26 A26 1 2 AD22
C/BE#[3] IDSEL C/BE#[3] IDSEL
1

B CI20 AD23 AD23 B

B27 AD[23] +3.3V A27 B27 AD[23] +3.3V A27
B28 A28 AD22 100-04 B28 A28 AD22 100-04
10P-04 AD21 GROUND AD[22] AD20 AD21 GROUND AD[22] AD20
B29 A29 B29 A29
2

AD19 AD[21] AD[20] AD19 AD[21] AD[20]

B30 AD[19] GROUND A30 B30 AD[19] GROUND A30
B31 A31 AD18 B31 A31 AD18
AD17 +3.3V AD[18] AD16 AD17 +3.3V AD[18] AD16
B32 AD[17] AD[16] A32 B32 AD[17] AD[16] A32
CBE-2 B33 A33 CBE-2 B33 A33
C/BE#[2] +3.3V FRAME- C/BE#[2] +3.3V FRAME-
B34 GROUND FRAME# A34 FRAME- 13 B34 GROUND FRAME# A34
IRDY- B35 A35 IRDY- B35 A35
13 IRDY- IRDY# GROUND TRDY- IRDY# GROUND TRDY-
B36 +3.3V TRDY# A36 TRDY- 13 B36 +3.3V TRDY# A36
DEVSEL- B37 A37 DEVSEL- B37 A37
13 DEVSEL- DEVSEL# GROUND STOP- DEVSEL# GROUND STOP-
B38 GROUND STOP# A38 STOP- 13 B38 GROUND STOP# A38
PLOCK- B39 A39 PLOCK- B39 A39
PERR- LOCK# +3.3V PERR- LOCK# +3.3V
13 PERR- B40 PERR# RESERVED5 A40 SMB_SCL 15,19,21 B40 PERR# RESERVED5 A40 SMB_SCL 15,19,21
B41 +3.3V RESERVED6 A41 SMB_SDA 15,19,21 B41 +3.3V RESERVED6 A41 SMB_SDA 15,19,21
SERR- B42 A42 SERR- B42 A42
13 SERR- SERR# GROUND PAR SERR# GROUND PAR
B43 +3.3V PAR A43 PAR 13 B43 +3.3V PAR A43
CBE-1 B44 A44 AD15 CBE-1 B44 A44 AD15
AD14 C/BE#[1] AD[15] AD14 C/BE#[1] AD[15]
B45 AD[14] +3.3V A45 B45 AD[14] +3.3V A45
B46 A46 AD13 B46 A46 AD13
AD12 GROUND AD[13] AD11 AD12 GROUND AD[13] AD11
B47 AD[12] AD[11] A47 B47 AD[12] AD[11] A47
AD10 B48 A48 AD10 B48 A48
AD[10] GROUND AD9 AD[10] GROUND AD9
B49 GROUND AD[9] A49 B49 GROUND AD[9] A49

AD8 B52 A52 CBE-0 AD8 B52 A52 CBE-0

AD7 AD[8] C/BE#[0] AD7 AD[8] C/BE#[0]
B53 AD[7] +3.3V A53 B53 AD[7] +3.3V A53
B54 A54 AD6 B54 A54 AD6
AD5 +3.3V AD[6] AD4 AD5 +3.3V AD[6] AD4
B55 AD[5] AD[4] A55 B55 AD[5] AD[4] A55
AD3 B56 A56 AD3 B56 A56
AD[3] GROUND AD2 AD[3] GROUND AD2
B57 GROUND AD[2] A57 B57 GROUND AD[2] A57
C AD1 B58 A58 AD0 AD1 B58 A58 AD0 C
AD[1] AD[0] AD[1] AD[0]
B59 +5V(I/O) +5V(I/O) A59 B59 +5V(I/O) +5V(I/O) A59
PACK64-1 B60 A60 PREQ64-1 PACK64-2 B60 A60 PREQ64-2
ACK64# REQ64# ACK64# REQ64#
B61 +5V +5V A61 B61 +5V +5V A61
B62 +5V +5V A62 B62 +5V +5V A62

PCI-W PCI-W

AD21 WXYZ VCC3 AD22 XYZWVCC5 VCC3_DUAL

2
CI21 CI24 CI26

1U-06-O 1U-06-O 1U-06-O

1
VCC3
RN22 VCC3 RN24 VCC3
8.2K-8P4R 8.2K-8P4R
STOP- 2 1 FRAME- 2 1 R142 8.2K-04
PLOCK- 4 3 IRDY- 4 3 PCI_INTZ- 1 2
PERR- 6 5 TRDY- 6 5
SERR- 8 7 DEVSEL- 8 7 PCI_REQ1- 1 2
R143 8.2K-04 VCC3
RN18
8.2K-8P4R
D TMS 2 1 PACK64-2 2 1 2 1 PCI_INTW- 2 1 D
TDI 4 3 PREQ64-2 4 3 4 3 PCI_INTY- 4 3
13 LANREQ-
PCI_INTX- 6 5 PREQ64-1 6 5 6 5 6 5
13 PCI_REQ4-
PCI_REQ0- 8 7 PACK64-1 8 7 8 7 8 7
13 1394REQ-
RN23 RN25 RN29
8.2K-8P4R 8.2K-8P4R 8.2K-8P4R Elitegroup Computer Systems
MCP61M-M3
Title

Size Document Number Rev

Custom PCI 1 & 2 1.0A
Date: Wednesday, August 26, 2009 Sheet 20 of 31
1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

VCC3_DUAL
+12V
Diagramas.com.br
2

2
VCC3 CI27 BC2
2
BC3 .1U-04-O 1u-16VX-06

1
CI28 1
2 2
.1U-04-O 1U-06 CI29 BC4
1 R154
10K-04 PCIEX1 .1U-04-O 1U-06
A 1 1 A
B1 +12v PRSNT1# A1
B2 +12v +12V A2
B3 +12v +12V A3
B4 GND GND A4
SMB_SCL B5 A5
15,19,20 SMB_SCL SMCLK JTAG2
SMB_SDA B6 A6
15,19,20 SMB_SDA SMDAT JTAG3
B7 GND JTAG4 A7
B8 +3.3V JTAG5 A8
B9 JTAG1 +3.3V A9
B10 3.3Vaux +3.3V A10
PE_WAKE- B11 A11 PE_RESET-
11,19 PE_WAKE- WAKE# PERST# PE_RESET- 11,19
KEY
B12 RSVD GND A12
B13 A13 PE2_REFCLK
GND REFCLK+ PE2_REFCLK 12
C300 .1U-04 B14 A14 PE2_REFCLK-
12 PE2_TX_P PETp0 REFCLK- PE2_REFCLK- 12
C301 .1U-04 B15 A15
12 PE2_TX_N PETn0 GND
B16 GND PERp0 A16 PE2_RX_P 12
PE2_PRSNT- B17 A17
12 PE2_PRSNT- PRSNT2# PERn0 PE2_RX_N 12
B18 GND GND A18

PCIEX-36P-W

B
SO8 MN and MW co-layout layout draw B

VCC3_DUAL VCC3_DUAL
ROM2 SMT
SPI_CS 1 8 R69
SPI_DO CE# VCC HOLD-
2 7

.
-WP_ROM SO HOLD# SPI_CLK
3 WP# SCK 6
4 5 SPI_DI 4.7K-04
150 mil 208 mil GND SI

SPI-ROM-S-4M-O
01-530-004110

208mil width

VCC3_DUAL
ROM1 DIP
SPI_CS 1 8
SPI_DO SPI_DO CE# VCC HOLD-
SPI_DI_MCP 15 2 SO HOLD# 7
-WP_ROM 3 6 SPI_CLK
SPI_DI WP# SCK SPI_DI
SPI_DO_MCP 15,22 4 GND SI 5

SPI_CLK SPI_CLK_MCP 15 SPI-8D

SPI_CS 01-510-008080 SPI-ROM-D-8M
SPI_CS_MCP 15
AM2+ Co-lay
-WP_ROM -WP_ROM 22

C C

for SPI ROM

U3(104)

For 104 CLR_CMOS1(1-2)

SPI_ROM_D(104) USBPWR_R(1-2)

SPI-ROM-D-8M
JP-Y
JP-R

BT(104)
USBPWR_F(1-2) HS-37X37X13-SL
For 103 +
X1(wire) KTS
LITHIUM BATTERY
CD2032
JP-Y
D JP-WI-P6.25 D
CR2032

Elitegroup Computer Systems

MCP61M-M3
Title

Size Document Number Rev

Custom PCI-E X1/SPI 1.0A
Date: Wednesday, August 26, 2009 Sheet 21 of 31
1 2 3 4 5 6 7 8
 5 4 3 2 1

ACPI
Temperature Monitor RSMRST-
5VSB
SIOPME
SIO_PME- 15
PS_PWRGD
Diagramas.com.br SLP_S5-
SLP_S5- 15,28,30

2
C122 2200P-04-O PSON- SLP_S3-
SLP_S3- 15
SYSTMP 1 2 SLP_S3- R240
BTN_OUT 10K-04 PS_PWRGD
MCP61_PWRGD 15
RT1 NTC-10K-1-06 +3.3V_VBAT 1 2 COPEN- IO_PWRBTN- R105 0-04-O PSON-
SIO_PSON- 28

1
ER58 10K-1-04 R98 2M-04 SIOPME IO_PWRBTN- 1 2 PWRBTN- PWOK
PWRBTN- 28,30 PWRGD_PS 28

t
SIOVREF 1 2 HM_AGND FB23 0-06-SH PWOK IO_PWRBTN-
IO_PWRBTN- 30
2 1 HM_AGND SLP_S5- BTN_OUT
SIO_PWRON- 15
BC90 1 2 1U-06 SYSTMP
CPUTMP RSMRST- 1 2
DEL R253 PWRGD_SB 15,30
ER59 15K-1-04-O C320 2200P-04 SIOVREF R106 0-04
D D
1 2 1 2 RSTPCI1
CPU_THERMDC 6
VIN2 OVT-
CPU_THERM- 15
CPUTMP VIN1 PMCLK ACPILED
CPU_THERMDA 6 SUSLED 28
VIN0 PMDAT PWRLED
PWRLED 28
KBCLK
KBDAT
VCC5 VCC VCC3 3VSB
SLCT OVT- S3_SW
-3VSBSW 30
FAN Ctrol PE EX_GPIO_3

FAN_TAC1 CASE
BUSY PWRLED
LPC
28 FAN_TAC1 FAN_CTL1 COPEN- 1 LAD0
1

102
101
100
28 FANPWM1 LAD1 LAD[0..3]
IO

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
2 2 LPC_AD[0..3] 13

1
FAN_TAC2 BC29 LAD2
28 FAN_TAC2 FAN_CTL2 1000P-04-O H2*1-P-BL LAD3

BUSY
PE

VCC
VIN1(Vcore)

AGND(D-)

PWSOUT#/GPIO27

ATXPG_IN/GPIO24

GND

KCLK
MCLK
MDATA

KDATA
VSB

GPIO16/LED_VCC
SLCT

VREF
D1+(CPU)

D3+(System)
VIN2
VIN3
VIN4
VIN5
VIN6

D2+

COPEN#
VBAT
RSMRST#/GPIO33
PWOK/GPIO32
PS_ON#/GPIO31
S3#/GPIO30

PWSIN#/GPIO26
PME#/GPIO25

S5#/GPIO23/RSTCON#
PCIRST3#/GPIO22
PCIRST2#/GPIO21
PCIRST1#/GPIO20

OVT#
GPIO17
28 FANPWM2

2
COM SIOPCIRST-
PCIRST_SIO- 13
RI-A LFRAME-
23 -RIA LPC_FRAME- 13
DCD-A LPC_CLK0
23 -DCDA LPCCLK_SIO 13
SOUTA SIRQ
23 TXDA LPC_SERIRQ 13
SINA LDRQ-
23 RXDA LPC_DRQ0- 13
DTR-A
23 -DTRA
RTS-A
23 -RTSA
DSR-A ACK- 103 64 ACPILED
23 -DSRA ACK# GPIO15/LED_VSB/ALERT#
CTS-A SLIN- 104 63
23 -CTSA SLIN# GPIO14/FWH_DIS/WDTRST#/SPI_CS1#
INIT 105 62
ERR- INIT# GPIO13/SPI_MOSI/BEEP
106 ERR# GPIO12/SPI_MISO/FANCTL1_1 61

C
LPT AFD-
STB-
107
108
AFD# GPIO11/SPI_CS0 60
59
Open Drain 3VSB VCC3 C
ERR- PD0 STB# GPIO10/SPI_CLK RN3 1K-8P4R
23 -LPT-ERR 109 PD0 PECI/AMDSI_DAT 58
ACK- PD1 110 57 RSMRST- 1 2
23 -LPT-ACK PD1 AMDSI_CLK
BUSY PD2 111 56 S3_SW 3 4
23 LPT-BUSY PD2 ST1/GPIO03/WDTRST#
PE PD3 112 55 RSTPCI1 5 6
23 LPT-PE PD3 ST2/SLOTOCC#/GPIO02
SLCT PD4 113 54 DISABLE_EUP_IO OVT- 7 8

F71862FG
23 LPT-SLCT PD4 GPIO01 DISABLE_EUP_IO 30
23 -LPT-STB STB- PD5 114 53
AFD- PD6 PD5 GPIO00
23 -LPT-AFD 115 PD6 VIDOUTD 52
INIT PD7 116 51 3VSB
23 -LPT-INIT PD7 VIDOUTC
23 -LPT-SLIN SLIN- 117 50 RN1 1K-8P4R
PD[0..7] DCD-A GND VIDOUTB PS_PWRGD
23 LPT-D[0..7] 118 DCD1# VIDOUTA 49 1 2
PD0 RI-A 119 48 BTN_OUT 3 4
PD1 CTS-A RI1# GND SIOPME
120 CTS1# GPIO45 47 5 6
PD2 DTR-A 121 46 -WP_ROM -WP_ROM 21 S3_SW 7 8
PD3 RTS-A DTR1#/FAN60_100 GPIO44
122 RTS1# VIDIND 45
PD4 DSR-A 123 44 RN2 4.7K-8P4R
PD5 SOUTA DSR1# VIDINC PWRLED
124 SOUT1/Config4E_2E VIDINB 43 1 2
PD6 SINA 125 42 ACPILED 3 4
PD7 SIN1 VIDINA GA20
126 DCD2# GA20 41 15,21 SPI_DO_MCP 5 6
SIOKBRST

DTR2#/FWH_TRAP
127 40 7 8

SOUT2/SPI_TRAP
RI2# KBRST#

FANCTL3/GPIO41
SIO24M SIO24M

RTS2#/PWM_DC
128 39
Voltage Monitor

FANIN3/GPIO40
15 BUF_SIO_CLK CTS2# CLKIN

IRRX/GPIO43
IRTX/GPIO42
KB/MS VCORE V_DIMM VCC

DSKCHG#
DENSEL#

FANCTL1

FANCTL2

LRESET#
WGATE#
WDATA#

RDATA#

LFRAM#
HDSEL#
GPIO

SERIRQ

PCICLK
INDEX#

FANIN1

FANIN2
DRVA#

LDRQ#
DSR2#

STEP#

TRK0#
MOA#

WPT#
KBCLK VCC3

LAD0
LAD1
LAD2
LAD3
DIR#
SIN2

GND
VCC

VCC
23 KCLK
1

KBDAT RJ13
23 KDATA
23 MCLK
PMCLK ER60 ER62 ER63 01-210-862520 1
PMDAT 10K-1-04 10K-1-04 200K-1-04 EX_GPIO_1 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
23 MDATA
15 SIO_KBRST-
SIOKBRST GPIO41/EX_GPIO_1 3
2

B VCC3 B
15 A20GATE
GA20 High-W/LPT
DTR-B Low-WO/LPT 4.7K-04(2-3)
VIN0 RTS-B VCC3
VIN1 VCC3 SOUT-B RJ14
VIN2 LPC_CLK0 1
LAD3 EX_GPIO_2 2
1

* HM_VIN0 for VCORE LAD2 GPIO42/EX_GPIO_2 3

Power On Strap. ER61 ER64
100K-1-04-O 47K-04
RWC-
MO-A
LAD1
LAD0
High-W/IR
4.7K-04(2-3)
* HM_VIN1 for V_DIMM Low-WO/IR 3VSB
(F71862FG Initial Pull High) DS-A LFRAME-
2

* HM_VIN2 for VCC5 WD- SIRQ RJ15

DIR- LDRQ- 1
R100 1K-04-O STEP- SIOPCIRST- EX_GPIO_3 2
DTR-A 1 2 HEAD- IRRX 3
1 => CPUFAN PWM 50% VCC WE- IRTX
0 => CPUFAN PWM 100% RDATA- EX_GPIO_2 4.7K-04-O
R457 1 2 1K-04 TRK0- EX_GPIO_1
INDEX- R270 1 2 330-04 FAN_CTL2

SOUTA
R101
1
1K-04
2
RN51 8
6
7 1K-8P4R
5
FDD WP-
DSKCHG- FCT1 R244 1 2 330-04
FAN_TAC2
FAN_CTL1
1 => IO Address : 4E 4 3 FAN_TAC1
0 => IO Address : 2E 2 1 FDD LPC_CLK0 SIO24M

1
RWC-
R102 1K-04-O 2 1 BC24 BC25
DTR-B 4 3 10P-04-O 10P-04
1 2

2
1 => SPI ROM Backup Mode INDEX- 6 5
0 => SPI ROM Primary Mode MO-A 8 7
10 9
DS-A 12 11
A A
14 13
R103 1K-04-O
16 15
Please place it near SIO
RTS-B 1 2 DIR-
1 => FAN CTL PWM Mode 18 17 3VSB +3.3V_VBAT VCC3
0 => FAN CTL DAC Mode
STEP-
WD- 20
22
19
21
IR VCC
BC208 .1U-04
WE- 1 2
TRK0- 24
26
23
25 IR Elitegroup Computer Systems
1

1
R104 1K-04-O WP- 1
SOUT-B RDATA- 28 27 MC60 BC28 MC61 BC26 MC62 BC27 Title
1 2 30 29 3 4
1 => SPI Disable HEAD- IRTX 5 6 IRRX .1U-04 .1U-04 .1U-04
10U-08-O 1U-06-O 10U-08-O
MCP61M-M3
2

2
0 => SPI Enable DSKCHG- 32 31
34 33 H3X2-P2E-B-O Size Document Number Rev
H17X2-P5E-W Custom
Place Near To SIO Super I/O (F71862F) 1.0A
Date: Wednesday, August 26, 2009 Sheet 22 of 31
5 4 3 2 1
 5 4 3 2 1

Diagramas.com.br
CI33 .1U-04-O H1 TH8 H2 TH8
VCC5

COM 1
1 2 1 8 1 8
VCC12_COM1 2 7 2 7
+12V CI34 .1U-04-O 3 6 3 6
D 1 2 4 5 4 5 D
U13
D7 P N 1N4148-S 1 20 COM

9
12V VCC VCC5_COM1 5
19 2 NRIA NRIA 9
22 -RIA RA1 RY1 NDTRA NDTRA
22 -DTRA 15 DA2 DY2 6 4
18 3 NCTSA NCTSA 8
22 -CTSA RA2 RY2 NTXDA NTXDA
22 TXDA 13 DA3 DY3 8 3
16 5 NRTSA NRTSA 7
22 -RTSA DA1 DY1
14 7 NRXDA NRXDA 2 10
22 RXDA RA4 RY4 NDSRA NDSRA TH8 TH8
-12V 22 -DSRA 17 RA3 RY3 4 6 11 H3 H4
12 9 NDCDA NDCDA 1 1 8 1 8
22 -DCDA RA5 RY5
2 7 2 7
D8 N P 1N4148-S 10 11 CONN-9P2R-COM 3 6 3 6
-12V GND
4 5 4 5
2

5VSB
Close to IC CI36
75232L-P20S

9
.1U-04-O
1

2
R183
4.7K-04-O

1
RING- 15

C
R180 Q5 Board Edge(PS/2)
NRIA CN1 7 8 180P-8P4C-O 1 2 B 2N3904-S

1
NCTSA 5 6 BC8

2
NDSRA 3 4 10K-04 1000P-04

E
NRTSA 1 2 R181

2
10K-04 13 H5 TH8 H6 TH8
NDTRA CN2 7 8 180P-8P4C-O GND KDT PWR 1 8 1 8

1
C NRXDA 5 6 15 14 2 7 2 7 C
NTXDA 3 1 2 4
3 4 3 6 3 6
NDCDA 1 2 KCK 4 5 4 5
5 6

9
GND MDT PWR
17 16
9 7 8 10
MCK
AUGND AUGND
11 12

Top View

5VSB PSKMVCC
LPT-D[7..0]
22 LPT-D[7..0]
RN31 33-8P4R-O VCC5 RN34 RN36

2
-LPT-INIT 1 2 -NPINIT D13 RN33 4.7K-8P4R-O RN35 4.7K-8P4R-O
22 -LPT-INIT LPT-D2 NPRD2 1N4148-S-O 4.7K-8P4R-O 4.7K-8P4R-O R184 R185
3 4
-LPT-SLIN 5 6 -NSLIN P N LPTVCC 0-08-O 0-08
22 -LPT-SLIN

LPT
LPT-D3 7 8 NPRD3

1
2

8
6
4
2

8
6
4
2

8
6
4
2

8
6
4
2
LPT-D4RN32 1 2 33-8P4R-O NPRD4 CI37 R182

7
5
3
1
LPT-D5 3 4 NPRD5 .1U-04-O 4.7K-04-O
1

B LPT-D6 NPRD6 RN38 CI41 B

5 6
1

7
5
3
1

7
5
3
1

7
5
3
1

7
5
3
1
LPT-D7 7 8 NPRD7 4.7K-8P4R .1U-04
LPT

8
6
4
2
RN37 1 2 33-8P4R-O -NSTB LPT-SLCT
22 -LPT-STB
3 4 -NAFD 22 LPT-SLCT 13
25
PS2
22 -LPT-AFD LPT-D0 NPRD0 LPT-PE
22 LPT-D0 5 6 22 LPT-PE 12
LPT-D1 7 8 NPRD1 24 PSKBM
22 LPT-D1 LPT-BUSY KDATA
22 LPT-BUSY 11 22 KDATA 1 KBDATA
23 2 NC
CN5 1 2 180P-8P4C-O LPT-SLCT -LPT-ACK 10 3
LPT-PE 22 -LPT-ACK GND
3 4 22 4 VCC
5 6 LPT-BUSY NPRD7 9 KCLK 5
22 KCLK KBCLK
7 8 -LPT-ACK 21 6
NPRD6 NC
8 13 HOLE
CN6 1 2 180P-8P4C-O NPRD3 20 14
-NSLIN NPRD5 HOLE
3 4 7 15 HOLE
5 6 NPRD2 19
7 8 -NPINIT NPRD4 6 MDATA 7
22 MDATA MSDATA
18 8 NC
CN7 1 2 180P-8P4C-O NPRD7 NPRD3 5 9
NPRD6 -NSLIN GND
3 4 17 10 VCC
5 6 NPRD5 NPRD2 4 MCLK 11
22 MCLK MSCLK
7 8 NPRD4 -NPINIT 16 12 NC

1
3
5
7
NPRD1 3 16
CN9 HOLE
1 2 180P-8P4C-O NPRD1 22 -LPT-ERR
-LPT-ERR 15 26 CN8 17 HOLE
3 4 NPRD0 NPRD0 2 27 180P-8P4C
5 6 -NAFD -NAFD 14 28 PS2-KB-MS

2
4
6
8
7 8 -LPT-ERR -NSTB 1

C312 1 2 220P-04-O -NSTB CONN-25P2R-LPT-O

A
10-006-025680 A

<OrgAddr1> Elitegroup Computer Systems

Title
MCP61M-M3
Size Document Number Rev
Custom
LPT / COM / PS2 1.0A
Date: Wednesday, August 26, 2009 Sheet 23 of 31
5 4 3 2 1
 1 2 3 4 5 6 7 8

Diagramas.com.br
PSKMVCC R368 0-08
110 mils 2 1 VCC5_DUAL_R

2 1

1
CI44 CI42 F2 FUSE-1.1A-18
.1U-04
.1U-04

2
A A

AUGND2 USBVCC1
100 mils AUGND2 PCB Impedance control
Impedance Trace Width Trace Length Pre-preg
(ohm) (mil) (S/W/S) (inch)
USB * 60 5 (20/5/20) 6 2116
1 VCC0 VCC1 5
15 USB_0-
UDATA0- 2 -DATA0 -DATA1 6 UDATA1-
USB_1- 15 50 4 (50/4/50) 6 1080
UDATA0+ 3 7 UDATA1+
15 USB_0 +DATA0 +DATA1 USB_1 15
4 GND0 GND1 8 42 6 (50/6/50) 6 1080
G1 HOLE1 HOLE3 G3
G2 HOLE2 HOLE4 G4

USBX2

AUGND2 AUGND2 1)Circuit type 1

USBVCC2

USBVCC1 100 mils Layer 1:TOP

U5

1
UDATA0+ 1 4 UDATA1+ Layer 2:PWR

1
2 5 CI43 + EC16
UDATA0- 3 6 UDATA1- 220U-16DE
.1U-04-O Layer 3:GND

2
SRVO5-4
AUGND2
B
Layer 4:BOTTOM B
AUGND2

+1.2V_HT IP Trace on layer 1

3 1 IMPEDANCE_T
4 2 IMPEDANCE_B

J2X2_IP-O Trace on layer 4

VCC5_DUAL_F
R364 0-08
C 2 1 C
120 mils
USBVCC3 2 1

110 mils 110 mils F1 FUSE-1.1A-18

110 mils
1

BC7
1U-06 + EC17
220U-16DE
2

F_USB1 F_USB3 F_USB2

1 VCC VCC 2 1 VCC VCC 2 1 VCC VCC 2

USB_4- 3 4 USB_5- USB_6- 3 4 USB_7- USB_8- 3 4 USB_9-

15 USB_4- USB0- USB1- USB_5- 15 15 USB_6- USB0- USB1- USB_7- 15 15 USB_8- USB0- USB1- USB_9- 15
USB_4 5 6 USB_5 USB_6 5 6 USB_7 USB_8 5 6 USB_9
15 USB_4 USB0+ USB1+ USB_5 15 15 USB_6 USB0+ USB1+ USB_7 15 15 USB_8 USB0+ USB1+ USB_9 15
7 KEY KEY 8 7 KEY KEY 8 7 KEY KEY 8

9 NC GND 10 9 NC GND2 10 9 NC GND 10

H5X2-P9E-Y H5X2-P9E-Y H5X2-P9E-Y

D USBVCC3 USBVCC3 USBVCC3 D

U1 U2 U18
USB_4 1 4 USB_5 USB_6 1 4 USB_7 USB_8 1 4 USB_9
2 5 2 5 2 5
USB_4- 3 6 USB_5- USB_6- 3 6 USB_7- USB_8- 3 6 USB_9-

SRVO5-4 SRVO5-4 SRVO5-4

Elitegroup Computer Systems
MCP61M-M3
Title

Size Document Number Rev

Custom USB Conn. 1.0A
Date: Wednesday, August 26, 2009 Sheet 24 of 31
1 2 3 4 5 6 7 8
 5 4 3 2 1

Diagramas.com.br USBVCC2

LPHYX1 3VSB VDDPHY

LPHYX2
ER1 2.49K-1-04 VDDREG USBLAN
1 2 PHY_RSET 5 1
External Connection REG_PHY RGMII_RXER USBD- 6
VCC
-DATA1
VCC
-DATA0 2 USBC-
LED_1000 USBD+ 7 3 USBC+
D +DATA1 +DATA0 3VSB D
USBVCC2 USBVCC2 8 GND GND 4
VCC3_DUAL 3VSB
LAN
Cm G3 H_USB H_USB G1

48
47
46
45
44
43
42
41
40
39
38
37
AUGND2 G4 H_USB H_USB G2 AUGND2
9

REGOUT/PWOUT12A
GND

VDDREG
VDDREG

AVDD12/PWOUT12D
ENREG/RXER/FXEN
LED2RXDLY/COLMII/SNIB
RSET

CKXTAL2
CKXTAL1
AVDD33

DVDD33
MDI0+ TCT(P01) LINK
10 TX1+ GLED(P11) 19
AUGND2 AUGND2 MDI0- 11 20
3VSB MDI1+ TX1- OLED(P12) ACTIVE
12 TX2+ YLED(P13) 21

2
Pin36 MDI1- 13 TX2- VCC(P14) 22
RGMII_MDC R5 1.5K-04 R4 MDI2+
12 MII_MDC
RGMII_MDIO MDI0+ 1 36 RGMII_CRS 1 2
Cb 0-04 MDI2-
14
15
TX3+ H_LAN G5
G6
12 MII_MDIO MDI[0]+ V12/CRS_RPTR TX3- H_LAN
12 MII_TXD0 RGMII_TXD0 MDI0- 2 35 LED_10_100 MDI3+ 16 G7

1
RGMII_TXD1 VDD10 MDI[0]- LED1/PHYAD1 LED_0 MDI3- TX4+ H_LAN
12 MII_TXD1 3 FB10 LED0/PHYAD0 34 17 TX4- H_LAN G8
12 MII_TXD2 RGMII_TXD2 MDI1+ 4 33 18
RGMII_TXD3 MDI1- MDI[1]+ GND R414 1.5K-04 RCT(P10)
12 MII_TXD3 5 MDI[1]- CLK125 32 Cc

2
12 MII_TXEN RGMII_TXCTL 6 31 RGMII_MDIO 1 2 USBX2-LAN-100
AVDD33 MDIO 3VSB
RGMII_TXCLK 7 30 RGMII_MDC C424 AUGND2
12 MII_TXCLK GND MDC
RGMII_RXCTL MDI2+ RGMII_RST
8 29 Co .01U-04 Cn

1
12 MII_RXDV MDI[2]+ PHYRSTB
12 MII_RXD0
RGMII_RXD0 MDI2- 9 MDI[2]-
RTL8211CL DVDD12 28
RGMII_RXD1 VDD10 10 27 RGMII_TXCTL
12 MII_RXD1 RGMII_RXD2 MDI3+ 11
AVDD12 RTL8201EL TXCTL/TXEN
26 RGMII_TXD3 AUGND2 close to connector

RXCTL/RXDV/RMII
12 MII_RXD2 RGMII_RXD3 MDI3- MDI[3]+ TXD3 RGMII_TXD2
12 MII_RXD3 12 MDI[3]- TXD2 25
RGMII_RXCLK
12 MII_RXCLK

RXD1/TXDLY
LED_1000 3VSB
12 MII_COL

RXD2/AN0
RXD3/AN1
RGMII_CRS C425 1 2 .1U-04-O
12 MII_CRS

DVDD33

DVDD33
RGMII_RST
12 MII_RST-

RXD0

TXD0
TXD1
RGMII_RXER FB25 0-06-SH AUGND2
Ca

GND
RXC

TXC
12 MII_RXER 3VSB
AUGND2 1 2
15 USB_3 USB_C+ FB24 0-06-SH
C 15 USB_3- USB_C- RTL8201EL-GR AUGND2 1 2 C

13
14
15
16
17
18
19
20
21
22
23
24
1
15 USB_2 USB_D+
15 USB_2- USB_D- R415 02-462-201864
4.7K-04-O CMF1
RGMII_TXD1 USB_C+ 8 7 USBC+
2

RGMII_RXCTL RGMII_TXD0 USB_C- 8 7 USBC-

6 6 5 5
When you found some bug, please inform Hook(ext:26161) to RGMII_RXD0 RGMII_TXCLK USB_D+ 4 3 USBD+
4 3
1

update circuit. RGMII_RXD1 USB_D- 2 1 USBD-

R416 RGMII_RXD2 2 1
4.7K-04-O RGMII_RXD3 0-8P4R-SH
RGMII_RXC USBVCC2
2

U6
USBC+ 1 4 USBD+
2 5
USBC- 3 6 USBD-

SRVO5-4
G5

LPHYX1 AUGND2
L1 CK-4.7UD-PT2MM-O VDDPHY
X3 LPHYX2 REG_PHY 1 2
G1

G2

X-25M 1
Strapping

1
2 1 BC209 BC210 BC211
4

.1U-04 .1U-04 .1U-04 MC59 3VSB

GND

D0+

D0-

PWR
2

10U-08-O R21 4.7K-04

3

2
C253 C252 Closed to Closed to Closed to 1 2 Pin34
7

5
8

R417 4.7K-04-O R7 510-04

GND

D1+

D1-

PWR

27P-04 27P-04 Pin48 Pin40 Pin28

1

G3

G4

1 2 LED_0 1 2 LINK
B B
R418 4.7K-04-O
1 2 Pin38
13

17 D3-
15 D2-
G7

11

G8

R419 4.7K-04 R420 4.7K-04 R421 510-04

LED_1000 ACTIVE
TCT

D0- 12

D1- 14

1 2 1 2 1 2
RGMII_RXCLK R451 1 2 22-04 RGMII_RXC

C
10

18
16

2
R422 4.7K-04-O Q52
D0+

D1+

D2+

D3+

RCT

B
BOM Difference C426 C427 1 2 Pin35 2N3904-S
RTL8201EL RTL8211CL 10P-04-O 10P-04-O R423 4.7K-04 R424 4.7K-04

E
1

1
LED_10_100
Location 10/100M 1000M
1 2 1 2
19

20

21

22

Ca RTL8201EL-GR RTL8211CL-GR
GREEN

ORANGE

YELLOW

Cb V X
Cc 1.5K-04 10K-04 Closed to each PWR pin
Cd X V 3VSB
Cd BC212 1 2 .1U-04
Ce BC213 1 2 .1U-04
Strapping Pin13,39 Internal Pull Low VDDPHY BC214 1 2 .1U-04
Cf BC215 1 2 .1U-04
R29 0-04-O 3VSB BC216 1 2 .1U-04
Cg RTL8201EL RTL8211CL RGMII_CRS 1 2 R425 0-06-O BC217 1 2 .1U-04
VDDREG 1 2
Ch Pin13 1: RMII N/A R426 0-04-O
* 0: MII VDD10 1 2 1
Ci Pin[34:35] PHY Address:00H PHY Address:00H C428 C429
1

A .1U-04-O 10U-08-O A
2

Ck Pin36 1: Repeat mode C430 C431 Closed to Closed to

* 0: Disable .1U-04-O .1U-04-O Pin44 Pin45
2

Cm V X Pin38 1: SNI mode N/A Closed to Closed to

* 0: MII/RMII mode Pin10 Pin36
Cn USBX2-LAN-100 USBX2-LAN-1000 Pin39 1: Fiber mode R24 0-04-O

Co .01U-04 0-04 Pin[17:18]

* 0: UTP mode
N/A 11: AUTO Negotiation
RGMII_RXER 1
R427
2
4.7K-04-O
<OrgAddr1> Elitegroup Computer Systems
Pin17 RGMII_RXD2 1 2 Title
R428 4.7K-04-O
Pin18 RGMII_RXD3 1 2 MCP61M-M3
Size Document Number Rev

LAN PHY RTL8201EL&8211CL

Custom
1.0A
Date: Wednesday, August 26, 2009 Sheet 25 of 31
5 4 3 2 1
 5 4 3 2 1

External Connection
Diagramas.com.br
5VSB 5VSB +12V U4 +5VA MIC Bias
78L05-D D26
VCC VCC I O BAT54A-S
VIN VOUT R458 1
1 2 3.3K-04 MIC2_R
MIC2-VREFO 3

GND
+12V +12V

1
C3 2 R452 1 2 3.3K-04 MIC2_L

1
VCC3 VCC3 .1U-04 C2
EC51 .1U-04

G
2
D D
FB21 0-SH 22U-25DE D6
3VSB 3VSB Cf

2
1 2 BAT54A-S
15 HDA_RST- AZ_RST- FB22 0-SH 1 R30 1 2 2.2K-04 LINE2_R
1 2 LINE2-VREFO 3
15 HDA_BITCLK AZ_BIT_CLK AUGND AUGND 2 R61 1 2 2.2K-04 LINE2_L

15 HDA_SYNC AZ_SYNC AUGND MIC1_VREFO-R R453 1 2 2.2K-04 MIC1_R

AZ_SDAIN R33 1 2 0-04

15 HDA_SDIN_0

15 HDA_SDOUT AZ_SDOUT
R32 1 2 3.3K-04 MIC1_L

D27
BAT54A-S-O
1
AGND AUGND AUGND C27 2 1 47P-04-O MIC1_VREFO-L 3
2 R454 1 2 3.3K-04-O MIC1_R
PORT-F 27 MIC2_JD R13 1 2 20K-1-04 VCAP

1
MIC1_VREFO-R C25
R14 1 2 39.2K-1-04 F_SENSE LINE2-VREFO 10U-08-O
Cg
PORT-E 27 LINE2_JD
MIC2-VREFO

2
27 FRONT_L R28 1 2 EC52 2 1 10U-25DE
33-04 MIC1_VREFO-L
27 FRONT_R R22 1 2 EC53 2 1 10U-25DE AUGND
33-04
C4 1 2 10U-08

+5VA
Cd
C AUGND C

1
C5 C6

CODEC
10U-08-O .1U-04

36

35

34

33

32

31

30

29

28

27

26

25

2
PORT-D_R

VrefOut-G
PORT-D_L

SENSE B

VrefOut-D

VrefOut-E

VREF FILT
VrefOut-F

VrefOut-C_L

VrefOut-B_L

AVSS1

AVDD1
AUGND AUGND AUGND

如果空間不足,可將MIC1/MIC2/LINE1的電容改10U-X5R-08
+5VA 37 24 EC54 1 2 10U-25DE LINE1_R LINE1_R 27
VrefOut-A PORT-C_R
38 23 EC55 1 2 10U-25DE LINE1_L LINE1_L 27
AVDD2 PORT-C_L
Cb 39 22 EC23 1 2 10U-25DE MIC1_R
PORT-A_L PORT-B_R MIC1_R 27
ER12 1 2 5.1K-1-04 JDREF 40 21 EC25 1 2 10U-25DE MIC1_L MIC1_L 27
VrefOut-H PORT-B_L
C28 2 1 47P-04-O 41 20 C8 1 2 1U-06 CD-R CD-R 27
AUGND PORT-A_R CD-R
42 19 CDG C9 1 2 1U-06 CD-G CD-G 27
AVSS3 CD-G
43
Ca C10 2 1U-06 CD-L
PORT-G_L VT1705 CD-L 18 1 CD-L 27
44 PORT-G_R
02-301-705620 PORT-F_R 17 EC56 1 2 10U-25DE MIC2_R
MIC2_R 27
45 16 EC57 1 2 10U-25DE MIC2_L
PORT-H_L PORT-F_L MIC2_L 27
B B
46 15 EC58 1 2 100U-16DEL LINE2_R
PORT-H_R PORT-E_R LINE2_R 27
47 14 EC59 1 2 100U-16DEL LINE2_L
S/PDIF IN / EAPD PORT-E_L LINE2_L 27
SPDIFO SENSE-A ER52 2 5.1K-1-04
XO / DVDD_IO
27 SPDIFO 48 13 1 FRONT_JD 27 PORT-D
DVDD_CORE

DVDD_CORE
S/PDIF-OUT SENSE A
ER16 2 10K-1-04

PC_BEEP
1
XI / DVSS

LINE1_JD 27 PORT-C

RESET#
SYNC
DVSS

DVSS
BCLK
ER51 1 2 20K-1-04
SDO MIC1_JD 27 PORT-B

SDI
AUGND

2
Cc C26
1

10

11

12
RJ8 VCC3_CODEC 47P-04-O

1
VCC3 1
2
BOM Difference 3VSB 3
1

C11 AZ_RST- For Normal link : 3.3V (pin2-3)

0-04(2-3) .1U-04
AZ_SYNC
Location ALC662 VT1708B-CE VT1705
2

V_HDA_SEL
Ca ALC662-VC-GRS VT1708B-CE VT1705 V_HDA_SEL VCC3_CODEC
AZ_SDAIN

1
Cb 20K-1-04 5.1K-1-04 5.1K-1-04
AZ_SDOUT AZ_BIT_CLK C12
Cc RJ2(1-2) RJ2(2-3) RJ2(2-3) C13 22P-04-O .1U-04

2
1 2
Cd 2.2K-04 3.3K-04 3.3K-04
A Ce 75-04 16-04 16-04 A

Cf V X V
VT1708BS 02-301-708621 (rev:CD)
Cg X V X
VT1708B-CE 02-301-708623 (rev:CE)
When you change BOM, remember change GPI to inform
BIOS use different Verb-Table.
Elitegroup Computer Systems
Title
MCP61M-M3
Size Document Number Rev

AUDIO VT1705/ALC662 (CHIP)

Custom
1.0A
Date: Wednesday, August 26, 2009 Sheet 26 of 31
5 4 3 2 1
 5 4 3 2 1

Diagramas.com.br

D D

REAR-AUDIO

VCC3_CODEC
FRONT-AUDIO

1
26 LINE1_JD LINE1_JD 3
FB4 0-06-SH R10
LINE1_L 1 2 LINE1_LL
4
2
BLUE Ce 10K-04
26 LINE1_L
FB5 0-06-SH Line In F_AUDIO

2
26 LINE1_R LINE1_R 1 2 LINE1_RR 5 26 MIC2_L 1 2
1 26 MIC2_R 3 4 HDPANEL_DETECT
1

AUDIOA 26 LINE2_R R8 1 2 16-04 5 6 MIC2_JD 26

1
R11 R12 C14 C15 AUDIO-3P-HDA 7
22K-04-O 0-SH-06 100P-04 100P-04 26 LINE2_L R9 1 2 16-04 9 10 LINE2_JD 26
2

2
H5X2-P8E-PU
AUGND AUGND

1
AUGND AUGND AUGND AUGND
26 FRONT_JD FRONT_JD 8 R455 R456 C16 C17 C18 C19
FB6 0-06-SH
FRONT_L 1 2 FRONT_LL
9
7
LIME 22K-04 100P-04-O 100P-04-O
26 FRONT_L

2
FRONT_R
FB7 0-06-SH
FRONT_RR
Line Out 22K-04 100P-04-O 100P-04-O
26 FRONT_R 1 2 10
C 6 AUGND AUGND AUGND AUGND AUGND AUGND C
1

AUDIOB
1

1
R17 R18 C20 C21 AUDIO-3P-HDA
22K-04-O 0-SH-06 100P-04 100P-04
2

CD_IN
SPDIF-OUT
AUGND AUGND AUGND AUGND

26 MIC1_JD MIC1_JD 13
FB8 0-06-SH CD_IN
MIC1_L 1 2 MIC1_LL
14
12
PINK R 1 2 CD-R VCC
26 MIC1_L R CD-R 26
MIC1_R
FB9 0-06-SH
MIC1_RR
Mic In G1 G1 R23 47K-04 CD-G CD-G 26
SPDIFO
26 MIC1_R 1 2 15 G2 G2
11 L 1 2 CD-L CD-L 26 1 SPDIFO 26
L
1

16 R25 47K-04 2
1

1
R19 R20 C22 C23 17 H4*1 C24
22K-04-O 22K-04-O 100P-04 100P-04 AUDIOC 4 100P-04-O
18

1
AUDIO-3P-HDA
2

2
R26 R27 H4X1-P3E-PU
AUGND AUGND AUGND AUGND AUGND

2
100K-04 100K-04

AUGND AUGND

B B

Line in

16 17

12 13 11 14 15 Front out

7 8 9 10
1 6
2 3 4 5 Mic in

TOP VIEW
A A

FRONT VIEW

Elitegroup Computer Systems

Title
MCP61M-M3
Size Document Number Rev

AUDIO VT1705/ALC662 (PANEL)

Custom
1.0A
Date: Wednesday, August 26, 2009 Sheet 27 of 31
5 4 3 2 1
 5 4 3 2 1

VCC3 +MSGLED PWRSW CLR_CMOS CLEAR_CMOS

5VSB VCC5 VCC5 +12V Diagramas.com.br
* 1-2
2-3
NORMAL
CLEAR
-12V VCC3 5VSB VCC5 VCC3_DUAL VCC5 2 4 6 8 5VSB 5VSB

PANEL1
2
PWR
R235 13 3V3 3V3 1 1 3 5 7 9
4.7K-04 14 2
-12V 3V3

2
4
6
8
15 3

1
GND GND
22 SIO_PSON- 16 PS-ON 5V 4 R236 R237 R238 +HDLED RST R239 RN49
17 5 5.6K-1-04 10K-04 180-04 10K-04 330-8P4R
D GND GND D
18 6

1
3
5
7
GND 5V PANEL
1 19 GND GND 7
20 8 HDD_LEDP 1 2 GRN_PWRLED
C352 RES PW-OK PWRGD_PS 22 HDD_LED- YLW_SBLED
21 5V 5VSB 9 14 HDD_LED- 3 4
470P-04-O 22 10 5 6 1 2 PWRBTN-
2

5V 12V PWRBTN- 22,30

23 5V 12V 11 15 FP_RESET- 1 2 7 8 R242 100-04
24 12 9 C353
GND 3.3V

2
R243 .1U-04
ATX-PW-24P2R MC5 33-04 H5X2-P10E-B
1U-06

1
Layout :
Bypass capacitors close to ATX power
connector for EMI solution. F_PANEL

+HDDLED

+MSGLED
1 2
VCC3 VCC5 +12V 5VSB -12V
12V_POWER ATX12V 3 4
1 1 2 2 5 6
1

PWR
RST
BC206 BC204 BC200 BC202 BC205 3 4
3 4
7 8

1
.1U-04 .1U-04 .1U-04 .1U-04 .1U-04 ATX-PW-4P2R
2

C BC201 9 C
.1U-04

2
YLW_SBLED GRN_PWRLED

C
1 2 B Q7 B 1 2
22 SUSLED PWRLED 22
2N3904-S

Speaker R249 R250

E
1K-04 Q8 1K-04
2N3904-S

1
VCC5

D
SPK R258
1 Q9 0-04
1 2N7002-S-O
15 GPIO4 G

2
1
R263 3

S
3 R256
2 1 4 4
33-04 1K-04-O
C

R264 H4X1-P2E-LI

2
1 2 B Q11 C358
15 SPEAKER

D
2N3904-S
1

10K-04 .1U-04-O Q32

E

R268 G 2N7002-S-O
15,22,30 SLP_S5-
1K-04

S
2

B B

+12V VCC5 +12V VCC5

N

N
2

2
D20 D19
R269 1N4148-S-O R271 R254 1N4148-S R252
4.7K-04-O 10K-04-O SYS_FAN 4.7K-04 10K-04
P

P
R260 CPU_FAN
1

1
4 27K-04 4
22 FANPWM2 GPO 22 FANPWM1 GPO
22 FAN_TAC2 1 R78 2 3 SENSE 22 FAN_TAC1 1 2 3 SENSE
+12V 2 +12V +12V 2 +12V
1

27K-04-O 1 1
GND GND
1

C356 C355 C184 R259

1
470P-04-O R77 H3X1-P-W 470P-04 10K-04 EC44 C183 H4X1-P-W
2

10K-04-O .1U-04 22U-25DE

1

1U-06-O

2
A A

Near to IO chip Near to IO chip

Elitegroup Computer Systems
Title
MCP61M-M3
Size Document Number Rev
Custom PWR CON / FNT PNL 1.0A
Date: Wednesday, August 26, 2009 Sheet 28 of 31
5 4 3 2 1
 5 4 3 2 1

External Connection VCORE_VIN

ADD R261 VCORE_PHASE1 VCORE_PHASE2 VCORE_PHASE3
15 CPUVDD_EN
15 CPU_VLD
CPUVDD_EN
CPU_VLD Diagramas.com.br

D
2

2
CPU_VDDNB_FB
6 CPU_VDDNB_FB VCORE
CPU_VDDNB_FB- R499 R502 R503 R208 2.2-06 MF1
6 CPU_VDDNB_FB-
VCORE_UG1 1 2 G MN252-9MS
12V_POWER

1 1

1 1

1 1
CPU_CORE_FB- 1K-04 1K-04 1K-04 L13
6 CPU_CORE_FB-

S
CPU_CORE_FB CPU_PVEN Light_Load-O Normal_Load-O Full_Load-O PIND-0.6UD
6 CPU_CORE_FB
CPU_SVD VCORE_PHASE1 1 2
CPU_PVEN CPU_SVC LED-Yellow LED-Yellow LED-Yellow

D
6 CPU_PVEN

2
CPU_SVD SVID_OK MF2
D 6 CPU_SVD D
CPU_SVC CPUVDD_EN R209 R210 0-06 R211

D
6 CPU_SVC

2
2.2-06 VCORE_LG1 1 2 G MF3 2.2-06

1
MN252-9MS

S
1

2 1
2

2
VCC3 1 2 CPU_VLD G R212
R261 4.7K-04 TP1 VDD R215 R214TP3 TP4 TP5 MN252-9MS 1-04

S
27K-04 C432

2
1
18K-1-04 R213 3300P-04

1
VCC 1 2 SVID_OK 30K-04 C433
R257 100K-04 1u-16VX-06

2
PWM CS_N

43

18

33

31

30

32

29

28

27

26

25

24

48
12V_POWER 12V_POWER

5
VCORE_VIN R216 33K-04
CSP 1 2

VDD

EN

SVIDOK

VID3/SVC

VID2/SVD

VID0/VFIX
VR_HOT

PSI1

PSI3

PSI2

VID5

VID4

VID1/SEL

VCC12
2

R217 R218 20K-04

D
2 D11 ISEN1 1 2
100K-04 CPU_VLD 17 44 VCORE_BOOT1 3 R219 2.2-06 MF4
POK BOOT1 BAT54C-S-O VCORE_UG2 MN252-9MS
1 1 2 G
2 1

2
42 45 VCORE_UG1 L14

S
RT3 TM UG1 C456 PIND-0.6UD
NB_PWM 41 46 VCORE_PHASE1 .1U-X7R-06 VCORE_PHASE2 1 2

1
NB_PWM PH1
NTC-10K-1-06-O
UP6217

D
CPU_VDDNB

2
NB_ISEN 40 47 VCORE_LG1 MF5
1

NB_ISEN LG1 R220 0-06 R221

D
8 ISEN1 VCORE_LG2 1 2 G MF6 2.2-06
ISEN1
2

1
GND 2 D12 MN252-9MS

2 1
R222 4 VCORE_BOOT2 3 G R223
100-04 C434 R224 R429 C435 BOOT2 BAT54C-S-O MN252-9MS
34 1 1-04

S
NB_FB

2
100P-04 0-04 10K-04 1000P-04 3 VCORE_UG2 C436
1

2
CPU_VDDNB_FB UG2 C457 3300P-04
2 1 2 1 2 1 2 1 35

1
NB_COMP VCORE_PHASE2 .1U-X7R-06
C 2 C

1
PH2 CS_N
2 1 2 1 36 NB_FBRTN VCORE_VIN
1 VCORE_LG2
LG2
1

R430 C437 38 C439 R227 33K-04

NB_EAP
1

C4581K-04 33P-04 9 ISEN2 2 1 CSP 1 2

D
C438 33P-04-O ISEN2
37
2

NB_DAC/SS
2

33P-04-O 6 PWM3 D25 .1U-X7R-06 R229 2.2-06 MF7 R230 20K-04

12V_POWER
2

R228 PWM3 BAT54C-S U14 VCORE_UG3 MN252-9MS ISEN2 1

39 NB_IMAX 1 2 G 2
DAC/SS

CPU_VDDNB_FB- 1K-04 10 ISEN3 1

FBRTN

S
PWM4
COMP

ISEN3
2

ISEN4
PGND

L15
IMAX

3 1 8
CSN

CSP
EAP
1

BST DRVH
1

2
R231 PIND-0.6UD
RT
TB

FB

2
100-04 C440 R232 PWM3 2 7 VCORE_PHASE3 1 2
IN SW
33P-04-O UP6217AQGK 02-437-217750 2.2-06

D
1

49

14

15

16

21

22

23

20

19

12

13

11

2
3 6 MF8

1
PWM4 OD PGND R233 0-06 R234

D
2

1
CSP 4 5 VCORE_LG3 1 2 G MF9 2.2-06

GND
R431 CSN VCC DRVL MN252-9MS R432

2 1
2

1
75K-04 G 1-04
1

R433 C444 UP6281 MN252-9MS

S
1

2
1.58K-1-04 1u-16VX-06 02-415-281750 C443

2
VCC5 VCC5 3300P-04
1

1
2

R459 CS_N
2

C442 R434 37.4K-1-04

1

C178 C179 C441 330P-0410K-04 C445

.1U-04 .1U-04 RT4 NTC-10K-1-06-O R241 33K-04
CPU_CORE_FB
1

1
1

.1U-04 .1U-04 1 2 R436 82K-04-O CSP 1 2

2

R435 R437 1K-04-O 1 2 CSP

15.4K-1-04 1 2 R438 20K-04

1
C459 ISEN3 1 2
2

1000P-04 C284
1

B B
R245 C285 C446 R246 510-04 .1U-16VX7-04

2
100-04 33P-04-O 220P-04 CSN 1 2 CS_N
CPU_CORE_FB-
1 1

1
VCC5 VCORE_VIN
C448 R247 R248 C449 VDD C447
100P-04 0-04 10K-04 1000P-04 .1U-X7R-06-O

2
1

C175 C450 2 1 2 1 2 1 2 1 Disable PWM4

2

33P-04-O

D
1

.1U-04 CPU_CORE_FB 2 1 2 1 C327

2

1U-06 R441 R442 0-06 MF10

R440 R439 C451 1K-04 HG4 1 2 G MN252-9MS
CPU_VDDNB
2

100-04 1K-04 33P-04

S
2

L16
1

C452 PWM4 C453 .1U-X7R-06 PIND-0.6UD

56P-04-O 1 2 PHASE4 1 2

2
VCORE

D
MF11 R385
R443 0-06 2.2-06
LG4 1 2 G
VCORE CPU_VDDNB

2 1
D14 BAT54C-S U15 MN252-9MS

S
2
3 1 8 C454
BST DRVH 3300P-04
1

1
1

EC28 EC29 EC30 EC31 EC32 EC33 NB_PWM 2 7

IN SW
+ + + + + +
3 OD PGND 6
R255 2.2-06
2

1 2 4 5 R444 20K-04
GND

12V_POWER VCC DRVL NB_ISEN 1 2

1

A 820U-2.5D-OS-J 820U-2.5D-OS-J 820U-2.5D-OS-J 820U-2.5D-OS-J A

C455 UP6281
VCORE_VIN
9

12V_POWER 820U-2.5D-OS-J 820U-2.5D-OS-J 1u-16VX-06 02-415-281750

2

2 1
1

LL1 EC45 EC46 EC47

Elitegroup Computer System
1

+ + +
RCK-0.9UD MC55 MC56 MC57 MC58 Title
MCP61M-M3
2

Size Document Number Rev

10U-16V-08 10U-16V-08 10U-16V-08 10U-16V-08 Custom 1.0A
270U-16D-OS 270U-16D-OS 270U-16D-OS
Date:
CPU VCORE
Wednesday, August 26, 2009 Sheet 29 of 31
5 4 3 2 1
 5 4 3 2 1

Power for MCP61/68 Core

VREF25 +12V +12V V_DIMM
VCC5 Diagramas.com.br
+1.2V_CORE +1.2V_HT
+1.2V_HT(VLDT)

2
VCC3 R308 VREF25 R163
ER66 R149 68.1-1-04 0-08-O
1K-1-04 Soft Start. 1K-04 1 2 1 2

D
4
U30B +1.2V_CORE CI62 CI63
for 1A@MCP61 / 1.5A@CPU

1
5 Q20 1U-06 1U-06 1 2
+
7 G MN252-20MS
for 0.85A@MCP68 / 1.5A@CPU R164 Reserve for MCP68

C
2

1
03-050-751377 0-08-O
6 - D22 R163.R164

S
ER70 MC64 MC48 BC11 431-S
1K-1-04 4.7U-08 1U-06-O OP324-S 1U-06 R

11

2
1
D D

A
VREF25 +12V +12V V_DIMM

1
EC35

2
1000U-6V3D8H11.5E
VCC3_DUAL ER65 R148
for MCP61/68@10A

2
1K//1K=1.25V 1.24K-1-04 Soft Start. 1K-04

D
4
U30C

1
2
1.24K//1.15K=1.2V 5VSB 10 +
Q19
R315 5VSB 8 G P3055LDG-S

1
Q20=(1.56V-1.25) X 8A = 2.48W 10K-04 9 03-050-705528
-

S
2
ER69 MC47

2
R314 1.15K-1-04 1U-06-O OP324-S +1.2V_HT

11
10K-04 HT_VLD 15 R317

1
10K-04

1
Q31

C
1
+1.2V_HT G 2N7002-S
+3.3V_DUAL for MCP61/68@200mA

1
R316 B

S
2K-04 Q51 EC36

C
1 2 B 2N3904-S 220U-16DE

2
15 HTVDD_EN 1 2 B

1
R165 Q30 ER25 1K-04

E
5VSB 0-08-O VCC3_DUAL C390 2N3904-S Q44

E
U8 1 2 1U-06 2N3904-S

2
I IN OUT O S D
Q23 APM2301ACTRL-S +12V
1

110

4
ER29 U30D
G

1
A 100-04 12
ADJ +
BC12 EC37 14
2

1U-06 100U-16DE 13 -

2
ADJ1086-S
1

180 OP324-S

11
ER30 USB conn./PS2
Vo=1.25(1+Rb/Rt) 169-1-04
VCC5 VCC5
VCC5_DUAL_1 VCC5_DUAL_1
2

C Defaul(1-2) Defaul(1-2) C
VCC5_DUAL_F VCC5_DUAL_R
USBPWR_F USBPWR_R
3VSB
1 1
5VSB 2 2
MCP61 AUX(1.2V) @850mA
G

Q24 3 3
2N7002-S

S D R144
H3X1-B H3X1-B VCC3_DUAL 136mA (Measure)
22 DISABLE_EUP_IO
200K-04

1
U10 5VSB
2 USBPWR_F / R R318 VCC3_DUAL 9173DPSP-S
3 6.98K-1-04 1 VIN 8
22,28 PWRBTN- Vcntl
1 D15 1-2 VCC5 2 GND 7

2
S

BAT54C-S MC30 Vcntl

3 REFEN Vcntl 6
G 1U-06-O 2-3 VCC5_DUAL 4 VOUT 5

GND
+12V Vcntl
Q25 V_DIMM
2N7002-S MC63
C

1
4.7U-08-O

9
Q26 B R319 C392
CD

22 IO_PWRBTN- 2N3904-S 4.02K-1-04 1U-06

R146

2
R145 +12V +1.2V_DUAL
VCC5_DUAL_1 +5V_DUAL FOR USB,PS2
E

2
10K-04 B Q27 10K-04
15,22 PWRGD_SB
2N3904-S
1

RT9202 RT9214
E

MC65 MC31 R404 Q37 R345 10 X

D

10U-08-O 1U-06 4.7K-04 MN252-9MS D30 X V C391 MC54

1
R344 X 30K 1U-06-O 10U-08
2

G R445 R752 24K X Near Pin 4

VCC3_DUAL 1K-04
C

1 2 B Q43 VCC5
R401 4.7K-04 2N3904-S 5VSB+12V VCC5_DUAL_1
VCC3 下版修正
E

5VSB

1
5VSB C173

2
B B
5VSB 5VSB VCC3 VCC3 .1U-04-O R326 D23
10-04-O BAT54C-S L34

1
1

RCK-0.5UD

1
1

R320
D

3
EC38 CI64 CI65 CI66 4.7K-04 5VSB
1U-06 1U-06 1U-06 R322 0-04 Q38
2

1
1000U-6V3D8H11.5E 1 2 G APM2301ACTRL-S C303 R327
VCC3_DUAL 1 2 2 1
C

1
5VSB 24K-04-O
1 2 B Q35 1u-16VX-06 D24

1
R325 4.7K-04 2N3904-S BAT54C-S C396 EC40
1

5
VCC5 U7 C397 10U-08 560U-6.3D-OS
DDR3 = 1.56V

D
E

C402 3 1 1 2

VCC
22 -3VSBSW

2
GND BOOT
2

.01U-04-O .1U-16VX7-04 Q33 V_DIMM

2

C174
UGATE 2 1 2 G MN252-9MS 1pcs [email protected]

2
.1U-04 R328 2.2-06 L35

S
R329 8 1 2 Iocp = R330*40uA-0.4V/Q40@Rds(on)
1

1.05K-1-04 PHASE CK-2.2UD

2
7 2 1 R330/EC2：

1
COMP/OCSET R330 18K-1-04 R331 2 Dimm 18K/1000uF
6 4 2.2-06

D
FB LGATE

1 1
V_DIMM=0.8V*(1+RT/RB) APW7120KE-TRLS Q34
V_DIMM 1 2 G MN252-9MS

1
DDR_VTT 2pcs Dual [email protected] R329 / V_DIMM： R334 0-06 C398

S
1.13K / 1.50V R147 .01U-04

2
1

U9 5VSB 1.05K / 1.56V ** 0-04-O

R332 9173DPSP-S
Memory Power Output Control 1.02K / 1.58V

2
10K-1-04 V_DIMM 1 8 R336 C399
2
VIN Vcntl
7 1K / 1.6V 1 2 1 2
2

GND Vcntl 1K-04-O 4700P-04-O

3 REFEN Vcntl 6
1

4 5 PSON- PWOK SLP_S5- SLP_S3- -3VSBSW

GND

VOUT Vcntl
1 R338 2
EC41 C400 1K-1-04
2

2
1

22U-25DE-O 1U-06 APM2510/2SK4212

9

R337
10K-1-04
C401
.1U-04
S0 0 1 1 1 1 5VSB
Memory Power OCP Rocset (R330) 18KΩ( 40A )
2

A A
2

2
S1 0 1 1 1 1 R339

D
DDR_VTT 4.7K-04-O
1 Q41
G 2N7002-S-O
S3 1 0 1 0 0
C

S
15,22,28 SLP_S5- 2 1 B
MC52 MC53 R340 22K-04-O Q42
Elitegroup Computer Systems
4.7U-08 4.7U-08
S4 1 0 0 0 1 2N3904-S-O <OrgAddr1>
E

Title
MCP61M-M3
S5 1 0 0 0 1 Size Document Number Rev
C DC-DC 1.0A
Date: Wednesday, August 26, 2009 Sheet 30 of 31
5 4 3 2 1
 1 2 3 4 5 6 7 8

Diagramas.com.br
CPU Vcore ATX Power Connector
CPU (ISL6566)
100/133/200 MHz VCCVID 0.8375 ~ 1.55V 12V 3.3V 5V SB5V
CPUCLK * 2
100/133/200 MHz LDO
A A
(2N7002)
VCC3 to +2.5V_VDDA
PCIEX16 Slot
100 MHz
100 MHz
MCP68-S

CPUCLK * 2 DIMM1
PCIEX16CLK Switcher
V_DIMM (RT9214+3023)
VOSCI (VGA) Switch VCC5_DUAL_1 to V_DIMM
DIMM2

B DDR Vtt LDO B

ZCLK (RT9173)
100 MHz SATACLK * 2 3.3V_Dual to 0.9V
AUDIO
MCP68 PCICLK
CODEC
OSCI (Legacy I/O)
USBCLK BIT_CLK BIT_CLK Switcher
+1.2V_CORE
RTCCLK CLK_IN (RT9214+3023)
33 MHz 5V to +1.2V_CORE

33 MHz
33 MHz
33 MHz
25 MHz
LAN
LANCLK

LDO
To MCP68 +1.2V_DUAL
C
(RT9173) C

3.3V_Dual to +1.2V_DUAL

Super I/O
LPCCLK_SIO
BUF_SIO_CLK

VCC_DUAL
To USB & PS2 Keyboard / Mouse 5V Dual
PCI Slot 1, 2 Switch

24 MHz / 14.318 MHz

14.318 MHz
14.318 MHz
D
14.318 MHz D

Elitegroup Computer Systems

32.768 kHz 25 MHz
MCP61M-M3
Title

Clock & Power Distribution

Size Document Number Rev
Custom 1.0A

Date: Wednesday, August 26, 2009 Sheet 31 of 31

1 2 3 4 5 6 7 8