“The Design of XOR GATE Is Based On Quantum Dot Cellular Automata

Technology”
A Thesis Submitted to
CHHATTISGARH SWAMI VIVEKANAND TECHNICAL
UNIVESITY, BHILAI (C.G), India
In partial fulfillment
For the award of the degree
Of
Master of technology
In
Electronics and telecommunication Engineering
Specialization in VLSI Design
By
Aparajita
Enrollment No.:BH031
Roll No.:501406019003
Under the Guidance of
Mr. Ravi Tiwari
Assistant Professor (ETC)
Department of Electronics and Telecommunication Engineering
Faculty of Engineering and technology

Department of Electronics and Telecommunication Engineering

Shri Shankaracharya Technical Campus (FET)
Junwani, P.O. Nehru Nagar Bhilai-490020,Chhattisgarh,India
Session:2019-2021
 DECLARATION BY THE CANDIDATE

I the undersigned solemnly declares that the report of the thesis entitled “The Design of XOR GATE Is Based on
Quantum Dot Cellular Automata Technology” is based on my own carried out during the course of my study under
the supervisor of Mr. Ravi Tiwari, Assistant Professor, Dept. Of Electronics and Telecommunication Engineering,
Shri Shankaracharya Technical Campus(SSTC), SSGI, Bhilai.

I assert that the statement made and conclusions drawn are an outcome of the project work. I further declare that to
the best of my knowledge and belief that the report does not contain any work which has been submitted for the
award of any other degree or certificate in this University of India or any other country. All helps received and
citations used for the preparation of the thesis have been duly acknowledged.

Aparajita
Roll No.: 501406019003
Enrollment No.:BH031
Department of Electronics and Telecommunication
Shri Shankaracharya Technical Campus
Junwani Bhilai, Chhattisgarh

Project Supervisor
Mr. Ravi Tiwari
Assistant Proffesor
Department Of Electronics and Telecommunication
Shri Shankaracharya Technical Campus
Junwani Bhilai, Chhattisgarh

i
 CERTIFICATE BY THE SUPERVISOR

This is to certify that the report of the thesis entitled “The Design of XOR GATE is Based on Quantum Dot
Cellular Automata Technology” is a record of bona fide research work carried out by Aparajita, bearing Roll No.:
501406019003, & Enrollment No.: BH031 under my guidance and supervision for the award of Master of
Engineering, in Electronics & Telecommunication Engineering( Specialization in VLSI) of Chhattisgarh Swami
Vivekanand Technical University, Bhilai(C.G),India.

To the best of my Knowledge the report

i) Embodies the work of the candidate herself,
ii) Has duly been completed,
iii) Fulfills the requirement of the ordinance relating to the MTEC degree of the University and
iv) Is up to the desired standard for the purpose of which is submitted.

Project Supervisor
Mr. Ravi Tiwari
Assistant Professor
Department of Electronics and Telecommunication
Faculty of Engineering and Technology
Shri Shankaracharya Technical Campus
Junwani Bhilai, Chhattisgarh

ii
 DISSERTATION APPROVAL SHEET

Report entitled “The Design of XOR GATE Is Based on Quantum Dot Cellular Automata Technology” by
Aparajita, bearing Roll No.: 501406019003 and Enrollment No.: BH031 for the fulfilment of Master of technology
in Electronics and Telecommunication (Specialization in VLSI Design) is approved and forwarded to Chhattisgarh
Swami Vivekanand Technical University, Bhilai (C.G.), India.

(Signature of the [Link] Incharge) (Signature of the H.O.D)

Mr. Ravi Tiwari Dr. Chinmay Chandrakar
Assistant Professor H.O.D & Associate Professor
Department of ET&T Department of ET&T
Faculty of Engineering and Technology Faculty of Engineering and Technology
Shri Shankaracharya Technical Campus Shri Shankaracharya Technical Campus
Junwani, Bhilai, Chhattisgarh Junwani, Bhilai, Chhattisgarh

Forwarded to Chhattisgarh Swami Vivekanand Technical University, Bhilai(C.G.)

Dr. P. B. Deshmukh
Faculty of Engineering and Technology
Shri Shankaracharya Technical Campus
Junwani, Bhilai, Chhattisgarh

iii
 CERTIFICATE BY THE EXAMINER

This thesis entitled “The Design of XOR GATE is Based on Quantum Dot Cellular Automata Technology”
submitted by Aparajita (Roll No.: 501406019003, Enrollment No.: BH031) has been examined by the undersigned
as a part the examination and here by recommended for the award of degree of master of technology in Very Large
Scale Integration stream in the faculty of Engineering and technology of Chhattisgarh Swami vivekanand technical
university, Bhilai (C.G.) ,India.

Internal examiner External examiner

Date: Date:

iv
 ACKNOWLEDGEMENT

This project report is a product of four semester of learning and dialogues with my project supervisor Mr. Ravi
Tiwari . I sincerely thank him for his numerous suggestions and commend his patience. It was an honor to have him
as my project supervisior.

I am highly thankful to Dr. Chinmay Chandrakar, Head of the Department, Electronics and
Telecommunication Engineering Department and Asst. Prof. Ravi Tiwari, M. Tech. In-charge, for providing me
necessary facilities and co-operation during the course of study.

I am also thankful to all the professors of the department for their support and encouragement. I must
acknowledge the academic resources that I have got from SSTC Bhilai.

Aparajita
[Link] (VLSI Design)
4 Sem. Research Scholar
Department of Electronics and Telecommunication
Faculty of Engineering and Technology
Shri Shankaracharya Technical Campus
Junwani, Bhilai, Chhattisg

v
 ABSTRACT

Quantum dot cellular automata has been recognized as one of the revolutionary nanoscale computing devices. QCA
has a major advantage over other nanoelectronic architectural styles is that the same cells that are used for making
logic gates can be used to build wires carrying logic signals. QCA allows very high operating frequencies that can be
in range of THz. Its device integration densities is also very high which is about 900 times more than the current end
of CMOS scaling limits, which is not possible in current CMOS technologies. It also has potentially very fast in speed
and has ultra low power consumption. Its above mentioned unbelievable characteristics develops research craze for it
in researchers mind. The heart of every processor’s arithematic unit is adder. It is most important in all operation
because of reason that all other operation like subtraction, division and multiplication can be implemented by using
adders. So for designing a good arithmetic circuit we have to put our focus on making efficient adder circuit. This
major project present the design of QCA full adder, QCA full subtractor and QCA adder-subtractor circuit with least
number of cells used, compared to design previously proposed. Here we use majority voter gate to design adder and
then as previously mentioned all other operation can be make using adder, making a very simple change in design we
show to make a subtractor circuit. And not only that but making another simple change in adder design we can able to
make a Adder-subtractor circuit that can able to perform adding as well as subtracting operation with single circuit.
This Adder-Subtractor QCA circuit takes three input and give sum/diff, carry and borrow bit as output. In this thesis
we present all our design output using QCA Designer tool software and then a comparision table is make to show
how this design is better from previous design in terms of cell count and area.
 TABLE OF CONTENT

CONTENT PAGE NO.

Declaration
Certificate
Acknowledgement
Abstract
Table of content
List of tables
List of figures

1. Introduction
1.1 Fundamental concept
1.2 QCA wire
1.3 QCA clocking
1.4 Inverter gate.
1.5 Majority voter gate
1.5.1 Majority gate as OR gate
1.5.2 Majority gate as AND gate
1.6 Basic of XOR gate
1.7 QCA designer 2.0 tool

2. Literature review
2.1 Literature Review
2.2 Noteworthy contribution

3. Problem Identification
3.1 Problem Identification
3.2 Objective of proposed work

4. Methodology
4.1 QCA tool 2.0 parameters
4.2 QCA Full Adder Design
4.3 QCA Full Subtractor Design
4.4 QCA Adder- Subtractor Design

5. Result and Discussion

5.1 Table of comparision for QCA Full Adder Design
5.2 Table of comparision for QCA Full Subtractor Design
 5.3 Table of comparision for QCA Full Adder- Subtractor Design

6. Conclusion and future scope

6.1 Conclusion
6.2 Limitation
6.3 Future work

7. List of Paper Publication

8. Bibliography
 LIST OF FIGURES

SNO. FIGURE TITLE PAGE NO.

Fig 1.1 Basic QCA cell
Fig 1. 2 (a) Binary Logic ‘1’, and
(b) Binary Logic ‘0
Fig1.3 Cell in Null state
Fig 1.4 QCA wire(90 degree)
Fig 1.5 QCA wire (45 degree)
Fig 1.6 Clock zone in QCA

Fig 1.7 Four phases of a clock

Fig 1.8 Inverter as cells placed at 45 degree from one another

Fig 1.9 Inverter design placed side by side in row

Fig 1.10 NOT gate or inverter
Fig 1.11 NOT gate design in QCA
Fig 1.12 NOT gate simulation result
Fig 1.13 Block diagram of majority voter gate
Fig 1.14 Diagram of QCA majority gate
Fig 1.15 Majority gate design in QCA tool

Fig 1.16 Majority gate design in QCA tool simulation result

Fig 1.17 inverted signal majority voter gate realization in QCA technology

Fig 1.18 inverter signal majority gate design in QCA tool

Fig 1.19 simulation result of inverter signal majority gate in QCA tool

Fig 1.20 OR gate

Fig 1.21 Majority voter gate as OR gate
Fig 1.22 OR gate design in QCA tool
Fig 1.23 simulation result of OR gate in QCA tool
Fig 1.24 AND gate
Fig 1.25 majority voter gate as AND gate
Fig 1.26 AND gate design in QCA tool
Fig 1.27 simulation of AND gate design in QCA
Fig 1.28 XOR gate
Fig 1.29 XOR gate in QCA
Fig 1.30 XOR gate design in QCA tool
Fig 1.31 simulation result of XOR gate in QCA tool

Fig 1.32 Bistable Engine simulation option

Fig 1.33 Coherence Vector simulation engine options
Fig 4.1 Block diagram of full adder
Fig 4.2 (a) full adder circuit in QCA, (b) its simulation result

Fig 4.3 Block diagram of full subtractor

Fig 4.4 (a) full subtractor QCA circuit, (b) its simulation result

Fig 4.5 Block diagram of adder-subtractor circuit

Fig 4.6 (a)adder-subtractor circuit in QCA, (b) its simulation result

LIST OF TABLES
TABLES TITLE PAGE NO.
Table 1.1 Operation of QCA phase
Table 1.2 Truth table of inverter
Table 1.3 Truth table of majority voter gate
Table 1.4 Truth table OR gate
Table 1.5 Truth table of AND gate
Table 1.6 Truth table XOR gate
Table 4.1 Truth-table of full adder
Table 4.2 Truth-table of full subtractor
Table 4.3 Truth table of adder-subtractor circuit
Table 5.1 Comparision table of QCA Full adder circuit
Table 5.2 Comparision table of QCA Full subtractor circuit
Table 5.3 Comparision table of QCA Full adder- subtractor
circuit.

LIST OF ABBREVIATIONS
 CHAPTER-I
INTRODUCTION
Overview
This chapter sect a stage for understanding the design of QCA Full adder, QCA Full subtractor and QCA full adder-
subtractor. Section 1.1 describes the fundamental concept of QCA technology. Section 1.2 and Section 1.3 describes
QCA technology’s basic element like QCA wire and QCA clocking. Section 1.4 describes QCA inverter gate. Section
1.5 gives the information about fundamental gate in QCA called majority voter gate. Section 1.5.1 describes Majority
gate as OR gate and Section 1.5.2 describes Majority gate as AND gate. Section 1.6 gives information about basic of
XOR gate and present one of the least cell QCA design of XOR gate. Section 1.7 give brief introduction of adder
which is sub divided in section 1.7.1 that present information about full adder whereas Section 1.8 give brief
introduction of subtractor which is sub divided in section 1.8.1 that present information about full subtractor. Section
1.9 describes concept of adder-subtractor that performs both addition and subtraction operation on a single circuit.
The QCA designer 2.0 tool required for presenting the correctness of result of proposed designs in this thesis is
checked and presented in section 1.10.

1.1 FUNDAMENTAL CONCEPT:

Form very long time CMOS technology gives very good real-time applications in integrated circuit field.
We saw it continuously updating time to time and now it already achieve its best possible practical as well as
theoretical limits. Beyond this limit it starts showing some issues like leakage current problem and transistor is found
to be no more able to switch properly and start dissipating heat. This heat is too much that it can able to melt chip.
The other problem seen in CMOS technology is that if we are trying to increase speed then the power consumption of
circuit also increases and if we are trying to decrease power then it decreases speed automatically. High-noise
absorption, high-power consumption, short circuit effects and reducing gate control are also problems seen in CMOS
technology. All such problems make it quite difficult to further create VLSI circuits with CMOS technology. This
make researchers to think to explore a new technology for designing future integrated circuits. And now they found
one very promising technology which can work much beyond the limits of CMOS technology. This new technology
named as Quantum dot cellular automata and can be abbreviated as QCA.
This QCA technology seems very attractive because of its various features like high speed, high packaging
density, highly scalable, higher switching frequency and low power. Many researches already done in QCA and
shows quiet interesting results about this technology, it shows QCA can able to achieve very high device density up to
1012 devices/cm2 and it can also able to achieve remarkable switching speed that can be up to 10 ps and power
dissipation up to 100 W/cm2.
QCA technology doesn’t have transistor, it uses symmetric square cells to design circuit. This square cell
describes the QCA devices. With these square cells we can make any logic gates as well as any memory circuit.
Inside cell there tunnel junction present which couple all four electrons sites together. Two moving electrons exist
inside the cell. By tunnelling we simply means that, the electron are free to move and can occupy any of the quantum
sites in the cell. Information transfer is seen because of coulomb interactions that found between alternate cells. By
putting QCA cells side by side we can make different patterns, this specific pattern give specific output. The cell has
four quantum dots and two electron always placed diagonally from one another. Voltage and current does not play
any role in QCA. The working of this technology is totally depends on the very important coulombic interaction
principle that exist between electrons inside quantum dots. In QCA cell there we see two stable states in which two
free electron settles and each of this state encoded as binary states of digital circuit. Cells can be arranged in array or
very different specific manner for getting desired output. The QCA basic cell has four quantum dot each of which is
10nm diameter and placed at distance of 20nm from one another, it can be shown in figure below:

Fig 1.1 Basic QCA cell

For making functional QCA cell, two free electron are placed inside diagonal dots and allowed to tunnel. This
tunnelling cause electron to settle down in two stable states ‘1’ and ‘-1’. These states are then encoded to logic ‘1’ and
‘0’binary states .The two binary states illustrated in Figure 1.2(a) and (b) respectively.

(a) (b)
Fig 1.2 (a) Binary Logic ‘1’ and (b) Binary Logic ‘0’
Here P represent the polarization of cell. The polarization in QCA cell is used to encode the binary information. Other
then binary 1 and binary 0, there is one more state seen in QCA named as null state. Null state is said to has
polarization zero. Every normal cell in QCA is actually has polarization as 0 and can be called is in null state.

Fig 1.3 Cell in Null state

1.2 QCA WIRE

For designing purpose the basic knowledge of QCA wires is very important. QCA wire is simply a array of cells
putting one after another having same polarity. Its work is similar to the real world wire. It used to transfer data from
one point to another. In real world current flow inside wire. But QCA circuits doesn’t allow current flow, there
changes in electronic polarization seen. Due to this reason QCA circuits dissipates extremely low power.
QCA wire is the most simplest design in QCA, in which we can place cells side by side, so that it can
propagate signal from one end to another. State changes happened, due to interaction of electrostatic or magnetic
fields which is seen between the neighbouring cells. The Figure illustrates below shows binary wire realization in
QCA technology and it also shows clearly two different ways in which QCA wire can be connected and due to
difference in degree in which cell is placed the change reflect in output side:

Fig 1.4 QCA wire(90 degree)

 Figure 1.5: QCA wire (45 degree)

1.3 QCA CLOCKING

In QCA, clock simply provides energy to run the circuit. It also provides delay to the circuit. The clock also control
flow of information inside circuit. There are 4 types of clock used in QCA they are also called different clock zones
and labelled as clock 0, clock 1, clock 2 and clock 3. Every feature of all clocks are quite similar but the only
difference which makes one clock different from another is seen in its phase. Every next clock is at 90 degree phase
difference from previous one. With different colours different clock is represent in QCA, green colour cell represent
clock 0 is applied to it, pink represent clock 1, light blue represent clock 2 and white represent clock 3.

Fig 1.6 Clock Zone in QCA

In each clock zone we find four different phases named as switch, hold, release and relax. And in particular clock
zone there is 90 degree phase shift present in between every four adjacent phases. The figure shown below illustrates
4-phase clocking scheme:
 Fig 1.7 Four phases of a clock.
Clock provides power gain of QCA circuit. Clock is only source that powered cell and there is not at all any other
external source apart from it. The polarization of the input cell can be fixed and then as its result the system is relax to
the ground state. Certain process involves in the whole relaxation process which are shown below as follows.

 Release: A potential barrier is seen between the tunnel junction, the less the potential barrier is, more it is
easy for the electron to tunnel from one dot to the other.

 Relax: When the lowest possible state of the potential barrier is found. The polarization of the cell is said to
be ‘0’. This makes all previous input state of the cell removes the relax stage

 Switch: New input is applied to the Switch position and then the potential barrier is seen to be raised
automatically. With this state of the input cell the QCA cell seems to gets polarised easily. Actual
computation of the QCA occurs in this state.

 Hold: Potential barrier is now ready to raised as high as possible. And thus it becomes easily possible to
suppress any more electron tunnelling, so after a point comes in which the state seems to be fixed.

Table 1.1
operation of QCA clock phase

1.4 QCA INVERTER

Inverter simply invert input signal and passes it to output. So if we has signal ‘0’ in input side of inverter then at
output side we get ‘1’. And if we has signal ‘1’ in input side of inverter then at output side we get ‘0’.The figure
shown below shows the most widely used QCA inverters. Figure shows for making inverter we can either place
cells at 45 degree from one another or can use rotated cells side by side in row:

Fig 1.8 Inverter as cells placed at 45 degree from one another

 Fig 1.9 Inverter design placed side by side in row

The Equation representing inverter:

F = I’

The symbol of inverter is shown below as follows:

Fig 1.10 Not gate or inverter

The truth table of inverter is shown below as follows:

Table 1.2 Truth table of inverter

It is very easy to implement an inverter using QCA cells, we have to simply place two QCA cells at 45 degrees with
respect to each other. In figure below the inverter design is shown using QCA Designer tool with its stimulation
result.

Fig 1.11 NOT gate design in QCA

 Fig 1.12 Not gate simulation result

1.5 MAJORITY VOTER GATE

Majority voter (MV) gate is most fundamental gate in QCA technology. QCA majority gate is made from 5 cells that
makes a cross like structure. There is a centre cell called device cell over which other four cell are surrounded. In
these four cells there is three input cells and one output cell. The majority voter gate working is very simple, it simply
passes the majority of input to the output. In simple words if MV found two or more input as ‘0’ then it simply passes
‘0’ as output and if it found two or more input as ‘1’ then it simply passes ‘1’as output. The QCA majority voter gate
is illustrated below:

Fig 1.13 Block diagram of majority voter gate

Fig 1.14 Diagram of QCA majority gate

The logical function representation of majority voter gate is shown below as follows[14,18]:

F(A,B,C)= AB+AC+BC
Here we simply have three inputs as A,B and C and one output.

When we fix polarization of any one of the input of Majority gate to either “0” or “1”, it can be used successively as
AND or OR gate [9, 18].
Let us fix input C to 1 then we get output as A+B whereas fixing input C to 0 the output we get output as A.B. The
logic function representation for majority voter gate as AND and OR gate is shown below as follows[19]:

M(A,B,1)=A+B
M(A,B,0)=A.B

The truth table of majority gate is also very simple,it shows majority gate simply give the more weighted input as
[Link] truth table of majority voter gate is show below:

Table 1.3 Truth table of majority voter gate.

In figure below the Majority gate QCA design is shown using QCA Designer tool with its stimulation result.
 Fig 1.15 Majority gate design in QCA tool

Fig 1.16 Majority gate design in QCA tool simulation result

With making one simple specific change in input of Majority gate, it start acting like either as AND gate or as OR
gate. If we fix polarization of any one of input to ‘-1’, it become AND gate and if we fix polarization of any one of
input to ‘1’, it become OR gate. So because of this reason any Boolean function can be implemented using majority
gate and inverter.
There is another way to place cells of majority gate which look quite different from conventional design of
majority gate it can be called as inverted signal design of majority gate. The output function is same in both design,
or concept is same it simply passes the majority. We can choose any design to make circuit. The inverted signal
design of majority gate is illustrated in figure below:

Fig 1.17 inverted signal majority voter gate realization in QCA technology

Fig 1.18 inverter signal majority gate design in QCA tool

 Fig 1.19 simulation result of inverter signal majority gate in QCA tool

1.5.1 MAJORITY GATE AS OR GATE

The OR gate is a digital logic gate which results a HIGH output (1) if one or both the inputs to the gate are HIGH
(1).And if neither input is high, it results a LOW output (0) .

The Equation of OR gate is

Q = A+B.

The symbol of OR gate is shown below as follows:

Fig 1.20 OR gate

The truth table of OR gate is shown below as follows:

Table 1.4 Truth table OR gate

By setting one of the inputs of majority gate to one, we can easily design OR gate. So when c is given ‘1’ the out we
get as a + b.

𝑀𝑎𝑗 (𝐴, 𝐵, 1) = 𝐴 + 𝐵
The design of majority voter gate as OR gate is shown below as follows:

Fig 1.21 Majority voter gate as

OR gate.

The below figure shows the OR gate using QCA designer tool.

Fig 1.22 OR gate design in QCA tool

Fig 1.23 simulation result of OR gate in QCA tool

1.5.2 MAJORITY GATE AS AND GATE

The AND gate is a basic digital logic gate which shows A HIGH output (1) only if all the inputs to the AND gate are
HIGH (1). And if all inputs is not HIGH it results LOW output .

The Equation of AND gate is F = A.B

The symbol of AND gate is shown below as follows:

Fig 1.24 AND gate

The truth table of AND gate is shown below as follows:

Table 1.5 Truth table of AND gate

By setting one of the two input to zero, we can easily design AND gate from majority gate. The equation shown
below illustrated Majority Voter gate working as OR gate. When c is given ‘0’ the output we get as a . b.

𝑀𝑎𝑗 (𝐴, 𝐵, 0) = 𝐴. B

The design of majority voter gate as AND gate is shown below as follows:

Fig 1.25: majority voter gate as AND gate

The figure shown below shows the AND gate circuit in QCA designer tool with its simulation result.
 Fig 1.26 AND gate design in QCA tool

Fig 1.27 Simulation of AND gate design in QCA

1.6 BASICS OF XOR GATE

The three input XOR gate is a digital logic gate which simply passes HIGH output ‘1’ if it get odd
number of HIGH ‘1’ at input side otherwise it results a LOW output (0) .Because of this it is called as a
odd detector.

The logic function representation of XOR is shown below as follows[26]:

F(A,B,C)= A⊕B⊕C=ABC+A’B’C+AB’C’+A’BC’
Here we simply have three inputs as A, B and C and one output.

The symbol and truth table is shown below as follows:

Fig 1.28: XOR gate

The truth table satisfying the above mentioned logical function of XOR gate is shown below:
 Table 1.6 Truth table XOR gate

The present most efficient least cell QCA XOR gate design is made by adding three more cells in majority voter gate
design and is presented in below as follows[28]:

Fig 1.29
XOR gate in QCA

The below figure shows the OR gate using QCA designer tool.

Fig 1.30 XOR gate design in QCA tool

 Fig 1.31 simulation result of XOR gate in QCA tool

1.7 QCAD DESIGNER 2.0 TOOL

The aim of this project is to show the correctness of proposed design with its simulation result, this can be done using
QCAD Designer 2.0 tool. It helps to determine the circuit’s functionality. Bistable simulation

engine and coherence vector simulation engine are two simulation engine in QCA tool. In Bistable stimulation
engine, the following engine option is present that shown below in figure as follows:

Fig 1.32 Bistable Engine simulation Option

In coherence vector stimulation engine, the following engine option is present that shown below in figure as follows:
Fig 1.33 Coherence Vector simulation engine options

CHAPTER-2
LITERATURE REVIEW
Overview
This chapter describes various attempts made by designers to minimize the cells and area of Full adder, Full
subtractor and adder- subtractor. Section 2.1 gives the Literature Review. Section 2.2 shows the noteworthy
contribution by different authors for our proposed work.

2.1 Papers Reviewed

The number of research papers of many conferences and jouranals were studied and survey of the presenting
literatures in the proposed work is reported below:

In 1994, C. S. Lent, W. Porod and P. D. Tougaw [1] proposed “Quantum cellular automata: the physics
of computing with arrays of quantum dot molecules” in which they presented a Full adder based on QCA
technology. This circuit consists of 198 cells and occupied 0.206 μm2 area.

In 2017, Goswami, Biplab K. Sikdar, Mrinal, Rijoy Mukherjee and Bibhash Sen,[2] proposed “Design
of Testable Adder in Quantum‐dot Cellular Automata with Fault Secure Logic” in which they presented a
Full adder based on QCA technology. This circuit consists of 168 cells and occupied 0.228 μm2 area.
In 2017, N K Mandal and Ratna Chakrabarty [3] proposed “ Design of a Controllable Adder-Subtractor
circuit using Quantum Dot Cellular Automata” in which they presented a Full adder based on QCA
technology. This circuit consists of 154 cells and occupied 0.180 μm2 area.

In 2003, W. Wang, G. A. Jullien and K. Walus [4] proposed “Quantum-dot cellular

automata adders,” in which they presented a Full adder based on QCA technology. This circuit consists of
135 cells and occupied 0.144 μm2 area.

In 2014, Suresh K. and Ghosh B [5] proposed “Ripple carry adder using two XOR gates in QCA”, in
which they presented a Full adder based on QCA technology. This circuit consists of 124 cells and occupied
0.097 μm2 area.

In 2007, Azghadi M.R., Navi K and Kavehei O. [6] proposed “A novel design for quantum dot cellular
automata cells and full-adders” in which they presented a Full adder based on QCA technology. This circuit
consists of 107 cells and occupied 0.920 μm2 area.

In 2015, S. Sayedsalehi, K. Navi, S. Angizi and M. Rahimi Azghadi [7] proposed “Restoring and non-
restoring array divider designs in quantum-dot cellular automata,” in which they presented a Full adder
based on QCA technology. This circuit consists of 105 cells and occupied 0.146 μm2 area.

In 2015, Mohammadyan, Somaye, Keivan Navi and Shaahin Angizi [8] proposed “ New fully single
layer QCA full-adder cell based on feedback model” in which they presented a Full adder based on QCA
technology. This circuit consists of 96 cells and occupied 0.120 μm2 area.

In 2012, B. Bishnoi [9] proposed “Ripple carry adder using five input majority gates,” in which they
presented a Full adder based on QCA technology. This circuit consists of 95 cells and occupied 0.087 μm2
area.

In 2006, R. Zhang[10] proposed “Performance comparison of quantum-dot cellular automata adders,” in

which they presented a Full adder based on QCA technology. This circuit consists of 93 cells and occupied
0.086 μm2 area.

In 2012, Sara Hashemi, Keivan Navi and Mohammad Tehrani [11] proposed “An efficient quantum-dot
cellular automata full-adder” in which they presented a Full adder based on QCA technology. This circuit
consists of 79 cells and occupied 0.050 μm2 area.

In 2010, K. Navi, M. Rahimi Azghadi, R. Farazkish and S. Sayedsalehi [12] proposed “A new quantum-
dot cellular automata full-adder,” in which they presented a Full adder based on QCA technology. This
circuit consists of 73 cells and occupied 0.044 μm2 area.

In 2015, Hashemi S. And Navi K. [13] proposed “A novel robust QCA full-adder” in which they
presented a Full adder based on QCA technology. This circuit consists of 71 cells and occupied 0.060 μm2
area.

In 2014, Kianpour M., Navi, K. and Sabbaghi-Nadooshan R.[14] proposed, “A novel design of 8-bit
adder/subtractor by quantum-dot cellular automata” in which they presented a Full adder based on QCA
technology. This circuit consists of 69 cells and occupied 0.070 μm2 area.
In 2016, H. Thapliyal and C. Labrado [15] proposed “Design of adder and subtractor circuits in majority
logic-based fieldcoupled
QCA nano computing” in which they presented a Full adder based on QCA technology. This circuit consists
of 63 cells and occupied 0.050 μm2 area.

In 2010, M.R. Azghadi, S. Sayedsalehi, k. Navi and R. Farazkish, [16] proposed “Five-input majority
gate, a new device for quantum-dot cellular automata”, in which they presented a Full adder based on QCA
technology. This circuit consists of 61 cells and occupied 0.030 μm2 area.

In 2015, D. Abedi, M. Sangsefidi and G. Jaberipur [17] proposed “Coplanar full adder in quantum-dot
cellular automata via clock-zone-based crossover” in which they presented a Full adder based on QCA
technology. This circuit consists of 59 cells and occupied 0.043 μm2 area.

In 2015, M. A. Rani and B. Ramesh [18] proposed “Design of binary to BCD code converter using area
optimized quantum dot cellular automata full Adder,” in which they presented a Full adder based on QCA
technology. This circuit consists of 52 cells and occupied 0.038 μm2 area.

In 2012, S. Hashemi, K. Navi and M. Tehrani [19] proposed “An efficient quantum dot cellular automata
full-adder,” in which they presented a Full adder based on QCA technology. This circuit consists of 51 cells
and occupied 0.034 μm2 area.

In 2017, Saeid Zoka and Mohammad Gholami [20] proposed “A novel efficient full adder–subtractor in
QCA nanotechnology”in which they presented a Full adder based on QCA technology. This circuit consists
of 44 cells and occupied 0.060 μm2 area.

In 2018 Hosseinzadeh S. R. and Asfestani M. N. [21] proposed “A full adder structure

without cross-wiring in quantum-dot cellular automata with energy dissipation analysis” in which they
presented a Full adder based on QCA technology. This circuit consists of 41 cells and occupied 0.030 μm2
area.

In 2016, M. Mohammadi, S. Gorgin and M. Mohammadi [22] proposed “An efficient design of full
adder in quantum-dot cellular automata (QCA) technology” in which they presented a Full adder based on
QCA technology. This circuit consists of 38 cells and occupied 0.020 μm2 area.

In 2017, Hamid Rashidi and Abdalhossein Rezai [23] proposed “High-performance full adder
architecture in quantum-dot cellular automata” in which they presented a Full adder based on QCA
technology. This circuit consists of 33 cells and occupied 0.020 μm2 area.

In 2013, Sen B., Sikdar B.K and Rajoria A.[24] proposed “Design of efficient full adder in quantum-dot
cellular automata” in which they presented a Full adder based on QCA technology. This circuit consists of
31 cells and occupied 0.019 μm2 area.

In 2020, Lei Wang and Jie Yan [25] proposed “An efficient full adder circuit design in Quantum-dot
Cellular Automata technology” in which they presented a Full adder based on QCA technology. This circuit
consists of 30 cells and occupied 0.011 μm2 area.
In 2017, M. Balali, S. Emadid, A. Rezai, F. Rabiei, and H. Balali [26] proposed “Towards coplanar
quantum-dot cellular automata adders based on efficient three-input XOR gate,” in which they presented a
Full adder based on QCA technology. This circuit consists of 29 cells and occupied 0.020 μm2 area.

In 2015, Roohi A., Khoshavi N and Demara R. [27] proposed “Design and evaluation of an ultra-area-
efficient fault-tolerant QCA full adder ” in which they presented a Full adder based on QCA technology.
This circuit consists of 23 cells and occupied 0.010 μm2 area.

In 2021, Ismail Gassoumi , Abdellatif Mtibaa and Lamjed Touil [28] proposed “An Efficient Design of
QCA Full-Adder-Subtractor with Low Power Dissipation” in which they presented a Full adder based on
QCA technology. This circuit consists of 19 cells and occupied 0.014 μm2 area.

In 2010, Lakshmi S.K., Ganesh, C., Athisha G. and Karthikeyan, M.[29] proposed “Design of
subtractor using nanotechnology based QCA” in which they presented a subtractor based on QCA
technology. This circuit consists of 186 cells and occupied 0.206 μm2 area.

In 2017, Ratna Chakrabarty and N K Mandal [3] proposed “ Design of a Controllable Adder-Subtractor
circuit using Quantum Dot Cellular Automata” in which they presented a Full subtractor based on QCA
technology. This circuit consists of 154 cells and occupied 0.180 μm2 area.

In 2015, M. Mehran and H. Dallaki [30] proposed “Novel subtractor design based on quantum-dot
cellular automata (QCA) nanotechnology,” in which they presented a Full subtractor based on QCA
technology. This circuit consists of 136 cells and occupied 0.168 μm2 area.

In 2014, Ahmad PZ, Khan RA, Ahmad F and Ahmad SM [31] proposed “Implementation of quantum
dot cellular automata based novel full adder and full subtractor” in which they presented a Full subtractor
based on QCA technology. This circuit consists of 108 cells and occupied 0.120 μm2 area.

In 2016, M. T. Banday and J. I. Reshi [32] proposed “Efficient design of nano scale adder and subtractor
circuits using quantum dot cellular automata,” in which they presented a Full subtractor based on QCA
technology. This circuit consists of 104 cells and occupied 0.028 μm2 area.

In 2019, Marshal raj and Gopalakrishnan Lakshminarayanan [33] proposed “Novel Reliable QCA
Subtractor Designs using Clock zone based Crossover” in which they presented a Full subtractor based on
QCA technology. This circuit consists of 84 cells and occupied 0.027 μm2 area.

In 2016, H. Thapliyal and C. Labrado [34] proposed “Design of adder and subtractor circuits in majority-
logic based field-coupled QCA nano computing,” in which they presented a Full subtractor based on QCA
technology. This circuit consists of 63 cells and occupied 0.050 μm2 area.

In 2017, Trailokya Nath Sasamal and Ramanand Jaiswal [35] proposed “Efficient Design of Full Adder
and Subtractor using 5-input Majority gate in QCA” in which they presented a Full subtractor based on
QCA technology. This circuit consists of 53 cells and occupied 0.047 μm2 area.

In 2020, Surendhar Balaji.B, [Link] Lakshmi, Shankar.S and Selvakumar. G[36] proposed
“An optimal design of full subtractor in QCA nanotechnology” in which they presented a Full subtractor
based on QCA technology. This circuit consists of 46 cells and occupied 0.015 μm2 area.
In 2017, Peer Zahoor Ahmad, Ali Newaz Bahar, Ghulam Mohammad Wani, Syed Mohammad
Khurshid Quadri, Firdous Ahmad and Shafiq Maqbool Tantary [37] proposed“Design of novel QCA-
based half/full subtractors” in which they presented a Full subtractor based on QCA technology. This circuit
consists of 37 cells and occupied 0.040 μm2 area.

In 2017, A. N. Bahar, M. Asaduzzaman, S. Waheed and N. Hossain [38] proposed “A novel 3-input
XOR function implementation in quantum dot cellular automata with energy dissipation analysis,” in which
they presented a Full subtractor based on QCA technology. This circuit consists of 32 cells and occupied
0.028 μm2 area.

In 2018, Ali Newaz Bahar and Md. Abdullah-Al-Shafi [39] proposed “An Architecture of 2-Dimensional
4-Dot 2-Electron QCA Full Adder and Subtractor with Energy Dissipation Study ” in which they presented
a Full subtractor based on QCA technology. This circuit consists of 27 cells and occupied 0.030 μm2 area.

In 2021, Ismail Gassoumi , Abdellatif Mtibaa and Lamjed Touil [28] proposed “An Efficient Design of
QCA Full-Adder-Subtractor with Low Power Dissipation” in which they presented a Full subtractor based
on QCA technology. This circuit consists of 20 cells and occupied 0.014 μm2 area.

In 2016, Angizi S ,Moaiyeri M. and Taherkhani E.[40] proposed “ A novel efficient reversible full
adder–subtractor in QCA nanotechnology” in which they presented a Full adder-subtractor based on QCA
technology. This circuit consists of 228 cells and occupied 0.400 μm2 area.

In 2010, Ganesh C., Lakshmi S.K., Karthikeyan M. and Athisha G.[41] proposed “ Design of
subtractor using nanotechnology based QCA” in which they presented a Full adder-subtractor based on
QCA technology. This circuit consists of 186 cells and occupied 0.132 μm2 area.

In 2011, Selamat A. And Shahidinejad A[42] proposed “ Design of First Adder/Subtractor using
Quantum-Dot Cellular Automata.” in which they presented a Full adder-subtractor based on QCA
technology. This circuit consists of 180 cells and occupied 0.190 μm2 area.

In 2015, Lisa N.J., Bardhan R. and Sultana T[43] proposed “ An efficient design of adder/subtractor
circuit using quantum dot cellular automata” in which they presented a Full adder-subtractor based on QCA
technology. This circuit consists of 109 cells and occupied 0.790 μm2 area.

In 2019, M. Raj and L. Gopalakrishnan [44] proposed “Fast quantum dot cellular automata
adder/subtractor using novel fault tolerant exclusive-or gate and full adder,” in which they presented a Full
adder-subtractor based on QCA technology. This circuit consists of 90 cells and occupied 0.110 μm2 area.

In 2017, Saeid Zoka and Mohammad Gholami [20] proposed “A novel efficient full adder–subtractor in
QCA nanotechnology” in which they presented a Full adder-subtractor based on QCA technology. This
circuit consists of 83 cells and occupied 0.090 μm2 area.

In 2020, M. Raj and L. Gopalakrishnan [45] proposed “Design and analysis of novel QCA full adder-
subtractor” in which they presented a Full adder-subtractor based on QCA technology. This circuit consists
of 75 cells and occupied 0.090 μm2 area.
In 2020, G. Lakshminarayanan and R. Marshal [46] proposed “ Fault Resistant Coplanar QCA Full
Adder- Subtractor Using Clock Zone-Based Crossover” in which they presented a Full adder-subtractor
based on QCA technology. This circuit consists of 54 cells and occupied 0.060 μm2 area.

In 2014, Abbas Rezaei and Mohsen Hayati[47] proposed “ Design of novel efficient adder and subtractor
for quantum-dot cellular automata” in which they presented a Full adder-subtractor based on QCA
technology. This circuit consists of 53 cells and occupied 0.039 μm2 area.

In 2020, G. Lakshminarayanan and R. Marshal [46] proposed “ Fault Resistant Coplanar QCA Full
Adder- Subtractor Using Clock Zone-Based Crossover” in which they presented a Full adder-subtractor
based on QCA technology. This circuit consists of 38 cells and occupied 0.030 μm2 area.

2.2 Noteworthy Contribution

In 2021, Ismail Gassoumi, Abdellatif Mtibaa and Lamjed Touil [28] proposed “An Efficient Design of
QCA Full-Adder-Subtractor with Low Power Dissipation” in which they presented a Full adder and Full
subtractor based on QCA technology. First only adding two new cells in majority voter gate the least cell
design of XOR is presented in this paper. With this XOR design they finally realised Full Adder design and
Full subtractor design. This full adder design is made only with 19 cells and occupied 0.014 μm2 area and
full subtractor design is made only with 20 cells and occupied 0.014 μm2 area. These proposed designs uses
very less area and power.
 CHAPTER -3
PROBLEM IDENTIFICATION
AND
OBJECTIVE
Overview
Section 3.1 gives the problems identified by the study of literature by the author in the field of the proposed work.
The problems are seen particularly related to cell count, area, more layers used, more clock used and delay .The
problems identified so that the main objective of the proposed work can be highlighted in section 3.2.

3.1 Problem Identification

The existing literature in the proposed area have major challenges that need to be addressed. Some of problems
identified are:
In “Quantum cellular automata: the physics of computing with arrays of quantum dot molecules”[1].
1. Inside cell there is 5 quantum sites that cause size issue and trying to decrease cell size it start increasing heat
dissipation.
2. Majority gate is of large size 8 cells, design from it make from it is bulkier design.
3. Between cells there is many waste space.

In “Design of a Controllable Adder-Subtractor circuit using Quantum Dot Cellular Automata”[3].

1. Large wasted space
2. Bit present before getting output signal. It may cause issue.

In “Ripple carry adder using two XOR gates in QCA” [5].

1. More than 130 cells area is wasted in this design.
2. It uses all four clock and thus seen increase in delay of circuit.

In “A novel design for quantum dot cellular automata cells and full-adders”[6].
1. Very large area 0.920.
2. More area is wasted in this design.

In “Restoring and non-restoring array divider designs in quantum-dot cellular automata”[7].

1. Area wasted is much more than used area.
2. 3 clocks are used, thus delay is more.
3. Multilayer used.

In “New fully single layer QCA full-adder cell based on feedback model”[8].
1. All 4 clock used, thus delay of circuit is more.
2. It shows carry and sum output together in one output signal.
3. It uses three input with one more clk input.
4. Output is not so clear to understand.

In “Ripple carry adder using five input majority gates”[9].

1. All 4 clock used, thus delay seems be more.
2. Before actual output signal it shows flase bit.

In “Performance comparison of quantum-dot cellular automata adders”[10].

1. Multilayer used.
2. Wasted area is much more.
In “An efficient quantum-dot cellular automata full-adder”[11].
1. Three layers are used in this design.
2. Three clock used
3. Delayed output.

In “A new quantum-dot cellular automata full-adder”[12].

1. Three layers are used in this design.
2. Three clock used.
3. Delayed output of SUM.

In “A novel robust QCA full-adder”[13].

1. All four clock used

In “A novel design of 8-bit adder/subtractor by quantum-dot cellular automata” [14].

1. More area is wasted.
2. All four clock is used.

In “Design of adder and subtractor circuits in majority logic-based field coupled QCA nano computing” [15].
1. Three clock used.

In “Design of binary to BCD code converter using area optimized quantum dot cellular automata full Adder”[18}
1. All four clock used.
2. Output of sum shows delay.

In “An efficient quantum dot cellular automata full-adder”[19].

1. Multilayer used.
2. All four clock used.
3. Delayed output.

In “A novel efficient full adder–subtractor in QCA nanotechnology” [20].

1. All four clock used.
2. More wasted area.
3. Result is not exact.

In “An efficient design of full adder in quantum-dot cellular automata (QCA) technology”[22].
1. Three layer are used, hence much more wasted area.

In “High-performance full adder architecture in quantum-dot cellular automata”[23].

1. More area is wasted.

In “Design of efficient full adder in quantum-dot cellular automata”[24].

1. Three layer are used.

In “Design and evaluation of an ultra-area-efficient fault-tolerant QCA full adder ”[27].

1. Three layers are used.
2. Three clock are used.

In “Novel subtractor design based on quantum-dot cellular automata (QCA) nanotechnology”[30].

1. All four clock used
2. Wasted area.

In “Implementation of quantum dot cellular automata based novel full adder and full subtractor”[31]
 1. More area is wasted.
2. Delay in diff output.

In “Efficient design of nano scale adder and subtractor circuits using quantum dot cellular automata”[32]
1. All four clock used.
2. Wasted area.
3. Both borrow and diff ,delayed output.

In “An optimal design of full subtractor in QCA nanotechnology” [36].

1. All four clock used.
2. Diff and borrow both shows delayed output

In “ A novel efficient reversible full adder–subtractor in QCA nanotechnology” [40].

1. More area is wasted.
2. All four clock used.
3. Not exact output.
4. Area is high.

In “ Design of subtractor using nanotechnology based QCA” [41].

1. Very high cell count.
2. More area is wasted.
3. All four clock are used.

3.2 Objective of proposed work

The main objective of our research work is to overcome above mention problems and to implement the QCA
Full adder, Full Subtractor and Adder-Subtractor using QCA Designer 2.0 tool which will have comparatively
less cell count and area.
 CHAPTER -4
METHODOLOGY

Overview
This chapter completely describes the designing and operation of full adder, full subtractor and adder - subtractor.
Section 4.1 gives information that there no change is made in by default set parameters in QCA tool for getting
required results. Section 4.2 shows proposed QCA design with methodology and area calculation of Full adder.
Section 4.3 shows proposed QCA design with methodology and area calculation of Full subtractor. Section 4.4 talks
about proposed QCA design and area calculation of adder- subtractor.

4.1 QCA 2.0 TOOL PARAMETERS

The results of simulation are obtained by QCA Designer simulation tool. This tool is used to stimulate computational
logic circuit constructed using QCA. It can be very simple to construct complex Quantum Dot cellular Circuits using
this very simple tool. The engines are used in this tool for simulation are Bistable and Coherence Simulation Engine.
For that we apply this various parameters of bistable approximation can be simulated with below listed parameters-

 Cell size = 18 nm
 Clock amplitude factor = 2.0000
 Clock high = 9.8000e−022 J
 Clock low = 3.5000e−023J
 Clock shift = 0
 Convergence tolerance = 0.0000100
 Layer separation = 11.50
 Maximum iterations per sample = 100
 Number of samples = 50000
 Radius of effect = 65.0000 nm
 Relative permittivity = 12.9000.

4.2 QCA FULL ADDER DESIGN

The 1-bit full-adder performs the addition of three inputs A,B,C which is one bit input [Link] get two outputs at the
end, one of the output termed as Sum and another one as Carry. The full adder block diagram with its truth table are
shown below.
 Fig 4.1 Block diagram of full adder.

The logical function for Sum and Carry is shown below[15]:

SUM=A⊕B⊕C
CARRY=AB+BC+AC

The truth table satisfying the above mentioned logical function of Sum and Carry is shown below:

Table 4.1 Truth table of full adder.

On analyzing the truth table of majority voter gate presented in table 2 we found that the output of majority voter gate
is similar to the carry bit of full adder, so we can use QCA design of majority voter gate presented in figure 6 in
designing carry bit of our full adder. And On analyzing the truth table of XOR gate presented in table 3 we found that
the output of XOR gate is similar to the SUM bit of full adder, so we can use QCA design of XOR gate presented in
figure 7 in designing SUM bit of our full adder. So by merging these two previously mentioned design the new
proposed design of QCA Full-Adder circuit is shown below in figure 9(a) and the correctness of result this proposed
design is successfully check using QCA Designer 2.0.3 tool and the output is shown in figure 9(b). Here the graph
showing A,B and C as three input and the SUM output we get as (0,1,1,0,1,0,0,1)and CARRY output we get as
(1,1,1,0,0,1,1,1) which are same as the desired output shown in truth table of full adder presented in table 4.
 (a)

(b)
Fig 4.2 (a) full adder circuit in QCA, (b) its simulation result

On counting the cells of full adder proposed here we can clearly see that our full adder design includes total 16 cells.
For calculating area we have to follow following steps which is shown below:
Step1: Here we can see total 6 cells are presented horizontally and each cell is having 18nm length and 18nm breadth
so 18*18nm2 area is being occupied by each cell. So for 6 cells with the particular gap between cells 2nm and the gap
between one cell from its last boundary are 1nm.
So the entire horizontal area of 6 cells = (1+18+2+18+2+18+2+18+2+18+2+18+1) = 120nm
Step2: Next we have on total 5 cells are presented vertically so by following previous similar calculation we have.
the entire vertical area of 5 cells = (1+18+2+18+2+18+2+18+2+18+1) = 100nm
Step 3: Total area occupied = 120nm * 100nm = 12000nm2
So the area occupied by proposed design of full adder is about 0.012 μm2.

4.3 QCA FULL SUBTRACTOR DESIGN

The one-bit full-subtractor performs the substraction of three inputs A,B,C which is one bit input [Link] get two
outputs at the end, one of the output termed as Difference and another one as Borrow. The full subtactor block
diagram with its truth table are shown below.
 Fig 4.3 Block diagram of full subtractor
The logical equations for difference and borrow is shown below as follows[15]:

Difference=A⊕B⊕C
Borrow=A’B+A’C+BC

The truth table satisfying the above mentioned logical function of difference and borrow is shown below:

Table 4.2: Truth-table for full

On analyzing the truth table of majority gate voter presented in table 2 we found that the if we invert one of input of
majority voter gate then we get the borrow bit of full subtractor, so we can use QCA design of inverter gate presented
in figure 5 merging with design of majority voter gate presented in figure 6 to get borrow bit of our full subtrator. And
On analyzing the truth table of XOR gate presented in table 3 we found that the output of XOR is similar to the
difference bit of full subtractor, so we can use QCA design of XOR gate presented in figure 7 in designing difference
bit of our subtractor. So by merging these previously mentioned designs the new proposed design of QCA Full-
subtractor circuit is shown below in figure 11(a) and the correctness of result this proposed design is successfully
check using the QCA designer tool and the output is shown in figure 11(b). Here the graph showing A,B and C as
three input and the diff output we get as (0,1,1,0,1,0,0,1)and borrow output we get as (0,1,1,1,0,0,0,1) which are same
as the desired output shown in truth table of full
subtractor presented in table 5.
 (a)

(b)
Fig 4.4 (a)full subtractor QCA circuit,(b) its simulation result.

On counting the cells of full subtractor proposed here we can clearly see that our full subtractor design includes total
17 cells.
For calculating area we have to follow following steps which is shown below:
Step1: Here we can see total 6 cells are presented horizontally and each cell is having 18nm lenth and 18nm
breadth so 18*18nm2 area is being occupied by each cell. So for 6 cells with the particular gap between cells 2nm and
the gap between one cell from its last boundary are 1nm.
So the entire horizontal area of 6 cells = (1+18+2+18+2+18+2+18+2+18+2+18+1) = 120nm
Step2: Next we have on total 5 cells are presented vertically so by following previous similar calculation we have.
the entire vertical area of 5 cells = (1+18+2+18+2+18+2+18+2+18+1) = 100nm
Step 3: Total area occupied = 120nm * 100nm = 12000nm2
So the area occupied by proposed design of full subtractor is about 0.012 μm2.
4.4 QCA ADDER-SUBTRACTOR DESIGN
An adder-subtractor circuit can perform both addition as well as subtraction operation in a single circuit. It works on
three 1-bit numbers taken as input A, input B, and input C, and the one output shows the sum/diff bit and one of the
other two output shows the carry bit and the other one shows borrow bit. In this thesis we present the way how to
make a least area possible cell adder-subtractor circuit using the concept of the least cell design of adder and least cell
design of subtractor circuit present in Ref[28].The below figure present the block diagram for adder- subtractor circuit
with its truth table:

Fig 4.5 Block diagram of an adder-subtractor circuit

Similarity of Equations of adder and subtractor
The equation of adder is

Sum=A⊕B⊕Cin
Carry=AB+BCin+CinA

The equation of subtractor is

Diff= A⊕B⊕Cin
borrow=A’.B+[Link]+BinA’

Here we see that the output SUM bit of adder and Diff bit of subtractor gives the same output as follows:

Sum=Diff =A⊕B⊕Cin
Whereas borrow bit of subtractor and Carry bit of adder is much more similar, here we see the only difference is A
and A’.
The A bit in Carry is seen as A’ bit in borrow:
Cout= A . B+[Link]+Cin.A
borrow= A’. B+[Link]+Bin.A’
 Table 4.3 Truth table of the adder-subtractor circuit
From the above truth table, it is clear that the Sum bit and difference bit is the [Link] below figure shows the
proposed design of the adder-subtractor circuit using the QCA designer tool.

(b)
Fig 4.6 (a)adder-subtractor circuit in QCA, (b) its simulation result.
On counting the cells of adder-subtractor proposed here we can clearly see that our full adder design includes total 26
cells.
For calculating area we have to follow following steps which is shown below:
Step1: Here we can see total 9 cells are presented horizontally and each cell is having 18nm length and 18nm breadth
so 18*18nm2 area is being occupied by each cell. So for 9 cells with the particular gap between cells 2nm and the gap
between one cell from its last boundary are 1nm.
So the entire horizontal area of 9 cells = (1+18+2+18+2+18+2+18+2+18+2+18+2+18+2+18+2+18+1) = 180nm
Step2: Next we have on total 5 cells are presented vertically so by following previous similar calculation we have.
the entire vertical area of 5 cells = (1+18+2+18+2+18+2+18+2+18+1) = 100nm
Step 3: Total area occupied = 180nm * 100nm = 18000nm2
So the area occupied by proposed design of full adder is about 0.018 μm2.

CHAPTER- 5
RESULT AND DISCUSSION
Overview
This Chapter gives the results of the proposed work. Section 5.1 shows the table of comparison of QCA full adder
design between all previous works with proposed work .Section 5.2 shows the table of comparison of QCA full
subtractor design between all previous works with proposed work . Section 5.3 shows the table of comparison of
QCA adder - subtractor design between the all previous works with proposed work .

5.1 TABLE OF COMPARISON OF QCA FULL ADDER DESIGNS

Results of full adder circuit are verified with their respective truth table. Various previous papers are compared and
the comparision table for it is shown below as follows.

[Link] REFERENCE CELL COUNT AREA

1 REF[1] 198 0.206

2 REF[2] 168 0.228

3 REF[3] 154 0.180

4 REF[4] 135 0.144

5 REF[5] 124 0.097

6 REF[6] 107 0.920

7 REF[7] 105 0.146

8 REF[8] 96 0.120

9 REF[9] 95 0.087

10 REF[10] 93 0.086

11 REF[11] 79 0.050

12 REF[12] 73 0.044

13 REF[13] 71 0.060

14 REF[14] 69 0.070

15 REF[15] 63 0.050

16 REF[16] 61 0.030

17 REF[17] 59 0.043

18 REF[18] 52 0.038

19 REF[19] 51 0.034

20 REF[20] 44 0.060

21 REF[21] 41 0.030

22 REF[22] 38 0.020

23 REF[23] 33 0.020

24 REF[24] 31 0.019

25 REF[25] 30 0.011

26 REF[26] 29 0.020

27 REF[27] 23 0.010

28 REF[28] 19 0.014

29 PROPOSED DESIGN 16 0.012

 Table 5.1: Comparision table of QCA Full adder circuit

5.2 TABLE OF COMPARISION OF QCA FULL SUBTRACTOR

DESIGNS
Results of full subtractor circuit are verified with their respective truth table. Various previous papers
are compared and the comparision table for it is shown below as follows.

[Link] REFERENCE CELL COUNT AREA

1 REF[29] 186 0.206

2 REF[3] 154 0.180

3 REF[30] 136 0.168

4 REF[31] 108 0.120

5 REF[32] 104 0.028

6 REF[33] 84 0.027

7 REF[34] 63 0.050

8 REF[35] 53 0.047

9 REF[36] 46 0.015

10 REF[37] 37 0.040

11 REF[38] 32 0.028

12 REF[39] 27 0.030

13 REF[28] 20 0.014

14 PROPOSED DESIGN 17 0.012

Table 5.2: Comparision table of QCA Full subtractor circuit

5.3 TABLE OF COMPARISION OF QCA ADDER-SUBTRACTOR

DESIGNS
Results of adder-subtractor circuit are verified with their respective truth table. Various previous papers
are compared and the comparision table for it is shown below as follows.

[Link]. REFERENCE CELL COUNT AREA

1 REF[40] 228 0.400

2 REF[41] 186 0.132

 3 REF[42] 180 0.190

4 REF[43] 109 0.790

5 REF[44] 90 0.110

6 REF[20] 83 0.090

7 REF[45] 75 0.090

8 REF[46] 54 0.060

9 REF[47] 53 0.039

10 REF[46] 38 0.030

11 PROPOSED DESIGN 26 0.018

Table 5.3: Comparision table of QCA Full adder- subtractor circuit.

The adder, subtractor and adder-subtractor circuit proposed design presented in this paper requires less
cell count and due to decrease in cells in shows reduction in area. And thus found a good design for
application.

CHAPTER- 6
CONCLUSION
AND
FUTURE WORK
Overview-

This chapter focuses on all the information discovered and has a conclusion on achievements. The entire work is
concluded in Section 6.1. Section 6.2 shows the limitations of the designs. Section6.3 gives a discussion of future
work that could be carried.

6.1 CONCLUSION
For designing circuit at nano scale level, QCA is new technology emerging very fast. It seems very suitable to design
highly scalable low power consuming circuits with QCA. Basics of QCA that required for designing purpose is
discussed in this thesis. The proposed design required basic knowledge of wire, clocks and majority gate is discussed
here. The proposed design of adder, subtractor and adder-subtractor here in this thesis uses least number of QCA cells
that minimises area. The correctness of proposed design shows with the simulation result is also present in this thesis.
The simulation result is tested using QCA designer 2.0.3 tool. After comparing proposed design with all previous
design we can conclude that the proposed design gives good result in terms of cells and area thus can be applicable.

6.2 LIMITATION
The proposed adder- subtractor has limitation that can be carried out during future work .The proposed design of
QCA adder- subtractor presented in this thesis has less cell count and required less area but the output waveform of
this design doesn’t show sharp edges. It may create problem in application of this design.

6.3 FUTURE WORK

In future, we will work more to explore new concept so that we can construct more exact output of QCA adder-
subtractor circuit in least cell count and area.
CHAPTER-7
LIST OF PUBLICATIONS
7.1 List of Papers Publications

 Ravi Tiwari, Chinmay chandrakar, Anil Kumar Sahu, Astha Jain, “An
evaluated optimal design of full adder and full subtractor in Quantum-Dot
Cellular Automata” in IJAREEIE volume 11 , issue 3, pp.2320-3765,
March2022.

 Ravi Tiwari, Chinmay chandrakar, Anil Kumar Sahu, Astha Jain, “An Efficient
Least Cell Design Of QCA Adder-Subtractor Circuit ” in IJAREEIE volume 11 ,
issue 3, pp.2320-3765, March2022.