Autogenerated Relay Logic Circuits for test1

Contents
SYSDEL 3
SYSERR 4
SYSINIT.1 5
SYSINIT 6
SYSON 7
GNR 8
GNCR 10
UNR 11
UNCR 12
WNR 13
WNCR 14
YNR 15
EGRNR 16
EMKEY_INR 17
EWNR 18
EUUYR 19
ESUYR 20
SMKEY 21
GSBR 22
NWWNR 23
OYNR 24
GN-UBLR 25
GN-BLR 29
LR 33
WLR 36
NCR1 37
NCR2 38
NCR3 39
RCR1 40
RCR2 41
RCR3 42
Z1NWR 43

2
Z1RWR 44
EWNCNT 45
NWR 46
RWR 48
XR 50
WJR 51
WJR.J 52
WJR1 53
NWCR 54
RWCR 55
NWKR 56
RWKR 57
UCR 58
UCR_ 61
ATR 63
ASR 64
OVSR 72
OVUYR 75
OVJSLR 78
OVJR 80
OYNZ 82
TSR 83
UYR 85
EUUYR_ 92
ESUYR_ 94
JSLR 96
JR 98
EUUYZ 101
ESUYZ 102
INT1HR 103
INT2HR 105
UHR 106
HR 107
ECPR 109
DR 111
JSLR_ 112
JR_ 113
COZ 114
YR 115
EYR 117
JPR 118
JPR.J 119
CHEYZCOUNT 120
NPR 121
VDUFAIL 122
RGKE_FLASH 123
RGKE 125
HGE_FLASH 127
HGKE 128
DGE_FLASH 129
DGKE 130
HGE-_FLASH 131
HGKE- 132
LRKE 133
FLASH- 135
LRK_FLASH 136
OVKE 138
OV_FLASH 140
FLASH 142
UGKE 143
UFLASH 144
RWK_FLASH 145
RWKE 146
RWKRE 147
WLKE 148
NWK_FLASH 149
NWKE 150
NWKRE 151
TKE 152
TKRE 155
TNKRE 156
TNKE 157
SFR_INT 158
SFR_JSLR 159
SFR_NJPR 160
SFR 161
SIG_FAIL_BUZ 162
SIG_FAIL_KE 163
SFMR 164
PFR_INT 165
PFR_JSLR 166
PFR_NJPR 167
PFR 168
PT_FAIL_BUZ 169
PT_FAIL_KE 170
PFMR 171
SYSDEL

ASSIGN ( PROCESSOR_HEALTHY · IO_HELATHY · SYSTEMBUS_OK · COMMUNICATION_OK · ¬ SYSERR · ¬ SYS_INIT · ¬ SYSON ) TO SYSDEL

PROCESSOR HEALTHY IO HELATHY SYSTEMBUS OK COMMUNICATION OK SYSERR SYS INIT SYSON

SYSDEL
Table 1: Figure for SYSDEL

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 6 of 171
SYSERR

ASSIGN ( ¬ SYSDEL · ¬ SYSINIT · ¬ SYSON ) TO SYSERR

SYSDEL SYSINIT SYSON

SYSERR
Table 2: Figure for SYSERR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 7 of 171
SYSINIT.1

ASSIGN ( ( SYSDEL + SYSINIT.1 ) · ¬ SYSERR · ¬ SYSON ) TO SYSINIT.1

SYSDEL SYSERR SYSON

SYSINIT.1
SYSINIT.1

Table 3: Figure for SYSINIT.1

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 8 of 171
SYSINIT

ASSIGN ( SYSINIT.1 ) TO SYSINIT

SYSINIT.1

SYSINIT
Table 4: Figure for SYSINIT

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 9 of 171
SYSON

ASSIGN ( ( ( SYSINIT.1 · SYSINIT ) + SYSON ) · ¬ SYSERR · ¬ SYSDEL ) TO SYSON

SYSINIT.1 SYSINIT SYSERR SYSDEL

SYSON
SYSON

Table 5: Figure for SYSON

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 10 of 171
GNR

ASSIGN ( S01GN-P · ¬ S11GNR · ¬ C11GNR · ¬ S02GNR · ¬ C01GNR · ¬ S04GNR · ¬ S03GNR · ¬ S05GNR · ¬ S08GNR · ¬ S07GNR · ( S01GN_UBLR + EGRNR ) · WNCR · SYSON ) TO S01GNR
S01GN-P S11GNR C11GNR S02GNR C01GNR S04GNR S03GNR S05GNR S08GNR S07GNR S01GN UBLR WNCR SYSON

S01GNR
EGRNR

Table 6: Figure for S01GNR

ASSIGN ( C01GN-P · ¬ S11GNR · ¬ C11GNR · ¬ S02GNR · ¬ S01GNR · ¬ S04GNR · ¬ S03GNR · ¬ S05GNR · ¬ S08GNR · ¬ S07GNR · ( C01GN_UBLR + EGRNR ) · WNCR · SYSON ) TO C01GNR
C01GN-P S11GNR C11GNR S02GNR S01GNR S04GNR S03GNR S05GNR S08GNR S07GNR C01GN UBLR WNCR SYSON

C01GNR
EGRNR

Table 7: Figure for C01GNR

ASSIGN ( S02GN-P · ¬ S11GNR · ¬ C11GNR · ¬ S01GNR · ¬ C01GNR · ¬ S04GNR · ¬ S03GNR · ¬ S05GNR · ¬ S08GNR · ¬ S07GNR · ( S02GN_UBLR + EGRNR ) · WNCR · SYSON ) TO S02GNR
S02GN-P S11GNR C11GNR S01GNR C01GNR S04GNR S03GNR S05GNR S08GNR S07GNR S02GN UBLR WNCR SYSON

S02GNR
EGRNR

Table 8: Figure for S02GNR

ASSIGN ( S03GN-P · ¬ S11GNR · ¬ C11GNR · ¬ S02GNR · ¬ S01GNR · ¬ C01GNR · ¬ S04GNR · ¬ S05GNR · ¬ S08GNR · ¬ S07GNR · ( S03GN_UBLR + EGRNR ) · WNCR · SYSON ) TO S03GNR
S03GN-P S11GNR C11GNR S02GNR S01GNR C01GNR S04GNR S05GNR S08GNR S07GNR S03GN UBLR WNCR SYSON

S03GNR
EGRNR

Table 9: Figure for S03GNR

ASSIGN ( S04GN-P · ¬ S11GNR · ¬ C11GNR · ¬ S02GNR · ¬ S01GNR · ¬ C01GNR · ¬ S03GNR · ¬ S05GNR · ¬ S08GNR · ¬ S07GNR · ( S04GN_UBLR + EGRNR ) · WNCR · SYSON ) TO S04GNR
S04GN-P S11GNR C11GNR S02GNR S01GNR C01GNR S03GNR S05GNR S08GNR S07GNR S04GN UBLR WNCR SYSON

S04GNR
EGRNR

Table 10: Figure for S04GNR

ASSIGN ( S05GN-P · ¬ S11GNR · ¬ C11GNR · ¬ S02GNR · ¬ S01GNR · ¬ C01GNR · ¬ S04GNR · ¬ S03GNR · ¬ S08GNR · ¬ S07GNR · ( S05GN_UBLR + EGRNR ) · WNCR · SYSON ) TO S05GNR
S05GN-P S11GNR C11GNR S02GNR S01GNR C01GNR S04GNR S03GNR S08GNR S07GNR S05GN UBLR WNCR SYSON

S05GNR
EGRNR

Table 11: Figure for S05GNR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 11 of 171
 ASSIGN ( S07GN-P · ¬ S11GNR · ¬ C11GNR · ¬ S02GNR · ¬ S01GNR · ¬ C01GNR · ¬ S04GNR · ¬ S03GNR · ¬ S05GNR · ¬ S08GNR · ( S07GN_UBLR + EGRNR ) · WNCR · SYSON ) TO S07GNR
S07GN-P S11GNR C11GNR S02GNR S01GNR C01GNR S04GNR S03GNR S05GNR S08GNR S07GN UBLR WNCR SYSON

S07GNR
EGRNR

Table 12: Figure for S07GNR

ASSIGN ( S08GN-P · ¬ S11GNR · ¬ C11GNR · ¬ S02GNR · ¬ S01GNR · ¬ C01GNR · ¬ S04GNR · ¬ S03GNR · ¬ S05GNR · ¬ S07GNR · ( S08GN_UBLR + EGRNR ) · WNCR · SYSON ) TO S08GNR
S08GN-P S11GNR C11GNR S02GNR S01GNR C01GNR S04GNR S03GNR S05GNR S07GNR S08GN UBLR WNCR SYSON

S08GNR
EGRNR

Table 13: Figure for S08GNR

ASSIGN ( S11GN-P · ¬ C11GNR · ¬ S02GNR · ¬ S01GNR · ¬ C01GNR · ¬ S04GNR · ¬ S03GNR · ¬ S05GNR · ¬ S08GNR · ¬ S07GNR · ( S11GN_UBLR + EGRNR ) · WNCR · SYSON ) TO S11GNR
S11GN-P C11GNR S02GNR S01GNR C01GNR S04GNR S03GNR S05GNR S08GNR S07GNR S11GN UBLR WNCR SYSON

S11GNR
EGRNR

Table 14: Figure for S11GNR

ASSIGN ( C11GN-P · ¬ S11GNR · ¬ S02GNR · ¬ S01GNR · ¬ C01GNR · ¬ S04GNR · ¬ S03GNR · ¬ S05GNR · ¬ S08GNR · ¬ S07GNR · ( C11GN_UBLR + EGRNR ) · WNCR · SYSON ) TO C11GNR
C11GN-P S11GNR S02GNR S01GNR C01GNR S04GNR S03GNR S05GNR S08GNR S07GNR C11GN UBLR WNCR SYSON

C11GNR
EGRNR

Table 15: Figure for C11GNR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 12 of 171
GNCR

ASSIGN ( ¬ S11GNR · ¬ C11GNR · ¬ S02GNR · ¬ S01GNR · ¬ C01GNR · ¬ S04GNR · ¬ S03GNR · ¬ S05GNR · ¬ S08GNR · ¬ S07GNR ) TO GNCR

S11GNR C11GNR S02GNR S01GNR C01GNR S04GNR S03GNR S05GNR S08GNR S07GNR

GNCR
Table 16: Figure for GNCR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 13 of 171
UNR

ASSIGN ( SMKEY · D-08UN-P · ¬ D-05UNR · ¬ D-04UNR · ¬ D-03UNR · ¬ D-SCHOMEUNR · ¬ D-02UNR · ¬ D-07UNR · ¬ D-KZJHOMEUNR · ¬ GSBR · ¬ GSRBR · ¬ NWWNR · ¬ RWWNR · D-08UN_UBLR · SYSON ) TO D-08UNR
SMKEY D-08UN-P D-05UNR D-04UNR D-03UNR D-SCHOMEUNR D-02UNR D-07UNR D-KZJHOMEUNR GSBR GSRBR NWWNR RWWNR D-08UN UBLR SYSON

D-08UNR
Table 17: Figure for D-08UNR

ASSIGN ( SMKEY · D-07UN-P · ¬ D-05UNR · ¬ D-04UNR · ¬ D-03UNR · ¬ D-SCHOMEUNR · ¬ D-02UNR · ¬ D-08UNR · ¬ D-KZJHOMEUNR · ¬ GSBR · ¬ GSRBR · ¬ NWWNR · ¬ RWWNR · D-07UN_UBLR · SYSON ) TO D-07UNR
SMKEY D-07UN-P D-05UNR D-04UNR D-03UNR D-SCHOMEUNR D-02UNR D-08UNR D-KZJHOMEUNR GSBR GSRBR NWWNR RWWNR D-07UN UBLR SYSON

D-07UNR
Table 18: Figure for D-07UNR

ASSIGN ( SMKEY · D-KZJHOMEUN-P · ¬ D-05UNR · ¬ D-04UNR · ¬ D-03UNR · ¬ D-SCHOMEUNR · ¬ D-02UNR · ¬ D-08UNR · ¬ D-07UNR · ¬ GSBR · ¬ GSRBR · ¬ NWWNR · ¬ RWWNR · D-KZJHOMEUN_UBLR · SYSON ) TO D-KZJHOMEUNR
SMKEY D-KZJHOMEUN-P D-05UNR D-04UNR D-03UNR D-SCHOMEUNR D-02UNR D-08UNR D-07UNR GSBR GSRBR NWWNR RWWNR D-KZJHOMEUN UBLR SYSON

D-KZJHOMEUNR
Table 19: Figure for D-KZJHOMEUNR

ASSIGN ( SMKEY · D-SCHOMEUN-P · ¬ D-05UNR · ¬ D-04UNR · ¬ D-03UNR · ¬ D-02UNR · ¬ D-08UNR · ¬ D-07UNR · ¬ D-KZJHOMEUNR · ¬ GSBR · ¬ GSRBR · ¬ NWWNR · ¬ RWWNR · D-SCHOMEUN_UBLR · SYSON ) TO D-SCHOMEUNR
SMKEY D-SCHOMEUN-P D-05UNR D-04UNR D-03UNR D-02UNR D-08UNR D-07UNR D-KZJHOMEUNR GSBR GSRBR NWWNR RWWNR D-SCHOMEUN UBLR SYSON

D-SCHOMEUNR
Table 20: Figure for D-SCHOMEUNR

ASSIGN ( SMKEY · D-03UN-P · ¬ D-05UNR · ¬ D-04UNR · ¬ D-SCHOMEUNR · ¬ D-02UNR · ¬ D-08UNR · ¬ D-07UNR · ¬ D-KZJHOMEUNR · ¬ GSBR · ¬ GSRBR · ¬ NWWNR · ¬ RWWNR · D-03UN_UBLR · SYSON ) TO D-03UNR
SMKEY D-03UN-P D-05UNR D-04UNR D-SCHOMEUNR D-02UNR D-08UNR D-07UNR D-KZJHOMEUNR GSBR GSRBR NWWNR RWWNR D-03UN UBLR SYSON

D-03UNR
Table 21: Figure for D-03UNR

ASSIGN ( SMKEY · D-05UN-P · ¬ D-04UNR · ¬ D-03UNR · ¬ D-SCHOMEUNR · ¬ D-02UNR · ¬ D-08UNR · ¬ D-07UNR · ¬ D-KZJHOMEUNR · ¬ GSBR · ¬ GSRBR · ¬ NWWNR · ¬ RWWNR · D-05UN_UBLR · SYSON ) TO D-05UNR
SMKEY D-05UN-P D-04UNR D-03UNR D-SCHOMEUNR D-02UNR D-08UNR D-07UNR D-KZJHOMEUNR GSBR GSRBR NWWNR RWWNR D-05UN UBLR SYSON

D-05UNR
Table 22: Figure for D-05UNR

ASSIGN ( SMKEY · D-02UN-P · ¬ D-05UNR · ¬ D-04UNR · ¬ D-03UNR · ¬ D-SCHOMEUNR · ¬ D-08UNR · ¬ D-07UNR · ¬ D-KZJHOMEUNR · ¬ GSBR · ¬ GSRBR · ¬ NWWNR · ¬ RWWNR · D-02UN_UBLR · SYSON ) TO D-02UNR
SMKEY D-02UN-P D-05UNR D-04UNR D-03UNR D-SCHOMEUNR D-08UNR D-07UNR D-KZJHOMEUNR GSBR GSRBR NWWNR RWWNR D-02UN UBLR SYSON

D-02UNR
Table 23: Figure for D-02UNR

ASSIGN ( SMKEY · D-04UN-P · ¬ D-05UNR · ¬ D-03UNR · ¬ D-SCHOMEUNR · ¬ D-02UNR · ¬ D-08UNR · ¬ D-07UNR · ¬ D-KZJHOMEUNR · ¬ GSBR · ¬ GSRBR · ¬ NWWNR · ¬ RWWNR · D-04UN_UBLR · SYSON ) TO D-04UNR
SMKEY D-04UN-P D-05UNR D-03UNR D-SCHOMEUNR D-02UNR D-08UNR D-07UNR D-KZJHOMEUNR GSBR GSRBR NWWNR RWWNR D-04UN UBLR SYSON

D-04UNR
Table 24: Figure for D-04UNR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 14 of 171
UNCR

ASSIGN ( ¬ D-05UNR · ¬ D-04UNR · ¬ D-03UNR · ¬ D-SCHOMEUNR · ¬ D-02UNR · ¬ D-08UNR · ¬ D-07UNR · ¬ D-KZJHOMEUNR · ¬ GSBR · ¬ GSRBR · ¬ NWWNR · ¬ RWWNR ) TO UNCR
D-05UNR D-04UNR D-03UNR D-SCHOMEUNR D-02UNR D-08UNR D-07UNR D-KZJHOMEUNR GSBR GSRBR NWWNR RWWNR

UNCR
Table 25: Figure for UNCR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 15 of 171
WNR

ASSIGN ( 11WN_P · ¬ 13WNR · GNCR · 11WN_UBLR · SYSON ) TO 11WNR

11WN P 13WNR GNCR 11WN UBLR SYSON

11WNR
Table 26: Figure for 11WNR

ASSIGN ( 13WN_P · ¬ 11WNR · GNCR · 13WN_UBLR · SYSON ) TO 13WNR

13WN P 11WNR GNCR 13WN UBLR SYSON

13WNR
Table 27: Figure for 13WNR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 16 of 171
WNCR

ASSIGN ( ¬ 11WNR · ¬ 13WNR ) TO WNCR

11WNR 13WNR

WNCR
Table 28: Figure for WNCR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 17 of 171
YNR

ASSIGN ( CH1YN_P · ¬ CH2YNR ) TO CH1YNR

CH1YN P CH2YNR

CH1YNR
Table 29: Figure for CH1YNR

ASSIGN ( CH2YN_P · ¬ CH1YNR ) TO CH2YNR

CH2YN P CH1YNR

CH2YNR
Table 30: Figure for CH2YNR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 18 of 171
EGRNR

ASSIGN ( EGRN_P · SYSON ) TO EGRNR

EGRN P SYSON

EGRNR
Table 31: Figure for EGRNR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 19 of 171
EMKEY_INR

ASSIGN ( EMKEY_IN · SYSON ) TO EMKEY_INR

EMKEY IN SYSON

EMKEY INR
Table 32: Figure for EMKEY_INR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 20 of 171
EWNR

ASSIGN ( EWN_P · EMKEY_INR · SYSON ) TO EWNR

EWN P EMKEY INR SYSON

EWNR
Table 33: Figure for EWNR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 21 of 171
EUUYR

ASSIGN ( EUUN_P · SMKEY · ¬ ESUYNR · SYSON ) TO EUUYR

EUUN P SMKEY ESUYNR SYSON

EUUYR
Table 34: Figure for EUUYR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 22 of 171
ESUYR

ASSIGN ( ESUN_P · SMKEY · EMKEY_INR · ¬ EUUYNR · SYSON ) TO ESUYR

ESUN P SMKEY EMKEY INR EUUYNR SYSON

ESUYR
Table 35: Figure for ESUYR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 23 of 171
SMKEY

ASSIGN ( SMKEY_IN1 + SMKEY_IN2 ) TO SMKEY

SMKEY IN1

SMKEY
SMKEY IN2

Table 36: Figure for SMKEY

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 24 of 171
GSBR

ASSIGN ( SMKEY · GSB_P · ¬ D-05UNR · ¬ D-04UNR · ¬ D-03UNR · ¬ D-SCHOMEUNR · ¬ D-02UNR · ¬ D-08UNR · ¬ D-07UNR · ¬ D-KZJHOMEUNR · ¬ GSRBR · ¬ NWWNR · ¬ RWWNR · SYSON ) TO GSBR
SMKEY GSB P D-05UNR D-04UNR D-03UNR D-SCHOMEUNR D-02UNR D-08UNR D-07UNR D-KZJHOMEUNR GSRBR NWWNR RWWNR SYSON

GSBR
Table 37: Figure for GSBR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 25 of 171
NWWNR

ASSIGN ( SMKEY · NWWN_P · ¬ D-05UNR · ¬ D-04UNR · ¬ D-03UNR · ¬ D-SCHOMEUNR · ¬ D-02UNR · ¬ D-08UNR · ¬ D-07UNR · ¬ D-KZJHOMEUNR · ¬ GSBR · ¬ GSRBR · ¬ RWWNR · SYSON ) TO NWWNR
SMKEY NWWN P D-05UNR D-04UNR D-03UNR D-SCHOMEUNR D-02UNR D-08UNR D-07UNR D-KZJHOMEUNR GSBR GSRBR RWWNR SYSON

NWWNR
Table 38: Figure for NWWNR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 26 of 171
OYNR

ASSIGN ( SMKEY · OYN_P · ¬ EUUYR · ¬ ESUYR · SYSON ) TO OYNR

SMKEY OYN P EUUYR ESUYR SYSON

OYNR
Table 39: Figure for OYNR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 27 of 171
GN-UBLR

ASSIGN ( ( ( ( S01GN-UBL + ( ALLGN-UBL ) ) · SMKEY ) + ( S01GN-UBLR · ¬ S01GN-BLR ) ) · SYSON ) TO S01GN-UBLR

S01GN-UBL SMKEY SYSON

S01GN-UBLR
ALLGN-UBL

S01GN-UBLR S01GN-BLR

Table 40: Figure for S01GN-UBLR

ASSIGN ( ( ( ( C01GN-UBL + ( ALLGN-UBL ) ) · SMKEY ) + ( C01GN-UBLR · ¬ C01GN-BLR ) ) · SYSON ) TO C01GN-UBLR

C01GN-UBL SMKEY SYSON

C01GN-UBLR
ALLGN-UBL

C01GN-UBLR C01GN-BLR

Table 41: Figure for C01GN-UBLR

ASSIGN ( ( ( ( S02GN-UBL + ( ALLGN-UBL ) ) · SMKEY ) + ( S02GN-UBLR · ¬ S02GN-BLR ) ) · SYSON ) TO S02GN-UBLR

S02GN-UBL SMKEY SYSON

S02GN-UBLR
ALLGN-UBL

S02GN-UBLR S02GN-BLR

Table 42: Figure for S02GN-UBLR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 28 of 171
 ASSIGN ( ( ( ( S03GN-UBL + ( ALLGN-UBL ) ) · SMKEY ) + ( S03GN-UBLR · ¬ S03GN-BLR ) ) · SYSON ) TO S03GN-UBLR

S03GN-UBL SMKEY SYSON

S03GN-UBLR
ALLGN-UBL

S03GN-UBLR S03GN-BLR

Table 43: Figure for S03GN-UBLR

ASSIGN ( ( ( ( S04GN-UBL + ( ALLGN-UBL ) ) · SMKEY ) + ( S04GN-UBLR · ¬ S04GN-BLR ) ) · SYSON ) TO S04GN-UBLR

S04GN-UBL SMKEY SYSON

S04GN-UBLR
ALLGN-UBL

S04GN-UBLR S04GN-BLR

Table 44: Figure for S04GN-UBLR

ASSIGN ( ( ( ( S05GN-UBL + ( ALLGN-UBL ) ) · SMKEY ) + ( S05GN-UBLR · ¬ S05GN-BLR ) ) · SYSON ) TO S05GN-UBLR

S05GN-UBL SMKEY SYSON

S05GN-UBLR
ALLGN-UBL

S05GN-UBLR S05GN-BLR

Table 45: Figure for S05GN-UBLR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 29 of 171
 ASSIGN ( ( ( ( S07GN-UBL + ( ALLGN-UBL ) ) · SMKEY ) + ( S07GN-UBLR · ¬ S07GN-BLR ) ) · SYSON ) TO S07GN-UBLR

S07GN-UBL SMKEY SYSON

S07GN-UBLR
ALLGN-UBL

S07GN-UBLR S07GN-BLR

Table 46: Figure for S07GN-UBLR

ASSIGN ( ( ( ( S08GN-UBL + ( ALLGN-UBL ) ) · SMKEY ) + ( S08GN-UBLR · ¬ S08GN-BLR ) ) · SYSON ) TO S08GN-UBLR

S08GN-UBL SMKEY SYSON

S08GN-UBLR
ALLGN-UBL

S08GN-UBLR S08GN-BLR

Table 47: Figure for S08GN-UBLR

ASSIGN ( ( ( ( S11GN-UBL + ( ALLGN-UBL ) ) · SMKEY ) + ( S11GN-UBLR · ¬ S11GN-BLR ) ) · SYSON ) TO S11GN-UBLR

S11GN-UBL SMKEY SYSON

S11GN-UBLR
ALLGN-UBL

S11GN-UBLR S11GN-BLR

Table 48: Figure for S11GN-UBLR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 30 of 171
 ASSIGN ( ( ( ( C11GN-UBL + ( ALLGN-UBL ) ) · SMKEY ) + ( C11GN-UBLR · ¬ C11GN-BLR ) ) · SYSON ) TO C11GN-UBLR

C11GN-UBL SMKEY SYSON

C11GN-UBLR
ALLGN-UBL

C11GN-UBLR C11GN-BLR

Table 49: Figure for C11GN-UBLR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 31 of 171
GN-BLR

ASSIGN ( S01GN-BL + ( S01GN-BLR · ¬ S01GN-UBLR ) + ( SYSINIT1 · ¬ SYSON ) ) TO S01GN-BLR

S01GN-BL

S01GN-BLR
S01GN-BLR S01GN-UBLR

SYSINIT1 SYSON

Table 50: Figure for S01GN-BLR

ASSIGN ( C01GN-BL + ( C01GN-BLR · ¬ C01GN-UBLR ) + ( SYSINIT1 · ¬ SYSON ) ) TO C01GN-BLR

C01GN-BL

C01GN-BLR
C01GN-BLR C01GN-UBLR

SYSINIT1 SYSON

Table 51: Figure for C01GN-BLR

ASSIGN ( S02GN-BL + ( S02GN-BLR · ¬ S02GN-UBLR ) + ( SYSINIT1 · ¬ SYSON ) ) TO S02GN-BLR

S02GN-BL

S02GN-BLR
S02GN-BLR S02GN-UBLR

SYSINIT1 SYSON

Table 52: Figure for S02GN-BLR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 32 of 171
 ASSIGN ( S03GN-BL + ( S03GN-BLR · ¬ S03GN-UBLR ) + ( SYSINIT1 · ¬ SYSON ) ) TO S03GN-BLR

S03GN-BL

S03GN-BLR
S03GN-BLR S03GN-UBLR

SYSINIT1 SYSON

Table 53: Figure for S03GN-BLR

ASSIGN ( S04GN-BL + ( S04GN-BLR · ¬ S04GN-UBLR ) + ( SYSINIT1 · ¬ SYSON ) ) TO S04GN-BLR

S04GN-BL

S04GN-BLR
S04GN-BLR S04GN-UBLR

SYSINIT1 SYSON

Table 54: Figure for S04GN-BLR

ASSIGN ( S05GN-BL + ( S05GN-BLR · ¬ S05GN-UBLR ) + ( SYSINIT1 · ¬ SYSON ) ) TO S05GN-BLR

S05GN-BL

S05GN-BLR
S05GN-BLR S05GN-UBLR

SYSINIT1 SYSON

Table 55: Figure for S05GN-BLR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 33 of 171
 ASSIGN ( S07GN-BL + ( S07GN-BLR · ¬ S07GN-UBLR ) + ( SYSINIT1 · ¬ SYSON ) ) TO S07GN-BLR

S07GN-BL

S07GN-BLR
S07GN-BLR S07GN-UBLR

SYSINIT1 SYSON

Table 56: Figure for S07GN-BLR

ASSIGN ( S08GN-BL + ( S08GN-BLR · ¬ S08GN-UBLR ) + ( SYSINIT1 · ¬ SYSON ) ) TO S08GN-BLR

S08GN-BL

S08GN-BLR
S08GN-BLR S08GN-UBLR

SYSINIT1 SYSON

Table 57: Figure for S08GN-BLR

ASSIGN ( S11GN-BL + ( S11GN-BLR · ¬ S11GN-UBLR ) + ( SYSINIT1 · ¬ SYSON ) ) TO S11GN-BLR

S11GN-BL

S11GN-BLR
S11GN-BLR S11GN-UBLR

SYSINIT1 SYSON

Table 58: Figure for S11GN-BLR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 34 of 171
 ASSIGN ( C11GN-BL + ( C11GN-BLR · ¬ C11GN-UBLR ) + ( SYSINIT1 · ¬ SYSON ) ) TO C11GN-BLR

C11GN-BL

C11GN-BLR
C11GN-BLR C11GN-UBLR

SYSINIT1 SYSON

Table 59: Figure for C11GN-BLR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 35 of 171
LR

ASSIGN ( ( ( S01GNR · D-03UNR · S01ASR · S03OVSR ) + S01ALR ) · ¬ S01ESUYR · ¬ S01EUUYR · ( ¬ S01UYR1 ) · ( ( ( 11WLR + 11NWR ) · ¬ 11RCR1 ) · ( ( 13WLR + 13NWR ) · ¬ 13RCR1 ) ) · ( ( S11ASR · C11ASR ) + 13RWR ) · ( ¬
S01GNR + ¬ EGRNR ) · ¬ VDU-FAIL ) TO S01ALR
S01GNR D-03UNR S01ASR S03OVSR S01ESUYR S01EUUYR S01UYR1 11WLR 11RCR1 13WLR 13RCR1 S11ASR C11ASR S01GNR VDU-FAIL

S01ALR
11NWR 13NWR EGRNR
S01ALR 13RWR

Table 60: Figure for S01ALR

ASSIGN ( ( ( S01GNR · D-05UNR · S01ASR · S05OVSR ) + S01BLR ) · ¬ S01ESUYR · ¬ S01EUUYR · ( ¬ S01UYR1 ) · ( ( ( 11WLR + 11RWR ) · ¬ 11NCR1 ) · ( ( 13WLR + 13RWR ) · ¬ 13NCR1 ) ) · ( ¬ S01GNR + ¬ EGRNR ) · ¬ VDU-FAIL ) TO
S01BLR
S01GNR D-05UNR S01ASR S05OVSR S01ESUYR S01EUUYR S01UYR1 11WLR 11NCR1 13WLR 13NCR1 S01GNR VDU-FAIL

S01BLR
11RWR 13RWR EGRNR
S01BLR

Table 61: Figure for S01BLR

ASSIGN ( ( ( C01GNR · D-03UNR ) + C01ALR ) · ¬ C01ESUYR · ¬ C01EUUYR · ( ( ( 11WLR + 11NWR ) · ¬ 11RCR1 ) ) · ¬ S01HECR · ¬ S01DECR · ( ( S11ASR · C11ASR ) + 13RWR ) · ( ¬ C01GNR + ¬ EGRNR ) · ¬ VDU-FAIL ) TO C01ALR
C01GNR D-03UNR C01ESUYR C01EUUYR 11WLR 11RCR1 S01HECR S01DECR S11ASR C11ASR C01GNR VDU-FAIL

C01ALR
11NWR EGRNR
C01ALR 13RWR

Table 62: Figure for C01ALR

ASSIGN ( ( ( C01GNR · D-05UNR ) + C01BLR ) · ¬ C01ESUYR · ¬ C01EUUYR · ( ( ( 11WLR + 11RWR ) · ¬ 11NCR1 ) ) · ¬ S01HECR · ¬ S01DECR · ( ¬ C01GNR + ¬ EGRNR ) · ¬ VDU-FAIL ) TO C01BLR

C01GNR D-05UNR C01ESUYR C01EUUYR 11WLR 11NCR1 S01HECR S01DECR C01GNR VDU-FAIL

C01BLR
11RWR EGRNR
C01BLR

Table 63: Figure for C01BLR

ASSIGN ( ( ( S02GNR · D-08UNR · S02ASR ) + S02LR ) · ¬ S02ESUYR · ¬ S02EUUYR · ( ¬ S02UYR1 + S02HR ) · ( ( ( 11WLR + 11NWR ) · ¬ 11RCR1 ) ) · ( ¬ S02GNR + ¬ EGRNR ) · ¬ VDU-FAIL ) TO S02LR

S02GNR D-08UNR S02ASR S02ESUYR S02EUUYR S02UYR1 11WLR 11RCR1 S02GNR VDU-FAIL

S02LR
S02HR 11NWR EGRNR
S02LR

Table 64: Figure for S02LR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 36 of 171
 ASSIGN ( ( ( S03GNR · D-07UNR · S03ASR ) + S03LR ) · ¬ S03ESUYR · ¬ S03EUUYR · ( ¬ S03UYR1 + S03HR ) · ( ( ( 13WLR + 13NWR ) · ¬ 13RCR1 ) ) · ( ¬ S03GNR + ¬ EGRNR ) · ¬ VDU-FAIL ) TO S03LR

S03GNR D-07UNR S03ASR S03ESUYR S03EUUYR S03UYR1 13WLR 13RCR1 S03GNR VDU-FAIL

S03LR
S03HR 13NWR EGRNR
S03LR

Table 65: Figure for S03LR

ASSIGN ( ( ( S04GNR · D-08UNR · S04ASR ) + S04LR ) · ¬ S04ESUYR · ¬ S04EUUYR · ( ¬ S04UYR1 + S04HR ) · ( ( ( 11WLR + 11RWR ) · ¬ 11NCR1 ) ) · ( ¬ S04GNR + ¬ EGRNR ) · ¬ VDU-FAIL ) TO S04LR

S04GNR D-08UNR S04ASR S04ESUYR S04EUUYR S04UYR1 11WLR 11NCR1 S04GNR VDU-FAIL

S04LR
S04HR 11RWR EGRNR
S04LR

Table 66: Figure for S04LR

ASSIGN ( ( ( S05GNR · D-07UNR · S05ASR ) + S05LR ) · ¬ S05ESUYR · ¬ S05EUUYR · ( ¬ S05UYR1 + S05HR ) · ( ( ( 13WLR + 13RWR ) · ¬ 13NCR1 ) ) · ( ¬ S05GNR + ¬ EGRNR ) · ¬ VDU-FAIL ) TO S05LR

S05GNR D-07UNR S05ASR S05ESUYR S05EUUYR S05UYR1 13WLR 13NCR1 S05GNR VDU-FAIL

S05LR
S05HR 13RWR EGRNR
S05LR

Table 67: Figure for S05LR

ASSIGN ( ( ( S07GNR · D-KZJHOMEUNR · S07ASR ) + S07LR ) · ¬ S07ESUYR · ¬ S07EUUYR · ( ¬ S07UYR1 ) · ( ¬ S07GNR + ¬ EGRNR ) · ¬ VDU-FAIL ) TO S07LR

S07GNR D-KZJHOMEUNR S07ASR S07ESUYR S07EUUYR S07UYR1 S07GNR VDU-FAIL

S07LR
EGRNR
S07LR

Table 68: Figure for S07LR

ASSIGN ( ( ( S08GNR · D-SCHOMEUNR · S08ASR ) + S08LR ) · ¬ S08ESUYR · ¬ S08EUUYR · ( ¬ S08UYR1 ) · ( ¬ S08GNR + ¬ EGRNR ) · ¬ VDU-FAIL ) TO S08LR

S08GNR D-SCHOMEUNR S08ASR S08ESUYR S08EUUYR S08UYR1 S08GNR VDU-FAIL

S08LR
EGRNR
S08LR

Table 69: Figure for S08LR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 37 of 171
 ASSIGN ( ( ( S11GNR · D-02UNR · S11ASR · S02OVSR ) + S11ALR ) · ¬ S11ESUYR · ¬ S11EUUYR · ( ¬ S11UYR1 ) · ( ( ( 13WLR + 13NWR ) · ¬ 13RCR1 ) · ( ( 11WLR + 11NWR ) · ¬ 11RCR1 ) ) · ( ( S01ASR · C01ASR ) + 11RWR ) · ( ¬
S11GNR + ¬ EGRNR ) · ¬ VDU-FAIL ) TO S11ALR
S11GNR D-02UNR S11ASR S02OVSR S11ESUYR S11EUUYR S11UYR1 13WLR 13RCR1 11WLR 11RCR1 S01ASR C01ASR S11GNR VDU-FAIL

S11ALR
13NWR 11NWR EGRNR
S11ALR 11RWR

Table 70: Figure for S11ALR

ASSIGN ( ( ( S11GNR · D-04UNR · S11ASR · S04OVSR ) + S11ELR ) · ¬ S11ESUYR · ¬ S11EUUYR · ( ¬ S11UYR1 ) · ( ( ( 13WLR + 13RWR ) · ¬ 13NCR1 ) · ( ( 11WLR + 11RWR ) · ¬ 11NCR1 ) ) · ( ¬ S11GNR + ¬ EGRNR ) · ¬ VDU-FAIL ) TO
S11ELR
S11GNR D-04UNR S11ASR S04OVSR S11ESUYR S11EUUYR S11UYR1 13WLR 13NCR1 11WLR 11NCR1 S11GNR VDU-FAIL

S11ELR
13RWR 11RWR EGRNR
S11ELR

Table 71: Figure for S11ELR

ASSIGN ( ( ( C11GNR · D-02UNR ) + C11ALR ) · ¬ C11ESUYR · ¬ C11EUUYR · ¬ T14TPR · ( ( ( 13WLR + 13NWR ) · ¬ 13RCR1 ) ) · ¬ S11HECR · ¬ S11DECR · ( ( S01ASR · C01ASR ) + 11RWR ) · ( ¬ C11GNR + ¬ EGRNR ) · ¬ VDU-FAIL ) TO
C11ALR
C11GNR D-02UNR C11ESUYR C11EUUYR T14TPR 13WLR 13RCR1 S11HECR S11DECR S01ASR C01ASR C11GNR VDU-FAIL

C11ALR
13NWR EGRNR
C11ALR 11RWR

Table 72: Figure for C11ALR

ASSIGN ( ( ( C11GNR · D-04UNR ) + C11ELR ) · ¬ C11ESUYR · ¬ C11EUUYR · ¬ T14TPR · ( ( ( 13WLR + 13RWR ) · ¬ 13NCR1 ) ) · ¬ S11HECR · ¬ S11DECR · ( ¬ C11GNR + ¬ EGRNR ) · ¬ VDU-FAIL ) TO C11ELR
C11GNR D-04UNR C11ESUYR C11EUUYR T14TPR 13WLR 13NCR1 S11HECR S11DECR C11GNR VDU-FAIL

C11ELR
13RWR EGRNR
C11ELR

Table 73: Figure for C11ELR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 38 of 171
WLR

ASSIGN ( ( ( C01ASR ) ) · ( ( S01ASR ) ) · ( ( S02ASR ) ) · ( ( S04ASR ) ) · ( ( S02OVSR ) ) · ( ( S04OVSR ) ) ) TO 11WLR

C01ASR S01ASR S02ASR S04ASR S02OVSR S04OVSR

11WLR
Table 74: Figure for 11WLR

ASSIGN ( ( ( C11ASR ) ) · ( ( S03ASR ) ) · ( ( S05ASR ) ) · ( ( S11ASR ) ) · ( ( S03OVSR ) ) · ( ( S05OVSR ) ) ) TO 13WLR

C11ASR S03ASR S05ASR S11ASR S03OVSR S05OVSR

13WLR
Table 75: Figure for 13WLR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 39 of 171
NCR1

ASSIGN ( C01ALR + S01ALR + S02LR + S11ALR ) TO 11NCR1

C01ALR

11NCR1
S01ALR

S02LR

S11ALR

Table 76: Figure for 11NCR1

ASSIGN ( C11ALR + S03LR + S11ALR + S01ALR ) TO 13NCR1

C11ALR

13NCR1
S03LR

S11ALR

S01ALR

Table 77: Figure for 13NCR1

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 40 of 171
NCR2

ASSIGN ( 11NCR1 · ¬ 11NWR · ¬ 11RCR2 ) TO 11NCR2

11NCR1 11NWR 11RCR2

11NCR2
Table 78: Figure for 11NCR2

ASSIGN ( 13NCR1 · ¬ 13NWR · ¬ 13RCR2 ) TO 13NCR2

13NCR1 13NWR 13RCR2

13NCR2
Table 79: Figure for 13NCR2

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 41 of 171
NCR3

ASSIGN ( 11NCR1 · ( 11NCR2 + 11NCR3 ) · ¬ 11NWKR ) TO 11NCR3

11NCR1 11NCR2 11NWKR

11NCR3
11NCR3

Table 80: Figure for 11NCR3

ASSIGN ( 13NCR1 · ( 13NCR2 + 13NCR3 ) · ¬ 13NWKR ) TO 13NCR3

13NCR1 13NCR2 13NWKR

13NCR3
13NCR3

Table 81: Figure for 13NCR3

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 42 of 171
RCR1

ASSIGN ( C01BLR + S01BLR + S04LR + S11ELR ) TO 11RCR1

C01BLR

11RCR1
S01BLR

S04LR

S11ELR

Table 82: Figure for 11RCR1

ASSIGN ( C11ELR + S05LR + S11ELR + S01BLR ) TO 13RCR1

C11ELR

13RCR1
S05LR

S11ELR

S01BLR

Table 83: Figure for 13RCR1

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 43 of 171
RCR2

ASSIGN ( 11RCR1 · ¬ 11RWR · ¬ 11NCR2 ) TO 11RCR2

11RCR1 11RWR 11NCR2

11RCR2
Table 84: Figure for 11RCR2

ASSIGN ( 13RCR1 · ¬ 13RWR · ¬ 13NCR2 ) TO 13RCR2

13RCR1 13RWR 13NCR2

13RCR2
Table 85: Figure for 13RCR2

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 44 of 171
RCR3

ASSIGN ( 11RCR1 · ( 11RCR2 + 11RCR3 ) · ¬ 11RWKR ) TO 11RCR3

11RCR1 11RCR2 11RWKR

11RCR3
11RCR3

Table 86: Figure for 11RCR3

ASSIGN ( 13RCR1 · ( 13RCR2 + 13RCR3 ) · ¬ 13RWKR ) TO 13RCR3

13RCR1 13RCR2 13RWKR

13RCR3
13RCR3

Table 87: Figure for 13RCR3

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 45 of 171
Z1NWR

ASSIGN ( ( ( ( ( 11ATPR · 13BTPR · ¬ EWNR ) + ( ( ¬ 11ATPR + ¬ 13BTPR ) · EWNR ) ) · 11WNR · NWWNR ) + ( 11NCR2 · 11ATPR · 13BTPR · CH1ZPR ) ) · ¬ 11WN_BLR ) TO 11Z1NWR

11ATPR 13BTPR EWNR 11WNR NWWNR 11WN BLR

11Z1NWR
11ATPR EWNR

13BTPR

11NCR2 11ATPR 13BTPR CH1ZPR

Table 88: Figure for 11Z1NWR

ASSIGN ( ( ( ( ( 13ATPR · T3TPR · ¬ EWNR ) + ( ( ¬ 13ATPR + ¬ T3TPR ) · EWNR ) ) · 13WNR · NWWNR ) + ( 13NCR2 · 13ATPR · T3TPR · CH2ZPR ) ) · ¬ 13WN_BLR ) TO 13Z1NWR

13ATPR T3TPR EWNR 13WNR NWWNR 13WN BLR

13Z1NWR
13ATPR EWNR

T3TPR

13NCR2 13ATPR T3TPR CH2ZPR

Table 89: Figure for 13Z1NWR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 46 of 171
Z1RWR

ASSIGN ( ( ( ( ( 11ATPR · 13BTPR · ¬ EWNR ) + ( ( ¬ 11ATPR + ¬ 13BTPR ) · EWNR ) ) · 11WNR · RWWNR ) + ( 11RCR2 · 11ATPR · 13BTPR · CH1ZPR ) ) · ¬ 11WN_BLR ) TO 11Z1RWR

11ATPR 13BTPR EWNR 11WNR RWWNR 11WN BLR

11Z1RWR
11ATPR EWNR

13BTPR

11RCR2 11ATPR 13BTPR CH1ZPR

Table 90: Figure for 11Z1RWR

ASSIGN ( ( ( ( ( 13ATPR · T3TPR · ¬ EWNR ) + ( ( ¬ 13ATPR + ¬ T3TPR ) · EWNR ) ) · 13WNR · RWWNR ) + ( 13RCR2 · 13ATPR · T3TPR · CH2ZPR ) ) · ¬ 13WN_BLR ) TO 13Z1RWR

13ATPR T3TPR EWNR 13WNR RWWNR 13WN BLR

13Z1RWR
13ATPR EWNR

T3TPR

13RCR2 13ATPR T3TPR CH2ZPR

Table 91: Figure for 13Z1RWR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 47 of 171
EWNCNT

ASSIGN ( EWNR · SYSON ) TO EWNCNT

EWNR SYSON

EWNCNT
Table 92: Figure for EWNCNT

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 48 of 171
NWR

ASSIGN ( ( ( ( ( ( 11ATPR · 13BTPR · ¬ EWNR ) + ( ( ¬ 11ATPR + ¬ 13BTPR ) · EWNR ) ) · 11WLR ) · ( ( ( 11WNR · NWWNR · ¬ 11NCR1 · ¬ 11RCR1 ) + ( ( ¬ 11WNR + ( ¬ NWWNR · ¬ RWWNR ) ) · ¬ EWNR · 11NCR2 · CH1ZPR ) ) · ¬ 11NWKR
) ) + ( ( ( 11NWR · ( 11NCR3 + ¬ 11Z1RWR + ¬ 11WLR ) ) + ( ¬ 11NWR · 11NDKR · ¬ 11RDKR · ¬ SYSON · SYSINIT ) ) ) ) · ¬ 11RWR ) TO 11NWR

11ATPR 13BTPR EWNR 11WLR 11WNR NWWNR 11NCR1 11RCR1 11NWKR 11RWR

11NWR
11ATPR EWNR 11WNR EWNR 11NCR2 CH1ZPR

13BTPR NWWNR RWWNR

11NWR 11NCR3

11Z1RWR

11WLR

11NWR 11NDKR 11RDKR SYSON SYSINIT

Table 93: Figure for 11NWR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 49 of 171
 ASSIGN ( ( ( ( ( ( 13ATPR · T3TPR · ¬ EWNR ) + ( ( ¬ 13ATPR + ¬ T3TPR ) · EWNR ) ) · 13WLR ) · ( ( ( 13WNR · NWWNR · ¬ 13NCR1 · ¬ 13RCR1 ) + ( ( ¬ 13WNR + ( ¬ NWWNR · ¬ RWWNR ) ) · ¬ EWNR · 13NCR2 · CH2ZPR ) ) · ¬ 13NWKR )
) + ( ( ( 13NWR · ( 13NCR3 + ¬ 13Z1RWR + ¬ 13WLR ) ) + ( ¬ 13NWR · 13NDKR · ¬ 13RDKR · ¬ SYSON · SYSINIT ) ) ) ) · ¬ 13RWR ) TO 13NWR

13ATPR T3TPR EWNR 13WLR 13WNR NWWNR 13NCR1 13RCR1 13NWKR 13RWR

13NWR
13ATPR EWNR 13WNR EWNR 13NCR2 CH2ZPR

T3TPR NWWNR RWWNR

13NWR 13NCR3

13Z1RWR

13WLR

13NWR 13NDKR 13RDKR SYSON SYSINIT

Table 94: Figure for 13NWR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 50 of 171
RWR

ASSIGN ( ( ( ( ( ( 11ATPR · 13BTPR · ¬ EWNR ) + ( ( ¬ 11ATPR + ¬ 13BTPR ) · EWNR ) ) · 11WLR ) · ( ( ( 11WNR · RWWNR · ¬ 11RCR1 · ¬ 11NCR1 ) + ( ( ¬ 11WNR + ( ¬ NWWNR · ¬ RWWNR ) ) · ¬ EWNR · 11RCR2 · CH1ZPR ) ) · ¬ 11RWKR
) ) + ( ( ( 11RWR · ( 11RCR3 + ¬ 11Z1NWR + ¬ 11WLR ) ) + ( ¬ 11RWR · 11RDKR · ¬ 11NDKR · ¬ SYSON · SYSINIT ) ) ) ) · ¬ 11NWR ) TO 11RWR

11ATPR 13BTPR EWNR 11WLR 11WNR RWWNR 11RCR1 11NCR1 11RWKR 11NWR

11RWR
11ATPR EWNR 11WNR EWNR 11RCR2 CH1ZPR

13BTPR NWWNR RWWNR

11RWR 11RCR3

11Z1NWR

11WLR

11RWR 11RDKR 11NDKR SYSON SYSINIT

Table 95: Figure for 11RWR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 51 of 171
 ASSIGN ( ( ( ( ( ( 13ATPR · T3TPR · ¬ EWNR ) + ( ( ¬ 13ATPR + ¬ T3TPR ) · EWNR ) ) · 13WLR ) · ( ( ( 13WNR · RWWNR · ¬ 13RCR1 · ¬ 13NCR1 ) + ( ( ¬ 13WNR + ( ¬ NWWNR · ¬ RWWNR ) ) · ¬ EWNR · 13RCR2 · CH2ZPR ) ) · ¬ 13RWKR )
) + ( ( ( 13RWR · ( 13RCR3 + ¬ 13Z1NWR + ¬ 13WLR ) ) + ( ¬ 13RWR · 13RDKR · ¬ 13NDKR · ¬ SYSON · SYSINIT ) ) ) ) · ¬ 13NWR ) TO 13RWR

13ATPR T3TPR EWNR 13WLR 13WNR RWWNR 13RCR1 13NCR1 13RWKR 13NWR

13RWR
13ATPR EWNR 13WNR EWNR 13RCR2 CH2ZPR

T3TPR NWWNR RWWNR

13RWR 13RCR3

13Z1NWR

13WLR

13RWR 13RDKR 13NDKR SYSON SYSINIT

Table 96: Figure for 13RWR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 52 of 171
XR

ASSIGN ( ¬ WJR.J · ( ( ¬ NCR1 · ¬ RCR1 ) + 11XR ) ) TO 11XR

WJR.J NCR1 RCR1

11XR
11XR

Table 97: Figure for 11XR

ASSIGN ( ¬ WJR.J · ( ( ¬ NCR1 · ¬ RCR1 ) + 13XR ) ) TO 13XR

WJR.J NCR1 RCR1

13XR
13XR

Table 98: Figure for 13XR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 53 of 171
WJR

ASSIGN ( 11WLR · ( ( 11Z1NWR · 11NWR ) + ( 11Z1RWR · 11RWR ) ) · 11XR ) TO 11WJR

11WLR 11Z1NWR 11NWR 11XR

11WJR
11Z1RWR 11RWR

Table 99: Figure for 11WJR

ASSIGN ( 13WLR · ( ( 13Z1NWR · 13NWR ) + ( 13Z1RWR · 13RWR ) ) · 13XR ) TO 13WJR

13WLR 13Z1NWR 13NWR 13XR

13WJR
13Z1RWR 13RWR

Table 100: Figure for 13WJR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 54 of 171
WJR.J

ASSIGN ( ( 11WJR + ( 11WJR.J · ¬ 11NWKR · ¬ 11RWKR ) ) · 11WJR1 ) TO 11WJR.J

11WJR 11WJR1

11WJR.J
11WJR.J 11NWKR 11RWKR

Table 101: Figure for 11WJR.J

ASSIGN ( ( 13WJR + ( 13WJR.J · ¬ 13NWKR · ¬ 13RWKR ) ) · 13WJR1 ) TO 13WJR.J

13WJR 13WJR1

13WJR.J
13WJR.J 13NWKR 13RWKR

Table 102: Figure for 13WJR.J

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 55 of 171
WJR1

ASSIGN ( ¬ 11WJR.J · 11WJR · SYSON ) TO 11WJR1

11WJR.J 11WJR SYSON

11WJR1
Table 103: Figure for 11WJR1

ASSIGN ( ¬ 13WJR.J · 13WJR · SYSON ) TO 13WJR1

13WJR.J 13WJR SYSON

13WJR1
Table 104: Figure for 13WJR1

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 56 of 171
NWCR

ASSIGN ( ¬ 11RWCR · ¬ 11NWKR · ¬ 11RWKR · ¬ 11XR · ( 11WJR.J + 11WJR ) · 11WLR · 11NWR · SYSON ) TO 11NWCR

11RWCR 11NWKR 11RWKR 11XR 11WJR.J 11WLR 11NWR SYSON

11NWCR
11WJR

Table 105: Figure for 11NWCR

ASSIGN ( ¬ 13RWCR · ¬ 13NWKR · ¬ 13RWKR · ¬ 13XR · ( 13WJR.J + 13WJR ) · 13WLR · 13NWR · SYSON ) TO 13NWCR

13RWCR 13NWKR 13RWKR 13XR 13WJR.J 13WLR 13NWR SYSON

13NWCR
13WJR

Table 106: Figure for 13NWCR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 57 of 171
RWCR

ASSIGN ( ¬ 11NWCR · ¬ 11NWKR · ¬ 11RWKR · ¬ 11XR · ( 11WJR.J + 11WJR ) · 11WLR · 11RWR · SYSON ) TO 11RWCR

11NWCR 11NWKR 11RWKR 11XR 11WJR.J 11WLR 11RWR SYSON

11RWCR
11WJR

Table 107: Figure for 11RWCR

ASSIGN ( ¬ 13NWCR · ¬ 13NWKR · ¬ 13RWKR · ¬ 13XR · ( 13WJR.J + 13WJR ) · 13WLR · 13RWR · SYSON ) TO 13RWCR

13NWCR 13NWKR 13RWKR 13XR 13WJR.J 13WLR 13RWR SYSON

13RWCR
13WJR

Table 108: Figure for 13RWCR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 58 of 171
NWKR

ASSIGN ( 11NWR · ¬ 11RWKR · ¬ 11RWR · 11NDKR ) TO 11NWKR

11NWR 11RWKR 11RWR 11NDKR

11NWKR
Table 109: Figure for 11NWKR

ASSIGN ( 13NWR · ¬ 13RWKR · ¬ 13RWR · 13NDKR ) TO 13NWKR

13NWR 13RWKR 13RWR 13NDKR

13NWKR
Table 110: Figure for 13NWKR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 59 of 171
RWKR

ASSIGN ( 11RWR · ¬ 11NWKR · ¬ 11NWR · 11RDKR ) TO 11RWKR

11RWR 11NWKR 11NWR 11RDKR

11RWKR
Table 111: Figure for 11RWKR

ASSIGN ( 13RWR · ¬ 13NWKR · ¬ 13NWR · 13RDKR ) TO 13RWKR

13RWR 13NWKR 13NWR 13RDKR

13RWKR
Table 112: Figure for 13RWKR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 60 of 171
UCR

ASSIGN ( 11NWKR · 13NWKR · 13NWKR · ( ( S11ASR · C11ASR · S11ASR · C11ASR ) + 13RWKR ) · S01ALR ) TO S01AUCR

11NWKR 13NWKR 13NWKR S11ASR C11ASR S11ASR C11ASR S01ALR

S01AUCR
13RWKR

Table 113: Figure for S01AUCR

ASSIGN ( 11RWKR · 13RWKR · 13RWKR · S01BLR ) TO S01BUCR

11RWKR 13RWKR 13RWKR S01BLR

S01BUCR
Table 114: Figure for S01BUCR

ASSIGN ( 11NWKR · ( ( S11ASR · C11ASR · S11ASR · C11ASR · S11ASR · C11ASR ) + 13RWKR ) · C01ALR ) TO C01AUCR

11NWKR S11ASR C11ASR S11ASR C11ASR S11ASR C11ASR C01ALR

C01AUCR
13RWKR

Table 115: Figure for C01AUCR

ASSIGN ( 11RWKR · C01BLR ) TO C01BUCR

11RWKR C01BLR

C01BUCR
Table 116: Figure for C01BUCR

ASSIGN ( 11NWKR · S02LR ) TO S02UCR

11NWKR S02LR

S02UCR
Table 117: Figure for S02UCR

ASSIGN ( 13NWKR · S03LR ) TO S03UCR

13NWKR S03LR

S03UCR
Table 118: Figure for S03UCR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 61 of 171
 ASSIGN ( 11RWKR · S04LR ) TO S04UCR

11RWKR S04LR

S04UCR
Table 119: Figure for S04UCR

ASSIGN ( 13RWKR · S05LR ) TO S05UCR

13RWKR S05LR

S05UCR
Table 120: Figure for S05UCR

ASSIGN ( S07LR ) TO S07UCR

S07LR

S07UCR
Table 121: Figure for S07UCR

ASSIGN ( S08LR ) TO S08UCR

S08LR

S08UCR
Table 122: Figure for S08UCR

ASSIGN ( 13NWKR · 11NWKR · 11NWKR · ( ( S01ASR · C01ASR · S01ASR · C01ASR ) + 11RWKR ) · S11ALR ) TO S11AUCR

13NWKR 11NWKR 11NWKR S01ASR C01ASR S01ASR C01ASR S11ALR

S11AUCR
11RWKR

Table 123: Figure for S11AUCR

ASSIGN ( 13RWKR · 11RWKR · 11RWKR · S11ELR ) TO S11EUCR

13RWKR 11RWKR 11RWKR S11ELR

S11EUCR
Table 124: Figure for S11EUCR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 62 of 171
 ASSIGN ( 13NWKR · ( ( S01ASR · C01ASR · S01ASR · C01ASR · S01ASR · C01ASR ) + 11RWKR ) · C11ALR ) TO C11AUCR

13NWKR S01ASR C01ASR S01ASR C01ASR S01ASR C01ASR C11ALR

C11AUCR
11RWKR

Table 125: Figure for C11AUCR

ASSIGN ( 13RWKR · C11ELR ) TO C11EUCR

13RWKR C11ELR

C11EUCR
Table 126: Figure for C11EUCR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 63 of 171
UCR_

ASSIGN ( ( C01ASR ) · ( ¬ C01UCR ) · ( S01AUCR + S01BUCR ) ) TO S01UCR_

C01ASR C01UCR S01AUCR

S01UCR
S01BUCR

Table 127: Figure for S01UCR_

ASSIGN ( ( S01ASR ) · ( ¬ S01UCR ) · ( C01AUCR + C01BUCR ) ) TO C01UCR_

S01ASR S01UCR C01AUCR

C01UCR
C01BUCR

Table 128: Figure for C01UCR_

ASSIGN ( ( S02UCR ) ) TO S02UCR_

S02UCR

S02UCR
Table 129: Figure for S02UCR_

ASSIGN ( ( S03UCR ) ) TO S03UCR_

S03UCR

S03UCR
Table 130: Figure for S03UCR_

ASSIGN ( ( S04UCR ) ) TO S04UCR_

S04UCR

S04UCR
Table 131: Figure for S04UCR_

ASSIGN ( ( S05UCR ) ) TO S05UCR_

S05UCR

S05UCR
Table 132: Figure for S05UCR_

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 64 of 171
 ASSIGN ( ( S07UCR ) ) TO S07UCR_

S07UCR

S07UCR
Table 133: Figure for S07UCR_

ASSIGN ( ( S08UCR ) ) TO S08UCR_

S08UCR

S08UCR
Table 134: Figure for S08UCR_

ASSIGN ( ( C11ASR ) · ( ¬ C11UCR ) · ( S11AUCR + S11EUCR ) ) TO S11UCR_

C11ASR C11UCR S11AUCR

S11UCR
S11EUCR

Table 135: Figure for S11UCR_

ASSIGN ( ( S11ASR ) · ( ¬ S11UCR ) · ( C11AUCR + C11EUCR ) ) TO C11UCR_

S11ASR S11UCR C11AUCR

C11UCR
C11EUCR

Table 136: Figure for C11UCR_

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 65 of 171
ATR

ASSIGN ( ( ( T1.S11ATPR ) ) ) TO S02ATR

T1.S11ATPR

S02ATR
Table 137: Figure for S02ATR

ASSIGN ( ( ( T1.S01ATPR ) ) ) TO S03ATR

T1.S01ATPR

S03ATR
Table 138: Figure for S03ATR

ASSIGN ( ( ( OLTPR ) ) ) TO S04ATR

OLTPR

S04ATR
Table 139: Figure for S04ATR

ASSIGN ( ( ( OLTPR ) ) ) TO S05ATR

OLTPR

S05ATR
Table 140: Figure for S05ATR

ASSIGN ( ( ( T12.S03.S05TPR ) ) ) TO S07ATR

T12.S03.S05TPR

S07ATR
Table 141: Figure for S07ATR

ASSIGN ( ( ( 1T.S02.S04TPR ) ) ) TO S08ATR

1T.S02.S04TPR

S08ATR
Table 142: Figure for S08ATR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 66 of 171
ASR

ASSIGN ( ( ( ( ¬ S01ALR · ¬ S01BLR ) · ( ( ( 1ATPR · 1TPR · T7TPR · 13BTPR · ( 11ATPR + 11NWR ) ) · ( ( ( ( ¬ S01/C01TSR · ¬ S01EUUYR · S01UYR1..6 ) + ( S01EUUYR · S01JSLR · ( ( S01JR ) ) ) ) · ( S01RECR ) ) + SYSINT ) ) +
( S01ESUYR · S01JR · ¬ EMKEY_INR ) ) ) + S01ASR ) · ( ¬ S01UCR ) · ( ( ( ¬ S01BUHR ) ) ) · ( ¬ S01HR · ¬ S01DR · ¬ S01DECR · ¬ S01HECR · ¬ S01UECR ) ) TO S01ASR
S01ALR S01BLR 1ATPR 1TPR T7TPR 13BTPR 11ATPR S01/C01TSR S01EUUYR S01UYR1..6 S01RECR S01UCR S01BUHR S01HR S01DR S01DECR S01HECR S01UECR

S01ASR
11NWR
S01EUUYR S01JSLR S01JR

SYSINT

S01ESUYR S01JR EMKEY INR

S01ASR

Table 143: Figure for S01ASR

ASSIGN ( ( ( ( ¬ C01ALR · ¬ C01BLR ) · ( ( ( 1ATPR · 1TPR · T7TPR · 13BTPR · ( 11ATPR + 11NWR ) ) · ( ( ( ( ¬ S01/C01TSR · ¬ C01EUUYR · C01UYR ) + ( C01EUUYR · C01JSLR · ( ( C01JR ) ) ) ) ) + SYSINT ) ) + ( C01ESUYR · C01JR
· ¬ EMKEY_INR ) ) ) + C01ASR ) · ( ¬ C01UCR ) ) TO C01ASR

C01ALR C01BLR 1ATPR 1TPR T7TPR 13BTPR 11ATPR S01/C01TSR C01EUUYR C01UYR C01UCR

C01ASR
11NWR
C01EUUYR C01JSLR C01JR

SYSINT

C01ESUYR C01JR EMKEY INR

C01ASR

Table 144: Figure for C01ASR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 67 of 171
 ASSIGN ( ( ( ( ¬ S02LR ) · ( ( ( 13BTPR ) · ( ( ( ( ¬ S02TSR · ¬ S02EUUYR · S02UYR1..2 ) + ( S02EUUYR · S02JSLR · ( ( S02JR ) + ( S02ATR ) ) ) ) · ( S02RECR ) ) + SYSINT ) ) + ( S02ESUYR · S02JR · ¬ EMKEY_INR ) ) ) +
S02ASR ) · ( ¬ S02UCR ) · ( ¬ S02HR · ¬ S02DR · ¬ S02DECR · ¬ S02HECR ) ) TO S02ASR
S02LR 13BTPR S02TSR S02EUUYR S02UYR1..2 S02RECR S02UCR S02HR S02DR S02DECR S02HECR

S02ASR
S02EUUYR S02JSLR S02JR

S02ATR

SYSINT

S02ESUYR S02JR EMKEY INR

S02ASR

Table 145: Figure for S02ASR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 68 of 171
 ASSIGN ( ( ( ( ¬ S03LR ) · ( ( ( T3TPR ) · ( ( ( ( ¬ S03TSR · ¬ S03EUUYR · S03UYR1..2 ) + ( S03EUUYR · S03JSLR · ( ( S03JR ) + ( S03ATR ) ) ) ) · ( S03RECR ) ) + SYSINT ) ) + ( S03ESUYR · S03JR · ¬ EMKEY_INR ) ) ) + S03ASR
) · ( ¬ S03UCR ) · ( ¬ S03HR · ¬ S03DR · ¬ S03DECR · ¬ S03HECR ) ) TO S03ASR
S03LR T3TPR S03TSR S03EUUYR S03UYR1..2 S03RECR S03UCR S03HR S03DR S03DECR S03HECR

S03ASR
S03EUUYR S03JSLR S03JR

S03ATR

SYSINT

S03ESUYR S03JR EMKEY INR

S03ASR

Table 146: Figure for S03ASR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 69 of 171
 ASSIGN ( ( ( ( ¬ S04LR ) · ( ( ( 11ATPR · ( 11RWR ) · ( 13BTPR + 11NWR ) ) · ( ( ( ( ¬ S04TSR · ¬ S04EUUYR · S04UYR1..3 ) + ( S04EUUYR · S04JSLR · ( ( S04JR ) + ( S04ATR ) ) ) ) · ( S04RECR ) ) + SYSINT ) ) + ( S04ESUYR ·
S04JR · ¬ EMKEY_INR ) ) ) + S04ASR ) · ( ¬ S04UCR ) · ( ¬ S04HR · ¬ S04HECR ) ) TO S04ASR
S04LR 11ATPR 11RWR 13BTPR S04TSR S04EUUYR S04UYR1..3 S04RECR S04UCR S04HR S04HECR

S04ASR
11NWR
S04EUUYR S04JSLR S04JR

S04ATR

SYSINT

S04ESUYR S04JR EMKEY INR

S04ASR

Table 147: Figure for S04ASR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 70 of 171
 ASSIGN ( ( ( ( ¬ S05LR ) · ( ( ( 13ATPR · ( 13RWR ) · ( T3TPR + 13NWR ) ) · ( ( ( ( ¬ S05TSR · ¬ S05EUUYR · S05UYR1..3 ) + ( S05EUUYR · S05JSLR · ( ( S05JR ) + ( S05ATR ) ) ) ) · ( S05RECR ) ) + SYSINT ) ) + ( S05ESUYR ·
S05JR · ¬ EMKEY_INR ) ) ) + S05ASR ) · ( ¬ S05UCR ) · ( ¬ S05HR · ¬ S05HECR ) ) TO S05ASR
S05LR 13ATPR 13RWR T3TPR S05TSR S05EUUYR S05UYR1..3 S05RECR S05UCR S05HR S05HECR

S05ASR
13NWR
S05EUUYR S05JSLR S05JR

S05ATR

SYSINT

S05ESUYR S05JR EMKEY INR

S05ASR

Table 148: Figure for S05ASR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 71 of 171
 ASSIGN ( ( ( ( ¬ S07LR ) · ( ( ( T14TPR · T14TPR ) · ( ( ( ( ¬ S07TSR · ¬ S07EUUYR · S07UYR1..2 ) + ( S07EUUYR · S07JSLR · ( ( S07JR ) + ( S07ATR ) ) ) ) · ( S07RECR ) ) + SYSINT ) ) + ( S07ESUYR · S07JR · ¬ EMKEY_INR ) ) )
+ S07ASR ) · ( ¬ S07UCR ) · ( ¬ S07DR · ¬ S07DECR ) ) TO S07ASR
S07LR T14TPR T14TPR S07TSR S07EUUYR S07UYR1..2 S07RECR S07UCR S07DR S07DECR

S07ASR
S07EUUYR S07JSLR S07JR

S07ATR

SYSINT

S07ESUYR S07JR EMKEY INR

S07ASR

Table 149: Figure for S07ASR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 72 of 171
 ASSIGN ( ( ( ( ¬ S08LR ) · ( ( ( 1ATPR ) · ( ( ( ( ¬ S08TSR · ¬ S08EUUYR · S08UYR1..2 ) + ( S08EUUYR · S08JSLR · ( ( S08JR ) + ( S08ATR ) ) ) ) · ( S08RECR ) ) + SYSINT ) ) + ( S08ESUYR · S08JR · ¬ EMKEY_INR ) ) ) + S08ASR
) · ( ¬ S08UCR ) · ( ¬ S08DR · ¬ S08DECR ) ) TO S08ASR

S08LR 1ATPR S08TSR S08EUUYR S08UYR1..2 S08RECR S08UCR S08DR S08DECR

S08ASR
S08EUUYR S08JSLR S08JR

S08ATR

SYSINT

S08ESUYR S08JR EMKEY INR

S08ASR

Table 150: Figure for S08ASR

ASSIGN ( ( ( ( ¬ S11ALR · ¬ S11ELR ) · ( ( ( T12TPR · T8TPR · T3TPR · ( 13ATPR + 13NWR ) ) · ( ( ( ( ¬ S11/C11TSR · ¬ S11EUUYR · S11UYR1..5 ) + ( S11EUUYR · S11JSLR · ( ( S11JR ) ) ) ) · ( S11RECR ) ) + SYSINT ) ) + (
S11ESUYR · S11JR · ¬ EMKEY_INR ) ) ) + S11ASR ) · ( ¬ S11UCR ) · ( ( ( ¬ S11EUHR ) ) ) · ( ¬ S11HR · ¬ S11DR · ¬ S11DECR · ¬ S11HECR · ¬ S11UECR ) ) TO S11ASR
S11ALR S11ELR T12TPR T8TPR T3TPR 13ATPR S11/C11TSR S11EUUYR S11UYR1..5 S11RECR S11UCR S11EUHR S11HR S11DR S11DECR S11HECR S11UECR

S11ASR
13NWR
S11EUUYR S11JSLR S11JR

SYSINT

S11ESUYR S11JR EMKEY INR

S11ASR

Table 151: Figure for S11ASR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 73 of 171
 ASSIGN ( ( ( ( ¬ C11ALR · ¬ C11ELR ) · ( ( ( T12TPR · T8TPR · T3TPR · ( 13ATPR + 13NWR ) ) · ( ( ( ( ¬ S11/C11TSR · ¬ C11EUUYR · C11UYR ) + ( C11EUUYR · C11JSLR · ( ( C11JR ) ) ) ) ) + SYSINT ) ) + ( C11ESUYR · C11JR · ¬
EMKEY_INR ) ) ) + C11ASR ) · ( ¬ C11UCR ) ) TO C11ASR

C11ALR C11ELR T12TPR T8TPR T3TPR 13ATPR S11/C11TSR C11EUUYR C11UYR C11UCR

C11ASR
13NWR
C11EUUYR C11JSLR C11JR

SYSINT

C11ESUYR C11JR EMKEY INR

C11ASR

Table 152: Figure for C11ASR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 74 of 171
OVSR

ASSIGN ( ( ¬ S11AUCR + ¬ S11ALR ) · ( ( ( ( OV02UYR · OV02JR ) + ( ( ( T1TPR ) + SYSINIT ) · ( ( ( S11ASR + ( ( 13RWR ) ) ) ) ) ) ) ) + OV02SR ) ) TO OV02SR

S11AUCR OV02UYR OV02JR

OV02SR
S11ALR
T1TPR S11ASR

13RWR
SYSINIT

OV02SR

Table 153: Figure for OV02SR

ASSIGN ( ( ¬ S01AUCR + ¬ S01ALR ) · ( ( ( ( OV03UYR · OV03JR ) + ( ( ( T1TPR ) + SYSINIT ) · ( ( ( S01ASR + ( ( 11RWR ) ) ) ) ) ) ) ) + OV03SR ) ) TO OV03SR

S01AUCR OV03UYR OV03JR

OV03SR
S01ALR
T1TPR S01ASR

11RWR
SYSINIT

OV03SR

Table 154: Figure for OV03SR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 75 of 171
 ASSIGN ( ( ¬ S11EUCR + ¬ S11ELR ) · ( ( ( ( OV04UYR · OV04JR ) + ( ( ( OLTPR ) + SYSINIT ) · ( ( ( S11ASR + ( ( 13NWR ) ) ) ) ) ) ) ) + OV04SR ) ) TO OV04SR

S11EUCR OV04UYR OV04JR

OV04SR
S11ELR
OLTPR S11ASR

13NWR
SYSINIT

OV04SR

Table 155: Figure for OV04SR

ASSIGN ( ( ¬ S01BUCR + ¬ S01BLR ) · ( ( ( ( OV05UYR · OV05JR ) + ( ( ( OLTPR ) + SYSINIT ) · ( ( ( S01ASR + ( ( 11NWR ) ) ) ) ) ) ) ) + OV05SR ) ) TO OV05SR

S01BUCR OV05UYR OV05JR

OV05SR
S01BLR
OLTPR S01ASR

11NWR
SYSINIT

OV05SR

Table 156: Figure for OV05SR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 76 of 171
 ASSIGN ( ( ¬ S03UCR + ¬ S03LR ) · ( ¬ S05UCR + ¬ S05LR ) · ( ( ( ( OV07UYR · OV07JR ) + ( ( SYSINIT ) · ( ( ( S03ASR ) · ( S05ASR ) ) ) ) ) ) + OV07SR ) ) TO OV07SR

S03UCR S05UCR OV07UYR OV07JR

OV07SR
S03LR S05LR
SYSINIT S03ASR S05ASR

OV07SR

Table 157: Figure for OV07SR

ASSIGN ( ( ¬ S02UCR + ¬ S02LR ) · ( ¬ S04UCR + ¬ S04LR ) · ( ( ( ( OV08UYR · OV08JR ) + ( ( SYSINIT ) · ( ( ( S02ASR ) · ( S04ASR ) ) ) ) ) ) + OV08SR ) ) TO OV08SR

S02UCR S04UCR OV08UYR OV08JR

OV08SR
S02LR S04LR
SYSINIT S02ASR S04ASR

OV08SR

Table 158: Figure for OV08SR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 77 of 171
OVUYR

ASSIGN ( ( ¬ S11ALR ) · ¬ OV02SR · ( ( ( ( ( ( S11ASR + ( ( 13RWR ) ) ) ) ) + ( OYNR · ( D-02UNR ) ) ) ) + OV02UYR ) · ( ( ¬ T1TPR ) ) ) TO OV02UYR

S11ALR OV02SR S11ASR T1TPR

OV02UYR
13RWR

OYNR D-02UNR

OV02UYR

Table 159: Figure for OV02UYR

ASSIGN ( ( ¬ S01ALR ) · ¬ OV03SR · ( ( ( ( ( ( S01ASR + ( ( 11RWR ) ) ) ) ) + ( OYNR · ( D-03UNR ) ) ) ) + OV03UYR ) · ( ( ¬ T1TPR ) ) ) TO OV03UYR

S01ALR OV03SR S01ASR T1TPR

OV03UYR
11RWR

OYNR D-03UNR

OV03UYR

Table 160: Figure for OV03UYR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 78 of 171
 ASSIGN ( ( ¬ S11ELR ) · ¬ OV04SR · ( ( ( ( ( ( S11ASR + ( ( 13NWR ) ) ) ) ) + ( OYNR · ( D-04UNR ) ) ) ) + OV04UYR ) · ( ( ¬ OLTPR ) ) ) TO OV04UYR

S11ELR OV04SR S11ASR OLTPR

OV04UYR
13NWR

OYNR D-04UNR

OV04UYR

Table 161: Figure for OV04UYR

ASSIGN ( ( ¬ S01BLR ) · ¬ OV05SR · ( ( ( ( ( ( S01ASR + ( ( 11NWR ) ) ) ) ) + ( OYNR · ( D-05UNR ) ) ) ) + OV05UYR ) · ( ( ¬ OLTPR ) ) ) TO OV05UYR

S01BLR OV05SR S01ASR OLTPR

OV05UYR
11NWR

OYNR D-05UNR

OV05UYR

Table 162: Figure for OV05UYR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 79 of 171
 ASSIGN ( ( ¬ S03LR · ¬ S05LR ) · ¬ OV07SR · ( ( ( ( ( ( S03ASR ) · ( S05ASR ) ) ) + ( OYNR · ( D-07UNR ) ) ) ) + OV07UYR ) ) TO OV07UYR

S03LR S05LR OV07SR S03ASR S05ASR

OV07UYR

OYNR D-07UNR

OV07UYR

Table 163: Figure for OV07UYR

ASSIGN ( ( ¬ S02LR · ¬ S04LR ) · ¬ OV08SR · ( ( ( ( ( ( S02ASR ) · ( S04ASR ) ) ) + ( OYNR · ( D-08UNR ) ) ) ) + OV08UYR ) ) TO OV08UYR

S02LR S04LR OV08SR S02ASR S04ASR

OV08UYR

OYNR D-08UNR

OV08UYR

Table 164: Figure for OV08UYR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 80 of 171
OVJSLR

ASSIGN ( OV01UYR ) TO OV01JSLR

OV01UYR

OV01JSLR
Table 165: Figure for OV01JSLR

ASSIGN ( OV02UYR ) TO OV02JSLR

OV02UYR

OV02JSLR
Table 166: Figure for OV02JSLR

ASSIGN ( OV03UYR ) TO OV03JSLR

OV03UYR

OV03JSLR
Table 167: Figure for OV03JSLR

ASSIGN ( OV04UYR ) TO OV04JSLR

OV04UYR

OV04JSLR
Table 168: Figure for OV04JSLR

ASSIGN ( OV05UYR ) TO OV05JSLR

OV05UYR

OV05JSLR
Table 169: Figure for OV05JSLR

ASSIGN ( OV07UYR ) TO OV07JSLR

OV07UYR

OV07JSLR
Table 170: Figure for OV07JSLR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 81 of 171
 ASSIGN ( OV08UYR ) TO OV08JSLR

OV08UYR

OV08JSLR
Table 171: Figure for OV08JSLR

ASSIGN ( OV11UYR ) TO OV11JSLR

OV11UYR

OV11JSLR
Table 172: Figure for OV11JSLR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 82 of 171
OVJR

ASSIGN ( OV01JSLR ) TO OV01JR

OV01JSLR

OV01JR
Table 173: Figure for OV01JR

ASSIGN ( OV02JSLR ) TO OV02JR

OV02JSLR

OV02JR
Table 174: Figure for OV02JR

ASSIGN ( OV03JSLR ) TO OV03JR

OV03JSLR

OV03JR
Table 175: Figure for OV03JR

ASSIGN ( OV04JSLR ) TO OV04JR

OV04JSLR

OV04JR
Table 176: Figure for OV04JR

ASSIGN ( OV05JSLR ) TO OV05JR

OV05JSLR

OV05JR
Table 177: Figure for OV05JR

ASSIGN ( OV07JSLR ) TO OV07JR

OV07JSLR

OV07JR
Table 178: Figure for OV07JR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 83 of 171
 ASSIGN ( OV08JSLR ) TO OV08JR

OV08JSLR

OV08JR
Table 179: Figure for OV08JR

ASSIGN ( OV11JSLR ) TO OV11JR

OV11JSLR

OV11JR
Table 180: Figure for OV11JR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 84 of 171
OYNZ

ASSIGN ( ( ( ¬ OV02SR · OV02UYR ) + ( ¬ OV04SR · OV04UYR ) + ( ¬ OV03SR · OV03UYR ) + ( ¬ OV05SR · OV05UYR ) ) · OYNR ) TO OYNZ

OV02SR OV02UYR OYNR

OYNZ
OV04SR OV04UYR

OV03SR OV03UYR

OV05SR OV05UYR

Table 181: Figure for OYNZ

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 85 of 171
TSR

ASSIGN ( 1ATPR · ( ( S01ASR · ( C01ASR ) · ( ¬ S01ALR ) · ( ¬ S01BLR ) ) + S01TSR ) ) TO S01TSR

1ATPR S01ASR C01ASR S01ALR S01BLR

S01TSR

S01TSR

Table 182: Figure for S01TSR

ASSIGN ( 13BTPR · ( ( S02ASR · ( ¬ S02LR ) ) + S02TSR ) ) TO S02TSR

13BTPR S02ASR S02LR

S02TSR

S02TSR

Table 183: Figure for S02TSR

ASSIGN ( T3TPR · ( ( S03ASR · ( ¬ S03LR ) ) + S03TSR ) ) TO S03TSR

T3TPR S03ASR S03LR

S03TSR

S03TSR

Table 184: Figure for S03TSR

ASSIGN ( 11ATPR · ( ( S04ASR · ( ¬ S04LR ) ) + S04TSR ) ) TO S04TSR

11ATPR S04ASR S04LR

S04TSR

S04TSR

Table 185: Figure for S04TSR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 86 of 171
 ASSIGN ( 13ATPR · ( ( S05ASR · ( ¬ S05LR ) ) + S05TSR ) ) TO S05TSR

13ATPR S05ASR S05LR

S05TSR

S05TSR

Table 186: Figure for S05TSR

ASSIGN ( 1ATPR · ( ( S08ASR · ( ¬ S08LR ) ) + S08TSR ) ) TO S08TSR

1ATPR S08ASR S08LR

S08TSR

S08TSR

Table 187: Figure for S08TSR

ASSIGN ( T12TPR · ( ( S11ASR · ( C11ASR ) · ( ¬ S11ALR ) · ( ¬ S11ELR ) ) + S11TSR ) ) TO S11TSR

T12TPR S11ASR C11ASR S11ALR S11ELR

S11TSR

S11TSR

Table 188: Figure for S11TSR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 87 of 171
UYR

ASSIGN ( ¬ S11_C11ASR · (( ¬ T14TPR · ¬ T12TPR · T8TPR) + S11_C11UYR1)) TO S11_C11UYR1

S11 C11ASR T14TPR T12TPR T8TPR

S11 C11UYR1
S11 C11UYR1

Table 189: Figure for S11_C11UYR1

ASSIGN ( S11_C11UYR1 · ((( T12TPR · ¬ T8TPR · ¬ T3TPR) + S11_C11UYR2))) TO S11_C11UYR2

S11 C11UYR1 T12TPR T8TPR T3TPR

S11 C11UYR2
S11 C11UYR2

Table 190: Figure for S11_C11UYR2

ASSIGN ( S11_C11UYR2 · ((( T8TPR · ¬ T3TPR) · ((( 13NWR · ¬ T1TPR) + ( 13RWR · ¬ 13ATTPR))) + S11_C11UYR3))) TO S11_C11UYR3

S11 C11UYR2 T8TPR T3TPR 13NWR T1TPR

S11 C11UYR3
13RWR 13ATTPR

S11 C11UYR3

Table 191: Figure for S11_C11UYR3

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 88 of 171
 ASSIGN ( S11_C11UYR3 · (( T3TPR · ((( 13NWR · ¬ T1TPR) + ( 13RWR · ¬ 13ATTPR · ¬ OLTTPR))) + S11_C11UYR4))) TO S11_C11UYR4

S11 C11UYR3 T3TPR 13NWR T1TPR

S11 C11UYR4
13RWR 13ATTPR OLTTPR

S11 C11UYR4

Table 192: Figure for S11_C11UYR4

ASSIGN ( S11_C11UYR4 · (( ( 13RWR · 13ATTPR · ¬ OLTTPR ) + ( 13NWR ) ) + S11_C11UYR5)) TO S11_C11UYR5

S11 C11UYR4 13RWR 13ATTPR OLTTPR

S11 C11UYR5
13NWR

S11 C11UYR5

Table 193: Figure for S11_C11UYR5

ASSIGN ( ¬ S01_C01ASR · (( ¬ TPR · ¬ 1ATTPR · 1TTPR) + S01_C01UYR1)) TO S01_C01UYR1

S01 C01ASR TPR 1ATTPR 1TTPR

S01 C01UYR1
S01 C01UYR1

Table 194: Figure for S01_C01UYR1

ASSIGN ( S01_C01UYR1 · ((( 1ATTPR · ¬ 1TTPR · ¬ T7TPR) + S01_C01UYR2))) TO S01_C01UYR2

S01 C01UYR1 1ATTPR 1TTPR T7TPR

S01 C01UYR2
S01 C01UYR2

Table 195: Figure for S01_C01UYR2

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 89 of 171
 ASSIGN ( S01_C01UYR2 · ((( 1TTPR · ¬ T7TPR · ¬ 13BTTPR) + S01_C01UYR3))) TO S01_C01UYR3

S01 C01UYR2 1TTPR T7TPR 13BTTPR

S01 C01UYR3
S01 C01UYR3

Table 196: Figure for S01_C01UYR3

ASSIGN ( S01_C01UYR3 · ((( T7TPR · ¬ 13BTTPR) · ((( 11NWR · ¬ T1TPR) + ( 11RWR · ¬ 11ATTPR))) + S01_C01UYR4))) TO S01_C01UYR4

S01 C01UYR3 T7TPR 13BTTPR 11NWR T1TPR

S01 C01UYR4
11RWR 11ATTPR

S01 C01UYR4

Table 197: Figure for S01_C01UYR4

ASSIGN ( S01_C01UYR4 · (( 13BTTPR · ((( 11NWR · ¬ T1TPR) + ( 11RWR · ¬ 11ATTPR · ¬ OLTTPR))) + S01_C01UYR5))) TO S01_C01UYR5

S01 C01UYR4 13BTTPR 11NWR T1TPR

S01 C01UYR5
11RWR 11ATTPR OLTTPR

S01 C01UYR5

Table 198: Figure for S01_C01UYR5

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 ASSIGN ( S01_C01UYR5 · (( ( 11RWR · 11ATTPR · ¬ OLTTPR ) + ( 11NWR ) ) + S01_C01UYR6)) TO S01_C01UYR6

S01 C01UYR5 11RWR 11ATTPR OLTTPR

S01 C01UYR6
11NWR

S01 C01UYR6

Table 199: Figure for S01_C01UYR6

ASSIGN ( ¬ S02ASR · (( ¬ T1TPR · ¬ 13BTTPR · T7TPR) + S02UYR1)) TO S02UYR1

S02ASR T1TPR 13BTTPR T7TPR

S02UYR1
S02UYR1

Table 200: Figure for S02UYR1

ASSIGN ( S02UYR1 · (( 13BTTPR · ¬ T7TPR) + S02UYR2)) TO S02UYR2

S02UYR1 13BTTPR T7TPR

S02UYR2
S02UYR2

Table 201: Figure for S02UYR2

ASSIGN ( ¬ S03ASR · (( ¬ T1TPR · ¬ T3TPR · T8TPR) + S03UYR1)) TO S03UYR1

S03ASR T1TPR T3TPR T8TPR

S03UYR1
S03UYR1

Table 202: Figure for S03UYR1

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 ASSIGN ( S03UYR1 · (( T3TPR · ¬ T8TPR) + S03UYR2)) TO S03UYR2

S03UYR1 T3TPR T8TPR

S03UYR2
S03UYR2

Table 203: Figure for S03UYR2

ASSIGN ( ¬ S04ASR · (( ¬ OLTTPR · ¬ 11ATTPR · 13BTTPR) + S04UYR1)) TO S04UYR1

S04ASR OLTTPR 11ATTPR 13BTTPR

S04UYR1
S04UYR1

Table 204: Figure for S04UYR1

ASSIGN ( S04UYR1 · (( 11ATTPR · ¬ 13BTTPR · ¬ T7TPR) + S04UYR2)) TO S04UYR2

S04UYR1 11ATTPR 13BTTPR T7TPR

S04UYR2
S04UYR2

Table 205: Figure for S04UYR2

ASSIGN ( S04UYR2 · (( 13BTTPR · ¬ T7TPR) + S04UYR3)) TO S04UYR3

S04UYR2 13BTTPR T7TPR

S04UYR3
S04UYR3

Table 206: Figure for S04UYR3

ASSIGN ( ¬ S05ASR · (( ¬ OLTTPR · ¬ 13ATTPR · T3TPR) + S05UYR1)) TO S05UYR1

S05ASR OLTTPR 13ATTPR T3TPR

S05UYR1
S05UYR1

Table 207: Figure for S05UYR1

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 ASSIGN ( S05UYR1 · (( 13ATTPR · ¬ T3TPR · ¬ T8TPR) + S05UYR2)) TO S05UYR2

S05UYR1 13ATTPR T3TPR T8TPR

S05UYR2
S05UYR2

Table 208: Figure for S05UYR2

ASSIGN ( S05UYR2 · (( T3TPR · ¬ T8TPR) + S05UYR3)) TO S05UYR3

S05UYR2 T3TPR T8TPR

S05UYR3
S05UYR3

Table 209: Figure for S05UYR3

ASSIGN ( ¬ S07ASR · (( ¬ T12TPR · ¬ T14TPR) + S07UYR1)) TO S07UYR1

S07ASR T12TPR T14TPR

S07UYR1
S07UYR1

Table 210: Figure for S07UYR1

ASSIGN ( S07UYR1 · (( T14TPR) + S07UYR2)) TO S07UYR2

S07UYR1 T14TPR

S07UYR2
S07UYR2

Table 211: Figure for S07UYR2

ASSIGN ( ¬ S08ASR · (( ¬ 1TTPR · ¬ 1ATTPR) + S08UYR1)) TO S08UYR1

S08ASR 1TTPR 1ATTPR

S08UYR1
S08UYR1

Table 212: Figure for S08UYR1

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 ASSIGN ( S08UYR1 · (( 1ATTPR) + S08UYR2)) TO S08UYR2

S08UYR1 1ATTPR

S08UYR2
S08UYR2

Table 213: Figure for S08UYR2

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 94 of 171
EUUYR_

ASSIGN ( ( ¬ S01HR · ¬ C01HR ) · ( ¬ S01ALR · ¬ S01BLR · ¬ C01ALR · ¬ C01BLR ) · ( 1ATPR · 1TPR · T7TPR · 13BTPR · ( 11ATPR + 11NWR ) ) · ( ( ¬ C01ASR · ( ( C01GNR · EUUYNR ) + S01/C01EUUYR ) ) + ( S01/C01TSR · ( ( ¬ S01ASR
· ( ( S01GNR · EUUYNR ) + S01/C01EUUYR ) ) ) ) ) · ¬ ESUYR · SYSON ) TO S01/C01EUUYR_
S01HR C01HR S01ALR S01BLR C01ALR C01BLR 1ATPR 1TPR T7TPR 13BTPR 11ATPR C01ASR C01GNR EUUYNR ESUYR SYSON

S01/C01EUUYR
11NWR
S01/C01EUUYR

S01/C01TSR S01ASR S01GNR EUUYNR

S01/C01EUUYR

Table 214: Figure for S01/C01EUUYR_

ASSIGN ( ( ¬ S02HR ) · ( ¬ S02LR ) · ( 13BTPR ) · ( ( S02TSR · ( ( ¬ S02ASR · ( ( S02GNR · EUUYNR ) + S02EUUYR ) ) ) ) ) · ¬ ESUYR · SYSON ) TO S02EUUYR_

S02HR S02LR 13BTPR S02TSR S02ASR S02GNR EUUYNR ESUYR SYSON

S02EUUYR
S02EUUYR

Table 215: Figure for S02EUUYR_

ASSIGN ( ( ¬ S03HR ) · ( ¬ S03LR ) · ( T3TPR ) · ( ( S03TSR · ( ( ¬ S03ASR · ( ( S03GNR · EUUYNR ) + S03EUUYR ) ) ) ) ) · ¬ ESUYR · SYSON ) TO S03EUUYR_

S03HR S03LR T3TPR S03TSR S03ASR S03GNR EUUYNR ESUYR SYSON

S03EUUYR
S03EUUYR

Table 216: Figure for S03EUUYR_

ASSIGN ( ( ¬ S04HR ) · ( ¬ S04LR ) · ( 11ATPR · ( 11RWR ) · ( 13BTPR + 11NWR ) ) · ( ( S04TSR · ( ( ¬ S04ASR · ( ( S04GNR · EUUYNR ) + S04EUUYR ) ) ) ) ) · ¬ ESUYR · SYSON ) TO S04EUUYR_

S04HR S04LR 11ATPR 11RWR 13BTPR S04TSR S04ASR S04GNR EUUYNR ESUYR SYSON

S04EUUYR
11NWR
S04EUUYR

Table 217: Figure for S04EUUYR_

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 ASSIGN ( ( ¬ S05HR ) · ( ¬ S05LR ) · ( 13ATPR · ( 13RWR ) · ( T3TPR + 13NWR ) ) · ( ( S05TSR · ( ( ¬ S05ASR · ( ( S05GNR · EUUYNR ) + S05EUUYR ) ) ) ) ) · ¬ ESUYR · SYSON ) TO S05EUUYR_

S05HR S05LR 13ATPR 13RWR T3TPR S05TSR S05ASR S05GNR EUUYNR ESUYR SYSON

S05EUUYR
13NWR
S05EUUYR

Table 218: Figure for S05EUUYR_

ASSIGN ( ( ¬ S07HR ) · ( ¬ S07LR ) · ( T14TPR · T14TPR ) · ( ( S07TSR · ( ( ¬ S07ASR · ( ( S07GNR · EUUYNR ) + S07EUUYR ) ) ) ) ) · ¬ ESUYR · SYSON ) TO S07EUUYR_

S07HR S07LR T14TPR T14TPR S07TSR S07ASR S07GNR EUUYNR ESUYR SYSON

S07EUUYR
S07EUUYR

Table 219: Figure for S07EUUYR_

ASSIGN ( ( ¬ S08HR ) · ( ¬ S08LR ) · ( 1ATPR ) · ( ( S08TSR · ( ( ¬ S08ASR · ( ( S08GNR · EUUYNR ) + S08EUUYR ) ) ) ) ) · ¬ ESUYR · SYSON ) TO S08EUUYR_

S08HR S08LR 1ATPR S08TSR S08ASR S08GNR EUUYNR ESUYR SYSON

S08EUUYR
S08EUUYR

Table 220: Figure for S08EUUYR_

ASSIGN ( ( ¬ S11HR · ¬ C11HR ) · ( ¬ S11ALR · ¬ S11ELR · ¬ C11ALR · ¬ C11ELR ) · ( T12TPR · T8TPR · T3TPR · ( 13ATPR + 13NWR ) ) · ( ( ¬ C11ASR · ( ( C11GNR · EUUYNR ) + S11/C11EUUYR ) ) + ( S11/C11TSR · ( ( ¬ S11ASR · ( (
S11GNR · EUUYNR ) + S11/C11EUUYR ) ) ) ) ) · ¬ ESUYR · SYSON ) TO S11/C11EUUYR_
S11HR C11HR S11ALR S11ELR C11ALR C11ELR T12TPR T8TPR T3TPR 13ATPR C11ASR C11GNR EUUYNR ESUYR SYSON

S11/C11EUUYR
13NWR
S11/C11EUUYR

S11/C11TSR S11ASR S11GNR EUUYNR

S11/C11EUUYR

Table 221: Figure for S11/C11EUUYR_

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 96 of 171
ESUYR_

ASSIGN ( ( ¬ S01HR · ¬ C01HR ) · ( ¬ S01ALR · ¬ S01BLR · ¬ C01ALR · ¬ C01BLR ) · ( ( ¬ C01ASR · ( ( C01GNR · ESUYR ) + S01/C01ESUYR ) ) + ( ¬ S01ASR · ( ( S01GNR · ESUYR ) + S01/C01ESUYR ) ) ) · ¬ EUUYR · SYSON ) TO
S01/C01ESUYR_

S01HR C01HR S01ALR S01BLR C01ALR C01BLR C01ASR C01GNR ESUYR EUUYR SYSON

S01/C01ESUYR
S01/C01ESUYR

S01ASR S01GNR ESUYR

S01/C01ESUYR

Table 222: Figure for S01/C01ESUYR_

ASSIGN ( ( ¬ S02HR ) · ( ¬ S02LR ) · ( ( ¬ S02ASR · ( ( S02GNR · ESUYR ) + S02ESUYR ) ) ) · ¬ EUUYR · SYSON ) TO S02ESUYR_

S02HR S02LR S02ASR S02GNR ESUYR EUUYR SYSON

S02ESUYR
S02ESUYR

Table 223: Figure for S02ESUYR_

ASSIGN ( ( ¬ S03HR ) · ( ¬ S03LR ) · ( ( ¬ S03ASR · ( ( S03GNR · ESUYR ) + S03ESUYR ) ) ) · ¬ EUUYR · SYSON ) TO S03ESUYR_

S03HR S03LR S03ASR S03GNR ESUYR EUUYR SYSON

S03ESUYR
S03ESUYR

Table 224: Figure for S03ESUYR_

ASSIGN ( ( ¬ S04HR ) · ( ¬ S04LR ) · ( ( ¬ S04ASR · ( ( S04GNR · ESUYR ) + S04ESUYR ) ) ) · ¬ EUUYR · SYSON ) TO S04ESUYR_

S04HR S04LR S04ASR S04GNR ESUYR EUUYR SYSON

S04ESUYR
S04ESUYR

Table 225: Figure for S04ESUYR_

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 ASSIGN ( ( ¬ S05HR ) · ( ¬ S05LR ) · ( ( ¬ S05ASR · ( ( S05GNR · ESUYR ) + S05ESUYR ) ) ) · ¬ EUUYR · SYSON ) TO S05ESUYR_

S05HR S05LR S05ASR S05GNR ESUYR EUUYR SYSON

S05ESUYR
S05ESUYR

Table 226: Figure for S05ESUYR_

ASSIGN ( ( ¬ S07HR ) · ( ¬ S07LR ) · ( ( ¬ S07ASR · ( ( S07GNR · ESUYR ) + S07ESUYR ) ) ) · ¬ EUUYR · SYSON ) TO S07ESUYR_

S07HR S07LR S07ASR S07GNR ESUYR EUUYR SYSON

S07ESUYR
S07ESUYR

Table 227: Figure for S07ESUYR_

ASSIGN ( ( ¬ S08HR ) · ( ¬ S08LR ) · ( ( ¬ S08ASR · ( ( S08GNR · ESUYR ) + S08ESUYR ) ) ) · ¬ EUUYR · SYSON ) TO S08ESUYR_

S08HR S08LR S08ASR S08GNR ESUYR EUUYR SYSON

S08ESUYR
S08ESUYR

Table 228: Figure for S08ESUYR_

ASSIGN ( ( ¬ S11HR · ¬ C11HR ) · ( ¬ S11ALR · ¬ S11ELR · ¬ C11ALR · ¬ C11ELR ) · ( ( ¬ C11ASR · ( ( C11GNR · ESUYR ) + S11/C11ESUYR ) ) + ( ¬ S11ASR · ( ( S11GNR · ESUYR ) + S11/C11ESUYR ) ) ) · ¬ EUUYR · SYSON ) TO
S11/C11ESUYR_

S11HR C11HR S11ALR S11ELR C11ALR C11ELR C11ASR C11GNR ESUYR EUUYR SYSON

S11/C11ESUYR
S11/C11ESUYR

S11ASR S11GNR ESUYR

S11/C11ESUYR

Table 229: Figure for S11/C11ESUYR_

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 98 of 171
JSLR

ASSIGN ( ( S01EUUYR + S01ESUYR ) ) TO S01JSLR

S01EUUYR

S01JSLR
S01ESUYR

Table 230: Figure for S01JSLR

ASSIGN ( ( C01EUUYR + C01ESUYR ) ) TO C01JSLR

C01EUUYR

C01JSLR
C01ESUYR

Table 231: Figure for C01JSLR

ASSIGN ( ( S02EUUYR + S02ESUYR ) ) TO S02JSLR

S02EUUYR

S02JSLR
S02ESUYR

Table 232: Figure for S02JSLR

ASSIGN ( ( S03EUUYR + S03ESUYR ) ) TO S03JSLR

S03EUUYR

S03JSLR
S03ESUYR

Table 233: Figure for S03JSLR

ASSIGN ( ( S04EUUYR + S04ESUYR ) ) TO S04JSLR

S04EUUYR

S04JSLR
S04ESUYR

Table 234: Figure for S04JSLR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 99 of 171
 ASSIGN ( ( S05EUUYR + S05ESUYR ) ) TO S05JSLR

S05EUUYR

S05JSLR
S05ESUYR

Table 235: Figure for S05JSLR

ASSIGN ( ( S07EUUYR + S07ESUYR ) ) TO S07JSLR

S07EUUYR

S07JSLR
S07ESUYR

Table 236: Figure for S07JSLR

ASSIGN ( ( S08EUUYR + S08ESUYR ) ) TO S08JSLR

S08EUUYR

S08JSLR
S08ESUYR

Table 237: Figure for S08JSLR

ASSIGN ( ( S11EUUYR + S11ESUYR ) ) TO S11JSLR

S11EUUYR

S11JSLR
S11ESUYR

Table 238: Figure for S11JSLR

ASSIGN ( ( C11EUUYR + C11ESUYR ) ) TO C11JSLR

C11EUUYR

C11JSLR
C11ESUYR

Table 239: Figure for C11JSLR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 100 of 171
JR

ASSIGN ( S01JSLR ) TO S01JR

S01JSLR

S01JR
Table 240: Figure for S01JR

ASSIGN ( C01JSLR ) TO C01JR

C01JSLR

C01JR
Table 241: Figure for C01JR

ASSIGN ( S02JSLR ) TO S02JR

S02JSLR

S02JR
Table 242: Figure for S02JR

ASSIGN ( S03JSLR ) TO S03JR

S03JSLR

S03JR
Table 243: Figure for S03JR

ASSIGN ( S04JSLR ) TO S04JR

S04JSLR

S04JR
Table 244: Figure for S04JR

ASSIGN ( S05JSLR ) TO S05JR

S05JSLR

S05JR
Table 245: Figure for S05JR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 101 of 171
 ASSIGN ( S07JSLR ) TO S07JR

S07JSLR

S07JR
Table 246: Figure for S07JR

ASSIGN ( S08JSLR ) TO S08JR

S08JSLR

S08JR
Table 247: Figure for S08JR

ASSIGN ( S11JSLR ) TO S11JR

S11JSLR

S11JR
Table 248: Figure for S11JR

ASSIGN ( C11JSLR ) TO C11JR

C11JSLR

C11JR
Table 249: Figure for C11JR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 102 of 171
test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 103 of 171
EUUYZ

ASSIGN ( ( ( C01EUUYR · ( C01JR + C01ATR ) ) + ( C11EUUYR · ( C11JR + C11ATR ) ) + ( S01EUUYR · ( S01JR + S01ATR ) ) + ( S02EUUYR · ( S02JR + S02ATR ) ) + ( S03EUUYR · ( S03JR + S03ATR ) ) + ( S04EUUYR · ( S04JR + S04ATR )
) + ( S05EUUYR · ( S05JR + S05ATR ) ) + ( S07EUUYR · ( S07JR + S07ATR ) ) + ( S08EUUYR · ( S08JR + S08ATR ) ) + ( S11EUUYR · ( S11JR + S11ATR ) ) ) ) TO EUUYZ
C01EUUYR C01JR

EUUYZ
C01ATR

C11EUUYR C11JR

C11ATR

S01EUUYR S01JR

S01ATR

S02EUUYR S02JR

S02ATR

S03EUUYR S03JR

S03ATR

S04EUUYR S04JR

S04ATR

S05EUUYR S05JR

S05ATR

S07EUUYR S07JR

S07ATR

S08EUUYR S08JR

S08ATR

S11EUUYR S11JR

S11ATR

Table 250: Figure for EUUYZ

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 104 of 171
ESUYZ

ASSIGN ( ( ( C01ESUYR · C01JR ) + ( C11ESUYR · C11JR ) + ( S01ESUYR · S01JR ) + ( S02ESUYR · S02JR ) + ( S03ESUYR · S03JR ) + ( S04ESUYR · S04JR ) + ( S05ESUYR · S05JR ) + ( S07ESUYR · S07JR ) + ( S08ESUYR · S08JR ) + (
S11ESUYR · S11JR ) ) ) TO ESUYZ

C01ESUYR C01JR

ESUYZ
C11ESUYR C11JR

S01ESUYR S01JR

S02ESUYR S02JR

S03ESUYR S03JR

S04ESUYR S04JR

S05ESUYR S05JR

S07ESUYR S07JR

S08ESUYR S08JR

S11ESUYR S11JR

Table 251: Figure for ESUYZ

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 105 of 171
INT1HR

ASSIGN ( SYSON · ¬ S01ESUYR · ¬ S01EUUYR · ¬ S01JSLR · ( ¬ S01UYR1 ) · ( ¬ S01UYR2 ) · ( ¬ S01UYR3 ) · ( ¬ S01UYR4 ) · ( ¬ S01UYR5 ) · ( ¬ 11WLR · 11NWKR ) · ( ¬ 11WLR · 11RWKR ) · CH1NPR · S01TSR · S01UCR · ¬ S01ASR · ( ¬
C01HR ) ) TO S01INT1HR
SYSON S01ESUYR S01EUUYR S01JSLR S01UYR1 S01UYR2 S01UYR3 S01UYR4 S01UYR5 11WLR 11NWKR 11WLR 11RWKR CH1NPR S01TSR S01UCR S01ASR C01HR

S01INT1HR

Table 252: Figure for S01INT1HR

ASSIGN ( SYSON · ¬ C01ESUYR · ¬ C01EUUYR · ¬ C01JSLR · ( ¬ 11WLR · 11NWKR ) · ( ¬ 11WLR · 11RWKR ) · CH1NPR · C01UCR · ¬ C01ASR · ( ¬ S01HR ) ) TO C01INT1HR

SYSON C01ESUYR C01EUUYR C01JSLR 11WLR 11NWKR 11WLR 11RWKR CH1NPR C01UCR C01ASR S01HR

C01INT1HR
Table 253: Figure for C01INT1HR

ASSIGN ( SYSON · ¬ S02ESUYR · ¬ S02EUUYR · ¬ S02JSLR · ( ¬ S02UYR1 ) · ( ¬ 11WLR · 11NWKR ) · CH1NPR · S02TSR · S02UCR · ¬ S02ASR ) TO S02INT1HR

SYSON S02ESUYR S02EUUYR S02JSLR S02UYR1 11WLR 11NWKR CH1NPR S02TSR S02UCR S02ASR

S02INT1HR
Table 254: Figure for S02INT1HR

ASSIGN ( SYSON · ¬ S03ESUYR · ¬ S03EUUYR · ¬ S03JSLR · ( ¬ S03UYR1 ) · ( ¬ 13WLR · 13NWKR ) · CH2NPR · S03TSR · S03UCR · ¬ S03ASR ) TO S03INT1HR

SYSON S03ESUYR S03EUUYR S03JSLR S03UYR1 13WLR 13NWKR CH2NPR S03TSR S03UCR S03ASR

S03INT1HR
Table 255: Figure for S03INT1HR

ASSIGN ( SYSON · ¬ S04ESUYR · ¬ S04EUUYR · ¬ S04JSLR · ( ¬ S04UYR1 ) · ( ¬ S04UYR2 ) · ( ¬ 11WLR · 11RWKR ) · CH1NPR · S04TSR · S04UCR · ¬ S04ASR ) TO S04INT1HR
SYSON S04ESUYR S04EUUYR S04JSLR S04UYR1 S04UYR2 11WLR 11RWKR CH1NPR S04TSR S04UCR S04ASR

S04INT1HR
Table 256: Figure for S04INT1HR

ASSIGN ( SYSON · ¬ S05ESUYR · ¬ S05EUUYR · ¬ S05JSLR · ( ¬ S05UYR1 ) · ( ¬ S05UYR2 ) · ( ¬ 13WLR · 13RWKR ) · CH2NPR · S05TSR · S05UCR · ¬ S05ASR ) TO S05INT1HR
SYSON S05ESUYR S05EUUYR S05JSLR S05UYR1 S05UYR2 13WLR 13RWKR CH2NPR S05TSR S05UCR S05ASR

S05INT1HR
Table 257: Figure for S05INT1HR

ASSIGN ( SYSON · ¬ S07ESUYR · ¬ S07EUUYR · ¬ S07JSLR · ( ¬ S07UYR1 ) · S07TSR · S07UCR · ¬ S07ASR ) TO S07INT1HR

SYSON S07ESUYR S07EUUYR S07JSLR S07UYR1 S07TSR S07UCR S07ASR

S07INT1HR
Table 258: Figure for S07INT1HR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 106 of 171
 ASSIGN ( SYSON · ¬ S08ESUYR · ¬ S08EUUYR · ¬ S08JSLR · ( ¬ S08UYR1 ) · S08TSR · S08UCR · ¬ S08ASR ) TO S08INT1HR

SYSON S08ESUYR S08EUUYR S08JSLR S08UYR1 S08TSR S08UCR S08ASR

S08INT1HR
Table 259: Figure for S08INT1HR

ASSIGN ( SYSON · ¬ S11ESUYR · ¬ S11EUUYR · ¬ S11JSLR · ( ¬ S11UYR1 ) · ( ¬ S11UYR2 ) · ( ¬ S11UYR3 ) · ( ¬ S11UYR4 ) · ( ¬ 13WLR · 13NWKR ) · ( ¬ 13WLR · 13RWKR ) · CH2NPR · S11TSR · S11UCR · ¬ S11ASR · ( ¬ C11HR ) ) TO
S11INT1HR
SYSON S11ESUYR S11EUUYR S11JSLR S11UYR1 S11UYR2 S11UYR3 S11UYR4 13WLR 13NWKR 13WLR 13RWKR CH2NPR S11TSR S11UCR S11ASR C11HR

S11INT1HR

Table 260: Figure for S11INT1HR

ASSIGN ( SYSON · ¬ C11ESUYR · ¬ C11EUUYR · ¬ C11JSLR · ( ¬ 13WLR · 13NWKR ) · ( ¬ 13WLR · 13RWKR ) · CH2NPR · C11UCR · ¬ C11ASR · ¬ T14TPR · ( ¬ S11HR ) ) TO C11INT1HR
SYSON C11ESUYR C11EUUYR C11JSLR 13WLR 13NWKR 13WLR 13RWKR CH2NPR C11UCR C11ASR T14TPR S11HR

C11INT1HR
Table 261: Figure for C11INT1HR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 107 of 171
INT2HR

ASSIGN ( S01INT1HR · T12TPR · T3TPR · T8TPR · CH2NPR · ( ¬ 13WLR · 13NWKR ) · ¬ S03OVSR · ¬ S03OVJSLR · S03ECPR · ¬ S03UECR · ¬ S01UHR · S01UCR · S01ALR ) TO S01INT2HR
S01INT1HR T12TPR T3TPR T8TPR CH2NPR 13WLR 13NWKR S03OVSR S03OVJSLR S03ECPR S03UECR S01UHR S01UCR S01ALR

S01INT2HR
Table 262: Figure for S01INT2HR

ASSIGN ( S02INT1HR · ¬ S08OVSR · ¬ S08OVJSLR · S08ECPR · ¬ S08UECR · ¬ S02UHR · S02UCR · S02LR ) TO S02INT2HR

S02INT1HR S08OVSR S08OVJSLR S08ECPR S08UECR S02UHR S02UCR S02LR

S02INT2HR
Table 263: Figure for S02INT2HR

ASSIGN ( S03INT1HR · ¬ S07OVSR · ¬ S07OVJSLR · S07ECPR · ¬ S07UECR · ¬ S03UHR · S03UCR · S03LR ) TO S03INT2HR

S03INT1HR S07OVSR S07OVJSLR S07ECPR S07UECR S03UHR S03UCR S03LR

S03INT2HR
Table 264: Figure for S03INT2HR

ASSIGN ( S07INT1HR · T14TPR · ¬ KZJHOMEOVSR · ¬ KZJHOMEOVJSLR · KZJHOMEECPR · ¬ KZJHOMEUECR · ¬ S07UHR · S07UCR · S07LR ) TO S07INT2HR

S07INT1HR T14TPR KZJHOMEOVSR KZJHOMEOVJSLR KZJHOMEECPR KZJHOMEUECR S07UHR S07UCR S07LR

S07INT2HR
Table 265: Figure for S07INT2HR

ASSIGN ( S08INT1HR · ¬ SCHOMEOVSR · ¬ SCHOMEOVJSLR · SCHOMEECPR · ¬ SCHOMEUECR · ¬ S08UHR · S08UCR · S08LR ) TO S08INT2HR

S08INT1HR SCHOMEOVSR SCHOMEOVJSLR SCHOMEECPR SCHOMEUECR S08UHR S08UCR S08LR

S08INT2HR
Table 266: Figure for S08INT2HR

ASSIGN ( S11INT1HR · 13BTPR · 1TPR · T7TPR · CH1NPR · ( ¬ 11WLR · 11NWKR ) · ¬ S02OVSR · ¬ S02OVJSLR · S02ECPR · ¬ S02UECR · ¬ S11UHR · S11UCR · S11ALR ) TO S11INT2HR
S11INT1HR 13BTPR 1TPR T7TPR CH1NPR 11WLR 11NWKR S02OVSR S02OVJSLR S02ECPR S02UECR S11UHR S11UCR S11ALR

S11INT2HR
Table 267: Figure for S11INT2HR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 108 of 171
UHR

ASSIGN ( ( ( ¬ S01BUHR ) ) · S01UECR ) TO S01UHR

S01BUHR S01UECR

S01UHR
Table 268: Figure for S01UHR

ASSIGN ( ( ( ¬ S11EUHR ) ) · S11UECR ) TO S11UHR

S11EUHR S11UECR

S11UHR
Table 269: Figure for S11UHR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 109 of 171
HR

ASSIGN ( ( S01INT2HR + S01UHR ) · S01UCR ) TO S01HR

S01INT2HR S01UCR

S01HR
S01UHR

Table 270: Figure for S01HR

ASSIGN ( ( C01INT2HR + C01UHR ) · C01UCR ) TO C01HR

C01INT2HR C01UCR

C01HR
C01UHR

Table 271: Figure for C01HR

ASSIGN ( ( S02INT2HR + S02UHR ) · S02UCR ) TO S02HR

S02INT2HR S02UCR

S02HR
S02UHR

Table 272: Figure for S02HR

ASSIGN ( ( S03INT2HR + S03UHR ) · S03UCR ) TO S03HR

S03INT2HR S03UCR

S03HR
S03UHR

Table 273: Figure for S03HR

ASSIGN ( ( S04INT2HR + S04UHR ) · S04UCR ) TO S04HR

S04INT2HR S04UCR

S04HR
S04UHR

Table 274: Figure for S04HR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 110 of 171
 ASSIGN ( ( S05INT2HR + S05UHR ) · S05UCR ) TO S05HR

S05INT2HR S05UCR

S05HR
S05UHR

Table 275: Figure for S05HR

ASSIGN ( ( S07INT2HR + S07UHR ) · S07UCR ) TO S07HR

S07INT2HR S07UCR

S07HR
S07UHR

Table 276: Figure for S07HR

ASSIGN ( ( S08INT2HR + S08UHR ) · S08UCR ) TO S08HR

S08INT2HR S08UCR

S08HR
S08UHR

Table 277: Figure for S08HR

ASSIGN ( ( S11INT2HR + S11UHR ) · S11UCR ) TO S11HR

S11INT2HR S11UCR

S11HR
S11UHR

Table 278: Figure for S11HR

ASSIGN ( ( C11INT2HR + C11UHR ) · C11UCR ) TO C11HR

C11INT2HR C11UCR

C11HR
C11UHR

Table 279: Figure for C11HR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 111 of 171
ECPR

ASSIGN ( SYSON · ( S01DECR + S01HECR + S01RECR ) ) TO S01ECPR

SYSON S01DECR

S01ECPR
S01HECR

S01RECR

Table 280: Figure for S01ECPR

ASSIGN ( SYSON · ( S02DECR + S02HECR + S02RECR ) ) TO S02ECPR

SYSON S02DECR

S02ECPR
S02HECR

S02RECR

Table 281: Figure for S02ECPR

ASSIGN ( SYSON · ( S03DECR + S03HECR + S03RECR ) ) TO S03ECPR

SYSON S03DECR

S03ECPR
S03HECR

S03RECR

Table 282: Figure for S03ECPR

ASSIGN ( SYSON · ( S04HECR + S04RECR ) ) TO S04ECPR

SYSON S04HECR

S04ECPR
S04RECR

Table 283: Figure for S04ECPR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 112 of 171
 ASSIGN ( SYSON · ( S05HECR + S05RECR ) ) TO S05ECPR

SYSON S05HECR

S05ECPR
S05RECR

Table 284: Figure for S05ECPR

ASSIGN ( SYSON · ( S07HECPR + S07DECPR + S07RECR ) ) TO S07ECPR

SYSON S07HECPR

S07ECPR
S07DECPR

S07RECR

Table 285: Figure for S07ECPR

ASSIGN ( SYSON · ( S08HECPR + S08DECPR + S08RECR ) ) TO S08ECPR

SYSON S08HECPR

S08ECPR
S08DECPR

S08RECR

Table 286: Figure for S08ECPR

ASSIGN ( SYSON · ( S11DECR + S11HECR + S11RECR ) ) TO S11ECPR

SYSON S11DECR

S11ECPR
S11HECR

S11RECR

Table 287: Figure for S11ECPR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 113 of 171
DR

ASSIGN ( SYSON · S01HR · ¬ S01UHR · ¬ S01UECR · S03DR · S03DECR · S01ALR · 11NWKR ) TO S01DR

SYSON S01HR S01UHR S01UECR S03DR S03DECR S01ALR 11NWKR

S01DR
Table 288: Figure for S01DR

ASSIGN ( SYSON · S02HR · ¬ S02UHR · ¬ S02UECR · S08DR · S08DECR · S02LR · 11NWKR ) TO S02DR

SYSON S02HR S02UHR S02UECR S08DR S08DECR S02LR 11NWKR

S02DR
Table 289: Figure for S02DR

ASSIGN ( SYSON · S03HR · ¬ S03UHR · ¬ S03UECR · S07DR · S07DECR · S03LR · 13NWKR ) TO S03DR

SYSON S03HR S03UHR S03UECR S07DR S07DECR S03LR 13NWKR

S03DR
Table 290: Figure for S03DR

ASSIGN ( SYSON · S07HR · ¬ S07UHR · ¬ S07UECR · KZJHOMEDR · KZJHOMEDECR · S07LR ) TO S07DR

SYSON S07HR S07UHR S07UECR KZJHOMEDR KZJHOMEDECR S07LR

S07DR
Table 291: Figure for S07DR

ASSIGN ( SYSON · S08HR · ¬ S08UHR · ¬ S08UECR · SCHOMEDR · SCHOMEDECR · S08LR ) TO S08DR

SYSON S08HR S08UHR S08UECR SCHOMEDR SCHOMEDECR S08LR

S08DR
Table 292: Figure for S08DR

ASSIGN ( SYSON · S11HR · ¬ S11UHR · ¬ S11UECR · S02DR · S02DECR · S11ALR · 13NWKR ) TO S11DR

SYSON S11HR S11UHR S11UECR S02DR S02DECR S11ALR 13NWKR

S11DR
Table 293: Figure for S11DR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 114 of 171
JSLR_

ASSIGN ( SYSON · ( ¬ S01EUYR · ¬ S01EUUYR · ¬ S01JSLR ) · ¬ C01ASR · ¬ C01HR1 · C01UCR ) TO C01JSLR_

SYSON S01EUYR S01EUUYR S01JSLR C01ASR C01HR1 C01UCR

C01JSLR
Table 294: Figure for C01JSLR_

ASSIGN ( SYSON · ( ¬ S11EUYR · ¬ S11EUUYR · ¬ S11JSLR ) · ¬ T14TPR · ¬ C11ASR · ¬ C11HR1 · C11UCR ) TO C11JSLR_

SYSON S11EUYR S11EUUYR S11JSLR T14TPR C11ASR C11HR1 C11UCR

C11JSLR
Table 295: Figure for C11JSLR_

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 115 of 171
JR_

ASSIGN ( C01JSLR ) TO C01JR_

C01JSLR

C01JR
Table 296: Figure for C01JR_

ASSIGN ( C11JSLR ) TO C11JR_

C11JSLR

C11JR
Table 297: Figure for C11JR_

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 116 of 171
COZ

ASSIGN ( SYSON · ( ( C01HR1 · C01JR ) + ( C11HR1 · C11JR ) ) ) TO COZ

SYSON C01HR1 C01JR

COZ
C11HR1 C11JR

Table 298: Figure for COZ

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 117 of 171
YR

ASSIGN ( ( ( SMKEY · 11WLR · ¬ CH1EYR · ( ( CH1YNR · GSBNR ) + ( CH1YR · ( ¬ CH1YNR + ¬ GSRBNR + ¬ CH1KLNR ) ) ) ) + ( ( ( CH1EYR · CH1JPR.J ) + ( CH1YR · ¬ 11WLR ) ) ) ) · ECHRBPR · SYSON ) TO CH1YR

SMKEY 11WLR CH1EYR CH1YNR GSBNR ECHRBPR SYSON

CH1YR
CH1YR CH1YNR

GSRBNR

CH1KLNR

CH1EYR CH1JPR.J

CH1YR 11WLR

Table 299: Figure for CH1YR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 118 of 171
 ASSIGN ( ( ( SMKEY · 13WLR · ¬ CH2EYR · ( ( CH2YNR · GSBNR ) + ( CH2YR · ( ¬ CH2YNR + ¬ GSRBNR + ¬ CH2KLNR ) ) ) ) + ( ( ( CH2EYR · CH2JPR.J ) + ( CH2YR · ¬ 13WLR ) ) ) ) · ECHRBPR · SYSON ) TO CH2YR

SMKEY 13WLR CH2EYR CH2YNR GSBNR ECHRBPR SYSON

CH2YR
CH2YR CH2YNR

GSRBNR

CH2KLNR

CH2EYR CH2JPR.J

CH2YR 13WLR

Table 300: Figure for CH2YR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 119 of 171
EYR

ASSIGN ( SMKEY · ( ¬ 11NCR1 · ¬ 11RCR1 · ¬ 11WLR ) · ¬ CH1YR · ( ( CH1YNR · GSBNR ) + ( CH1EYR · ¬ CH1YNR · ( ¬ GSRBNR ) ) ) )ECHRBPRSYSON TO CH1EYR

SMKEY 11NCR1 11RCR1 11WLR CH1YR CH1YNR GSBNR ECHRBPRSYSON

CH1EYR
CH1EYR CH1YNR GSRBNR

Table 301: Figure for CH1EYR

ASSIGN ( SMKEY · ( ¬ 13NCR1 · ¬ 13RCR1 · ¬ 13WLR ) · ¬ CH2YR · ( ( CH2YNR · GSBNR ) + ( CH2EYR · ¬ CH2YNR · ( ¬ GSRBNR ) ) ) )ECHRBPRSYSON TO CH2EYR

SMKEY 13NCR1 13RCR1 13WLR CH2YR CH2YNR GSBNR ECHRBPRSYSON

CH2EYR
CH2EYR CH2YNR GSRBNR

Table 302: Figure for CH2EYR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 120 of 171
JPR

ASSIGN ( CH1EYR ) TO CH1JPR

CH1EYR

CH1JPR
Table 303: Figure for CH1JPR

ASSIGN ( CH2EYR ) TO CH2JPR

CH2EYR

CH2JPR
Table 304: Figure for CH2JPR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 121 of 171
JPR.J

ASSIGN ( CH1JPR ) TO CH1JPR.J

CH1JPR

CH1JPR.J
Table 305: Figure for CH1JPR.J

ASSIGN ( CH2JPR ) TO CH2JPR.J

CH2JPR

CH2JPR.J
Table 306: Figure for CH2JPR.J

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 122 of 171
CHEYZCOUNT

ASSIGN ( ( ( CH2YR · CH2JPR.J ) + ( CH1YR · CH1JPR.J ) ) ) TO CHEYZCOUNT

CH2YR CH2JPR.J

CHEYZCOUNT
CH1YR CH1JPR.J

Table 307: Figure for CHEYZCOUNT

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 123 of 171
NPR

ASSIGN ( CH1KLNR · ¬ CH1YR ) TO CH1NPR

CH1KLNR CH1YR

CH1NPR
Table 308: Figure for CH1NPR

ASSIGN ( CH2KLNR · ¬ CH2YR ) TO CH2NPR

CH2KLNR CH2YR

CH2NPR
Table 309: Figure for CH2NPR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 124 of 171
VDUFAIL

ASSIGN ( ( ( ¬ EI1_PC1_COM · ¬ EI2_PC1_COM · ¬ EI1_PC2_COM · ¬ EI2_PC2_COM ) + ¬ ECH_PR ) ) TO VDUFAIL

EI1 PC1 COM EI2 PC1 COM EI1 PC2 COM EI2 PC2 COM

VDUFAIL
ECH PR

Table 310: Figure for VDUFAIL

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 125 of 171
RGKE_FLASH

ASSIGN ( SYSON · ¬ S01RECR · ¬ S01HR ) TO S01RGKE_FLASH

SYSON S01RECR S01HR

S01RGKE FLASH
Table 311: Figure for S01RGKE_FLASH

ASSIGN ( SYSON · ¬ S02RECR · ¬ S02HR ) TO S02RGKE_FLASH

SYSON S02RECR S02HR

S02RGKE FLASH
Table 312: Figure for S02RGKE_FLASH

ASSIGN ( SYSON · ¬ S03RECR · ¬ S03HR ) TO S03RGKE_FLASH

SYSON S03RECR S03HR

S03RGKE FLASH
Table 313: Figure for S03RGKE_FLASH

ASSIGN ( SYSON · ¬ S04RECR · ¬ S04HR ) TO S04RGKE_FLASH

SYSON S04RECR S04HR

S04RGKE FLASH
Table 314: Figure for S04RGKE_FLASH

ASSIGN ( SYSON · ¬ S05RECR · ¬ S05HR ) TO S05RGKE_FLASH

SYSON S05RECR S05HR

S05RGKE FLASH
Table 315: Figure for S05RGKE_FLASH

ASSIGN ( SYSON · ¬ S07RECR · ¬ S07HR ) TO S07RGKE_FLASH

SYSON S07RECR S07HR

S07RGKE FLASH
Table 316: Figure for S07RGKE_FLASH

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 126 of 171
 ASSIGN ( SYSON · ¬ S08RECR · ¬ S08HR ) TO S08RGKE_FLASH

SYSON S08RECR S08HR

S08RGKE FLASH
Table 317: Figure for S08RGKE_FLASH

ASSIGN ( SYSON · ¬ S11RECR · ¬ S11HR ) TO S11RGKE_FLASH

SYSON S11RECR S11HR

S11RGKE FLASH
Table 318: Figure for S11RGKE_FLASH

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 127 of 171
RGKE

ASSIGN ( SYSON · S01RECR ) TO S01RGKE

SYSON S01RECR

S01RGKE
Table 319: Figure for S01RGKE

ASSIGN ( SYSON · S02RECR ) TO S02RGKE

SYSON S02RECR

S02RGKE
Table 320: Figure for S02RGKE

ASSIGN ( SYSON · S03RECR ) TO S03RGKE

SYSON S03RECR

S03RGKE
Table 321: Figure for S03RGKE

ASSIGN ( SYSON · S04RECR ) TO S04RGKE

SYSON S04RECR

S04RGKE
Table 322: Figure for S04RGKE

ASSIGN ( SYSON · S05RECR ) TO S05RGKE

SYSON S05RECR

S05RGKE
Table 323: Figure for S05RGKE

ASSIGN ( SYSON · S07RECR ) TO S07RGKE

SYSON S07RECR

S07RGKE
Table 324: Figure for S07RGKE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 128 of 171
 ASSIGN ( SYSON · S08RECR ) TO S08RGKE

SYSON S08RECR

S08RGKE
Table 325: Figure for S08RGKE

ASSIGN ( SYSON · S11RECR ) TO S11RGKE

SYSON S11RECR

S11RGKE
Table 326: Figure for S11RGKE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 129 of 171
HGE_FLASH

ASSIGN ( SYSON · S01HR · ¬ S01DECR · ¬ S01HECR ) TO S01HGE_FLASH

SYSON S01HR S01DECR S01HECR

S01HGE FLASH
Table 327: Figure for S01HGE_FLASH

ASSIGN ( SYSON · S02HR · ¬ S02DECR · ¬ S02HECR ) TO S02HGE_FLASH

SYSON S02HR S02DECR S02HECR

S02HGE FLASH
Table 328: Figure for S02HGE_FLASH

ASSIGN ( SYSON · S03HR · ¬ S03DECR · ¬ S03HECR ) TO S03HGE_FLASH

SYSON S03HR S03DECR S03HECR

S03HGE FLASH
Table 329: Figure for S03HGE_FLASH

ASSIGN ( SYSON · S07HR · ¬ S07DECR · ¬ S07HECR ) TO S07HGE_FLASH

SYSON S07HR S07DECR S07HECR

S07HGE FLASH
Table 330: Figure for S07HGE_FLASH

ASSIGN ( SYSON · S08HR · ¬ S08DECR · ¬ S08HECR ) TO S08HGE_FLASH

SYSON S08HR S08DECR S08HECR

S08HGE FLASH
Table 331: Figure for S08HGE_FLASH

ASSIGN ( SYSON · S11HR · ¬ S11DECR · ¬ S11HECR ) TO S11HGE_FLASH

SYSON S11HR S11DECR S11HECR

S11HGE FLASH
Table 332: Figure for S11HGE_FLASH

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 130 of 171
HGKE

ASSIGN ( SYSON · S01HR · S01HECR ) TO S01HGKE

SYSON S01HR S01HECR

S01HGKE
Table 333: Figure for S01HGKE

ASSIGN ( SYSON · S02HR · S02HECR ) TO S02HGKE

SYSON S02HR S02HECR

S02HGKE
Table 334: Figure for S02HGKE

ASSIGN ( SYSON · S03HR · S03HECR ) TO S03HGKE

SYSON S03HR S03HECR

S03HGKE
Table 335: Figure for S03HGKE

ASSIGN ( SYSON · S07HR · S07HECR ) TO S07HGKE

SYSON S07HR S07HECR

S07HGKE
Table 336: Figure for S07HGKE

ASSIGN ( SYSON · S08HR · S08HECR ) TO S08HGKE

SYSON S08HR S08HECR

S08HGKE
Table 337: Figure for S08HGKE

ASSIGN ( SYSON · S11HR · S11HECR ) TO S11HGKE

SYSON S11HR S11HECR

S11HGKE
Table 338: Figure for S11HGKE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 131 of 171
DGE_FLASH

ASSIGN ( SYSON · S01DR · ¬ S01DECR ) TO S01DGE_FLASH

SYSON S01DR S01DECR

S01DGE FLASH
Table 339: Figure for S01DGE_FLASH

ASSIGN ( SYSON · S02DR · ¬ S02DECR ) TO S02DGE_FLASH

SYSON S02DR S02DECR

S02DGE FLASH
Table 340: Figure for S02DGE_FLASH

ASSIGN ( SYSON · S03DR · ¬ S03DECR ) TO S03DGE_FLASH

SYSON S03DR S03DECR

S03DGE FLASH
Table 341: Figure for S03DGE_FLASH

ASSIGN ( SYSON · S07DR · ¬ S07DECR ) TO S07DGE_FLASH

SYSON S07DR S07DECR

S07DGE FLASH
Table 342: Figure for S07DGE_FLASH

ASSIGN ( SYSON · S08DR · ¬ S08DECR ) TO S08DGE_FLASH

SYSON S08DR S08DECR

S08DGE FLASH
Table 343: Figure for S08DGE_FLASH

ASSIGN ( SYSON · S11DR · ¬ S11DECR ) TO S11DGE_FLASH

SYSON S11DR S11DECR

S11DGE FLASH
Table 344: Figure for S11DGE_FLASH

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 132 of 171
DGKE

ASSIGN ( SYSON · S01DR · S01DECR ) TO S01DGKE

SYSON S01DR S01DECR

S01DGKE
Table 345: Figure for S01DGKE

ASSIGN ( SYSON · S02DR · S02DECR ) TO S02DGKE

SYSON S02DR S02DECR

S02DGKE
Table 346: Figure for S02DGKE

ASSIGN ( SYSON · S03DR · S03DECR ) TO S03DGKE

SYSON S03DR S03DECR

S03DGKE
Table 347: Figure for S03DGKE

ASSIGN ( SYSON · S07DR · S07DECR ) TO S07DGKE

SYSON S07DR S07DECR

S07DGKE
Table 348: Figure for S07DGKE

ASSIGN ( SYSON · S08DR · S08DECR ) TO S08DGKE

SYSON S08DR S08DECR

S08DGKE
Table 349: Figure for S08DGKE

ASSIGN ( SYSON · S11DR · S11DECR ) TO S11DGKE

SYSON S11DR S11DECR

S11DGKE
Table 350: Figure for S11DGKE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 133 of 171
HGE-_FLASH

ASSIGN ( SYSON · C01HR · ¬ C01HECR ) TO C01HGE-_FLASH

SYSON C01HR C01HECR

C01HGE- FLASH
Table 351: Figure for C01HGE-_FLASH

ASSIGN ( SYSON · C11HR · ¬ C11HECR ) TO C11HGE-_FLASH

SYSON C11HR C11HECR

C11HGE- FLASH
Table 352: Figure for C11HGE-_FLASH

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 134 of 171
HGKE-

ASSIGN ( SYSON · C01HR · C01HECR ) TO C01HGKE-

SYSON C01HR C01HECR

C01HGKE-
Table 353: Figure for C01HGKE-

ASSIGN ( SYSON · C11HR · C11HECR ) TO C11HGKE-

SYSON C11HR C11HECR

C11HGKE-
Table 354: Figure for C11HGKE-

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 135 of 171
LRKE

ASSIGN ( SYSON · ( S01ALR + S01BLR + C01ALR + C01BLR ) ) TO S01/C01LRKE

SYSON S01ALR

S01/C01LRKE
S01BLR

C01ALR

C01BLR

Table 355: Figure for S01/C01LRKE

ASSIGN ( SYSON · ( S02LR ) ) TO S02LRKE

SYSON S02LR

S02LRKE
Table 356: Figure for S02LRKE

ASSIGN ( SYSON · ( S03LR ) ) TO S03LRKE

SYSON S03LR

S03LRKE
Table 357: Figure for S03LRKE

ASSIGN ( SYSON · ( S04LR ) ) TO S04LRKE

SYSON S04LR

S04LRKE
Table 358: Figure for S04LRKE

ASSIGN ( SYSON · ( S05LR ) ) TO S05LRKE

SYSON S05LR

S05LRKE
Table 359: Figure for S05LRKE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 136 of 171
 ASSIGN ( SYSON · ( S07LR ) ) TO S07LRKE

SYSON S07LR

S07LRKE
Table 360: Figure for S07LRKE

ASSIGN ( SYSON · ( S08LR ) ) TO S08LRKE

SYSON S08LR

S08LRKE
Table 361: Figure for S08LRKE

ASSIGN ( SYSON · ( S11ALR + S11ELR + C11ALR + C11ELR ) ) TO S11/C11LRKE

SYSON S11ALR

S11/C11LRKE
S11ELR

C11ALR

C11ELR

Table 362: Figure for S11/C11LRKE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 137 of 171
FLASH-

ASSIGN ( SYSON · S01UCR · S01JSLR ) TO C01FLASH-

SYSON S01UCR S01JSLR

C01FLASH-
Table 363: Figure for C01FLASH-

ASSIGN ( SYSON · S11UCR · S11JSLR ) TO C11FLASH-

SYSON S11UCR S11JSLR

C11FLASH-
Table 364: Figure for C11FLASH-

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 138 of 171
LRK_FLASH

ASSIGN ( ( S01/C01ESUYR + S01/C01EUUYR ) · S01/C01JSLR · SYSON ) TO S01/C01LRK_FLASH

S01/C01ESUYR S01/C01JSLR SYSON

S01/C01LRK FLASH
S01/C01EUUYR

Table 365: Figure for S01/C01LRK_FLASH

ASSIGN ( ( S02ESUYR + S02EUUYR ) · S02JSLR · SYSON ) TO S02LRK_FLASH

S02ESUYR S02JSLR SYSON

S02LRK FLASH
S02EUUYR

Table 366: Figure for S02LRK_FLASH

ASSIGN ( ( S03ESUYR + S03EUUYR ) · S03JSLR · SYSON ) TO S03LRK_FLASH

S03ESUYR S03JSLR SYSON

S03LRK FLASH
S03EUUYR

Table 367: Figure for S03LRK_FLASH

ASSIGN ( ( S04ESUYR + S04EUUYR ) · S04JSLR · SYSON ) TO S04LRK_FLASH

S04ESUYR S04JSLR SYSON

S04LRK FLASH
S04EUUYR

Table 368: Figure for S04LRK_FLASH

ASSIGN ( ( S05ESUYR + S05EUUYR ) · S05JSLR · SYSON ) TO S05LRK_FLASH

S05ESUYR S05JSLR SYSON

S05LRK FLASH
S05EUUYR

Table 369: Figure for S05LRK_FLASH

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 139 of 171
 ASSIGN ( ( S07ESUYR + S07EUUYR ) · S07JSLR · SYSON ) TO S07LRK_FLASH

S07ESUYR S07JSLR SYSON

S07LRK FLASH
S07EUUYR

Table 370: Figure for S07LRK_FLASH

ASSIGN ( ( S08ESUYR + S08EUUYR ) · S08JSLR · SYSON ) TO S08LRK_FLASH

S08ESUYR S08JSLR SYSON

S08LRK FLASH
S08EUUYR

Table 371: Figure for S08LRK_FLASH

ASSIGN ( ( S11/C11ESUYR + S11/C11EUUYR ) · S11/C11JSLR · SYSON ) TO S11/C11LRK_FLASH

S11/C11ESUYR S11/C11JSLR SYSON

S11/C11LRK FLASH
S11/C11EUUYR

Table 372: Figure for S11/C11LRK_FLASH

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 140 of 171
OVKE

ASSIGN ( SYSON ) TO S01OVKE

SYSON

S01OVKE
Table 373: Figure for S01OVKE

ASSIGN ( SYSON · ¬ S02OVSR · ¬ S02JSLR ) TO S02OVKE

SYSON S02OVSR S02JSLR

S02OVKE
Table 374: Figure for S02OVKE

ASSIGN ( SYSON · ¬ S03OVSR · ¬ S03JSLR ) TO S03OVKE

SYSON S03OVSR S03JSLR

S03OVKE
Table 375: Figure for S03OVKE

ASSIGN ( SYSON · ¬ S04OVSR · ¬ S04JSLR ) TO S04OVKE

SYSON S04OVSR S04JSLR

S04OVKE
Table 376: Figure for S04OVKE

ASSIGN ( SYSON · ¬ S05OVSR · ¬ S05JSLR ) TO S05OVKE

SYSON S05OVSR S05JSLR

S05OVKE
Table 377: Figure for S05OVKE

ASSIGN ( SYSON · ¬ S07OVSR · ¬ S07JSLR ) TO S07OVKE

SYSON S07OVSR S07JSLR

S07OVKE
Table 378: Figure for S07OVKE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 141 of 171
 ASSIGN ( SYSON · ¬ S08OVSR · ¬ S08JSLR ) TO S08OVKE

SYSON S08OVSR S08JSLR

S08OVKE
Table 379: Figure for S08OVKE

ASSIGN ( SYSON ) TO S11OVKE

SYSON

S11OVKE
Table 380: Figure for S11OVKE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 142 of 171
OV_FLASH

ASSIGN ( SYSON · ¬ S01OVSR · S01JSLR ) TO S01OV_FLASH

SYSON S01OVSR S01JSLR

S01OV FLASH
Table 381: Figure for S01OV_FLASH

ASSIGN ( SYSON · ¬ S02OVSR · S02JSLR ) TO S02OV_FLASH

SYSON S02OVSR S02JSLR

S02OV FLASH
Table 382: Figure for S02OV_FLASH

ASSIGN ( SYSON · ¬ S03OVSR · S03JSLR ) TO S03OV_FLASH

SYSON S03OVSR S03JSLR

S03OV FLASH
Table 383: Figure for S03OV_FLASH

ASSIGN ( SYSON · ¬ S04OVSR · S04JSLR ) TO S04OV_FLASH

SYSON S04OVSR S04JSLR

S04OV FLASH
Table 384: Figure for S04OV_FLASH

ASSIGN ( SYSON · ¬ S05OVSR · S05JSLR ) TO S05OV_FLASH

SYSON S05OVSR S05JSLR

S05OV FLASH
Table 385: Figure for S05OV_FLASH

ASSIGN ( SYSON · ¬ S07OVSR · S07JSLR ) TO S07OV_FLASH

SYSON S07OVSR S07JSLR

S07OV FLASH
Table 386: Figure for S07OV_FLASH

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 143 of 171
 ASSIGN ( SYSON · ¬ S08OVSR · S08JSLR ) TO S08OV_FLASH

SYSON S08OVSR S08JSLR

S08OV FLASH
Table 387: Figure for S08OV_FLASH

ASSIGN ( SYSON · ¬ S11OVSR · S11JSLR ) TO S11OV_FLASH

SYSON S11OVSR S11JSLR

S11OV FLASH
Table 388: Figure for S11OV_FLASH

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 144 of 171
FLASH

ASSIGN ( SYSON · S01UHR · ¬ S01UECR ) TO S01FLASH

SYSON S01UHR S01UECR

S01FLASH
Table 389: Figure for S01FLASH

ASSIGN ( SYSON · S02UHR · ¬ S02UECR ) TO S02FLASH

SYSON S02UHR S02UECR

S02FLASH
Table 390: Figure for S02FLASH

ASSIGN ( SYSON · S03UHR · ¬ S03UECR ) TO S03FLASH

SYSON S03UHR S03UECR

S03FLASH
Table 391: Figure for S03FLASH

ASSIGN ( SYSON · S11UHR · ¬ S11UECR ) TO S11FLASH

SYSON S11UHR S11UECR

S11FLASH
Table 392: Figure for S11FLASH

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 145 of 171
UGKE

ASSIGN ( SYSON · S01UHR · S01UECR ) TO S01UGKE

SYSON S01UHR S01UECR

S01UGKE
Table 393: Figure for S01UGKE

ASSIGN ( SYSON · S11UHR · S11UECR ) TO S11UGKE

SYSON S11UHR S11UECR

S11UGKE
Table 394: Figure for S11UGKE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 146 of 171
UFLASH

ASSIGN ( SYSON · S01UHR · ¬ S01UECR ) TO S01UFLASH

SYSON S01UHR S01UECR

S01UFLASH
Table 395: Figure for S01UFLASH

ASSIGN ( SYSON · S11UHR · ¬ S11UECR ) TO S11UFLASH

SYSON S11UHR S11UECR

S11UFLASH
Table 396: Figure for S11UFLASH

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 147 of 171
RWK_FLASH

ASSIGN ( SYSON · 11RWR · ¬ 11NWKR · ¬ 11RWKR ) TO 11RWK_FLASH

SYSON 11RWR 11NWKR 11RWKR

11RWK FLASH
Table 397: Figure for 11RWK_FLASH

ASSIGN ( SYSON · 13RWR · ¬ 13NWKR · ¬ 13RWKR ) TO 13RWK_FLASH

SYSON 13RWR 13NWKR 13RWKR

13RWK FLASH
Table 398: Figure for 13RWK_FLASH

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 148 of 171
RWKE

ASSIGN ( SYSON · 11ATPR · 11RWKR · ¬ 11NWKR · 11RWR ) TO 11ARWKE

SYSON 11ATPR 11RWKR 11NWKR 11RWR

11ARWKE
Table 399: Figure for 11ARWKE

ASSIGN ( SYSON · 13BTPR · 11RWKR · ¬ 11NWKR · 11RWR ) TO 11BRWKE

SYSON 13BTPR 11RWKR 11NWKR 11RWR

11BRWKE
Table 400: Figure for 11BRWKE

ASSIGN ( SYSON · T3TPR · 13RWKR · ¬ 13NWKR · 13RWR ) TO 13BRWKE

SYSON T3TPR 13RWKR 13NWKR 13RWR

13BRWKE
Table 401: Figure for 13BRWKE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 149 of 171
RWKRE

ASSIGN ( SYSON · ¬ 11ATPR · 11RWKR · ¬ 11NWKR · 11RWR ) TO 11ARWKRE

SYSON 11ATPR 11RWKR 11NWKR 11RWR

11ARWKRE
Table 402: Figure for 11ARWKRE

ASSIGN ( SYSON · ¬ 13BTPR · 11RWKR · ¬ 11NWKR · 11RWR ) TO 11BRWKRE

SYSON 13BTPR 11RWKR 11NWKR 11RWR

11BRWKRE
Table 403: Figure for 11BRWKRE

ASSIGN ( SYSON · ¬ T3TPR · 13RWKR · ¬ 13NWKR · 13RWR ) TO 13BRWKRE

SYSON T3TPR 13RWKR 13NWKR 13RWR

13BRWKRE
Table 404: Figure for 13BRWKRE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 150 of 171
WLKE

ASSIGN ( SYSON · ¬ 11WLR ) TO 11WLKE

SYSON 11WLR

11WLKE
Table 405: Figure for 11WLKE

ASSIGN ( SYSON · ¬ 13WLR ) TO 13WLKE

SYSON 13WLR

13WLKE
Table 406: Figure for 13WLKE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 151 of 171
NWK_FLASH

ASSIGN ( SYSON · 11NWR · ¬ 11NWKR · ¬ 11RWKR ) TO 11NWK_FLASH

SYSON 11NWR 11NWKR 11RWKR

11NWK FLASH
Table 407: Figure for 11NWK_FLASH

ASSIGN ( SYSON · 13NWR · ¬ 13NWKR · ¬ 13RWKR ) TO 13NWK_FLASH

SYSON 13NWR 13NWKR 13RWKR

13NWK FLASH
Table 408: Figure for 13NWK_FLASH

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 152 of 171
NWKE

ASSIGN ( SYSON · 11ATPR · 11NWKR · ¬ 11RWKR · 11NWR ) TO 11ANWKE

SYSON 11ATPR 11NWKR 11RWKR 11NWR

11ANWKE
Table 409: Figure for 11ANWKE

ASSIGN ( SYSON · 13BTPR · 11NWKR · ¬ 11RWKR · 11NWR ) TO 11BNWKE

SYSON 13BTPR 11NWKR 11RWKR 11NWR

11BNWKE
Table 410: Figure for 11BNWKE

ASSIGN ( SYSON · T3TPR · 13NWKR · ¬ 13RWKR · 13NWR ) TO 13BNWKE

SYSON T3TPR 13NWKR 13RWKR 13NWR

13BNWKE
Table 411: Figure for 13BNWKE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 153 of 171
NWKRE

ASSIGN ( SYSON · 11NWKR · ¬ 11RWKR · 11NWR ) TO 11NWKRE

SYSON 11NWKR 11RWKR 11NWR

11NWKRE
Table 412: Figure for 11NWKRE

ASSIGN ( SYSON · 13NWKR · ¬ 13RWKR · 13NWR ) TO 13NWKRE

SYSON 13NWKR 13RWKR 13NWR

13NWKRE
Table 413: Figure for 13NWKRE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 154 of 171
TKE

ASSIGN ( SYSON · ( ¬ S01ASR + ¬ C01ASR + ¬ S08ASR ) · 1ATPR ) TO 1ATKE

SYSON S01ASR 1ATPR

1ATKE
C01ASR

S08ASR

Table 414: Figure for 1ATKE

ASSIGN ( SYSON · ( ¬ S01ASR + ¬ C01ASR + ¬ S02ASR + ¬ S04ASR + ¬ S08ASR + ¬ S11ASR ) · 1TPR ) TO 1TKE

SYSON S01ASR 1TPR

1TKE
C01ASR

S02ASR

S04ASR

S08ASR

S11ASR

Table 415: Figure for 1TKE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 155 of 171
 ASSIGN ( SYSON · ( ¬ S04ASR + ¬ S11ASR + ( ¬ S01ASR · 11RWR ) + ( ¬ C01ASR · 11RWR ) ) · 11ATPR ) TO 11ATKE

SYSON S04ASR 11ATPR

11ATKE
S11ASR

S01ASR 11RWR

C01ASR 11RWR

Table 416: Figure for 11ATKE

ASSIGN ( SYSON · ( ¬ S01ASR + ¬ S05ASR + ( ¬ S11ASR · 13RWR ) + ( ¬ C11ASR · 13RWR ) ) · 13ATPR ) TO 13ATKE

SYSON S01ASR 13ATPR

13ATKE
S05ASR

S11ASR 13RWR

C11ASR 13RWR

Table 417: Figure for 13ATKE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 156 of 171
 ASSIGN ( SYSON · ( ¬ S01ASR + ¬ C01ASR + ¬ S02ASR + ( ¬ S04ASR · 11RWR ) + ( ¬ S11ASR · 11RWR ) ) · 13BTPR ) TO 13BTKE

SYSON S01ASR 13BTPR

13BTKE
C01ASR

S02ASR

S04ASR 11RWR

S11ASR 11RWR

Table 418: Figure for 13BTKE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 157 of 171
TKRE

ASSIGN ( SYSON · ¬ 1ATPR ) TO 1ATKRE

SYSON 1ATPR

1ATKRE
Table 419: Figure for 1ATKRE

ASSIGN ( SYSON · ¬ 1TPR ) TO 1TKRE

SYSON 1TPR

1TKRE
Table 420: Figure for 1TKRE

ASSIGN ( SYSON · ¬ 11ATPR ) TO 11ATKRE

SYSON 11ATPR

11ATKRE
Table 421: Figure for 11ATKRE

ASSIGN ( SYSON · ¬ 13ATPR ) TO 13ATKRE

SYSON 13ATPR

13ATKRE
Table 422: Figure for 13ATKRE

ASSIGN ( SYSON · ¬ 13BTPR ) TO 13BTKRE

SYSON 13BTPR

13BTKRE
Table 423: Figure for 13BTKRE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 158 of 171
TNKRE

ASSIGN ( SYSON · ¬ 11ATPR · ( 11NWR ) ) TO 11ATNKRE

SYSON 11ATPR 11NWR

11ATNKRE
Table 424: Figure for 11ATNKRE

ASSIGN ( SYSON · ¬ 13ATPR · ( 13NWR ) ) TO 13ATNKRE

SYSON 13ATPR 13NWR

13ATNKRE
Table 425: Figure for 13ATNKRE

ASSIGN ( SYSON · ¬ 13BTPR · ( 11NWR ) ) TO 13BTNKRE

SYSON 13BTPR 11NWR

13BTNKRE
Table 426: Figure for 13BTNKRE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 159 of 171
TNKE

ASSIGN ( SYSON · 11ATPR · ( ¬ S04ASR + ¬ S11ASR ) ) TO 11ATNKE

SYSON 11ATPR S04ASR

11ATNKE
S11ASR

Table 427: Figure for 11ATNKE

ASSIGN ( SYSON · 13ATPR · ( ¬ S01ASR + ¬ S05ASR ) ) TO 13ATNKE

SYSON 13ATPR S01ASR

13ATNKE
S05ASR

Table 428: Figure for 13ATNKE

ASSIGN ( SYSON · 13BTPR · ( ¬ S01ASR + ¬ C01ASR + ¬ S02ASR ) ) TO 13BTNKE

SYSON 13BTPR S01ASR

13BTNKE
C01ASR

S02ASR

Table 429: Figure for 13BTNKE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 160 of 171
SFR_INT

ASSIGN ( ( S01DECR + S01HECR + S01RECR ) · ( S02DECR + S02HECR + S02RECR ) · ( S03DECR + S03HECR + S03RECR ) · ( S11DECR + S11HECR + S11RECR ) · ( S01UECR + ¬ S01UHR ) · ( S11UECR + ¬ S11UHR ) · ( S04RECR + S04HECR ) · (
S05RECR + S05HECR ) · ( S07RECR + S07HECR + S07DECR ) · ( S08RECR + S08HECR + S08DECR ) · ( ¬ C01HR + C01HECR ) · ( ¬ C11HR + C11HECR ) ) TO SFR_INT
S01DECR S02DECR S03DECR S11DECR S01UECR S11UECR S04RECR S05RECR S07RECR S08RECR C01HR C11HR

SFR INT
S01HECR S02HECR S03HECR S11HECR S01UHR S11UHR S04HECR S05HECR S07HECR S08HECR C01HECR C11HECR

S01RECR S02RECR S03RECR S11RECR S07DECR S08DECR

Table 430: Figure for SFR_INT

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 161 of 171
SFR_JSLR

ASSIGN ( ¬ SFR_INT ) TO SFR_JSLR

SFR INT

SFR JSLR
Table 431: Figure for SFR_JSLR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 162 of 171
SFR_NJPR

ASSIGN ( SFR_JSLR ) TO SFR_NJPR

SFR JSLR

SFR NJPR
Table 432: Figure for SFR_NJPR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 163 of 171
SFR

ASSIGN ( SFR_INT + ¬ SFR_NJPR ) TO SFR

SFR INT

SFR
SFR NJPR

Table 433: Figure for SFR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 164 of 171
SIG_FAIL_BUZ

ASSIGN ( ¬ SFR · ¬ SFMR ) TO SIG_FAIL_BUZ

SFR SFMR

SIG FAIL BUZ

Table 434: Figure for SIG_FAIL_BUZ

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 165 of 171
SIG_FAIL_KE

ASSIGN ( ¬ SFR ) TO SIG_FAIL_KE

SFR

SIG FAIL KE
Table 435: Figure for SIG_FAIL_KE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 166 of 171
SFMR

ASSIGN ( ¬ SFR · ( SIG_FACK_P + SFMR ) ) TO SFMR

SFR SIG FACK P

SFMR
SFMR

Table 436: Figure for SFMR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 167 of 171
PFR_INT

ASSIGN ( ( 11NDKR + 11RDKR ) · ( 13NDKR + 13RDKR ) ) TO PFR_INT

11NDKR 13NDKR

PFR INT
11RDKR 13RDKR

Table 437: Figure for PFR_INT

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 168 of 171
PFR_JSLR

ASSIGN ( ¬ PFR_INT ) TO PFR_JSLR

PFR INT

PFR JSLR
Table 438: Figure for PFR_JSLR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 169 of 171
PFR_NJPR

ASSIGN ( PFR_JSLR ) TO PFR_NJPR

PFR JSLR

PFR NJPR
Table 439: Figure for PFR_NJPR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 170 of 171
PFR

ASSIGN ( PFR_INT + PFR_NJPR ) TO PFR

PFR INT

PFR
PFR NJPR

Table 440: Figure for PFR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 171 of 171
PT_FAIL_BUZ

ASSIGN ( ¬ PFR · ¬ PFMR ) TO PT_FAIL_BUZ

PFR PFMR

PT FAIL BUZ
Table 441: Figure for PT_FAIL_BUZ

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 172 of 171
PT_FAIL_KE

ASSIGN ( ¬ PFR ) TO PT_FAIL_KE

PFR

PT FAIL KE
Table 442: Figure for PT_FAIL_KE

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 173 of 171
PFMR

ASSIGN ( ¬ PFR · ( PT_FACK_P + PFMR ) ) TO PFMR

PFR PT FACK P

PFMR
PFMR

Table 443: Figure for PFMR

test1 logic circuits | Generated using SigDATE v4.0.1.3 | Tuesday 27th August, 2024 (21:37) Page 174 of 171