Series 7200 UPS

(Single & 1+1 Modules)

Service Manual (Vol 1 of 2)

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Manual Part Nº04577435-3

7200 Series UPS Service Manual

MANUAL REGISTRATION
• THIS MANUAL IS A CONTROLLED DOCUMENT AND WILL BE PERIODICALLY
UPDATED.
• THIS MANUAL IS ISSUED IN TWO VOLUMES
VOL.1 CONTAINING THE TECHNICAL INFORMATION
VOL.2 CIRCUIT DIAGRAMS AND DRAWINGS.
• REGISTRATION IS FOR BOTH VOLUMES
• IN ORDER TO ENSURE THAT YOU RECEIVE ANY AMMENDMENT PLEASE
REGISTER THIS MANUAL WITH THE TECHNICAL SUPPORT DEPARTMENT BY
RETURNING A COPY OF THIS FORM TO:

GAYNOR SWADLING
TECHNICAL SUPPORT DEPARTMENT
LIEBERT GLOBAL SERVICES
GLOBE PARK
MARLOW
BUCKINGHAMSHIRE
SL7 1YG
ENGLAND

• ALTERNATIVELY FAX A COPY OF THIS FORM TO THE ABOVE ADDRESS ON

44 (0)1628 403296

Manual Registration
Number

Name of Registered Holder

Address of Holder Company

Name/Building

Street/Road

Area/region

Town/City

County/State

Post/Zip Code

Country

Telephone Number

FAX Number

Issue 2 Dated 21/08/97 i

 7200 Series UPS Service Manual )

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7200 Series UPS Service Manual

AMENDMENT RECORD

Series 7200 1+1 Service Manual

Please enter the Manual Serial

Manual Serial Number:
Nº for future record

Issue
Issue Nº Amendment Amended By Date
Date

Issue 1 16/04/97 Initial issue for single modules – 16/04/97

Issue 2 21/08/97 Re issue of complete Vol. 1 & Vol. 2 updated to 1+1

Updated Amendment Record Sheet.

Volume 1 Front Cover
Sect 2
Pages 2-19 to 2-22 : 2-25 & 2-26 : 2-33 to 2-38 : 2-
41 to 2-52 : 2-57 to 2-64 : 2-67 to 2-70 : SET UP
MENU commissioning record sheet.
Vol. -1 Sect 4
09/11/98
Issue 3 Pages 4-37 & 4-38.
Sect 10
Pages 10-3 & 10-4.
Sect 11
Pages 11-27 to 11-34.
Appendix C
Pages C3 to C6.

Volume 2 Front Cover

Issue of latest drawings to
Sect 1 Power circuit diaagrams(40 pages)
Vol. -2 Sect 3 Inverter Sub-Assembly diagrams (4 pages)
09/11/98
Issue 3 Sect 4 PCB Assembly Diagrams (72 pages)
Sect 5 Battery Considerations (21 pages)
Sect 6 Alarm Relay Options & RAMS (6 pages)
Sect 7 Input Harmonic Filters (14 pages)

Issue 3 Dated 09/11/98 iii

 7200 Series UPS Service Manual )

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7200 Series UPS Service Manual

This Service manual contains information concerning the installation operation and service of the
following Liebert 7200 series UPS

Series 7200 Single Models

Part Number
(1+1 Compatable)
30kVA Single Module UPS (1+1 Compatable) 5410305 R

40kVA Single Module UPS (1+1 Compatable) 5410307 T

60kVA Single Module UPS (1+1 Compatable) 5410310 W

Series 7200 Single Model Part Number

30kVA Single Module UPS 5410303 P

40kVA Single Module UPS 5410304 Q

60kVA Single Module UPS 5410308 U

This manual should always be read in conjunction with Volume 2 which contains the circuit and assem-
bly drawings for the above Liebert 7200 series modules.

Liebert pursues a policy of continual product improvement and reserves the right to make changes to
equipment design without notice.

If any problems or mistakes are encountered with the procedures contained in the Service manual contact
the local Liebert office for assistance, or alternatively contact Liebert Global Support at the address
below.

Liebert Global Services,

Globe Park, Marlow, Bucks. SL71YG, UK
Telephone: 44 (0) 1628 403200
Fax: 44 (0) 1628 403203

Liebert is a BS EN ISO9001:1994 registered company.

 Copyright 1997 by Liebert Global Services.

Unauthorised reproduction prohibited.
All rights Reserved.

Issue 2 Dated 21/08/97 v

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7200 Series UPS Service Manual

Limitations of Use

ELECTROMAGNETIC COMPATABILITY
The equipment covered by this manual complies with the requirements of the
EMC Directive 89/336/EEC and the published technical standards. Continued
compliance requires installation in accordance with these instructions and use of
manufacturer approved accessories only.

WARNING The 7200 series UPS is a Class A product.

When used in a domestic environment a unit may cause radio interference,
If this is the case the user may be required to take additional measures

WARNING HIGH EARTH LEAKAGE CURRENT.

Earth connection is essential before connecting the utility supply.
This equipment must be earthed in accordance with local electrical codes.

WARNING This UPS does not incorporate automatic back-feed protection. A warning label
must be fitted to all external primary power isolators stating:
ISOLATE THE UNINTERRUPTIBLE POWER SYSTEM BEFORE WORKING ON
THIS CIRCUIT.

UTILITY SUPPLY WARNING

The 7200 series UPS should not be supplied from electrical power systems of the
`IT' (Impédance à Terre) type.
(IEC 364 - ELECTRICAL INSTALLATION OF BUILDINGS)
Note: Where use on ‘IT’ systems is required an optional input isolation transform-
er should be fitted.

CAUTION This equipment is fitted with RFI suppression filters

Earth leakage exceeds 3.5mA but is less than 300mA.
Transient and steady-state earth leakage currents, which occur when starting the
equipment, should be taken into account when selecting instantaneous RCCB or
RCCD devices.
Note also that the earth leakage currents of the load will be carried by this RCCB
or RCCD.

PLEASE NOTE These products are intended for Commercial/Industrial use only, and are not suit-
able for use in any life support applications.

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 7200 Series UPS Service Manual )

Important Instructions for safe use

GENERAL The UPS must be commissioned by a Liebert approved engineer before it is put
into service. Failure to observe this condition will invalidate any implied warranty.

In common with other types of high power equipment, dangerous voltages are
present with the UPS and battery enclosure. The risk of contact with these volt-
ages is minimised as the live component parts are housed behind a hinged lock-
able door.
Further internal safety screens make the equipment protected to IP20 standards.
No risk exists to any personnel when operating the equipment in the normal man-
ner, following the recommended operating procedures.
All equipment maintenance and servicing procedures involving internal access,
should be carried out by trained personnel.

The UPS is for indoor use [Link] must be protected from rain or excessive mois-
ture and installed in a clean environment, free from flammable liquids, gasses, or
corrosive substances. Do not put drinks, plants, or any other containers holding
liquids, on top of the unit.

BATTERIES Battery manufacturers supply details of the necessary precautions to be observed

when working on, or in the vicinity of, a large bank of battery cells. These precau-
tions should be followed at all times.
Particular attention should be paid to the recommendations concerning local en-
vironmental conditions and the provision of protective clothing, first aid and fire-
fighting facilities.

TEST EQUIPMENT
When the battery is under charge it is earth-referenced about its mid-point e.g. if
the battery is being charged at 460V the battery extremities will be =230V and -
230V with respect to neutral (earth). When using mains powered test equipment
such as oscilloscopes in the UPS high voltage area, always use a differential
mode of operation to avoid the need to disconnect the oscilloscope frame earth.

PERSONNEL When working inside the UPS (trained personnel only) is recommended that pro-
tection be worn to prevent eye damage, should an electric arc be struck by mis-
handling or severe electrical fault.
Some of the power components are very heavy. If their removal is necessary en-
sure that sufficient manpower is available, otherwise use adequate mechanical
handling equipment.
When working in the general area of the UPS where high voltages are present, a
second person should be standing-by to assist and summon help in case of acci-
dent.

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7200 Series UPS Service Manual

Personnel Categorisation

The following definitions are given to categorise the scope, and use of this service manual:
Operator/User
This service manual is outside the scope for use by personnel who have received
instruction on the correct operation of the UPS controls; limited to operation of the
unit circuit breakers and the Front Control Panel; operator/users are not permitted
to remove any panels which are retained by screws.

Competent Personnel
The Troubleshooting section, and Service procedures contained in this manual
are normally outside the scope of personnel categorised competent; though they
may be aware of the dangers appropriate to working with hazardous voltages. A
Competent engineer is deemed to have sufficient technical skills/training to make
electrical connections, install batteries, close and open circuit breakers/fuses etc.
(i.e. a qualified electrician) he is not categorised as service personnel.

Service Personnel
This Service manual is designed for use by engineers who have received the rel-
evant Liebert training and are password authorised.

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7200 Series UPS Service Manual CONTENTS

7200 Series UPS Service Manual

Contents

Section 1 - System Description

Chapter 1 : Provides a functional description of the UPS equipment and explains its
power operation at ‘block diagram’ level. It describes the function of the
Rectifier, Battery, Inverter and Static Bypass power blocks together with
the function and use of the power switches and circuit breakers.

Chapter 2 : Provides a detailed circuit description of the UPS main power circuit
diagrams – each modules’ diagrams are described independently.

Section 2 - Installation & Commissioning

Chapter 1 : Provides information regarding the UPS installation procedures including

positioning and environmental considerations, preliminary checks, power
and control cable connection, and battery installation.

Chapter 2 : Provides a detailed commissioning procedure which includes pre-

commissioning checks, PCB configuration, voltage & frequency
conversion, start-up and software commissioning, and final power checks.

Section 3 - Control Power Supply

Chapter 1: Provides a general description of the control power philosophy and

contains simplified diagrams to illustrate the power supply primary
sources and distribution.

Chapter 2: Provides a detailed description of the AC-DC Power Supply Board.

Chapter 3: Provides a detailed description of the DC-DC Power Supply Board.

Section 4 - Rectifier Operation & Control

Chapter 1: Describes the principles of operation of the power rectifier, beginning

with a basic description of phase controlled techniques and continuing
with a more detailed description of the three phase rectifier block as used
in the 7200 equipment. It continues by describing, at block diagram level,
the major features concerning the rectifier regulation and control circuits.

Chapter 2: Provides a detailed description of the Rectifier Logic Board.

Chapter 3: Provides a detailed description of the Rectifier Gate Drive Interface

Board.

Chapter 4: Provides a detailed description of the Rectifier Snubber Board.

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CONTENTS 7200 Series UPS Service Manual

Section 5 - Inverter Operation & Control

Chapter 1: Describes the principles of operation of the power inverter power section.
It begins with a basic description of Pulse-Width Modulation (PWM)
control techniques and details of the IGBT operation, and continues with
a more detailed description of the three-phase inverter block, as used in
the 7200 equipment. Finally, it describes, at block diagram level, the
major features concerning the inverter regulation and control circuits.

Chapter 2: Provides a detailed description of the Inverter Logic Board (4530025T)

which is the standard board fitted to modules built post February 1997.

Chapter 3: Provides a detailed description of the Inverter Logic Board (4530024S)

which was fitted to modules built before February 1997.

Chapter 4: Provides a detailed description of the Inverter Gate Driver Board.

Section 6 - Static Switch Operation & Control

Chapter 1: Describes the function of the static switch power block and its basic
control principles.

Chapter 2: Provides a detailed description of the Static Switch Driver Board

(4542043Z) which is the standard board fitted to modules built post
February 1997.

Chapter 3: Provides a detailed description of the Static Switch Driver Board

(4542041X) which was fitted to modules built before February 1997.

Section 7 - UPS System Control

Chapter 1: Describes the purpose of the UPS System Control boards and their
relationship with other areas of the UPS.

Chapter 2: Provides a detailed description of the High Voltage Interface Board.

Chapter 3: Provides a detailed description of the UPS Logic Board (4550007H)

which is the standard board fitted to modules built post February 1997.

Chapter 4: Provides a detailed description of the UPS Logic Board (4550004E)

which was fitted to modules built before February 1997.

Chapter 5: Provides a detailed description of the Operator Logic Board.

Chapter 6: Provides a detailed description of the Operator Control Panel.

Chapter 7: Provides a basic understanding of the System Software responsibilities.

Section 8 - ‘1+1’ UPS System control

Chapter 1: Describes the principles of operation of a ‘1+1’ configured UPS system.

Chapter 2: Provides a detailed description of the Parallel Logic Board.

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7200 Series UPS Service Manual CONTENTS

Section 9 - Options

Chapter 1: Alarm Interface Board 4590055P

Chapter 2 : Remote Alarm Interface Board 4590056Q

Chapter 3: Remote Alarm Monitor 4305001Z

Chapter 4: Battery Cabinets

Chapter 5: Battery Breaker Boxes

Chapter 6: Input Harmonic filters

Chapter 7: RS232 Communications Kit 4645101T

Section 10 - Maintenance

Chapter 1: Contains detailed Scheduled Maintenance Procedures

Section 11 - Troubleshooting

Chapter 1: Provides information regarding basic troubleshooting philosophy and

procedures.

Chapter 2: Provides details of fault diagnosis, including a chart of alarm

interpretations and suggested corrective actions.

Chapter 3: Contains detailed procedures for replacing, calibrating, and functionally

checking all the major circuit boards contained in the UPS.

Chapter 4: Contains Functional Check Procedures which describe how to carry out
various check and repair actions relevant to troubleshooting the unit.

Section 12 - Recommended Spares

Chapter 1: Contains a basic list of recommended replacement parts for each model.

Section 13 - Appendices

Appendix A: Device specifications

Appendix B: Controller Area Networking (CAN) Bus

Appendix C: PCB Layout Diagrams

Appendix D: PCB Configuration link details

Appendix E: Specification

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CONTENTS 7200 Series UPS Service Manual

XIV S0.fm5 - Issue 2 Dated 21/08/97

 Section 1: System Description

Chapter 1 - Functional Description

1.1 System overview ...................................................................................... 1-1
1.2 7200 Series UPS ‘single-module’ configuration ...................................... 1-2
1.2.1 Power rectifier & battery charging .............................................. 1-2
1.2.2 Battery charging modes ............................................................... 1-3
1.2.3 Power inverter .............................................................................. 1-4
1.2.4 Static switch assembly ................................................................. 1-5
1.3 UPS Power Switch Configuration ............................................................ 1-6
1.3.1 Maintenance bypass supply ......................................................... 1-6
1.3.2 Static bypass configuration .......................................................... 1-6
1.4 “1+1” Parallel-module system ................................................................. 1-7
1.4.1 Redundant vs Non-Redundant configuration ............................... 1-7
1.4.2 Inter-module power rectifier control ............................................ 1-8
1.4.3 Inter-module inverter control ....................................................... 1-8
1.4.4 Inter-module static switch control ............................................... 1-9

Chapter 2 - Main Power Circuit Diagram Descriptions

2.1 Chapter overview ................................................................................... 1-11
2.2 30kVA Model description – SE-5410303-P .......................................... 1-12
2.3 40kVA Model description – SE-5410304-Q .......................................... 1-17
2.4 60kVA Model description – SE-5410308-U .......................................... 1-22

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SECTION 1 - System Description 7200 Series UPS Service Manual

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 Section 1:

Chapter 1 - Functional Description

1.1 System overview

A 7200 Series Uninterruptible Power Supply (UPS) system is designed to furnish
a well regulated 3 phase power supply to a critical load, such as a computer, under
all rated load and input supply conditions. Being of a category known as an ‘on-
line’ UPS system, it is permanently connected between the utility 3-phase supply
and the load equipment and operational at all times, as shown in Figure 1-1.

Figure 1-1: UPS System connections

Q1 Q4

Output
Input 7200 UPS to
Mains
Load
Input Sw Output Sw

SW-BAT BATTERY

The UPS system offers the user the following advantages:

Increased power quality: The UPS has its own internal voltage and frequency
regulator circuits which ensure that its output is maintained within close toleranc-
es independent of voltage and frequency variations on the mains power lines.
Increased noise rejection: By rectifying the input AC power to DC power, and
then converting it back to AC, any electrical noise present on the input mains
supply line is effectively isolated from the UPS output, therefore the critical load
sees only clean power.
Power blackout protection: If the mains power fails, the UPS continues to
power the critical load from its back-up battery source, leaving the load immune
from power disturbances – even complete power blackouts.
This manual describes two types of system configuration; a single-module sys-
tem, and a two-module parallel-operating system which is known as a “1+1” sys-
tem. Note that the modules used in both system configurations are broadly
identical, and it is possible to convert a “single-module” system to a “1+1” paral-
lel-operating system with the addition of a second module and a degree of inter-
module control and power wiring.
This chapter continues by functionally describing a “single-module” UPS system
followed by details of the changes and additions applicable to the “1+1” config-
uration. To understand the functional operation of a “1+1” system you should
therefore first read the “single-module” description.

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SECTION 1 - System Description 7200 Series UPS Service Manual
CHAPTER 1 - Functional Description

1.2 7200 Series UPS ‘single-module’ configuration

The 7200 UPS comprises two major controlled power modules, the ‘rectifier’ and
‘inverter’, which together operate as an AC-DC-AC converter (See Figure 1-2).

1.2.1 Power rectifier & battery charging

The first conversion stage (from AC to DC) uses a 3 phase, fully-controlled SCR
bridge rectifier to convert the incoming mains supply into a regulated d.c. busbar
which, when the input supply is present, powers the inverter section and also pro-
vides the battery with its continuous float charging voltage. The nominal d.c.
busbar voltage (i.e. battery float voltage) depends on the number of cells forming
the battery, which in turn varies according to the system’s nominal working volt-
age (See Table 1-1). Also, a temperature-compensated battery charging regime is
used to prolong battery life, and this will slightly affect the dc busbar (float) volt-
age produced by the rectifier – by reducing the charge voltage as the battery tem-
perature rises.

Table 1-1: DC Bus voltage parameters

Parameter 380V 400V 415V

Number of battery cells 192 198 204

Nominal battery float charge 432Vdc 446Vdc 459Vdc

Nominal battery boost charge 460Vdc 475Vdc 490Vdc

End of battery discharge 320Vdc 330Vdc 340Vdc

Absolute maximum (manual) 480Vdc 495Vdc 510Vdc

In the event of a mains power failure, the rectifier becomes inoperative and the
inverter is powered solely from the battery, which obviously begins to discharge.
Critical load power is thus maintained under these conditions until either the input
mains is restored or the battery is fully discharged (See Table 1-1) – whereupon
the UPS shuts down.
The period for which the load can be maintained following a mains power failure
is known as the system's ‘Autonomy Time’ and is dependent upon both the battery
A/Hr capacity and the applied percentage load.

Figure 1-2: Block diagram of main power flow

DC Busbar
Q1 Q4

Output
Input Rectifier Inverter to
Mains
Load
Input Sw Output Sw

SW-BAT

BATTERY

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7200 Series UPS Service Manual SECTION 1 - System Description
CHAPTER 1 - Functional Description

1.2.2 Battery charging modes

The batteries are connected to the DC busbar via an external circuit breaker and
the rectifier voltage can be controlled at three selected battery charge levels.
These level are described as:
• Float charge
• Boost charge
• Manual charge

Caution Boost charge should not be used with valve-regulated (sealed-cell) batteries

[Link] Float charge

This is the normal mode of operation when using non-sealed cells and the ONLY
permissible mode when using sealed-cells. In the ‘float charge’ mode the rectifier
is set to operate at 2.27V/cell (2.23V/cell for Yuasa batteries) – calibrated by a
potentiometer on the Rectifier Logic Board (See section 4 paragraph 2.3.2).

Battery current limit

A hall-effect DCCT fitted in the battery feeder monitors the charging current and
drives a ‘current-limit’ circuit on the Rectifier Logic Board (See section 4 para-
graph [Link]) which, when appropriate, restricts the charge current to a preset
maximum level by reducing the DC busbar voltage. This is adjustable within the
range 0–25% of the rectifier input current rating and is factory set at 15%.
In practice, this circuit is only likely to come into operation when the mains
supply is restored following a prolonged outage and the batteries are heavily dis-
charged. Under these circumstances you may observe a reduced DC busbar volt-
age when the mains initially return. As the batteries take on charge, and the charge
current therefore reduces, the effects of the current limit control is gradually lifted
and the busbar voltage increases to nominal.

[Link] Boost charge

If the ‘boost charge’ facility is enabled and the batteries undergo a heavy dis-
charge during a mains outage, the Rectifier can automatically switch to its ‘boost
charge’ mode of operation when the mains supply returns. This increases the DC
busbar voltage to the preset boost charge level (See Table 1-1). The resulting in-
crease in battery charge current reduces the time taken by the batteries to regain
their lost charge – in readiness for the next mains failure. The boost charge level
is set on the Rectifier Logic Board (See section 4 paragraph 2.3.2).
Note: the battery current limit function is still active when ‘boost charge’ is in-
voked.

Float/Boost changeover
If the ‘boost charge’ facility is enabled the rectifier does not necessarily adopt the
‘boost charge’ mode every time the mains supply returns from an outage; but is
invoked only if the charge current exceeds a certain threshold (known as the
“float/boost changeover threshold”) after a brief time has elapsed – i.e. if the
charge current does not exceed the “float/boost changeover threshold” the rectifi-
er will adopt, and remain in, its ‘float’ charge mode upon mains return.
If the current does exceed the “float/boost changeover threshold” the rectifier will
adopt the ‘boost mode’ until the batteries are sufficiently charged that their charge
current falls below the “changeover threshold”, whereupon it will switch back to

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SECTION 1 - System Description 7200 Series UPS Service Manual
CHAPTER 1 - Functional Description

it’s ‘float charge’ level. The time for which the batteries are subjected to the boost
charge is therefore mainly dependant on the discharge level.

Boost duration timer

If there is a fault on the battery string, such as several shorted cells, the resulting
increased charge current could be sufficient to trigger off the boost mode irrespec-
tive of whether or not the batteries had been heavily discharged. Also, under such
circumstances the charge current is unlikely to fall back below the float/boost
threshold and the rectifier will continue to operate at its boost charge level indef-
initely; which in turn could lead to yet further battery damage. To overcome such
events, a timer in included in the float/boost changeover control logic which
limits the duration for which the rectifier is allowed to operate in the boost charge
mode.
Although the rectifier ‘float’ and ‘boost’ charge voltages are set by variable resis-
tors located on the Rectifier Logic Board, the “changeover threshold” and “dura-
tion timer” are processor controlled and can be set from the UPS Control Panel.
Note: it is also possible to invoke an immediate ‘boost charge’ manually from the
UPS Control Panel (normally undertaken only during commissioning).

[Link] Manual charge

When ‘manual charge’ is selected (from the UPS Control Panel) the rectifier
(D.C. busbar) voltage is manually controlled by a potentiometer on the Rectifier
Logic Board and can be adjusted from “zero” up to the rated “maximum” (See
Table 1-1). In practice this facility is used as a means of controlling the rectifier
during troubleshooting and can also be useful when applying the initial battery
charge during commissioning (open vented cells only).
When the rectifier is operating in the manual mode the inverter is automatically
shut-down to prevent damage.

1.2.3 Power inverter

Embracing the latest IGBT switching technology, the inverter power section em-
ploys PWM control techniques to convert the dc busbar into an a.c. voltage which
is then transformed up to the nominal system working voltage and fed to the load
terminals via the output static switch.
The purpose of the inverter is therefore to convert the wide-ranging D.C. busbar
voltage (See Table 1-1) into a tightly controlled 3-phase 50Hz sinusoidal output.
The inverter control philosophy includes independent voltage regulation control
of each of the output three phases, together with current limit and overload pro-
tection. The output frequency is digitally controlled and normally synchronised to
the bypass supply – see description of the Static Switch operation below.

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7200 Series UPS Service Manual SECTION 1 - System Description
CHAPTER 1 - Functional Description

1.2.4 Static switch assembly

Figure 1-3: Block diagram showing Static Bypass

Q2

BYPASS
BYP-SS

Bypass Sw

Static
Q1 Switch Q4
MAINS

Rectifier Inverter INV-SS

Input Sw Output Sw

Figure 1-3 shows a block diagram of the static switch and its relationship with the
other UPS power blocks. As the diagram shows, the static switch comprises two
areas: one (INV-SS) is connected between the inverter and output terminals and
the other (BYP-SS) is connected between the output terminals and a switched 3-
phase bypass supply line.
The purpose of the static switch is to provide a means of transferring the load be-
tween the inverter and raw bypass supply in a controlled manner such that it ex-
periences no power-break when transferring from one to the other.
Under normal circumstances the ‘inverter-side’ static switch (INV-SS) is closed
and the load is powered from the inverter output; however in the event of an in-
verter fault, or overload which exceeds the inverter capability, the ‘inverter-side’
static switch opens and the ‘bypass-side’ closes, in a make-before break fashion,
and transfers the load to the 3-phase bypass supply. Conversely, when the inverter
becomes available (or the overload condition clears) the load is transferred back
to the ‘inverter-side’ and the system continues its normal operation.
In order for a ‘no-break’ transfer to take place the inverter frequency is normally
synchronised to the bypass supply at all times – provided the bypass frequency
remains within a specified frequency window. An ‘out of sync’ alarm annunciates
if the inverter is unable to synchronise to the bypass supply due to an out-of-
window condition or unstable bypass supply. This does not affect the normal UPS
operation, in as much as the inverter frequency will remain within its prescribed
limits, however if this condition is present when a transfer-to-bypass is requested
then there will be a slight break (max 1 cycle) in the load supply while the transfer
takes place – to protect the critical load from possible high voltage transients
when switching between out-of-phase supplies.
In practice, the ‘inverter-side’ static switch function is served by a contactor while
the ‘bypass-side’ static switch comprises a pair of inverse-parallel connected
SCRs in each bypass line (6 SCRs in total). The contactor coil and SCR gates are
controlled by an interlocking circuit on a common control circuit board which
prevents both sides of the static switch from being energised at the same time.

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SECTION 1 - System Description 7200 Series UPS Service Manual
CHAPTER 1 - Functional Description

1.3 UPS Power Switch Configuration

Figure 1-4: Power Switch configuration

Q3

Maint Bypass SW

Q2
BYPASS

BYP-SS

Bypass Sw

Q1 Q4
MAINS

Rectifier Inverter INV-SS

Input Sw
Output Sw

1.3.1 Maintenance bypass supply

An alternative hard-wired bypass supply is ‘made’ when Q3 is closed. This con-
nects the UPS output terminals directly to the bypass supply and is designed to
allow the load to be powered from the bypass while the remainder of the UPS is
shut-down for maintenance or troubleshooting.
If the UPS control logic detects that Q3 and Q4 are closed simultaneously, it will
shut-down the inverter and open the ‘inverter-side’ static switch to prevent the
UPS being damaged by reverse power flowing into the inverter output terminals
from the maintenance bypass line.

Caution The load is not protected against supply aberrations when connected to the by-
pass supply – either on Maintenance Bypass or when running on Static Bypass

1.3.2 Static bypass configuration

Figure 1-4 illustrates that links are connected between the bypass supply termi-
nals and UPS input mains terminals. This allows the UPS to be configured for
either a ‘split’ or ‘common’ bypass system – as explained below.

Common-bypass configuration
In a ‘common-bypass’ installation the bypass supply lines are connected to the
input mains terminals via the bypass links and there are no external power con-
nections to the bypass terminals.

Split-bypass configuration
In a ‘split-bypass’ installation the links between the input mains and bypass ter-
minals are removed and a dedicated 3-phase bypass supply is connected to the
bypass terminals. The advantage of this type of installation is that a separate
power source may be used for the bypass lines which can be totally segregated
from the UPS input mains, thus leaving the bypass supply available on occasions
when the input mains supply has failed.

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CHAPTER 1 - Functional Description

1.4 “1+1” Parallel-module system

Figure 1-5: “1+1” System configuration block diagram

RECTIFIER INVERTER INV (SS)

Inverter Static
Rectifier BYP (SS)
Control Logic Bypass
Control Logic

Static Switch
Inter-Module Parallel Control Logic
Control Logic
Maint. Bypass
Output
(LOAD)
Power-
Supply
Maint. Bypass
Static Switch
Inter-Module Parallel Control Logic
Control Logic

Rectifier Inverter
Static BYP (SS)
Control Logic Control Logic
Bypass

RECTIFIER INVERTER INV (SS)

As illustrated in Figure 1-5 above, the 7200 Series ‘1+1’ system comprises two
standard UPS modules, as used in a ‘single-module’ system, which are modified
to allow their outputs to be connected in parallel. These can then be used in a ‘re-
dundant’ or ‘non-redundant’ configuration as explained below.
The diagram shows that from a ‘power’ viewpoint each module is internally iden-
tical to the ‘single-module’ configuration, with each module containing a rectifi-
er, inverter, static switch (inverter and bypass ‘sides’), together with static bypass
and maintenance bypass supplies.
However, due to the parallel connection of the two modules’ outputs a “1+1”
system requires additional inter-module control signals to manage current shar-
ing, synchronising and bypass switching between the modules.
As shown, the inter-module control features are implemented via a control bus
connected between the two modules which affects the rectifier, inverter and static
switch module control blocks. A brief description of the affects on each of these
blocks is given below.

1.4.1 Redundant vs Non-Redundant configuration

Redundant system
If a ‘1+1’ system is configured as a ‘redundant’ system the modules are sized
such that the potential maximum load can be powered by just one of the two mod-
ules. Under normal circumstances both modules are operational and share the
load current equally; but if one module develops a fault, or is shut down, the sec-
ond, healthy module is able to take over the full load demand and continue to pro-
vide it with processed, backed-up power.

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Non-redundant system
In a ‘non-redundant’ configuration, the system is sized such that both UPS mod-
ules are required to feed the potential maximum load, and if either of the two mod-
ules develops a fault, or is for some reason shut down, the other module is
automatically shut down also – note that in such an event the load is transferred
to the static bypass supply, as described later.
In terms of overall system reliability, the advantages of a redundant system over
that of a non-redundant system are self evident.
Changing a “1+1” system between a ‘redundant’ and ‘non-redundant’ configura-
tion is quite straightforward, and is carried out by selecting configuration links on
the control circuit boards fitted to both modules.

1.4.2 Inter-module power rectifier control

The power rectifier is only affected by the parallel control bus in a “1+1” system
if a ‘common battery’ is used – i.e. if both UPS modules are connected to a single
battery bank (via separate battery isolators of course). In this type of installation
the power rectifiers in each module are effectively connected in parallel and must
be controlled such that the battery charge current is shared equally between them.
A ‘common battery’ option kit is available. This contains DCCTs (DC Current
Transformers) which are fitted to the battery power lines and connected via the
parallel control bus to a sharing circuit in the rectifier control block.
See the Options section in the relevant system IOM user manual for full details.

1.4.3 Inter-module inverter control

Synchronisation:
As the outputs from both UPS modules are connected together to provide a single
critical load supply, it is imperative that the inverters are fully synchronised both
in frequency and phase. This is achieved by digitally locking the two inverter con-
trol oscillators. Similarly, as has previously been mentioned, it is necessary for the
inverters to be synchronised to the bypass supply to enable a ‘no-break’ transfer
to take place when the static switch transfers the load to the bypass supply. The
inverter control oscillators are therefore not only locked together but also made to
track the bypass frequency.

Current sharing:
The parallel control circuit compares each module's output current with that of its
partner and is thereby able to effect current sharing by making fine adjustments
to an individual module's output voltage.

Reverse current:
A reverse current monitor circuit detects current flowing into, rather than out of,
a module's output terminals. Such a condition can arise if one module develops an
internal power fault which sinks power from the second module’s output, or if for
some reason the two modules become unbalanced. A reverse current is liable to
further damage a module and also degrade the load supply.
If a reverse current is detected the inverter on the affected module is immediately
shut down and the load transferred to the bypass supply if the system is configured
to be non-redundant.

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1.4.4 Inter-module static switch control

Note: in the following text the term “inverter-side” static switch refers to the in-
verter output contactor.
There are three important conditions imposed on the static switch operation in a
“1+1” system:
1. Under no circumstances must the inverter-side of one module be closed at the
same time as the bypass-side is closed in the other module, as this would
effectively parallel the output of one module with the bypass mains supply
and likely to damage the system.
2. For similar reasons, the inverter-side of both modules must be opened if the
maintenance bypass isolator is closed in either module.
3. Finally, when the system is started up the inverter-side must not be closed
until its associated inverter is fully synchronised with the inverter in the sec-
ond module. This is especially important in the case of a ‘redundant’ installa-
tion where one module may be on-line and supplying the load before the
second module is started.
In a ‘non-redundant’ configuration the start-up control sequence operates
such that both inverters must be operating and fully synchronised before the
static switch is allowed to transfer the load from the static bypass to the
inverters.
In a ‘non-redundant’ system the parallel control bus effectively ties together the
static switches in both modules – i.e. both modules are either on inverter-side or
bypass-side.

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 Section 1:

Chapter 2 - Main Power Circuit Diagram Descriptions

2.1 Chapter overview

This chapter contains individual descriptions of the Power Drawings for each of
the 7200 Series models and should be read in conjunction with the appropriate cir-
cuit diagram and assembly drawings indicated in Table 1-2.

Table 1-2:

Model Circuit Diagram Assembly Diagram

30kVA SE-5410303-P (3 pages) AM-5410303-P (12 pages)

40kVA SE-5410304-Q (3 pages) AM-5410304-Q (12 pages)

60kVA SE-5410308-U (3 pages) AM-5410308-Q (12 pages)

Each drawing comprises several pages and a system of cross-referencing is used

where connections are made across different pages. The cross-reference takes the
form of a page number followed by a grid reference and will be shown in the fol-
lowing text encased in square brackets – for example [2/C3] refers to page ‘2’ area
‘C3’. The grid reference system is shown on the left-side (A-R) and top (1-19)
edges of the drawings.

30kVA Description – (see paragraph 2.2 on page 1-12)

40kVA Description – (see paragraph 2.3 on page 1-17)
60kVA Description – (see paragraph 2.4 on page 1-22)

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CHAPTER 2 - Main Power Circuit Diagram Descriptions

2.2 30kVA Model description – SE-5410303-P

SE-5410303-P Page 1. This page shows the UPS input, rectifier, dc bus, in-
verter and output transformer power circuits.

Bypass supply feed

The UPS input mains supply is connected to terminals U(1)-V(1)-W(1) which are
in turn connected directly to the input switch Q1.
If a ‘common bypass’ system is used the input supply terminals U(1)-V(1)-W(1)
are connected by links to the bypass terminals U(3)-V(3)-W(3)-N(3) [2/G2]. If a
‘split-bypass’ system is used then these links must be removed and a dedicated
bypass supply connected to U(3)-V(3)-W(3)-N(3) [page 2].

Input switch Q1 to rectifier

The input mains is connected to the rectifier via the input switch (Q1), input fuses
F10-F12, RFI filter (Z1), optional input filter (4641015P) and input choke (L1).
The input voltage is monitored by the control system via wires 15-17 and the High
Voltage Interface Board [3/N8]. This is used to detect input voltage failure
(-20%), input phase rotation error and also provides basic phase-timing informa-
tion for the rectifier SCR control logic. The V and W phases also power the con-
trol power supply transformer (T2) via F8 and F9. T2 primary has three taps
which are selected according to the working voltage to produce a nominal 30Vac
secondary voltage – tap selection details are shown on the diagram [R6]. T2’s sec-
ondary feeds one input to the AC-DC Power Supply (4503030-M) [3/D19]

Power rectifier block

The rectifier assembly, shown as a dashed block, is shown in detail in diagram
SE-4612043-H (circuit diagram) and AM-4612043-H (assembly drawing). This
assembly also contains the static switch power components in addition to those
belonging to the rectifier.
Considering the rectifier, this assembly contains the six SCRs associated with the
rectifier together with their Gate Drive Control Board (SE-4542040-W) and snub-
ber board (SE-4540043-B). There are also two thermostats fitted to the U and V
phase heatsinks (not normally used).
The rectifier gate drive signals are applied to connector X7 on the Gate Driver
Control Board (SE-4542040-W) via ribbon cable W4, and the rectifier’s output
DC power rails are connected to the dc busbar via cables 27 (+) and 28 (-).

DC Busbar
The DC busbar is controlled by the rectifier to be at the required battery charging
voltage at all times and is smoothed by a capacitor bank (C1-C4) – less than 1%
voltage ripple. The smoothed busbar is then connected to the batteries via an ex-
ternal circuit breaker, and to the inverter (4612143-D). In the battery line is a
DCCT (T11) which provides the UPS control system with a battery current sense
signal via the High Voltage Interface Board [3/G6] – used for battery current limit
control and metering. A battery fuse (F13) is fitted and monitored by means of a
micro-switch to detect its failure [3/G2].
Wires 27 and 28 provide the rectifier control system with a dc busbar (battery)
feedback voltage via the High Voltage Interface Board [3/N9] – used for closed-
loop voltage control and dc bus (battery) voltage metering. The dc busbar is also
connected to a DC-DC control power supply board [3/E7] via fuses F4-F5 – the

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same fused supply is connected to the inverter output contactor control circuit on
the static switch assembly [2/G8], described below.

Power inverter
The inverter assembly, shown as a dashed block, is shown in detail in diagram
SE-4612143-D (circuit diagram) and AM-4612143-D (assembly drawing). This
assembly contains the six inverter IGBT transistors (3 x twin pack devices), three
Base Drive Boards (4519015-H), and suppression capacitors.
The transistor drive signals from the inverter control electronics are connected via
ribbon cables W1-W2-W3 to CN1 on each Base Drive Board.

Power inverter to output switch

The inverter output is connected to the output transformer where it is stepped-up
to the required output voltage. The output transformer step-up ratio is 1:2 and it
is delta-star (zig-zag) wound with the output star point connected to the system’s
neutral.
Capacitors C5-C10, connected across the output line-to-line, act as a filter to
remove any remnants of the PWM switching frequency from the output wave-
form, thus producing a clean sinusoidal output at the nominal output frequency.
Current transformers T9 and T10 provide the inverter voltage regulation control
system with output current sense signals, via the High Voltage Interface Board
[3/G7-G8]. These are used by the inverter regulation control electronics to en-
hance the inverter regulation during load changes, and also by the output current
limit protection control system.
Wires 9-11 provide the inverter voltage control system with an output voltage
feedback signal, via the High Voltage Interface Board [3/H4]. This is used by the
inverter voltage regulation control system and static switch ‘fault and transfer’
control logic.
SE-5410303-P Page 2. This page shows the bypass input and UPS output
power connections together with the bypass circuits.

Bypass supply feed

If the UPS is connected with a ‘split-bypass’ supply the dedicated bypass supply
is connected to U(3)-V(3)-W(3)-N(3) from where it is connected to the static
bypass switch Q2 and maintenance bypass switch Q3. If a ‘common bypass’
system is used there are no external connections to U(3)-V(3)-W(3)-N(3) and the
power to Q2 and Q3 is obtained from the UPS input mains supply terminals
U(1)-V(1)-W(1) [page 1] via links which are connected between the mains and
bypass input terminals [1/C2].

Maintenance bypass switch

The maintenance bypass switch (Q3) makes a direct connection between the
bypass supply and UPS output terminals, therefore completely bypassing the UPS
for maintenance and troubleshooting purposes. This switch is always open during
normal UPS operation, and can be padlocked in that position. If the switch is
closed while the inverter is operating (i.e. while Q4 is closed) its auxiliary con-
tacts [3/L1] trigger a safety circuit in the UPS control system which will open the
inverter output contactor to isolate the power inverter from the output terminals
and prevent any damage which might otherwise occur due to reverse power flow.

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Static bypass switch (Q2) to static switch assembly

Q2 connects the three-phase bypass supply to the static switch assembly and must
be closed during normal UPS operation to ensure the availability of the static
bypass supply when required.
The bypass voltage at the switched side of Q2 is monitored by the High Voltage
Interface Board via wires 1,2,3 and 4. This is used for bypass voltage error detec-
tion and inverter synchronisation control; the U and V phases also power the con-
trol power supply transformer (T3) via F6 and F7. T3 primary has three taps
which are selected according to the working voltage to produce a nominal 30Vac
secondary voltage – tap selection details are shown on the diagram [G6]. T3’s sec-
ondary feeds one input to the AC-DC Power Supply (4503030-M) [3/D19].

Static switch assembly

The static switch assembly, shown as a dashed block, is shown in detail in dia-
gram SE-4612043-H (circuit diagram) and AM-4612043-H (assembly drawing).
This assembly also contains the rectifier power components in addition to those
belonging to the static switch, as described earlier.
From the static switch point of view, this assembly contains the six SCRs associ-
ated with the bypass static switch together with their Gate Drive Control Board
(SE-4542041-X) and snubber board (SE-4540043-B).
All the connectors shown in the static bypass block on page 2 refer to the Gate
Driver Control Board (SE-4542041-X):
• Connector X13 is connected to the UPS Logic Board X5 [3/G16] and
interfaces the Gate Driver Control Board with the remainder of the UPS
control system via ribbon cable W7.
• Connector X10 monitors the inverter output contactor’s auxiliary contacts,
which are used for interlocking and status indication purposes.
• Connector X9 carries the switched supply for energising the coil of the
inverter output contactor.
• Connector X8 is connected to the DC busbar [1/H8] via F4-F5 and is the
source of the inverter output contactor energising supply.
• Terminals A-C and A'-C' are the mains input/output power connections.

Static switch assembly to output switch Q4

The static switch power outputs are connected to the output switch (Q4) via an
output RFI filter (Z2) and output current sensing CTs (T4-T6), which are used for
metering purposes and overload monitoring. Note that the inverter output contac-
tor is connected in parallel with the bypass static switch outputs and is fed from
the output transformer [1/D18]
Wires 5-8 are used for output voltage monitoring and metering purposes, and are
connected to various sections of the UPS control system via the High Voltage In-
terface Board [3/N8]. They also provide power for the cooling fans which are all
single-phase operating and distributed across the phases as shown. There is no fan
redundancy, and the fan annotated ‘option input filter’ is fitted to the optional
input filter cabinet.
The output switch Q4 is a 4-pole switch with a set of auxiliary contacts which are
monitored by the control system in the same manner as those described above for
the maintenance bypass (Q3) [3/L1].

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Remote connections
The lower left-hand area of page 1 shows details of various remote connections
to terminal block X3 (X3 connections are made by ‘spade connectors’). These
connections are used for:
• Emergency stop – normally closed (volt-free) circuit connected between
X3 terminals 10 and 11. If an external emergency stop option is not in use
then these two terminals must be shorted together at the terminal block.
• Battery temperature sensing – the battery temperature is sensed by the
float charge control system such as to decrease the float voltage by
1.5Vdc/°C as the temperature increases above 25°C. The temperature sen-
sor is connected between X3 terminals 2 and 3, and is polarity sensitive.
Note: Only one temperature sensing device is used even if additional bat-
tery cabinets are utilised by the system.
• Battery CB-AUX – the external battery circuit breaker auxiliary contacts
are connected between X 3 terminals 4 (ground) and 3 such as to short
these terminals together when the breaker is closed.
• Battery trip – the battery circuit breaker is manually operated but can be
tripped by the UPS control system if required – e.g. Low Battery trip when
the battery discharges to 320Vdc. The trip circuit is connected via X3 ter-
minals 4 (ground) and 6 (logic high to trip) and is normally applied to the
breaker via an opto-coupled trip circuit for supply isolation.
SE-5410303-P Page 3. This page shows the UPS control system circuit boards
and their interconnections. A basic description of the individual boards’ functions
are provided below.

High Voltage Interface Board 4590054-O

This board interfaces the high-voltage sense and control signals of the UPS power
circuits with the low-voltage environment on the control circuit boards.
• X1 – connects the low voltage signals produced on this board to the UPS
Logic Board from where they are transmitted to the remaining boards
• X2 – DC bus (battery) voltage sense inputs [1/G8]
• X3 – Input mains voltage sensing inputs [1/F7]
• X4 – UPS output voltage sensing inputs [2/H14]
• X5 – Inverter output voltage sensing inputs [1/C16]
• X6 – Bypass voltage sensing inputs [2/G5]
• X7 – Power switch auxiliary contacts
• X8 – Interface to external connection block X3 [2/M2-M5]
• X9 – Battery cabinet temperature sensor inputs [2/M3]
• X10 – Input air temperature sensor inputs for display metering
• X11 – Inverter output air temperature sensor inputs for display metering
• X12 – Transformer cabinet temperature sensor inputs for display metering
• X13 – Inverter assembly thermostats (n/c – open above 90°C)
• X14 – Not in use
• X15 – Battery fuse monitor [1/N4]
• X16 – Not in use (linked out)
• X17 – Not in use (linked out)
• X18 – Rectifier assembly thermostats (n/o – not normally used)
• X19 – Output current monitoring W-ph [2/F16]
• X20 – Output current monitoring V-ph [2/F16]
• X21 – Output current monitoring U-ph [2/F16]
• X22 – Battery current monitoring [1/M8]
• X23 – Not in use

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• X24 – Inverter current monitoring V-ph [1/E13]

• X25 – Inverter current monitoring W-ph [1/F14]
• X26 – Not in use
• X27 – Not in use

UPS Logic Board 4550004-E

This board serves two major functions: first it contains the logic which controls
the static switch/inverter output contactor and load transfer between inverter and
static bypass supplies. Second, it contains the fault-detection-based general
system control logic which determines the operation of the rectifier (via the Rec-
tifier Logic Board) and inverter (via the Inverter Logic Board).
Note: When compared with the circuit boards fitted in the 7400 Series UPS, this
board combines the UPS Logic Board and Static Switch Logic Board functions.
In addition to the above functions this board also provides an interface between
the general control system and the Operator Panel and external alarms option.

Rectifier Logic Board 4520074-A

The Rectifier Logic Board provides the rectifier SCRs with their gate drive sig-
nals at a suitable conduction angle to produce the required battery charge voltage.
It receives battery voltage and battery current feedback signals, and input voltage
sense signals via the High Voltage Interface Board and UPS Logic Board. The
drive pulses are processed on the Rectifier Gate Drive Board (4542040-W) before
application to the SCR gates.
The Rectifier Logic Board receives its operating power from the AC-DC Power
Supply assembly (4503030-M) which is energised whenever the input mains
supply or bypass supply is live (via T2 [1/K5]) or (via T3 [2/H7]) – i.e. both these
transformers feed the same power supply circuit in parallel.

Inverter Logic Board 4530024-S

The Inverter Logic Board provides the inverter IGBTs with their base drive sig-
nals with a suitable PWM pattern to produce the required output voltage. It re-
ceives output voltage and current feedback signals, and bypass voltage sense
signals via the High Voltage Interface Board and UPS Logic Board. The drive
pulses are processed on the Inverter Drive Interface Boards (4519015-H) before
application to the IGBTs.
The Inverter Logic Board receives its operating power from the DC-DC Power
Supply assembly (4503028-K) which is energised via fuses F4-F5 [1/H8] when-
ever the DC busbar is live – i.e. either due to the rectifier being operative (when
the input mains is present) or when the batteries are connected to the dc busbar
(external circuit breaker closed).

Control power supplies

The power supplies from the Inverter Logic Board and Rectifier Logic Board are
paralleled on the UPS Logic Board and fed to the other boards as necessary.
Therefore when the UPS is started-up the ‘control system’ is powered-up as soon
as the AC-DC Power Supply is energised by the closure of the input mains switch
(Q1). Once the rectifier is fully operational the DC-DC Power Supply provides an
alternative (parallel) supply source which supports the control system operation
if the input mains supply subsequently fails.
Note: the Inverter Logic Board and Inverter Driver Board are energised from the
DC-DC supply only.

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2.3 40kVA Model description – SE-5410304-Q

SE-5410304-Q Page 1. This page shows the bypass input and UPS output
power connections together with the bypass circuits.

Bypass supply feed

If the UPS is connected with a ‘split-bypass’ supply the dedicated bypass supply
is connected to U(3)-V(3)-W(3)-N(3) from where it is connected to the static
bypass switch Q2 and maintenance bypass switch Q3. If a ‘common bypass’
system is used, there are no external connections to U(3)-V(3)-W(3)-N(3) and the
power for Q2 and Q3 is obtained from the UPS input mains supply terminals
U(1)-V(1)-W(1) [page 2] via links which are connected between the mains and
bypass input terminals [2/C2].

Maintenance bypass switch

The maintenance bypass switch (Q3) makes a direct connection between the
bypass supply and UPS output terminals, therefore completely bypassing the UPS
for maintenance and troubleshooting purposes. This switch is always open during
normal UPS operation, and can be padlocked in the open position. If the switch is
closed while the inverter is operating (i.e. while Q4 is closed) its auxiliary con-
tacts [3/L1] will trigger a safety circuit in the UPS control system which will open
the inverter output contactor to isolate the power inverter from the output termi-
nals and prevent any damage which might otherwise occur due to a reverse power
flow.

Static bypass switch (Q2) to static switch assembly

Q2 connects the three-phase bypass supply to the static switch assembly and must
be closed during normal UPS operation to ensure the availability of the static
bypass supply when required.
The bypass voltage at the switched side of Q2 is monitored by the High Voltage
Interface Board via wires 1,2,3 and 4. This is used for bypass voltage error detec-
tion and inverter synchronisation control; the U and V phases also power the con-
trol power supply transformer (T3) via F6 and F7. T3 primary has three taps
which are selected according to the working voltage to produce a nominal 30Vac
secondary voltage – tap selection details are shown on the diagram. T3’s second-
ary feeds one input to the AC-DC Power Supply (4503030-M) [3/D19].

Static switch assembly

The static switch assembly, shown as a dashed block, is shown in detail in dia-
gram SE-4612044-I (circuit diagram) and AM-4612044-I (assembly drawing).
This assembly also contains the rectifier power components in addition to those
belonging to the static switch.
From the static switch point of view, this assembly contains the six SCRs associ-
ated with the bypass static switch together with their Gate Drive Control Board
(SE-4542041-X) and snubber board (SE-4540043-B).
All the connectors shown in the static bypass block on page 1 refer to the Gate
Driver Control Board (SE-4542041-X):
• Connector X13 is connected to the UPS Logic Board X5 [3/G16] and
interfaces the Gate Driver Control Board with the remainder of the UPS
control system via ribbon cable W7.
• Connector X10 monitors the inverter output contactor’s auxiliary contacts,

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which are used for interlocking and status indication purposes.

• Connector X9 carries the switched supply for energising the coil of the
inverter output contactor.
• Connector X8 is connected to the DC busbar [2/H8] via F4-F5 and is the
source of the inverter output contactor energising supply mentioned above.
• Terminals A-C and A'-C' are the mains input/output power connections.

Static switch assembly to output switch Q4

The static switch power outputs are connected to the output switch (Q4) via an
output RFI filter (Z2) and output current sensing CTs (T4-T6), which are used for
metering and overload monitoring purposes. Note that the inverter output contac-
tor is connected in parallel with the bypass static switch outputs and is fed from
the output transformer [2/B17-B18]
Wires 5-8 are used for output voltage monitoring and metering purposes, and are
connected to various sections of the UPS control system via the High Voltage In-
terface Board [3/N8]. They also provide power for the cooling fans which are all
single-phase operating and distributed across the phases as shown. There is no fan
redundancy, and the fan annotated ‘option input filter’ is fitted to the optional
input filter cabinet.
The output switch Q4 is a 4-pole switch with a set of auxiliary contacts which are
monitored by the control system in the same manner as those described above for
the maintenance bypass switch (Q3).

Remote connections
The lower left-hand ares of page 1 shows details of various remote connections to
terminal block X3 (X3 connections are made by ‘spade connectors’). These con-
nections are used for:
• Emergency stop – normally closed (volt-free) circuit connected between
X3 terminals 10 and 11. If an external emergency stop option is not in use
then these two terminals must be shorted together at the terminal block.
• Battery temperature sensing – the battery temperature is sensed by the
float charge control system such as to decrease the float voltage by
1.5Vdc/°C as the temperature increases between 25°C and 35°C. The tem-
perature sensor is connected between X3 terminals 2 and 3, and is polarity
sensitive.
• Battery CB-AUX – the external battery circuit breaker auxiliary contacts
are connected between X 3 terminals 4 (ground) and 3 such as to short
these terminals together when the breaker is closed.
• Battery trip – the battery circuit breaker is manually operated but can be
tripped by the UPS control system if required – e.g. Low Battery trip when
the battery discharges to 320Vdc. The trip circuit is connected via X3 ter-
minals 4 (ground) and 6 (logic high to trip) and is normally applied to the
breaker via an opto-coupled trip circuit for supply isolation.
SE-5410304-Q Page 2. This page shows the UPS input, rectifier, dc bus, in-
verter and output transformer power circuits.

Bypass supply feed

The UPS input mains supply is connected to terminals U(1)-V(1)-W(1) which are
in turn connected directly to the input switch Q1.
If a ‘common bypass’ system is used the input supply terminals U(1)-V(1)-W(1)
are connected by links to the bypass terminals U(3)-V(3)-W(3)-N(3) [1/C1]. If a

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CHAPTER 2 - Main Power Circuit Diagram Descriptions

‘split-bypass’ system is used then these links must be removed and a dedicated
bypass supply is connected to U(3)-V(3)-W(3)-N(3) [page 1].

Input switch Q1 to rectifier

The input mains passes from the input switch Q1 to the rectifier via the input fuses
F10-F12, input RFI filter (Z1), optional input filter (4641016-Q) and input filter
choke.
The input voltage is monitored by the control system via wires 15-17 and the High
Voltage Interface Board [3/N8]. This is used to detect input voltage failure
(-20%), input phase rotation error and also provides basic phase-timing informa-
tion for the rectifier SCR control logic. The V and W phases also power the con-
trol power supply transformer (T2) via F8 and F9. This transformer is identical to
T3 which is fed from the bypass supply and described on the previous page, and
once again its primary is tapped to suit the working mains supply voltage – tap
details shown on [2/P7].

Power rectifier block

The rectifier assembly, shown as a dashed block, is shown in detail in diagram
SE-4612044-I (circuit diagram) and AM-4612044-I (assembly drawing). This as-
sembly also contains the static switch power components in addition to those be-
longing to the rectifier.
Considering the rectifier, this assembly contains the six SCRs associated with the
rectifier together with their Gate Drive Control Board (SE-4542040-W) and snub-
ber board (SE-4540043-B). There are also two thermostats fitted to the U and V
phase heatsinks but these are not normally used.
The rectifier gate drive signals are applied to connector X7 on the Gate Driver
Control Board (SE-4542040-W) via ribbon cable W4, and the rectifier’s output
DC power rails are connected to the dc busbar via cables 27 (+) and 28 (-).

DC Busbar
The DC busbar is controlled by the rectifier to be at the required battery charging
voltage at all times and is smoothed by a capacitor bank (C1-C4) – less than 1%
voltage ripple. The smoothed busbar is then connected to the batteries via an ex-
ternal circuit breaker, and to the inverter (4612145-F). In the battery line is a
DCCT (T11) which provides the UPS control system with a battery current sense
signal via the High Voltage Interface Board [3/G6], and a battery fuse (F13)
which is monitored by means of a micro-switch to detect its failure.
Wires 27 and 28 provide the rectifier control system with a dc busbar (battery)
feedback voltage via the High Voltage Interface Board [3/N9] – used for closed-
loop voltage control and dc bus (battery) voltage metering. This signal also pro-
vides a battery voltage metering function. The dc busbar is also connected to a
DC-DC control power supply board [3/E7] via fuses F4-F5 (1A) – the same fused
supply is connected to the inverter output contactor control circuit on the static
switch assembly [1/G8], as described earlier.

Power inverter
The inverter assembly, shown as a dashed block, is shown in detail in diagram
SE-4612145-F (circuit diagram) and AM-4612145-F (assembly drawing). This
assembly contains the six inverter IGBT transistors (single pack devices), three
Base Drive Boards (4519015-H), suppression capacitors and two normally-closed
series-connected thermostats.

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SECTION 1 - System Description 7200 Series UPS Service Manual
CHAPTER 2 - Main Power Circuit Diagram Descriptions

The transistor drive signals from the inverter control electronics are connected via
ribbon cables W1-W2-W3 to CN1 on each Base Drive Board.

Power inverter to output switch

The inverter output is connected to the output transformer where it is stepped-up
to the required output voltage. The output transformer step-up ratio is 1:2 and it
is delta-star (zig-zag) wound with the output star point connected to the system’s
neutral.
Capacitors C5-C10 connected across the output line-to-line act as a filter to
remove any remnants of the PWM switching frequency from the output wave-
form, thus producing a clean sinusoidal output at the nominal output frequency.
Current transformers T9 and T10 provide the inverter voltage regulation control
system with output current sense signals, via the High Voltage Interface Board
[3/G7-G8]. These are used by the inverter regulation control electronics to en-
hance the inverter regulation during load changes, and also by the output current
limit protection control system.
Wires 9-11 provide the inverter voltage control system with an output voltage
feedback signal, via the High Voltage Interface Board [3/H4]. This is used by the
inverter voltage regulation control circuits and static switch ‘fault and transfer’
control logic.
SE-5410304-Q Page 3. This page shows the UPS control system circuit
boards and their interconnections. A basic description of the individual boards’
functions are provided below.

High Voltage Interface Board 4590054-O

This board interfaces the high-voltage sense and control signals of the UPS power
circuits with the low-voltage environment on the control circuit boards.
• X1 – connects the low voltage signals produced on this board to the UPS
Logic Board from where they are transmitted to the remaining boards
• X2 – DC bus (battery) voltage sense inputs [2/G8].
• X3 – Input mains voltage sensing inputs [2/F7]
• X4 – UPS output voltage sensing inputs [1/H14]
• X5 – Inverter output voltage sensing inputs [2/C16]
• X6 – Bypass voltage sensing inputs [1/G5]
• X7 – Power switch auxiliary contacts
• X8 – Interface to external connection block X3 [1/M3]
• X9 – Battery cabinet temperature sensor inputs [1/M3]
• X10 – Input air temperature sensor inputs for display metering
• X11 – Inverter output air temperature sensor inputs for display metering
• X12 – Transformer cabinet temperature sensor inputs for display metering
• X13 – Inverter assembly thermostats (n/c – open above 90°C)
• X14 – Not in use
• X15 – Battery fuse monitor [1/N4]
• X16 – Not in use (linked out)
• X17 – Not in use (linked out)
• X18 – Rectifier assembly thermostats (n/o – not normally used)
• X19 – Output current monitoring W-ph [1/F16]
• X20 – Output current monitoring V-ph [1/F16]
• X21 – Output current monitoring U-ph [1/F16]
• X22 – Battery current monitoring [2/M8]
• X23 – Not in use

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CHAPTER 2 - Main Power Circuit Diagram Descriptions

• X24 – Inverter current monitoring V-ph [2/E13]

• X25 – Inverter current monitoring W-ph [2/F14]
• X26 – Not in use
• X27 – Not in use

UPS Logic Board 4550004-E

This board serves two major functions:
• first it contains the logic which controls the static switch/inverter output
contactor and load transfer between inverter and static bypass supplies.
• second, it contains the fault-detection-based general system control logic
which determines the operation of the rectifier (via the Rectifier Logic
Board) and inverter (via the inverter Logic Board).
Note: When compared with the circuit boards fitted in the 7400 Series UPS, this
board combines the UPS Logic Board and Static Switch Logic Board functions.
In addition to the above functions this board also provides an interface between
the general control system and the Operator Panel and external alarms option.

Rectifier Logic Board 4520074-A

The Rectifier Logic Board provides the rectifier SCRs with their gate drive sig-
nals at a suitable conduction angle to produce the required battery charge voltage.
It receives battery voltage and battery current feedback signals, and input voltage
sense signals via the High Voltage Interface Board and UPS Logic Board. The
drive pulses are processed on the Rectifier Gate Drive Board (4542040-W) before
application to the SCR gates.
The Rectifier Logic Board receives its operating power from the AC-DC Power
Supply assembly (4503030-M) which is energised whenever the input mains
supply or bypass supply is live (via T2 [2/K5]) or (via T3 [1/H7]) – i.e. both these
transformers feed the same power supply circuit in parallel.

Inverter Logic Board 4530024-S

The Inverter Logic Board provides the inverter IGBTs with their base drive sig-
nals with a suitable PWM pattern to produce the required output voltage. It re-
ceives output voltage and current feedback signals, and bypass voltage sense
signals via the High Voltage Interface Board and UPS Logic Board. The drive
pulses are processed on the Inverter Drive Interface Boards (4519015-H) before
application to the IGBTs.
The Inverter Logic Board receives its operating power from the DC-DC Power
Supply assembly (4503028-K) which is energised via fuses F4-F5 [2/H8] when-
ever the DC busbar is live – i.e. either due to the rectifier being operative (when
the input mains is present) or when the batteries are connected to the dc busbar
(external circuit breaker closed).

Control power supplies

The power supplies from the Inverter Logic Board and Rectifier Logic Board are
paralleled on the UPS Logic Board and fed to the other boards in the control
system as necessary. Therefore when the UPS is started-up the ‘control system’
is powered-up as soon as the AC-DC Power Supply is energised by the closure of
the input mains switch (Q1). Once the rectifier is fully operational the DC-DC
Power Supply provides an alternative (parallel) supply source which supports the
control system operation if the input mains supply subsequently fails.
The power supplies from the Inverter Logic Board and Rectifier Logic Board are

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SECTION 1 - System Description 7200 Series UPS Service Manual
CHAPTER 2 - Main Power Circuit Diagram Descriptions

paralleled on the UPS Logic Board and fed to the other boards as necessary.
Therefore when the UPS is started-up the ‘control system’ is powered-up as soon
as the AC-DC Power Supply is energised by the closure of the input mains switch
(Q1). Once the rectifier is fully operational the DC-DC Power Supply provides an
alternative (parallel) supply source which supports the control system operation
if the input mains supply subsequently fails.
Note: the Inverter Logic Board and Inverter Driver Board are energised from the
DC-DC supply only.

2.4 60kVA Model description – SE-5410308-U

SE-5410308-U Page 1. This page shows the bypass input and UPS output
power connections together with the bypass circuits.

Bypass supply feed

If the UPS is connected with a ‘split-bypass’ supply the dedicated bypass supply
is connected to U(3)-V(3)-W(3)-N(3) from where it is connected to the static
bypass switch Q2 and maintenance bypass switch Q3. If a ‘common bypass’
system is used, there are no external connections to U(3)-V(3)-W(3)-N(3) and the
power for Q2 and Q3 is obtained from the UPS input mains supply terminals
U(1)-V(1)-W(1) [page 2] via links which are connected between the mains and
bypass input terminals [2/C2].

Maintenance bypass switch

The maintenance bypass switch (Q3) makes a direct connection between the
bypass supply and UPS output terminals, therefore completely bypassing the UPS
for maintenance and troubleshooting purposes. This switch is always open during
normal UPS operation, and can be padlocked in the open position. If the switch is
closed while the inverter is operating (i.e. while Q4 is closed) its auxiliary con-
tacts [3/L1] will trigger a safety circuit in the UPS control system which will open
the inverter output contactor to isolate the power inverter from the output termi-
nals and prevent any damage which might otherwise occur due to a reverse power
flow.

Static bypass switch (Q2) to static switch assembly

Q2 connects the three-phase bypass supply to the static switch assembly and must
be closed during normal UPS operation to ensure the availability of the static
bypass supply when required.
The bypass voltage at the switched side of Q2 is monitored by the High Voltage
Interface Board via wires 1,2,3 and 4. This is used for bypass voltage error detec-
tion and inverter synchronisation control; the U and V phases also power the con-
trol power supply transformer (T3) via F6 and F7. T3 primary has three taps
which are selected according to the working voltage to produce a nominal 30Vac
secondary voltage – tap selection details are shown on the diagram. T3’s second-
ary feeds one input to the AC-DC Power Supply (4503030-M) [3/D19].

Static switch assembly

The static switch assembly, shown as a dashed block, is shown in detail in dia-
gram SE-4612045-J (circuit diagram) and AM-4612045-J (assembly drawing).
This assembly also contains the rectifier power components in addition to those
belonging to the static switch.

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CHAPTER 2 - Main Power Circuit Diagram Descriptions

From the static switch point of view, this assembly contains the six SCRs associ-
ated with the bypass static switch together with their Gate Drive Control Board
(SE-4542041-X) and snubber board (SE-4540043-B).
All the connectors shown in the static bypass block on page 1 refer to the Gate
Driver Control Board (SE-4542041-X):
• Connector X13 is connected to the UPS Logic Board X5 [3/G16] and
interfaces the Gate Driver Control Board with the remainder of the UPS
control system via ribbon cable W7.
• Connector X10 monitors the inverter output contactor’s auxiliary contacts,
which are used for interlocking and status indication purposes.
• Connector X9 carries the switched supply for energising the coil of the
inverter output contactor.
• Connector X8 is connected to the DC busbar [2/H8] via F4-F5 and is the
source of the inverter output contactor energising supply mentioned above.
• Terminals A-C and A'-C' are the mains input/output power connections.

Static switch assembly to output switch Q4

The static switch power outputs are connected to the output switch (Q4) via an
output RFI filter (Z2) and output current sensing CTs (T4-T6), which are used for
metering and overload monitoring purposes [3/G6]. Note that the inverter output
contactor is connected in parallel with the bypass static switch outputs and is fed
from the output transformer [2/B17-B18]
Wires 5-8 are used for output voltage monitoring and metering purposes, and are
connected to various sections of the UPS control system via the High Voltage In-
terface Board [3/N8]. They also provide power for the cooling fans which are all
single-phase operating and distributed across the phases as shown.
The output switch Q4 is a 4-pole switch with a set of auxiliary contacts which are
monitored by the control system in the same manner as those described above for
the maintenance bypass switch (Q3).

Remote connections
The lower left-hand ares of page 1 shows details of various remote connections to
terminal block X3 (X3 connections are made by ‘spade connectors’). These con-
nections are used for:
• Emergency stop – normally closed (volt-free) circuit connected between
X3 terminals 10 and 11. If an external emergency stop option is not in use
then these two terminals must be shorted together at the terminal block.
• Battery temperature sensing – the battery temperature is sensed by the
float charge control system such as to decrease the float voltage by
1.5Vdc/°C as the temperature increases between 25°C and 35°C. The tem-
perature sensor is connected between X3 terminals 2 and 3, and is polarity
sensitive.
• Battery CB-AUX – the external battery circuit breaker auxiliary contacts
are connected between X 3 terminals 4 (ground) and 3 such as to short
these terminals together when the breaker is closed.
• Battery trip – the battery circuit breaker is manually operated but can be
tripped by the UPS control system if required – e.g. Low Battery trip when
the battery discharges to 320Vdc. The trip circuit is connected via X3 ter-
minals 4 (ground) and 6 (logic high to trip) and is normally applied to the
breaker via an opto-coupled trip circuit for supply isolation.

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SECTION 1 - System Description 7200 Series UPS Service Manual
CHAPTER 2 - Main Power Circuit Diagram Descriptions

SE-5410308-U Page 2. This page shows the UPS input, rectifier, dc bus, in-
verter and output transformer power circuits.

Bypass supply feed

The UPS input mains supply is connected to terminals U(1)-V(1)-W(1) which are
in turn connected directly to the input switch Q1.
If a ‘common bypass’ system is used the input supply terminals U(1)-V(1)-W(1)
are connected by links to the bypass terminals U(3)-V(3)-W(3)-N(3) [1/C1]. If a
‘split-bypass’ system is used then these links must be removed and a dedicated
bypass supply is connected to U(3)-V(3)-W(3)-N(3) [page 1].

Input switch Q1 to rectifier

The input mains passes from the input switch Q1 to the rectifier via the input fuses
F10-F12, input RFI filter (Z1), optional input filter (4641017-R) and input filter
choke.
The input voltage is monitored by the control system via wires 15-17 and the High
Voltage Interface Board [3/N8]. This is used to detect input voltage failure
(-20%), input phase rotation error and also provides basic phase-timing informa-
tion for the rectifier SCR control logic. The V and W phases also power the con-
trol power supply transformer (T2) via F8 and F9 (1A). This transformer is
identical to T3 which is fed from the bypass supply and described on the previous
page, and once again its primary is tapped to suit the working mains supply volt-
age – tap details shown on [2/P7].

Power rectifier block

The rectifier assembly, shown as a dashed block, is shown in detail in diagram
SE-4612047-R (circuit diagram) and AM-4612047-R (assembly drawing). This
assembly also contains the static switch power components in addition to those
belonging to the rectifier.
Considering the rectifier, this assembly contains the six SCRs associated with the
rectifier together with their Gate Drive Control Board (SE-4542040-W) and snub-
ber board (SE-4540043-B). There are also two thermostats fitted to the U and V
phase heatsinks (not normally used).
The rectifier gate drive signals are applied to connector X7 on the Gate Driver
Control Board (SE-4542040-W) via ribbon cable W4, and the rectifier’s output
DC power rails are connected to the dc busbar via cables 27 (+) and 28 (-).

DC Busbar
The DC busbar is controlled by the rectifier to be at the required battery charging
voltage at all times and is smoothed by a capacitor bank (C1-C4) – less than 1%
voltage ripple. The smoothed busbar is then connected to the batteries via an ex-
ternal circuit breaker, and to the inverter (4612145-F). In the battery line is a
DCCT (T11) which provides the UPS control system with a battery current sense
signal via the High Voltage Interface Board [3/G6], and a battery fuse (F13)
which is monitored by means of a micro-switch to detect its failure.
Wires 27 and 28 provide the rectifier control system with a dc busbar (battery)
feedback voltage via the High Voltage Interface Board [3/N9] – used for closed-
loop voltage control and dc bus (battery) voltage metering. This signal also pro-
vides a battery voltage metering function. The dc busbar is also connected to a
DC-DC control power supply board [3/E7] via fuses F4-F5 (1A) – the same fused

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7200 Series UPS Service Manual SECTION 1 - System Description
CHAPTER 2 - Main Power Circuit Diagram Descriptions

supply is connected to the inverter output contactor control circuit on the static
switch assembly [1/G8], as described earlier.

Power inverter
The inverter assembly, shown as a dashed block, is shown in detail in diagram
SE-4612145-F (circuit diagram) and AM-4612145-F (assembly drawing). This
assembly contains the six inverter IGBT transistors (single pack devices), three
Base Drive Boards (4519015-H), suppression capacitors and two normally-closed
series-connected thermostats.
The transistor drive signals are connected via ribbon cables W1-W2-W3 to CN1
on each Base Drive Board.

Power inverter to output switch

The inverter output is connected to the output transformer where it is stepped-up
to the required output voltage. The output transformer step-up ratio is 1:2 and it
is delta-star (zig-zag) wound with the output star point connected to the system’s
neutral.
Capacitors C5-C10 connected across the output line-to-line act as a filter to
remove any remnants of the PWM switching frequency from the output wave-
form, thus producing a clean sinusoidal output at the nominal output frequency.
Current transformers T9 and T10 provide the inverter voltage regulation control
system with output current sense signals, via the High Voltage Interface Board
[3/G7-G8]. These are used by the inverter regulation control electronics to en-
hance the inverter regulation during load changes, and also by the output current
limit protection control system.
Wires 9-11 provide the inverter voltage control system with an output voltage
feedback signal, via the High Voltage Interface Board [3/H4]. This is used by the
inverter voltage regulation control circuits and static switch ‘fault and transfer’
control logic
SE-5410308-U Page 3. This page shows the UPS control system circuit
boards and their interconnections. A basic description of the individual boards’
functions are provided below.

High Voltage Interface Board 4590054-O

This board interfaces the high-voltage sense and control signals of the UPS power
circuits with the low-voltage environment on the control circuit boards.
• X1 – connects the low voltage signals produced on this board to the UPS
Logic Board from where they are transmitted to the remaining boards as
required.
• X2 – DC bus (battery) voltage sense inputs [2/G8].
• X3 – Input mains voltage sensing inputs [2/F7]
• X4 – UPS output voltage sensing inputs [1/H14]
• X5 – Inverter output voltage sensing inputs [2/C16]
• X6 – Bypass voltage sensing inputs [1/G5]
• X7 – Power switch auxiliary contacts
• X8 – Interface to external connection block X3 [1/M3]
• X9 – Battery cabinet temperature sensor inputs [1/M3]
• X10 – Input air temperature sensor inputs for display metering
• X11 – Inverter output air temperature sensor inputs for display metering
• X12 – Transformer cabinet temperature sensor inputs for display metering

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SECTION 1 - System Description 7200 Series UPS Service Manual
CHAPTER 2 - Main Power Circuit Diagram Descriptions

• X13 – Inverter assembly thermostats (n/c – open above 90°C)

• X14 – Not in use
• X15 – Battery fuse monitor [1/N4]
• X16 – Not in use (linked out)
• X17 – Not in use (linked out)
• X18 – Rectifier assembly thermostats (n/o – not normally used)
• X19 – Output current monitoring W-ph [1/F16]
• X20 – Output current monitoring V-ph [1/F16]
• X21 – Output current monitoring U-ph [1/F16]
• X22 – Battery current monitoring [2/M8]
• X23 – Not in use
• X24 – Inverter current monitoring V-ph [2/E13]
• X25 – Inverter current monitoring W-ph [2/F14]
• X26 – Not in use
• X27 – Not in use

UPS Logic Board 4550004-E

This board serves two major functions:
• first it contains the logic which controls the static switch/inverter output
contactor and load transfer between inverter and static bypass supplies.
• second, it contains the fault-detection-based general system control logic
which determines the operation of the rectifier (via the Rectifier Logic
Board) and inverter (via the inverter Logic Board).
Note: When compared with the circuit boards fitted in the 7400 Series UPS, this
board combines the UPS Logic Board and Static Switch Logic Board functions.
In addition to the above functions this board also provides an interface between
the general control system and the Operator Panel and external alarms option.

Rectifier Logic Board 4520074-A

The Rectifier Logic Board provides the rectifier SCRs with their gate drive sig-
nals at a suitable conduction angle to produce the required battery charge voltage.
It receives battery voltage and battery current feedback signals, and input voltage
sense signals via the High Voltage Interface Board and UPS Logic Board. The
drive pulses are processed on the Rectifier Gate Drive Board (4542040-W) before
application to the SCR gates.
The Rectifier Logic Board receives its operating power from the AC-DC Power
Supply assembly (4503030-M) which is energised whenever the input mains
supply or bypass supply is live (via T2 [2/K5]) or (via T3 [1/H7]) – i.e. both these
transformers feed the same power supply circuit in parallel.

Inverter Logic Board 4530024-S

The Inverter Logic Board provides the inverter IGBTs with their base drive sig-
nals with a suitable PWM pattern to produce the required output voltage. It re-
ceives output voltage and current feedback signals, and bypass voltage sense
signals via the High Voltage Interface Board and UPS Logic Board. The drive
pulses are processed on the Inverter Drive Interface Boards (4519015-H) before
application to the IGBTs.
The Inverter Logic Board receives its operating power from the DC-DC Power
Supply assembly (4503028-K) which is energised via fuses F4-F5 [2/H8] when-
ever the DC busbar is live – i.e. either due to the rectifier being operative (when

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7200 Series UPS Service Manual SECTION 1 - System Description
CHAPTER 2 - Main Power Circuit Diagram Descriptions

the input mains is present) or when the batteries are connected to the dc busbar
(external circuit breaker closed).

Control power supplies

The power supplies from the Inverter Logic Board and Rectifier Logic Board are
paralleled on the UPS Logic Board and fed to the other boards in the control
system as necessary. Therefore when the UPS is started-up the ‘control system’
is powered-up as soon as the AC-DC Power Supply is energised by the closure of
the input mains switch (Q1). Once the rectifier is fully operational the DC-DC
Power Supply provides an alternative (parallel) supply source which supports the
control system operation if the input mains supply subsequently fails.
Note: the Inverter Logic Board and Inverter Driver Board are energised from the
DC-DC supply only.

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CHAPTER 2 - Main Power Circuit Diagram Descriptions

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 Section 2: Installation & Commissioning

Chapter 1 - Installation
1.1 Introduction .............................................................................................. 2-1
1.1.1 Equipment positioning and environmental considerations .......... 2-2
1.1.2 Raised Floor Installation .............................................................. 2-2
1.1.3 Battery Location ........................................................................... 2-2
1.2 Preliminary Checks .................................................................................. 2-4
1.3 Connecting the UPS power cables ........................................................... 2-5
1.3.1 Cable entry ................................................................................... 2-5
1.3.2 Cable rating .................................................................................. 2-5
1.3.3 Cable connections ........................................................................ 2-6
1.3.4 Safety earth .................................................................................. 2-6
1.3.5 Cabling procedure ........................................................................ 2-6
1.4 Battery Installation ................................................................................. 2-10
1.4.1 Battery circuit breaker boxes ..................................................... 2-11

Chapter 2 - Commissioning Procedure

2.1 Introduction ............................................................................................ 2-13
2.2 Procedure overview ................................................................................ 2-14
2.3 Pre-commissioning Checks .................................................................... 2-16
2.3.1 Power cable installation ............................................................. 2-16
2.3.2 Control cable installation ........................................................... 2-17
2.3.3 Battery Power Cable Installation ............................................... 2-19
2.3.4 Printed circuit board configuration jumper selection ................. 2-20
2.3.5 Pre-power checks ....................................................................... 2-26
2.3.6 Initial utility power connection .................................................. 2-28
2.4 Start-Up and software commissioning ................................................... 2-29
2.4.1 Operator Control Panel display screen ...................................... 2-29
2.4.2 Applying power to the UPS ....................................................... 2-30
2.4.3 Password protection and operation ............................................ 2-30
2.4.4 Language Selection .................................................................... 2-31
2.4.5 Selecting the UPS SETUP parameters ....................................... 2-33
Setting the basic UPS configuration ................................ 2-34
Setting the UPS working voltage parameters .................. 2-34
Setting the UPS frequency parameters ............................ 2-35
Setting the Battery parameters ......................................... 2-36
2.4.6 Selecting the UPS MAINTENANCE parameters ...................... 2-39
Accessing the maintenance menu .................................... 2-39
Entering the Serial Number ............................................. 2-39
Entering the current Date and Time ................................. 2-40
Entering the Service details ............................................. 2-40

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SECTION 2 - Installation & Commissioning 7200 Series UPS Service Manual

2.4.7 Selecting the UPS FUNCTION parameters ............................... 2-40

Accessing the function menu ........................................... 2-40
Setting the Battery Test parameters ................................. 2-42
Setting the Generator parameters ..................................... 2-43
Setting the Panel Setup selections .................................... 2-44
Setting the NEXT PAGE selections ................................ 2-46
2.5 Power checks .......................................................................................... 2-47
2.5.1 Applying power to the UPS ....................................................... 2-47
2.5.2 Monitoring & recording the UPS operating parameters ............ 2-47
2.5.3 Power module ON/OFF functional checks ................................ 2-49
Accessing the ON/OFF menu screen ............................... 2-49
Inverter test ...................................................................... 2-50
Bypass test ....................................................................... 2-50
Rectifier and battery autonomy test ................................. 2-50
2.5.4 Battery test ................................................................................. 2-51
2.5.5 Emergency remote power off check .......................................... 2-53
2.5.6 Battery boost test (if applicable) ................................................ 2-53
2.5.7 On-Generator test (if applicable) ............................................... 2-54
2.6 Commissioning conclusion (‘single module’) ....................................... 2-55
2.7 Parallel System Start Up (‘1+1’ System) ............................................... 2-55
2.7.1 Initialisation ............................................................................... 2-55
2.7.2 Parallel logic PCB calibration .................................................... 2-56
2.8 Testing the Complete Parallel System .................................................... 2-57
2.8.1 Module starting .......................................................................... 2-57
2.8.2 Inverter bypass re-transfer checks ............................................. 2-57
Redundant configuration system power checks ............... 2-58
Non-redundant configuration system power checks ........ 2-59
2.9 Commissioning conclusion (‘1+1’ system) ............................................ 2-60
2.10 Voltage and Frequency Conversion ..................................................... 2-61
2.10.1 Rating considerations and battery sizing ................................. 2-61
2.10.2 Hardware conversion ............................................................... 2-61
2.10.3 Software conversion ................................................................. 2-62
Setting the UPS working voltage parameters .................. 2-63
Setting the UPS frequency parameters ............................ 2-63
Setting the Battery parameters ......................................... 2-64
2.10.4 Calibration conversions ........................................................... 2-67
Recalibrating the battery charging voltages ..................... 2-67
Completion of UPS SETUP configuration ...................... 2-68

Chapter 3 - Converting single (pre Jan 1997) units to 1+1 capability

3.1 Introduction ............................................................................................ 2-69
3.2 Conversion Procedure ............................................................................ 2-69

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 Section 2:

Chapter 1 - Installation

1.1 Introduction

WARNING Do not apply electrical power to the UPS equipment before the arrival of the com-
missioning engineer.

WARNING The UPS equipment should be installed by a qualified engineer in accordance

with the information contained in this chapter and the drawing package shipped
inside the UPS cabinet.

WARNING Battery hazards:

Special care should be taken when working with the batteries associated with this
equipment. When connected together, the battery terminal voltage will exceed
400 Vdc and is potentially lethal.
Eye protection should be worn to prevent injury from accidental electrical arcs.
Remove rings, watches and all metal objects.
Only use tools with insulated handles.
Wear rubber gloves.
If a battery leaks electrolyte, or is otherwise physically damaged, it should be
placed in a container resistant to sulphuric acid and disposed of in accordance
with local regulations.
If electrolyte comes into contact with the skin the affected area should be washed
immediately.

This chapter contains information regarding the positioning and cabling of the
UPS equipment and batteries.
Because every site has its peculiarities, it is not the aim of this chapter to provide
step-by-step installation instructions, but to act as a guide as to the general proce-
dures and practices that should be observed by the installing engineer.
Important Note: These instructions are written specifically for a ‘single-module’ installation. If
1+1 you are installing a two-module ‘1+1’ system you should follow the instructions
provided for the ‘single-module’ installation and then complete the inter-module
control cabling to complete the installation. If you are converting an early (pre
January 1997) module for ‘1+1’ operation then refer to Chapter 3 and carry out
the necessary modifications prior to installing the module.
Options: There are several options available in conjunction with a ‘1+1’ configured sys-
1+1 tem, such as common battery operation. Read the instructions that accompany any
such option prior to commencing installation to understand their impact (if any)
on the following procedure.

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SECTION 2 - Installation & Commissioning 7200 Series UPS Service Manual
CHAPTER 1 - Installation Procedure

1.1.1 Equipment positioning and environmental considerations

The UPS cabinets are fitted with castors to facilitate ease of movement and posi-
tioning. When the equipment has been finally positioned ensure the adjustable
jacking feet are set so that the UPS will remain stationary and stable.
The UPS can be lifted using either a fork lift or a cradle. When lifting, take care
not to damage the castors or jacking feet located on the bottom of the unit.

WARNING Ensure the UPS weight is within the designated S.W.L. of any handling equip-
ment. See the UPS specification for weight details.
Do not move battery cabinets with the batteries fitted.

The UPS module should be located in a cool, dry, clean-air environment with ad-
equate ventilation to keep the ambient temperature within the specified operating
range. Where ventilation is poor and the ambient temperature high, a system of
extractor fans should be installed to aid cooling-air flow; and a suitable air filtra-
tion system used where the UPS is to operate in a dirty environment.
Cables: All control cables should be screened and run in metal conduits (or
ducts) separate from the power cables; all conduits and ducts should be electrical-
ly bonded to the metalwork of the cabinets to which they are connected.
Cooling air flow: All the models in the 7200 range are force-cooled by internal
fans. Cooling air enters the cabinet through ventilation grills located at the bottom
of the front doors and is exhausted through the fan grills located on the rear panel;
you must therefore allow for a minimum gap of 250mm behind the unit to allow
adequate air flow (See Figure 2-1).
Clearances: Clearance around the front of the equipment should be sufficient to
enable free passage of personnel with the doors fully opened.

1.1.2 Raised Floor Installation

If the equipment is to be located on a raised floor it should be mounted on a ped-
estal suitably designed to accept the equipment point loading. The installation di-
agrams accompanying the system identify the location through which the cabinet
can be secured to the floor.

1.1.3 Battery Location

Temperature is a major factor in determining the battery life and capacity. Battery
manufacturers quote figures for an operating temperature of 20ºC. Operating
above this temperature will reduce the battery life, yet operating below will
reduce the battery capacity. In a normal installation the battery temperature
should be maintained between 15ºC and 25ºC.
Batteries should be mounted in an environment where the temperature is consist-
ent and even over the whole battery. Keep batteries away from main heat sources
or draughty air flows etc.
Pedestals are required for the battery cabinets if they are to be installed on raised
floors, in the same way as for the UPS cabinets.

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7200 Series UPS Service Manual SECTION 2 - Installation & Commissioning
CHAPTER 1 - Installation Procedure

Figure 2-1: Installation Diagram

FRONT VIEW SIDE VIEW

250 800

FRONT
1400

3
55

710

Adjustable fixing Castors for

feet ease of movement REAR VIEW

BASE

5
605

800
125

40
92.5

200 85 10 200 125 3

710

1 Entry panel for all power cables

REAR VIEW
2 Entry panel for all control cables

3 Air inlet ventilation grills

4 Minimum clearance from wall 250mm

5 Cabinet extractor fans - additional fans are fitted

when the input harmonic filter is included

Weights

30kVA = 480kg. 40kVA = 540kg. 60kVA = 620kg.

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SECTION 2 - Installation & Commissioning 7200 Series UPS Service Manual
CHAPTER 1 - Installation Procedure

1.2 Preliminary Checks

Before you install the UPS hardware you should carry out the following prelimi-
nary checks:
1. Verify that the UPS room satisfies the environmental conditions stipulated in
the equipment specification, paying particular attention to the ambient tem-
perature and air exchange system.
2. After removing any packaging debris, visually examine the UPS and battery
equipment for transit damage, both internally and externally. Report any such
damage to the shipper immediately.
3. Verify that the shipment is complete - e.g. that the battery contains the correct
number of cells etc. Report any discrepancy immediately.
4. When you are satisfied that the equipment is complete and in good condition
move it to its proposed final position.

Figure 2-2: Cable Entry Locations

Auxiliary terminal block

(X3)
Main chassis
earth busbar

Castors
Power cable
entry panel

Adjustable fixing feet

Control cables
entry position

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7200 Series UPS Service Manual SECTION 2 - Installation & Commissioning
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1.3 Connecting the UPS power cables

WARNING Before cabling-up the UPS, ensure that you are aware of the location and opera-
tion of the external isolators that connect the UPS input/bypass supply at the
mains distribution panel.
Check that these supplies are electrically isolated, and post any necessary warn-
ing signs to prevent their inadvertent operation.

1.3.1 Cable entry

Cables enter the UPS modules via entry panels in the base of the cabinet. As
shown in Figure 2-2, separate entry points are provided for the power cables
(which include the input, output and battery cables) and control cables (which in-
cludes battery control, remote stop and remote communication wiring).

1.3.2 Cable rating

The input/output cables can be sized to suit the modules' rating according to Table
2-1 below.
Table 2-1:

BUSBAR
NOMINAL CURRENT: Amps
CONNECTION
Recommended Cable Size (mm2)
STUD SIZE
UPS
Input Mains Input/
RATING Bypass/Output Battery
with full battery Battery at Output
(kVA) at full load Terminat
recharge min. Cable
ions
battery Terminat
+ve &
voltage ions
380V 400V 415V 380V 400V 415V -ve
U-V-W-N

64 59 56 46 44 42 82
30 M6 Bolt M8 Bolt
(16) (16) (16) (10) (10) (10) (25)

85 78 73 61 58 56 110 M6 Bolt M8 Bolt

40
(25) (25) (25) (16) (16) (16) (35)

128 117 109 91 87 84 163

60 M6 Bolt M8 Bolt
(35) (35) (35) (25) (25) (25) (50)

(nn) mm2 is the recommended minimum size according to BS7671 Table 4D1A
(IEE regs. 16th Edition).
The following recommendations are guidelines only and superseded by local
regulations and codes of practice where applicable:
1. The neutral conductor should be sized for 1.5 times the output/bypass phase
current.
2. The earth conductor should be sized at 2 times the output/bypass conductor
(this is dependent on the fault rating, cable lengths, type of protection etc.).
3. BS7671 Table 4D1A applies to single core PVC-insulated, non armoured
cable in an ambient temperature of 30ºC, according to fixing method 1 – sam-
ples shown in Figure 2-3.

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SECTION 2 - Installation & Commissioning 7200 Series UPS Service Manual
CHAPTER 1 - Installation Procedure

Figure 2-3: Cable fixing samples from method 1

Sheathed cables
clipped direct to or
lying on a non-metallic
surface

1.3.3 Cable connections

The input (bypass) mains cables, UPS output cables and main battery cables are
connected to busbars fitted to the power isolator switches (lug terminations re-
quired). The battery circuit breaker control cables and the external emergency
stop cables (optional) are connected using female spade connectors to an auxiliary
terminal block identified as “X3” - (See Figure 2-5).

1.3.4 Safety earth

The safety earth busbar is located near the input and output power supply connec-
tions as shown in Figure 2-5. The site safety earth cable must be connected to the
earth busbar and bonded to each cabinet in the system and all cabinets and cable
trunking should be earthed in accordance with local regulations.

WARNING Failure to follow adequate earthing procedures can result in electric shock hazard
to personnel, or the risk of fire, should an earth fault occur.

1.3.5 Cabling procedure

Once the equipment has been finally positioned and secured, connect the power
cables as described in the following procedure.
Study the connection diagram in Figure 2-5.

Input mains supply cables

1. Verify that the UPS equipment is totally isolated from its external power
source and all the UPS power isolators are open.
2. Connect the a.c. input supply cables between the mains distribution panel and
the UPS rectifier input supply busbars (top of Q1) and tighten the connections
to 5,4 Nm – ensure correct phase rotation.

Bypass mains supply cables

3. If the installation does not include the provision of a separate bypass supply
then:
a) Ensure that the ‘split bypass’ links are fitted between the input mains bus-
bars (top of Q1) and the bypass supply busbars (junction of Q2/Q3) – see
Figure 2-5.
b) Ensure that the input supply neutral is connected to N3.
c) Jump to step 5.
4. If the installation does include the provision of a separate bypass supply then:
a) Connect the bypass supply cables between the bypass mains distribution

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7200 Series UPS Service Manual SECTION 2 - Installation & Commissioning
CHAPTER 1 - Installation Procedure

panel and the bypass supply busbars (junction of Q2/Q3) – see Figure 2-5.
– ensure correct phase rotation.
b) Ensure that the bypass supply neutral is connected to N3
c) Tighten the connections to 5,4 Nm.
d) Remove the ‘split bypass’ links are (if fitted) between the input mains bus-
bars (top of Q1) and the bypass supply busbars (junction of Q2/Q3) – see
Figure 2-5.

Figure 2-4: UPS External Cables

D
A
E
B F
C G
H

A Rectifier a.c. input supply E Battery control/temp. compensation

B Bypass a.c. input supply F Communications to PC or modem

C UPS a.c. output G Communications to AS400/external alarms

D Battery power H Remote emergency power off (EPO)

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SECTION 2 - Installation & Commissioning 7200 Series UPS Service Manual
CHAPTER 1 - Installation Procedure

Figure 2-5: Power and control cable connections

K1

F13
Reset
button
Auxiliary terminal block (X3)
Terminals are male type spade connectors

Safety
Earth 1 2 3 4 5 6 7 8 9 10 11 12

These links
E.P.O.
Batt CB aux. contact
Batt.

Common

Batt CB trip
Temp

must be R S T N
removed for Output
split bypass Connections
systems (to Load)

R S T N
Input connections for
split bypass system
(from mains a.c. supply)
Bypass input supply neutral (split bypass system)
R S T N OR
Input supply neutral (non-split bypass)
UPS Rectifier (input mains)
connections
(from mains a.c. supply)
R S S T
F13
F11
F12

All power connections require lug type terminations.

Connections torque loading is 5,4Nm

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7200 Series UPS Service Manual SECTION 2 - Installation & Commissioning
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5. Connect the UPS output cables between the output busbars (junction Q3
&Q4) and the load distribution panel, and tighten the connections to 5,4 Nm.
6. Connect the battery power cables between the UPS battery terminals and the
associated battery circuit breaker - see Figure 2-5 and Figure 2-7 - observe the
correct battery cable polarity. As a safety precaution remove the battery fuse
in the module until the arrival of the commissioning engineer.

WARNING Do not close the battery circuit breaker before the equipment is commissioned.

7. Connect the safety earth and any necessary bonding earth cables to the copper
earth busbar located below the battery power connections.
Note: The earthing and neutral bonding arrangement must be in accordance
with local and national codes of practice.
8. Connect the battery circuit breaker control and temperature compensation
cables between the UPS auxiliary terminal block ‘X3’ and battery circuit
breaker controller board as shown in Figure 2-5 and Figure 2-7. These cable
must be shielded.

Caution If battery temperature compensation is not to be used, it must be de-activated by

the commissioning engineer.

9. If the remote emergency power off (EPO) facility is to be used then remove
the link between terminals 10 and 11 of the auxiliary terminal block ‘X3’ and
connect the ‘normally closed’ remote stop switch between these two termi-
nals using shielded cable.

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CHAPTER 1 - Installation Procedure

1.4 Battery Installation

SAFETY Only qualified personnel should install or service batteries.

WARNINGS Batteries present a risk of electric shock or burn from high short circuit currents.
Eye protection should be worn to prevent injury from accidental electrical arcs.
Remove rings, watches and all metal objects.
Only use tools with insulated handles.
Wear rubber [Link] a battery leaks electrolyte, or is otherwise physically dam-
aged, it should be placed in a container resistant to sulphuric acid and disposed
of in accordance with local regulations.
If electrolyte comes into contact with the skin the affected area should be washed
immediately.
Batteries must be disposed of according to local environmental laws.

Due to the IGBT inverter design, the required DC busbar voltage level is depend-
ent on the system output a.c. voltage; the required number of battery blocks there-
fore differ according to the system voltage, as shown below:-
380V a.c. system requires a 432V DC busbar = 192 battery cells.
400V a.c. system requires a 446V DC busbar = 198 battery cells.
415V a.c. system requires a 459V DC busbar = 204 battery cells.
The batteries associated with the UPS equipment are usually contained in a pur-
pose-built battery cabinet which sits alongside the main UPS equipment. Sealed,
maintenance-free batteries are normally used in this type of installation.
There are three types of battery cabinet offered with the Series 7200 UPS which
are graded according to their recommended ampere hour capacity. Type B is rated
at 38 Ah; Type C is rated at 50 Ah and Type D is rated at 85 Ah. The cabinets are
of the same height as the UPS and can be sited on either side of the UPS cabinet.
A full description of these cabinets is given in the Options Section of this manual.
Where battery racks are used, they should be sited and assembled in accordance
with the battery manufacturer's recommendations. In general, batteries require a
well ventilated, clean and dry environment at reasonable temperatures to obtain
efficient battery operation.
Battery manufacturers’ literature provides detailed safety measures to be ob-
served when employing large battery banks: these should be studied, and the pro-
posed battery installation checked, to verify compliance with the appropriate
recommendations.
In general a minimum space of 10 mm must be left on all vertical sides of the bat-
tery block. A minimum clearance of 20 mm should be allowed between the cell
surface and any walls. A clearance of 150 mm should be allowed between the top
of the cells and the underside of the shelf above (this is necessary to for monitor-
ing and servicing the cells). All metal racks and cabinets must be earthed. All live
cell connections must be shrouded.
The batteries are connected to the UPS through a circuit breaker which is manu-
ally closed and electronically tripped via the UPS control circuitry. If the batteries
are cabinet-mounted this circuit breaker is fitted within the cabinet; however, if
the batteries are rack-mounted or otherwise located remote from the main UPS
cabinet then the battery circuit breaker must be mounted as near as possible to the
batteries themselves, and the power and control cables connected to the UPS
using the most direct route possible. Liebert offer a purpose-designed remote bat-

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CHAPTER 1 - Installation Procedure

tery circuit breaker box, containing the circuit breaker and its necessary control
board, as a standard option kit. The battery cabinet or circuit breaker box should
be bonded to the UPS cabinet to maintain EMC compliance.

1.4.1 Battery circuit breaker boxes

A battery circuit breaker box houses the battery circuit breaker and its controller
board and is used to connect the battery to the UPS in installations where the bat-
teries are not contained in the standard battery cabinet.
Two boxes are available which are similar in design and content, and described
below:
• 100 Amp C/B Part No. 4641027 B for use with 30 - 40 kVA models.
• 160 Amp C/B Part No. 4641028 C for use with 60kVA model.

Usually the ‘box' is fitted as close as possible to the batteries. Battery circuit
breaker boxes must be earthed. The connections are similar to the connections
made to the battery cabinet.
Figure 2-6 shows details of the power and control cable connections between the
circuit breaker box or battery cabinet and the UPS itself. Two methods of connect-
ing the three pole battery circuit breaker are illustrated. Method A shows the spare
pole being used to divide the battery bank in half, thereby reducing the battery
total voltage to half when the circuit breaker is open during servicing etc. Method
B connects the spare pole in series with the positive connection, thereby providing
two sets of contacts in the positive line as an added safety precaution.
When installing the battery cabinet remove the battery fuse in the UPS before
making the battery circuit breaker power connections.

Figure 2-6: Battery CB layout of switching poles

UPS

Half Potential Switching Method

UPS

Double Positive Pole Method

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CHAPTER 1 - Installation Procedure

Figure 2-7: Battery Control and Power connections

LM355A Sensor
TO BATTERIES 0835047F

UPS CABINET

123456 12 D2 X3 X4
X5 X2
V<
X6 X10
11 14 D1 X8
X3 X9
BATTERY Battery CB
CIRCUIT Controller
BREAKER
12 345

HALF POTENTIAL SWITCHING METHOD

TO BATTERIES
LM355A Sensor
0835047F

UPS CABINET

123456 12 D2 X3 X4
X5 X2
V< X6 X10
X3
14 D1
11 X8
X9
Battery CB
BATTERY
Controller
CIRCUIT
BREAKER 12 345

DOUBLE POSITIVE POLE METHOD

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 Section 2:

Chapter 2 - Commissioning Procedure

2.1 Introduction
The information contained in this calibration procedure is intended for use only
by engineers employed by the Liebert service organisation or who have attended
a training course concerning the Series 7200 equipment. While every precaution
has been taken to ensure the accuracy of this information, Liebert assume no re-
sponsibility and disclaim all liability for damages resulting from the use of this
information or any errors or omissions contained within.
This procedure aims at satisfying two functions: first it should enable a product-
trained engineer to commission the equipment safely and correctly; second, it
should provide a recovery procedure to supplement the procedures contained in
the troubleshooting section of this manual – i.e. if the troubleshooting procedures
fail to identify/rectify a problem then this procedure provides the means of com-
pletely recalibrating the UPS equipment.

WARNING The UPS equipment contains POTENTIALLY LETHAL VOLTAGES at all times
NOTICES once power has been applied from the MAINS DISTRIBUTION PANEL.
Therefore, before applying mains power to the UPS ensure that the UPS output
Please read.
cables are safely isolated or, If they have already been connected to the load
equipment, ensure the load equipment is ready to receive power.

DO NOT close the battery circuit breaker before instructed to do so. Closing the
battery circuit breaker before the DC busbar is live could damage the UPS.

DO NOT apply BOOST CHARGE to sealed batteries.

Before commencing this procedure confirm the location and operation of the ex-
ternal power isolators used to switch the UPS input mains supply. If these isola-
tors cannot be LOCKED OUT, then post notices warning against their closure.
These precautions should be taken as necessary at any time during the commis-
sioning procedure.

The 7200 Series UPS leaves the manufacturer fully tested and adjusted to operate
at 400Vac, 50Hz, but it can be converted to operate at 380V or 415V, at either 50
or 60Hz. Such a conversion is effected by selecting the appropriate tap voltages
on the control power supply transformers and operating parameters via the Oper-
ator Control Panel menuing system – details are provided at the appropriate stages
of this procedure. An additional procedure is included at the end of the chapter
(See paragraph 2.10) which provides instructions for changing the working volt-
age/frequency parameters on an already-commissioned module. In both cases,
where reference is made to the ‘nominal’ voltage, this should be taken as the re-
quired equipment working voltage – e.g. 380/400/415 volts.
A set of Commissioning Records are included at the end of this section which can
be used to record the parameters set during commissioning and handed to the cus-
tomer if required. The pages are published in a single-sided format to facilitate
photocopying for in-field use.

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SECTION 2 - Installation and Commissioning 7200 Series UPS Service Manual
CHAPTER 2 - Commissioning Procedure

Important Note: When commissioning a ‘1+1’ system we recommend that the system is split into
1+1 two single modules; and each module then commissioned independent of the
other. Once both modules are fully working as ‘single modules’ they can be
reconfigured for ‘1+1’ operation and the remaining ‘parallel control’ functions
checked and calibrated as instructed.
This commissioning procedure is therefore based on a ‘single-module’ installa-
tion, and any actions which specifically apply to ‘1+1’ systems are identified by
a “1+1” graphic in the margin – as shown here.
Note: if you are converting an early (pre Jan ‘97) single module to operate in a
‘1+1’ system then ensure the appropriate control boards are fitted prior to com-
mencing the commissioning (See Chapter 3). (Later models are shipped with the
appropriate boards already fitted).

2.2 Procedure overview

This procedure has several defineable stages:
1. Pre-commissioning checks verify that:
– the main equipment has been correctly installed
– the circuit board configuration links have been selected correctly
– the battery installation is satisfactory
– the control power transformers are wired for the required working voltage
2. Start-up and software commissioning:
– low voltage supply checks
– Operator Control Panel language selection
– UPS Setup parameters selection (from Operator Control Panel)
– UPS Maintenance parameters selection (from Operator Control Panel)
– UPS Function parameters selection (from Operator Control Panel)
3. UPS Power checks:
– UPS Power measurements
– inverter checks
– bypass checks
– rectifier and battery autonomy checks
– programming automatic battery check parameters
– emergency power off (emergency stop) checks
– battery boost set-up (if applicable)
– on generator checks (if applicable)

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Figure 2-8: Major component location

14
7

8
1

9
2

10

4530025T
11
3

4 12
4550007H

13
X1
4520075B
X2
X3

15

Table 2-2:
1. Battery Cable Connections 9. AC - AC Power Supply PCB 4503030M

2. UPS Output Cable Connections 10. Rectifier Logic PCB 4520074A

3. Static Bypass Input Cable Connections 11. Inverter Logic PCB 4530025T

4. Rectifier Input Cable Connections 12. UPS Logic PCB 4550007H

5. Main Chassis Safety Earth Connection 13. Remote Alarm Interface 4590056Q

6. Auxiliary Terminal Block X3 14. UPS Serial Number Tag

7. Control Power Transformers T2 & T3 15. 1+1 Parallel Option 4645004A

(consisting of Parallel Logic Board
8. DC - DC Power Supply 4503028K 4520075B & ribbon cables)

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2.3 Pre-commissioning Checks

WARNING Ensure these checks are carried out before applying power to the unit.

2.3.1 Power cable installation

1. Verify that the input, output and battery cables are suitably rated, in accord-
ance with local regulations – see notes on cable rating in paragraph 1.3.2.
2. Check that the power cables entering the UPS have been correctly routed and
the appropriate gland has been fitted to the power cable entry panel.
3. Check that the power cables are correctly terminated and securely fitted to the
stepped input and output busbar studs as shown in Figure 2-9.
4. Check that the bypass links have been removed if the unit is to be operated in
the ‘Split Bypass’ configuration. If a separate supply is connected to the
bypass terminals without the “split bypass” links removed it could cause dam-
age to the supply distribution system.
Important Note: 5. In a ‘1+1’ system ensure that the paralleled module output cables are con-
1+1 nected with the correct phasing (i.e. U2-U2; V2-V2; W2-W2; N2-N2).

Figure 2-9: Power cable connections

Bypass Links
These links must be removed
for split-bypass operation

Output Cables connected to load

Input cables for split-bypass system Battery

Connected to Q2/Q3 busbar connection U3, V3, W3 & N3 Cables
From Bypass Supply distribution panel

Bypass Supply Neutral connection (split-bypass system)

OR
Input Supply Neutral connection (non-split-bypass system)

UPS rectifier input connection from input mains supply:

For non-split-bypass system:
a) Connect to Q1 busbar connections U1,V1,W1.
b) Connect input neutral to Q2/Q3 busbar connection N3.
Note: an input neutral connection to N3 is not required in a split-bypass system
as the bypass neutral will be used to reference the inverter output.

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CHAPTER 2 - Commissioning Procedure

2.3.2 Control cable installation

1. Verify that the battery control cables are correctly terminated and connected
to the auxiliary terminal block (X3) shown in Figure 2-10 in accordance with
Table 2-3.
Note: terminal block X3 requires 4mm (yellow) female spade terminations.

Figure 2-10: Auxiliary terminal block X3

Batt CB trip
Battery E.P.O.
Temperature Batt CB Aux contact
Common

Table 2-3: Auxiliary terminal block connections

UPS Auxiliary
Terminal block Battery Control Board
Function
X3 (4520067T) termination
Termination
X3 - 2 Battery temperature X1 - 5
X3 - 3 sense signal X1 - 4
X3 - 4 Battery circuit breaker X1 - 3
control common
X3 - 5 Battery circuit breaker X1 - 2
status signal
X3 - 6 Battery circuit breaker X1 - 1
trip signal
X3 - 10 Remote Emergency Stop Terminals normally linked
X3 - 11 normally closed if not used

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Important Note: 2. In a ‘1+1’ system:

1+1 a) Ensure that the Parallel Logic Board Part Nº 4520075B is firmly fitted in
the correct location as shown in Figure 2-8.
b) Ensure that the 60 way ribbon cable is connected from X1 on the Parallel
Logic Board, to X7 on the UPS Logic Board.
c) Ensure that the two 34-way ribbon cables providing inter module control
are fitted between the Parallel Logic Board connector X2 of one module
and X3 in the second module (See Figure 2-11). Note that it is crucial that
these cables are cross-coupled between X2/X3 as shown. Failure to
observe this rule will result in the modules being permanently shut down.

Figure 2-11: Module parallel logic PCB interconnection

Module 1 Module 2

4520075B 4520075B

X2 X2
X3 X3

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2.3.3 Battery Power Cable Installation

1. Verify that the battery has been correctly installed and all cables are con-
nected to the batteries and battery circuit breaker as shown in the installation
instructions (see paragraph 1.4 on page 2-10). Typical connection configura-
tions are shown in Figure 2-12.
2. Verify that the battery power cables are correctly terminated and securely fit-
ted to the DC busbar studs as shown in Figure 2-9.

Figure 2-12: Battery control and power connections

Temperature Sensor
To Batteries

X3

Battery Circuit
Breaker

Half Potential Switching Method of Connection

Battery C.B.
Controller PCB Part
Nº 4520067T
To Batteries

Temperature
Double Positive Pole Method of Connection Sensor

X3

Battery Circuit
Breaker

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CHAPTER 2 - Commissioning Procedure

2.3.4 Printed circuit board configuration jumper selection

Ensure that the printed circuit board jumpers are selected appropriately according
to the following tables:
Table 2-4: Rectifier Logic Board – 4520074A. 30 to 60kVA

JUMPER POSITION FUNCTION

Disable battery temperature/voltage compensation

1-2
X5 (Standard)

2-3 Enable battery temperature/voltage compensation

1-2 Increased DC regulation speed for units below 60kVA
X6
2-3 Decreased DC regulation speed for units above 80kVA

1-2 Fast walk-in : 1 Second

X7
2-3 Slow walk-in : 5 Seconds
0-1 open
Rectifier in Auto mode (Standard)
0-2 open

0-1 closed
Rectifier in Float mode
0-2 open
Set Rectifier to
0-1 open Manual Mode
Rectifier in Boost mode
0-2 closed from the Dis-
play Panel
0-1 closed
X9 Rectifier in ‘Test’ mode
0-2 closed

closed Reduced input current limit forced on

0-3
open (Standard)

closed Rectifier forced on - Ignore UPS Logic

0-4
open UPS Logic control enabled (Standard)

open Disable driver IC - D6

0-5
closed Enable driver IC - D6 (Standard)

1-2 Enable rectifier temperature monitor

X10
2-3 Disable rectifier temperature monitor (Standard)

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Table 2-5: Inverter Logic Board 4530025T. 30 - 60kVA

JUMPER POSITION FUNCTION

Test Inverter over-temperature sensors (Enables open cct. sen-

0-1 open
sors)

0-1 closed Disable Inverter over-temperature sensors (Standard)

0-2 open Enable ribbon cable detector (Standard)

0-2 closed Disable ribbon cable detector

X12
0-3 Voltage select Manual inverter
closed
0-4 override volts Adj R243
Testing only
0-5 Frequency select override
Open = standard
0-6 Force the Inverter ON => ignore all blocks

0-7 Ignore Inverter ‘On Load’ signal

0-1 2400 Hz switching frequency (Standard)

0-2 4800 Hz switching frequency

X15 0-1
9600 Hz switching frequency
0-2

0-5 1200 Hz switching frequency

0-1
6 pulse Inverter current feedback (Standard)
X16 0-2

0-3 12 pulse Inverter current feedback

Table 2-6: UPS Logic Board 4550007H. 30 - 60kVA

Note: when commissioning a ‘1+1’ system these jumpers will required temporary
reconfiguration (See paragraph [Link])

JUMPER POSITION FUNCTION

open Pre- Release Rev.:5.0G Software

Link if Rev.:5.0G or later and HVI PCB Part Nº 5490054O is

1-2
X12 fitted.

Link if Rev.:5.0G 0r later and HVI PCB Part Nº 5490058S is

3-4
fitted.
1-2 EPROM Enable
X13
2-3 RAM Enable (Standard)

1-2 Not Required

3-4 Not Required Testing only
X14 normally
5-6 Not Required open
7-8 Not Required

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JUMPER POSITION FUNCTION

1-2 PLL option with CAP IN

X15
2-3 PLL option with FIN AUX (Standard)

open CAN Bus to display disabled

X16
1-2 CAN Bus to display enabled (Standard)

1-2 ALE enable data save

X17
2-3 Power supply fail enable data save (Standard)
1-2 EPROM II enable (not required)
X19
2-3 RAM II enable (not required)

+5V PCB enables microprocessor ref.

1-2
For VA calculations (Standard)
X20
V ref. enables microprocessor ref.
2-3
For VA calculations

1-2 Not Required

X21
2-3 RAM enable (Standard)

1-2 EPROM enable (Standard)

X22
2-3 Not Required

1-2 Not Required

2-3 EPROM enable (Standard)

X23
3-4 Not Required

4-5 Not Required

1-2 RAM enable (Standard)

2-3 EPROM enable (not required)
X24
3-4 RAM enable (Standard)

4-5 EPROM enable (not required)

1-2 Manual reset of output buffers
X25
2-3 Microprocessor reset of output buffers (Standard)

Inverter operation in ‘Manual’ mode

(Bypass preferred) = Closed
1-2
Inverter operation in ‘Auto’ mode
(Inverter Preferred) = Open (Standard)

Inverter Bad voltage for 10 seconds

X26 3-4 Off latch enabled = Closed (Standard)
Off latch disabled = Open

5-6 Not Required

Security Password Over-ride.

7-8 Closed = Over-ride security Password
Open = Enable security Password (standard)

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JUMPER POSITION FUNCTION

open Power up reset enabled (Standard)

X28
closed Power up reset disabled

open 2.5V power supply monitor enabled (Standard)

X29
1-2 2.5V power supply monitor disabled

open Internal battery disabled

X31
1-2 Internal battery installed and charger enabled (Standard)
open RS485 port disabled
X32
1-2 RS485 port enabled (Standard)

1-2 Calendar IC supply from VRAM (Standard)

X33
2-3 Calendar IC supply from internal battery

1-2 G.V.C.O. to inverter logic (parallel module operation)

X34
2-3 Micro V.C.O. to inverter logic (single module operation)

1-2 Separate battery per module (1 for each rectifier)

X35
2-3 Common battery (parallel rectifiers)

1-2 Separate battery per module (1 for each rectifier)

X36
2-3 Common battery (parallel rectifiers)

Table 2-7: Operator Control Board 4550005F 30-60 kVA

JUMPER POSITION FUNCTION

open +5v enable main CPU (Standard)

X11
closed ALE enable main CPU

1-2 Main CPU enable EPROM

X12
2-3 +5v enable EPROM (Standard)
1-2 Main CPU enable RAM
X13
2-3 +5v enable RAM (Standard)

1-2 Not Required Testing Only

X14
2-3 Not Required Open = Standard

1-2 Main CPU enable EPROM (Standard)

X15
2-3 Not Required

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JUMPER POSITION FUNCTION

1-2 Not Required

2-3 Main CPU enable EPROM (Standard)

x16
3-4 Not Required
4-5 Not Required

1-2 Write to RAM enable (Standard)

2-3 Not Required

x17
3-4 Main CPU enable RAM (Standard)

4-5 Not Required

1-2 Not Required

X18
2-3 Main CPU enable RAM (Standard)

1-2 Not Required RAM extension

x19
2-3 Not Required Normally open

1-2 Read/Write RS232 enable (Standard)

x20
2-3 Read/Write RS485enable

1-2 Enable port x4 for RS485

x21
2-3 Enable port x4 for RS232 (Standard)
1-2 Enable port x4 for RS485
x22
2-3 Enable port x4 for RS232 (Standard)

1-2 Inhibit buzzer

x23
2-3 Enable buzzer (Standard)

1-2 Enable CAN bus to UPS logic (Standard)

x24
2-3 Disable CAN bus to UPS logic

1-2 Enable RS485 bus to port x4 (Standard)

x25
2-3 Disable RS485 bus to port x4

open +5v power supply reset enabled (Standard)

x26
closed +5v power supply reset disabled

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Table 2-8: Static Switch Driver Board 4542043Z 30-60 kVA

JUMPER POSITION FUNCTION

Enable load on inverter command

0-1 open
(Standard)

0-1 closed Disable load on inverter command

Enable load on bypass command
0-2 open
(Standard)

0-2 closed Disable load on bypass command

X11
0-3 open Disables bypass fire command

0-3 closed Enable bypass fire command (Standard)

0-4 N/A Not used

0-5 open Test static switch temperature monitor

Inhibit static switch temperature monitor

0-5 closed
(Standard)

Table 2-9: High Voltage Interface Board 4590058S & (old 4590054O) 30-
60kVA

JUMPER POSITION FUNCTION

— 0-1
X31 0-2 30 kVA CT burden selec-
tion
X31 : X32 : X33 : X34 : X35 : X37 :
0-3
X38 : X39 : X40
— 0-1
40 kVA CT burden selec-
X31 : X32 : X33 : X34 0-2
tion
X35 : X36 : X37 : X38 : X39 : X40 0-3
— 0-1
— 0-2 60 kVA CT burden selec-
tion
X31: X32 : X33 : X34 : X35 : X36 :
0-3
X37 : X38 : X39 : X40

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CHAPTER 2 - Commissioning Procedure

Applicable only to: Table 2-10: Parallel Logic Board 4520075B

1+1
JUMPER POSITION FUNCTION
open Priority selector disabled
0-1
closed Priority selector enabled (standard 1+1)
X4
0-2 open Priority selector for ≥ 2 modules (multi
to module use only)
0-8 open = standard for 1+1

open Link combination sets logic for number

0-1
closed of units operating
X5 to
For 1+1 operation links 0 - 1, 0 - 2, 0 - 3
0-5
are closed.

open 1 + 1 redundant module (standard)

0-1
closed 1 + 1 non-redundant module

open Common battery for all UPS modules

0-2
closed Separate battery for each module (std)

open Priority selector enabled (std)

0-3
closed Priority selector disabled

open No MSSC installed (1 + 1) (std)

X6 0-4
closed MSSC installed

0-5 N/A

0-6 N/A

open No contactor in MSSC (std)

0-7
closed Contactor in MSSC

open Normal operation

0-8
closed Test mode active

1-2 60 Hz operation
X7
2-3 50 Hz operation (std)

open G.V.C.O. slew rate = 0.1 Hz/Sec (std)

X11
closed G.V.C.O. slew rate = 0.2 Hz/Sec

1-2 Parallel cable screen earthed

X13
2-3 Parallel cable screen not earthed (std)

2.3.5 Pre-power checks

1. Ensure that all the UPS isolators, including the battery circuit breaker, are
open – i.e. OFF or in position ‘0’.
2. Carry out a thorough visual examination of the equipment. Check the security
of all cable terminations and ensure that all electrical connectors, plugs and
sockets are correctly located and firmly fitted.
3. Ensure that the correct primary voltage tap selections are made on the Power
Supply transformers T2 and T3, as shown below.

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Table 2-11: Power supply transformers T2 and T3 voltage selection.

380V Operation 400V Operation 415V Operation

A3 - B A2 - B A1 - B

4. Ensure that on the UPS Logic Board (4550007H):

a) S1 is selected OFF (Static Bypass disabled).
b) S2 is selected OFF (Inverter disabled).
c) S3 is selected OFF (Rectifier disabled).

[Link] ‘1+1’ system module split

Only applicable to: As mentioned at the beginning of this chapter, it is recommended that when deal-
1+1 ing with a ‘1+1’ parallel-operating system each module is checked individually
for correct single module function before any attempt is made at parallel opera-
tion. To satisfy this requirement the system must therefore be temporarily re-con-
figured to allow single-module operation by completing the following steps:
1. Override the parallel control functions by disconnecting the ribbon cable
between the Parallel Logic Board (4520075B) connector X7 and connector
X1 of the UPS Logic Board (4550007H).
2. Reconfigure the UPS Logic Board (4550007H) jumpers for single module
operation as shown in the table below – note that a complete link table for
this board is shown in Table 2-6.

Table 2-12: Temporary UPS Logic Board configuration changes.

1-2 *Inverter operation in ‘Auto’ mode (Open = Standard)

Inverter Bad voltage for 10 seconds
3-4 *Off latch enabled = Closed (Standard)
Off latch disabled = Open
X26
5-6 Not Required
Security Password Override.
7-8 *Closed = Override security Password
Open = Enable security Password (standard)
1-2 G.V.C.O. to inverter logic (parallel module operation)
X34
2-3 *Micro V.C.O. to inverter logic (single module operation)
1-2 *Separate battery per module (1 for each rectifier)
X35
2-3 Common battery (parallel rectifiers)
1-2 *Separate battery per module (1 for each rectifier)
X36
2-3 Common battery (parallel rectifiers)

X34 must be in position 2-3 for single module operation.

X26 must be in position 7-8 to override the password security control.

WARNING These jumpers must be returned to the ‘1+1’ configuration before the system is
operated in parallel (as instructed later in the commissioning procedure).

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CHAPTER 2 - Commissioning Procedure

2.3.6 Initial utility power connection

WARNINGS Check that the Maintenance Bypass isolator Q3 is open before applying external
power. If Q3 is to be closed, inform the user that power will be connected to the
load when the input utility isolator is made.

When commissioning a ‘1+1’ system module do not close any power isolators in
the second module while the module being commissioned is turned on.

1. Apply mains voltage to the input terminals – U1, V1and W1.

a) Measure the line-to-line voltage of all three phases and ensure that the val-
ues are within ±10% of nominal rating.
b) Ensure correct clockwise phase rotation U, V, W using an oscilloscope or
rotation meter.

WARNING If a separate supply is connected to the bypass terminals without the “split by-
pass” links removed it could cause damage to the supply distribution system.

2. If a split bypass is fitted, first ensure that the Split Bypass links have been
removed (See Figure 2-9) then energise the (bypass) mains voltage to the
bypass terminals – U3, V3, W3 and N.
a) Measure the line-to-line and line-to-neutral voltages of all three phases
and ensure that values are within ±10% of nominal rating.
b) Ensure correct clockwise phase rotation U, V, W using an oscilloscope or
phase rotation meter.

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Section 2:

2.4 Start-Up and software commissioning

During this part of the commissioning procedure, the bypass supply is connected
to the unit in order to power-up the control power supplies. With control power
available, the control circuit boards are live and the programmable UPS operating
parameters can be entered into control system’s non-volatile RAM (NVRAM) via
the Operator Control Panel, before energising the UPS power sections.

2.4.1 Operator Control Panel display screen

The LCD screen can display four rows of up to twenty characters, and normally
indicates the UPS operating status, warnings and alarms. However, it can also be
selected to show messages associated with the UPS configuration setup menuing
system which allows operational data to be entered, or control parameters to be
set – these menus are shown in Figure 2-14 to Figure 2-27.

Figure 2-13: LCD control screen & selection buttons

When selecting an option, pressing the ENTER button steps forward to the
ENTER
next LCD Display screen in the menu map.
When entering data or selecting a parameter, pressing the ENTER button
saves the chosen parameter in non-volatile memory.

ESCAPE
Pressing ESCAPE will cancel the most recent action – i.e. when entering
data or selecting parameters, pressing ESC steps back the LCD display to
the previous screen and exits the current screen without saving the new set-
tings.
To return to the default screen ESC must be pressed repeatedly.

The MENU buttons allow the window cursor to be moved up and down to
select a desired menu option.
UP
The UP button moves the cursor up through the options displayed in the
window; the highlighted option can then be selected by pressing ENTER.
When selecting a parameter value it also moves a rectangular “entry” cursor
horizontally to the next digit on the right.
DOWN
The DOWN button moves the cursor down through the options displayed in
the window, the highlighted option can then be selected by pressing
ENTER.
When changing a parameter value the DOWN button will rotate through an
available value table for the specific parameter digit.

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CHAPTER 2 - Commissioning Procedure

Important Note: This procedure refers to Version 4.0 software installed in all units manufactured
after 2nd May 1997. Units manufactured before this date may have Version 2.0,
or earlier, software installed and will exhibit slightly different menu screens and
parameter locations.

2.4.2 Applying power to the UPS

WARNING Do not close the Output Isolator Q4 during the setting-up procedure as this will
connect power to the load.

1. Close the Bypass Isolator Q2.

a) The power supply and electronics will energise.
b) The Operator Control Panel display will power up.
c) The rectifier and inverter power sections will remain off.
2. On the Operator Control Panel, verify that the bypass LED and amber battery
isolator LED are illuminated.
3. Verify that the LCD control screen initialising window activates and then
changes to the ‘Default’ screen.
Note: the screen shown below is referred to as the default screen in the
remainder of this procedure.

OUTPUT BREAKER OPEN INT USCITA APPERTO

RECTIFIER BREAKER OPEN DEFAULT SCREEN INT RADDRIZZ APERTO
BYPASS INHIBIT BATTERIA PINE SCAR
24-09-95 [Link] 24-09-95 [Link]

The module status alarms are initially displayed on the default screen in the
default language, e.g. Italian.
Note: The first three lines of the default screen will indicate any current UPS
alarm conditions, but these can be ignored at this stage.

2.4.3 Password protection and operation

A password is required to change parameters other than those listed below:
• Time and Calendar
• ON/OFF UPS CONTROL (rectifier, inverter and bypass)
• Battery test (star, time/date stamp, repetition rate)
• Modem configuration and operation

You can completely override the password system during initial start-up and com-
missioning by connecting a link to jumper X26 pins 7-8 on the UPS Logic Board.
This link, which must be removed when commissioning is completed, can be
fitted while the UPS is in its Normal Operation mode without affecting the system
integrity.
Note: any parameter not re-programmed during the commissioning procedure
will maintain its factory default setting.

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2.4.4 Language Selection

If required, select the appropriate language using the following procedure:

Figure 2-14: Language selection menu map

MAIN MENU SCREEN

FUNCTION MENU SCREEN

PANEL SETUP MENU SCREEN

1. Ensure a jumper link is fitted to X26 pins 7-8 on the UPS Logic Board (over-
rides the password protection facility as described previously).
2. Press the ‘ENTER’ button to access the main menu screen.
3. Press the ‘DOWN’ menu button to scroll the cursor to ‘FUNCTION’.
MEASUREMENT → MISURE ←
→ FUNCTION ← MAIN MENU FUNZIONI
MAINTENANCE SCREEN MANUTENZIONE
SETUP IMPOSTAZIONE

4. Press the ‘ENTER’ button to access the password entry screen.

↑ WRITE SAVE ↵ ↑ IMPOSTA MEMOR. ↵

↓ MOVE EXIT ESC
PASSWORD ↓ SPOSTA USCITA ESC

INPUT PASSWORD SCREEN DIGITARE PASSWORD

00000000 00000000

5. A password must be entered to gain further access to the function menu. The
initial default password of ‘00000000’ need not be changed at this point in time
– instructions for changing the password are given later. (See paragraph
[Link]) .
6. Press the ‘ENTER’ button to move from the password entry screen to the func-
tion menu screen.
BATTERY TEST → TEST BATTERIA ←
GENERATOR FUNCTION MENU GRUPPO ELETTR.
→ PANEL SETUP ← SCREEN DATI PANNELIO
NEXT PAGE PAGINE SUCCESSIVE

7. Press the ‘DOWN’ menu button to select ‘PANEL SETUP’.

8. Press ‘ENTER’ to display the panel setup menu screen.

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9. On the panel setup menu move the cursor to select ‘LANGUAGE’.

→ LANGUAGE ENG ← → LINGUA ITA ←
TYPE 0000 MASTER PANEL SETUP TIPO 0001 MASTER
GROUP 1 UPS 1 MENU SCREEN GROPPO 1 UPS 1
PASSWORD 00000000 PASSWORD 00000000

[Link] ‘ENTER’ to display the language selection screen.

↑ ROTATE SAVE ↵ ↑ MEMOR. ↵
EXIT ESC LANGUAGE USCITA ESC

SELECTION
LANGUAGE ENG SCREEN LINGUA ITA

[Link] the ‘UP’ menu button to rotate through the available options and select the
required default language – e.g. ‘ITA, ENG, FRA, DEU, SPA’
[Link] ‘ENTER’ to accept and store the language selection, then step back to the
default screen by repeatedly pressing ‘ESC’, as required; the current alarms
should now be displayed in the selected language.

IMPORTANT Ensure the data entered during the following procedures are recorded in the
appropriate commissioning documentation.

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2.4.5 Selecting the UPS SETUP parameters

The following procedure set-up the basic UPS operating parameters – e.g. kVA,
working voltage/frequency and battery parameters.
Menu selection is carried out in the same manner as previously described in the
‘language selection’ procedure – i.e. by first selecting a menu option using the ‘UP’
and ‘DOWN’ menu buttons and then accepting the selection by pressing the ‘ENTER’
button. In the remaining procedures these two actions are jointly summarized as
‘select and enter’.

Figure 2-15: UPS system ‘SETUP’ menu map (Issue 5.0 software)

MAIN MENU SCREEN

UPS MENU
SCREEN

SETUP MENU
SCREEN

VOLTAGE
MENU
SCREEN

FREQUENCY
MENU
SCREEN

BATTERY
MENU
SCREEN

Continued in
Figure 2-16

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CHAPTER 2 - Commissioning Procedure

1. From the default screen press ‘ENTER’ to access the main menu screen.
2. Select and enter ‘SETUP’ – the password screen will now be shown.
3. If the password has been left at the initial default setting, pressing ‘ENTER’
will now step forward to the setup menu screen, as shown in Figure 2-15. If
the password has been “set”, then enter the correct password to continue.

[Link] Setting the basic UPS configuration

1. Select and enter ‘UPS’ – this will access the UPS menu screen.
2. Select and enter ‘POWER’.
3. Enter the UPS module’s kVA rating using the data entry screen shown below.
↑ WRITE SAVE ↵
↓ MOVE EXIT ESC

POWER 0060 kVA

a) Pressing the ‘DOWN’ menu button will move the cursor to select each digit
in turn: the value of the selected digit can then be incremented by pressing
the ‘UP’ menu button.
b) When the indicated kVA rating is correct, press ‘ ENTER’ to save the selec-
tion, then press ‘ESC’ once to move back to the UPS menu screen.
4. Select and enter ‘TYPE’.
a) Press the ‘UP’ menu button repeatedly until the ‘TYPE’ is shown as ‘3PH’.
b) Press ‘ENTER’ to save the selection, then press ‘ESC’ once to move back to
the UPS menu screen.
5. Select and enter ‘CONFIG’.
a) Using the data entry method described above enter the word ‘SINGLE’.
1+1 (Note: in a ‘1+1’ installation this will be changed to ‘PAR 1+1’ later).
b) Press ‘ENTER’ to save the selection, then press ‘ESC’ to move back to the
UPS menu screen.
6. Verify that the UPS menu screen data shows the correct:
– UPS kVA rating (shown as 60kVA in the example screen in Figure 2-15)
– UPS type (3 phase)
– UPS configuration (single)
Repeat this procedure if any data is incorrect.
7. Press ‘ESC’ again to move back to the setup menu screen.

[Link] Setting the UPS working voltage parameters

1. Select and enter ‘VOLTAGE’ – this will access the voltage menu screen.
2. Select and enter ‘RATED VOLTS.’.
a) Press the ‘UP’ menu button repeatedly until the appropriate input/output
working voltage is indicated.
b) Press ‘ENTER’ to save the selection and then press ‘ESC’ once to move back
to the voltage menu screen.

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3. Select and enter ‘LOWER’.

a) Using the data entry method described above, enter the required input and
output voltage undervoltage thresholds.
Note: Standard settings are for -10% (input) and -10% (output).
b) Press ‘ENTER’ to save the selection, then press ‘ESC’ once to move back to
the voltage menu screen.
4. Select and enter ‘UPPER’.
a) Using the data entry method described above, enter the required input and
output overvoltage thresholds.
Note: Standard settings are for +10% (input) and +10% (output).
b) Press ‘ENTER’ to save the selection, then press ‘ESC’ once to move back to
the voltage menu screen.
5. Verify that the data shown on the voltage menu screen is correct and repeat
this procedure if necessary.
6. Press ‘ESC’ again to move back to the setup menu screen.

[Link] Setting the UPS frequency parameters

1. Select and enter ‘FREQUENCY’ – this will access the frequency menu screen.
2. Select and enter ‘NOMINAL’.
a) Press the ‘UP’ menu button repeatedly until the desired nominal frequency
is indicated.
b) Press ‘ENTER’ to save the selection, then press ‘ESC’ once to move back to
the frequency menu screen.
3. Select and enter ‘SYNC WINDOW’.
a) Enter the required sync window limit.
Note: Standard setting is ‘2.0%’.
b) Press ‘ENTER’ to save the selection, then press ‘ESC’ once to move back to
the frequency menu screen.
4. Select and enter ‘SLEWRATE’.
a) Enter the required slew rate from the following selections.
0.1 Hz/sec
0.5 Hz/sec
1.0 Hz/sec
Note: Standard setting is ‘0.10 Hz/s’.
b) Press ‘ENTER’ to save the selection, then press ‘ESC’ once to move back to
the frequency menu screen.
5. Verify that the data shown on the frequency menu screen is correct and repeat
this procedure if necessary.
6. Press ‘ESC’ again to move back to the setup menu screen.

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SECTION 2 - Installation & Commissioning 7200 Series UPS Service Manual
CHAPTER 2 - Commissioning Procedure

[Link] Setting the Battery parameters

Figure 2-16: ‘SETUP’ menu map continued for battery parameter (Issue 5
Continued from
software)
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1. From the setup menu select and enter ‘[Link]’ – this will access the bat-
tery menu screen (illustrated in Figure 2-16).
Setting the number of cells:
2. From the battery menu screen, select and enter ‘[Link]’.
3. Following the data entry method described earlier, using the ‘UP’, ‘DOWN’
menu buttons, enter the number of cells contained in the battery string.
4. Press ‘ENTER’ to save the data to memory, then press ‘ESC’ once to return to
the battery menu screen.
Setting the Battery Capacity:
5. From the battery menu screen, select and enter ‘CAPACITY’.
6. Using the ‘UP’, ‘DOWN’ menu buttons, enter the total battery A/Hr capacity (at
the 10Hr rate C10).

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7. Press ‘ENTER’ to save the data to memory, then press ‘ESC’ once to return to
the battery menu screen.
Setting the battery voltage characteristics:
8. From the battery menu screen, select and enter ‘ VOLTAGE’ – this will take you
to the battery voltage menu, which is concerned with selecting the battery
charging characteristics.

Battery undervoltage trip setting

9. From the battery voltage menu, select and enter ‘END DIS.’.
a) Using the ‘UP’, ‘DOWN’ menu buttons, enter the specified ‘end-of-dis-
charge’ voltage – standard setting is 1.67V/cell.
Note: this is the ‘end-of-discharge’ voltage and is the voltage at which the
battery breaker is tripped.
b) Press ‘ENTER’ to save the data to memory, then press ‘ESC’ once to return to
the battery voltage menu screen.

Battery low voltage warning setting

[Link] the battery voltage menu, select and enter ‘BAT LOW’.
a) Using the ‘UP’, ‘DOWN’ menu buttons, enter the specified ‘low battery volt-
age’ – standard setting is 1.82V/cell.
Note: this is the voltage at which ‘low-battery warning’ annunciates.
b) Press ‘ENTER’ to save the data to memory, then press ‘ESC’ once to return to
the battery voltage menu screen.

Battery overvoltage trip setting

[Link] the battery voltage menu, select and enter ‘MAX’.
a) Using the ‘UP’, ‘DOWN’ menu buttons, enter the specified ‘max battery
voltage’ – standard setting is 2.45V/cell. This sets the ‘slow’ overvoltage
level which is effective only when the batteries are in the float charge
mode, and is the voltage at which, after 3 minutes, the battery breaker is
tripped, and the rectifier and inverter turned OFF.
b) Press ‘ENTER’ to save the data to memory, then press ‘ESC’ once to return to
the battery voltage menu screen.

Battery boost charge values

WARNING DO NOT apply BOOST CHARGE to sealed batteries

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SECTION 2 - Installation & Commissioning 7200 Series UPS Service Manual
CHAPTER 2 - Commissioning Procedure

Figure 2-17: Battery boost charge parameters

Continued from
BATTERY VOLTAGE MENU SCREEN
Figure 2-16
BATTERY BOOST MENU SCREEN

BATTERY BOOST SETUP

MENU SCREEN

[Link] the battery voltage menu, select and enter ‘BOOST CHARGE’ – this will
take you to the boost charge menu screen.
[Link] the boost charge menu, select and enter ‘SETUP’ – this will take you to
the battery boost setup menu screen.
[Link] the battery boost setup menu, select and enter ‘DURATION’.
a) Using the ‘UP’, ‘DOWN’ menu buttons, enter the required boost operation
time (in minutes) – factory setting is 600 mins.
b) Press ‘ENTER’ to save the data to memory, then press ‘ESC’ once to return to
the battery boost setup menu screen.
[Link] the battery boost setup menu, select and enter ‘THRESHOLD’.
a) Using the ‘UP’, ‘DOWN’ menu buttons, enter the required current change-
over threshold – factory setting is 20% of the battery current limit.
Note: this is the level that the battery current must reach before boost
charge is enabled upon mains return.
b) Press ‘ENTER’ to save the data to memory, then press ‘ESC’ once to return to
the battery boost setup menu screen.
[Link] is advisable to set the ‘NOW’ and ‘AUTOMATIC’ parameters to ‘NO’ at this
stage in the commissioning, and reset to ‘YES’ (if required) once the rectifier
has been fully commissioned.
Verification:
[Link] ‘ENTER’ to save the data to memory, then press ‘ESC’ once to return to
the battery voltage menu screen.
[Link] that the data shown on the battery voltage menu screen is correct and
repeat this procedure if necessary.
[Link] setup menu parameters have now all been entered and stored in the con-
trol system’s non-volatile memory. Press ‘ENTER’ repeatedly to return to the
default menu

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2.4.6 Selecting the UPS MAINTENANCE parameters

Figure 2-18: ‘MAINTENANCE’ menu map

MAIN MENU SCREEN DEFAULT SCREEN

MAINTENANCE MENU
SCREEN

The UPS serial number, service information, and current time and date are all en-
tered via the maintenance menu map shown in Figure 2-18.

[Link] Accessing the maintenance menu

1. From the default screen press ‘ENTER’ to access the main menu screen.
2. Select and enter ‘MAINTENANCE’ – the password screen will now be shown.
3. If the password has been left at the initial default setting, pressing ‘ENTER’
will now step forward to the maintenance menu screen, shown in Figure 2-18.
If the password has been “set”, then enter the correct password to continue.

[Link] Entering the Serial Number

1. From the maintenance menu screen, select and enter ‘S.N.’
Note: The UPS serial number can be found stamped on a circular metal plate
attached to the top of the unit, behind the left hand door.
2. Using the ‘UP’ and ‘DOWN’ menu buttons, enter the UPS serial number.
3. Press ‘ENTER’ to save the settings, then press ‘ESC’ once to return to the main-
tenance menu screen.

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[Link] Entering the current Date and Time

1. From the maintenance menu screen, select and enter the line showing the
time and date. (This may initially indicate all zeroes).
2. Using the ‘UP’ and ‘DOWN’ menu buttons, enter the current time and date
information.
3. Press ‘ENTER’ to save the settings, then press ‘ESC’ once to return to the main-
tenance menu screen.

[Link] Entering the Service details

1. From the maintenance menu screen, select and enter ‘LAST SER.’ to register the
date of the current service or commissioning.
2. Using the ‘UP’ and ‘DOWN’ menu buttons, enter the current time and date
information.
3. Press ‘ENTER’ to save the settings, then press ‘ESC’ once to return to the main-
tenance menu screen.
4. Select and enter ‘NEXT SER.’ to record the date of the anticipated next service.
5. Using the ‘UP’ and ‘DOWN’ menu buttons, enter the current time and date
information.
6. Press ‘ENTER’ to save the settings, then press ‘ESC’ once to return to the main-
tenance menu screen.
7. Verify that the data shown on the maintenance menu screen is correct and
repeat this procedure if necessary. Then press ‘ESC’ repeatedly to step back to
the default menu screen.
8. The maintenance menu parameters have now all been entered and stored in
the control system’s non-volatile memory.

2.4.7 Selecting the UPS FUNCTION parameters

The function menu screens, shown in Figure 2-19 and Figure 2-20, enable certain
parameters to be set and also gives access to various software-initiated functional
checks.
The procedures contained in this section are concerned with parameter setting; the
‘functional checks’ facilities are used later in the commissioning procedure,
during the power checks.

[Link] Accessing the function menu

1. From the default screen press ‘ENTER’ to access the main menu screen.
2. Select and enter ‘FUNCTION’ – the password screen will now be shown – if the
password has been left at the initial default setting, pressing ‘ENTER’ will now
step forward to the main menu screen. If the password has been “set”, then
enter the correct password to continue.
3. From the main menu, select and enter ‘FUNCTION’ to access the function menu
screen.

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Figure 2-19: ‘FUNCTION’ selection menu map(Issue 5 software

BATTERY TEST MENU SCREEN

FUNCTION MENU
SCREEN

BATTERY TEST SETUP

MENU SCREEN

GENERATOR
MENU
SCREEN

PANEL
SETUP
MENU
SCREEN

Continued in Figure 2-20

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4. From the default screen press ‘ENTER’ to display the option selection screen.
5. Select and enter ‘FUNCTION’.
6. The password screen will now be shown.
7. If the password has not yet been set, pressing ‘ ENTER’ will step forward to the
maintenance selection screen shown in Figure 2-19.

[Link] Setting the Battery Test parameters

1. From the function menu screen, select and enter ‘BATTERY TEST’ to access the
battery test menu.
2. Three selections are available: ‘NOW’, ‘AUTOMATIC’ and ‘SETUP’.
‘NOW’ Selection: When ‘NOW’ is set to ‘YES’, it initiates an immediate battery
test by switching off the UPS rectifier section. This is not required at this time but
is used later in the commissioning during the “power checks”.
3. From the battery test menu, select and enter ‘NOW’.
4. Press ‘ENTER’ to step to the selection screen and, using the ‘UP’ menu button,
select NO (‘N’).
5. Press ‘ENTER’ to save the settings, then press ‘ESC’ to return to the battery test
menu screen.
‘AUTOMATIC’ Selection: ‘AUTOMATIC’ initiates a battery test cycle at a pre-
defined set time and date (as entered in the setup selection menu below).
6. From the battery test menu, select and enter ‘AUTOMATIC’.
7. If an automatic battery test function is required, press ‘ENTER’ to step to the
selection screen and, using the ‘UP’ menu button, select YES (‘Y’).
8. Press ‘ENTER’ to save the settings, then press ‘ESC’ to return to the battery test
menu screen.
SETUP Selection: ‘SETUP’ allows the parameters to be set for the automatic
testing cycle (see above).
9. From the battery test menu, select and enter ‘SETUP’ to access the battery test
setup menu screen.
[Link] the battery test setup menu select and enter ‘DURATION’.
[Link] the ‘UP’ and ‘DOWN’ menu buttons, enter the test ‘DURATION’ time in
minutes. (This would normally be set to 5 minutes).
[Link] ‘ENTER’ to save the settings, then press ‘ESC’ to return to the battery test
setup menu screen.
[Link] the battery test setup menu select and enter ‘THRESHOLD’.
[Link] the ‘UP’ and ‘DOWN’ menu buttons, enter the minimum battery test volt-
age ‘THRESHOLD’ level. (This would normally be set to 1.9V/Cell).
[Link] ‘ENTER’ to save the settings, then press ‘ESC’ to return to the battery test
setup menu screen.
[Link] the battery test setup menu select and enter ‘PERIOD’.

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[Link] the ‘UP’ and ‘DOWN’ menu buttons, enter the ‘PERIOD’ (in days) at which
the test is to occur in days.(This would normally be set to 90 days).
[Link] ‘ENTER’ to save the settings, then press ‘ESC’ to return to the battery test
setup menu screen.
Note: Once the first Automatic Battery test has been actioned, the time and
date will up-date according to the selected period. This will change on the
display to indicate when the next battery test will be carried out.
Verification:
[Link] that the data shown on the battery test setup menu screen is correct and
repeat this procedure if necessary.
[Link] back to the battery test menu screen by pressing ‘ESC’.
[Link] that the data shown on the battery test menu screen is correct and
repeat this procedure if necessary.
[Link] back to the function menu screen by pressing ‘ESC’.

[Link] Setting the Generator parameters

1. From the function menu screen, select and enter ‘GENERATOR’ to access the
generator menu screen.
2. Three selections are available: ‘INV: SYNC INHIBIT’, ‘RECT: I INHIBIT’ and
‘BAT: I INHIBIT’.
Note: These features require external control input via the Remote Alarms
Board in order to become active.
INV: SYNC INHIBIT Selection: This disables synchronisation between the
UPS and generator when the generator is on-line. When selected, it helps to over-
come “Sync Error” problems occurring when running on a generator whose fre-
quency is unstable.
3. From the generator menu screen, select and enter ‘INV: SYNC INHIBIT’.
4. Using the ‘UP’ menu button, set the attribute to YES ‘Y’ or NO ‘N’ as required.
5. Press ‘ENTER’ to save the settings, then press ‘ESC’ to return to the generator
menu screen.
BAT: I INHIBIT Selection: This restricts the maximum charge current to the
batteries when the generator is on-line and is used if the generator power output
is limited.
6. From the generator menu screen, select and enter ‘BAT: I INHIBIT’.
7. Using the ‘UP’ menu button, set the attribute to YES ‘Y’ or NO ‘N’ as required.
8. Press ‘ENTER’ to save the settings, then press ‘ESC’ to return to the generator
menu screen.
RECT: I INHIBIT Selection: This reduces the maximum UPS input current
by 30% of the standard factory-set current limit when the generator is on-line.
This facility is used if the generator power output is limited.
9. From the generator menu screen, select and enter ‘RECT: I INHIBIT’.
[Link] the ‘UP’ menu button, set the attribute to YES ‘Y’ or NO ‘N’ as required.

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[Link] ‘ENTER’ to save the settings, then press ‘ESC’ to return to the generator
menu screen.
Verification:
[Link] that the data shown on the generator menu screen is correct and repeat
this procedure if necessary.
[Link] back to the function menu screen by pressing ‘ESC’.

[Link] Setting the Panel Setup selections

1. From the function menu screen, select and enter ‘PANEL SETUP’ to access the
panel setup menu screen.
2. Four selections are available: ‘ LANGUAGE’, ‘TYPE (STATE)’, ‘GROUP’ and
‘PASSWORD’.

TYPE & STATE Selection: These parameters register the equipment type
number and Master/Slave paralleling configuration.
3. From the panel setup menu screen, select and enter ‘TYPE’ _(‘STATE’).
Note: The first selection, ‘LANGUAGE’, was completed earlier in this procedure
– (See paragraph 2.4.4) .
4. Using the ‘UP’ and ‘DOWN’ menu buttons:
a) Enter the ‘TYPE’ of UPS system – in this case enter ‘7200’.
b) Enter the UPS system ‘STATE’ – in the case of a “single module” system
enter the word ‘MASTER’.
5. Press ‘ENTER’ to save the settings, then press ‘ESC’ to return to the panel setup
menu screen.

GROUP & UPS Selection: This selection sets the communications address
for the UPS Module.
6. From the panel setup menu screen, select and enter ‘GROUP’ _ ‘UPS’.
7. Using the ‘UP’ and ‘DOWN’ menu buttons:
a) Enter the ‘UPS’ address – in the case of a “single module” system enter ‘1’
unless instructed otherwise.
b) Enter the ‘NODE’ address – in the case of a “single module” system enter
‘1’ unless instructed otherwise.
8. Press ‘ENTER’ to save the settings, then press ‘ESC’ to return to the panel setup
menu screen.

PASSWORD Selection: This selection sets the password which will give re-
stricted entry to certain screens once set – i.e. access to a password protected
screen is possible but no data can be entered or changed. Until now, the default
password (00000000) has been used.
9. From the panel setup menu screen, select and enter ‘PASSWORD’.

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Figure 2-20: ‘FUNCTION’ selection menu map ‘NEXT PAGE’ selections

Continued from
Figure 2-19
FUNCTION MENU SCREEN

MODEM MENU
SCREEN

NEXT PAGE MENU

SCREEN

ON/OFF
MENU
SCREEN

When selected to ‘YES’ and saved, all UPS

parameters are reset to zero. The parame-
ter values will then require
re-entering into the software

Important Once the eight digit password has been selected and saved into the NVRAM fur-
ther changes to the UPS parameters will be inhibited unless the correct password
is entered. ENSURE THE NEW PASSWORD IS SAFELY RECORDED IN THE
RELEVANT COMMISSIONING OR SERVICE DOCUMENTATION.

[Link] the ‘UP’ and ‘DOWN’ menu buttons enter an 8-digit password.
[Link] ‘ENTER’ to save the settings, then press ‘ESC’ to return to the panel setup
menu screen.

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Verification:
[Link] that the data shown on the panel setup menu screen is correct and
repeat this procedure if necessary.
[Link] back to the function menu screen by pressing ‘ESC’.

[Link] Setting the NEXT PAGE selections

1. From the function menu screen select and enter ‘NEXT PAGE’ – this accesses
the next page menu screen (See Figure 2-20).
2. Three selections are available: ‘PC-CONN’, ‘ON/OFF UPS’, ‘RELOAD UPS DATA’.
‘PC-CONN’ Setting: This establishes the UPS software settings to interface
via a modem to a remote location.
1. From the next page menu screen select and enter ‘MODEM CONNECTION ’ to
access the modem menu screen.
2. From the modem menu screen, select and enter ‘PC-CONN.’.
3. Select either ‘LOCAL’ or ‘REMOTE’ modem connection as appropriate.
4. Press ‘ENTER’ to save the settings, then press ‘ESC’ to return to the modem
menu screen.
5. From the modem menu screen, select and enter ‘RESET’.
6. Select either ‘NO’ or ‘YES’ as appropriate.
Note: Selecting ‘YES’ will enable any alarm to be reset from a connected PC.
7. Press ‘ENTER’ to save the settings, then press ‘ESC’ to return to the modem
menu screen.
8. Verify that the data shown on the modem menu screen is correct and repeat
this procedure if necessary.
9. Step back to the next page menu screen by pressing ‘ESC’.
‘ON/OFF UPS CONTROL’ Setting: The on/off menu screen allows the
UPS inverter, static bypass line, and rectifier sections to be switched on or off
from the control panel and will be covered in the power checks.
‘RELOAD UPS DATA’ Setting : Setting this option to YES resets the micro-
processor NVRAM to the default parameters and should be carried out only if a
complete reprogramming sequence is required.

WARNING DO NOT enter a ‘RELOAD UPS DATA’ selection while the UPS is on load, as it
will disable the inverter, rectifier and bypass sections, and remove load power.

[Link] the next page menu screen select and enter ‘RELOAD UPS DATA’. and if
you wish to reset the stored data to the default parameters select ‘YES’.
[Link] the setup menu screen locate and enter the ‘POWER’ screen and Re-enter
the units KVA rating.
[Link] the UPS off for 5 seconds then turn it back on
[Link] back to the default screen by repeatedly pressing ‘ESC’. The UPS func-
tion menu parameters have now all been stored in NVRAM

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Section 2: 1

2.5 Power checks

Once the UPS parameters have been entered into the software, full power can be
applied to the unit and the following power checks carried out.

WARNING Ensure that the load is isolated or safe to receive power, before continuing with
the following procedure

2.5.1 Applying power to the UPS

1. Check that the Bypass Isolator Q2 is still closed – close Q2 if it is open.
a) Verify that the LCD shows the default screen.
b) Verify that the Amber ‘Load on Bypass’ LED is flashing.
2. Close the UPS Input Isolator Q1.
a) Verify that after approximately 30 seconds the Green ‘Load on Inverter’
LED illuminates and the ‘Load on Bypass’ LED extinguishes.
b) The LCD default screen indication should be:
BATTERY BREAKER OPEN
OUTPUT SWITCH OPEN
DEFAULT SCREEN

24-09-95 [Link]

3. Close the Output Isolator Q4.

4. Close the Battery Circuit Breaker (located in the battery cabinet or adjacent to
any external battery racks).
a) The LCD default screen indication should be:

NORMAL OPERATION
DEFAULT SCREEN

24-09-95 [Link]

2.5.2 Monitoring & recording the UPS operating parameters

5. Using the menu screen navigation techniques described earlier in this section,
access the main menu screen and then access the measurement menu screen –
a menu map is shown in Figure 2-21.
6. From the measurement menu screen select and enter ‘INPUT’ then note and
record indicated input voltage in the appropriate commissioning documenta-
tion.
7. From the measurement menu screen select and enter ‘BATTERY’ then note and
record in the appropriate commissioning documentation the battery voltage,
current, and percentage charge.
8. From the measurement menu screen select and enter ‘TEMPERATURE’ then note
and record the indicated temperatures in the appropriate commissioning doc-
umentation:

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Figure 2-21: Menu tree for the MEASUREMENT parameters (Issue 5 software)

INITIALISATION
SCREEN
MAIN MENU SCREEN
DEFAULT MENU SCREENS

MEASUREMENT MENU
SCREEN

9. From the measurement menu screen select and enter ‘OUTPUT’ then further
select and record in the appropriate commissioning documentation:
– output voltage
– output current
– output power
– output frequency.

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Figure 2-22: Menu tree for the ‘FUNCTON’- ‘NEXT PAGE’ test selections
Continued from
Figure 2-19 FUNCTION MENU SCREEN

MODEM MENU
SCREEN

NEXT PAGE MENU

SCREEN

ON/OFF
MENU
SCREEN

[Link] back to the default screen by repeatedly pressing the ‘ESC’ button.

2.5.3 Power module ON/OFF functional checks

The UPS power sections can be independently switched off and on from the Op-
erator Control Panel, as checked below, which enables each section to be tested
individually.

[Link] Accessing the ON/OFF menu screen

The following functional checks are carried out from the ON/OFF menu screen.
To gain access to this screen:

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1. Using the menu navigation methods described previously, step from the
default screen via the main menu screen (‘FUNCTION’), password screen, func-
tion menu screen (‘NEXT PAGE’) and next page menu screen (‘ON/OFF UPS CON-
TROL’) to the ON/OFF menu screen.
Refer to the menu maps in Figure 2-18, Figure 2-19 and Figure 2-22 for
assistance if necessary.

[Link] Inverter test

1. Gain access to the ON/OFF menu screen (See paragraph [Link]).
2. From the ON/OFF menu screen, select and enter ‘INVERTER’.
3. Using the ‘UP’ menu button, select ‘INVERTER OFF’, then press ‘ENTER’ to save
the selection.
4. On the UPS mimic, verify that the inverter has turned off and the load has
transferred to the static bypass supply.
a) The green ‘Load on Inverter’ LED is extinguished and the amber ‘Load on
Bypass’ LED is flashing.
5. Step back to the default screen, by continually pressing the ‘ESC’ button, and
verify that:
a) The ‘INV: OFF VIA DISPLAY’ and ‘LOAD ON BYPASS’ alarms are present.
6. Repeat steps 1 and 2 to return to the ON/OFF menu inverter selection screen.
then select ‘INVERTER ON’ and press ‘ENTER’ to save the selection.
7. On the UPS mimic, verify that the inverter has turned on and the load has
transferred back to the inverter from the static bypass supply.
a) The green ‘load-on-inverter’ LED is illuminated and the amber ‘load-on-
bypass’ LED is extinguished.
8. Step back to the default screen, by continually pressing the ‘ESC’ button, and
verify that:
a) The ‘NORMAL OPERATION’ status indication is present.

[Link] Bypass test

1. Gain access to the ON/OFF menu screen (See paragraph [Link]).
2. From the ON/OFF menu screen, select and enter ‘LINE’.
3. Using the ‘UP’ menu button, select ‘BYPASS OFF’, then press ‘ENTER’ to save the
selection.
4. Step back to the default screen, by continually pressing the ‘ESC’ button, and
verify that the ‘BYP: OFF VIA DISPLAY’ (bypass remotely inhibited), is displayed.
5. Repeat steps 1 and 2 to return to the ON/OFF menu line selection screen. then
select ‘BYPASS ON’ and press ‘ENTER’ to save the selection.
6. Step back to the default screen, by continually pressing the ‘ESC’ button, and
verify that the ‘NORMAL OPERATION’ status indication is present.

[Link] Rectifier and battery autonomy test

1. Gain access to the ON/OFF menu screen (See paragraph [Link]).

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2. From the ON/OFF menu screen, select and enter ‘RECTIFIER’.

3. Using the ‘UP’ menu button, select ‘RECTIFIER OFF’, then press ‘ENTER’ to save
the selection.
4. Verify that the rectifier has turned off and the inverter is still operating from
battery power.
5. Step back to the default screen, by continually pressing the ‘ESC’ button, and
verify that:
a) The ‘RECT: OFF VIA DISPLAY’ and ‘ON BATTERY’ alarms are present.
b) The green battery bargraph LEDs indicate the remaining battery time.
Note: If the UPS is allowed to run in this condition the battery bargraph
LED’s will progressively turn off indicating the remaining autonomy time.
6. Step forward to the measurements menu screen (See paragraph 2.5.2), then
enter and select ‘BATTERY’, and note and record the indicated remaining
autonomy time. Each illuminate bar-graph segment is equivalent to 2 minutes
remaining. All 5 will be illuminated for greater than 10 minutes.
7. Step back to the default screen, by continually pressing the ‘ESC’ button.
8. Repeat steps 1 and 2 to return to the ON/OFF menu rectifier selection screen.
then select ‘RECTIFER ON’ and press ‘ENTER’ to save the selection.
9. Verify that the rectifier turns on.
[Link] back to the default screen, by continually pressing the ‘ESC’ button, and
verify that the ‘NORMAL OPERATION’ status indication is present.
[Link] forward to the measurements menu screen (See paragraph 2.5.2), then
enter and select ‘BATTERY’, and note and record the indicated capacity charge.
[Link] back to the default screen, by continually pressing the ‘ESC’ button.

2.5.4 Battery test

A software-controlled battery test facility can be initiated from the Operator Con-
trol Panel on an “immediate” or “periodic” basis. This test turns off the rectifier
and runs the inverter (and load) from the battery for a predetermined period. If the
battery voltage falls below a preset minimum level prior to the termination of the
test period a ‘BATTERY FAIL’ alarm is annunciated and the rectifier is immediately
turned on to prevent the load transferring to bypass – and recharge the battery.
The instructions given below initiates an immediate battery test.
For the following test to be ‘meaningful’ as part of the UPS commissioning pro-
cedure, the batteries should be fully charged prior to the test being carried out. The
UPS rectifier section must therefore be allowed to operate with the battery con-
nected for several hours to provide the battery with an adequate initial charge.

Caution Do not continue with this procedure if the battery has not yet been charged

1. Using the menu navigation methods described previously, step from the
default screen via the main menu screen (‘FUNCTION’), password screen, func-
tion menu screen (‘BATTERY TEST’) to the battery test menu screen.
Refer to the menu map in Figure 2-23 for assistance if necessary.
2. From the battery test menu screen, select and enter ‘SETUP’.

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Figure 2-23: Menu tree for the ‘FUNCTON’- ‘BATTERY TEST’ selections (Issue 5 software)

BATTERY TEST MENU SCREEN

FUNCTION MENU
SCREEN

BATTERY TEST SETUP

MENU SCREEN

Date & Time of

NEXT periodic test

3. Verify that the parameters entered in the battery test setup menu are appropri-
ate. If not then enter the correct setup parameters (See paragraph [Link]).
4. Press ‘ESC’ to return to the battery test menu screen.
5. From the battery test menu screen, select and enter ‘NOW’.
6. Using the ‘UP’ menu button, select Yes (‘Y’), then press ‘ENTER’ to initiate an
‘immediate’ battery test.
7. Verify that the rectifier enters the test mode by confirming that LED H1
(Amber) is illuminated on the Rectifier Logic Board. (The inverter will con-
tinue its operation and discharge the battery.)
8. Step back to the default screen, by continually pressing the ‘ESC’ button and
verify that the ‘ON BATTERY’ and ‘RECT: SOFTWARE BLOCK’ alarms are displayed.
The green LED battery bargraph will indicate the remaining battery time.
Note: If the UPS is allowed to run in this condition the battery bargraph
LED’s will progressively turn off indicating the remaining autonomy time.
9. The battery will be tested for the selected ‘DURATION’ time after which the
UPS will revert to normal operation.
– the rectifier will return to the Float mode.
– LED H3 (green) will be illuminated on the Rectifier Logic Board.
Note: If the battery fails the test (i.e. falls below the ‘THRESHOLD’ value before
the ‘DURATION’ time expires), the rectifier will immediately return to the float

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mode and the ‘BATTERY FAIL’ alarm will be displayed on the default screen.
This alarm can be reset by pressing the ‘RESET’ Button (S1) on the UPS Logic
Board.

2.5.5 Emergency remote power off check

1. Ensure that ‘NORMAL OPERATION’ is displayed on the default screen.
2. Remove the link between terminals 10 & 11 on the Auxiliary Terminal Block
(X3) (See Figure 2-10). Or open the remote EPO button if installed.
3. Verify that the UPS power sections shut down and ‘CUT-OFF: EMERGENCY’ is
displayed on the default screen.
4. Refit the link between terminals 10 & 11 on the Auxiliary Terminal Block
(X3) (See Figure 2-10). Or close the remote EPO button if installed.
5. Press the Reset Button (S1) on the UPS Logic Board.
6. Verify that the UPS returns to normal operation – ‘NORMAL OPERATION’ dis-
played on the default screen.

Figure 2-24: Menu tree for the ‘SETUP’- ‘BATTERY’ selection

Continued from
Figure 2-16 BATTERY VOLTAGE MENU SCREEN
BATTERY BOOST MENU SCREEN

BATTERY BOOST SETUP

MENU SCREEN

2.5.6 Battery boost test (if applicable)

A software-controlled battery boost facility can be initiated from the Operator
Control Panel on an ‘immediate’ or ‘periodic’ basis. This increases the rectifier
output (dc bus) to the selected boost voltage level for a predetermined period.
The instructions given below initiates an immediate battery boost charge.

WARNING DO NOT APPLY BOOST CHARGE TO SEALED BATTERIES

1. Using the menu navigation methods described previously, step from the
default screen via the main menu screen (‘SETUP’), password screen, setup
menu screen (‘BATTERY’) to the battery menu screen.
Refer to Figure 2-15 and Figure 2-16 for assistance if necessary.

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2. From the battery menu screen select and enter ‘VOLTAGE’ to access the battery
voltage menu screen.
3. From the battery voltage menu screen select and enter ‘BOOST CHARGE’ to
access the battery boost menu screen.
Note: The boost parameters (accessed via ‘SETUP’) were entered earlier in this
procedure (see page 2-37). These may reviewed here if required.
4. From battery boost menu screen, select and enter ‘NOW’.
5. Using the ‘UP’ menu button, select Yes (‘Y’), then press ‘ENTER’ to save the
selection, followed by ‘ESC’ to return to the battery boost menu screen.
6. The rectifier should now be in its boost charge mode.
a) Verify that the boost charge indicator LED H2 (green) is illuminated on
the Rectifier Logic Board.
b) Step back to the main menu screen and then access the measurement menu
screen (See Figure 2-21). Verify that the battery voltage has increased to
the appropriate boost charge level.
7. The rectifier will revert to its float charge mode (LED H3 illuminated and
LED H2 extinguished on the Rectifier Logic Board) in the event of:
a) The selected ‘DURATION’ time being reached.
b) The battery charge current falling below the boost ‘THRESHOLD’ current
prior to the completion of the boost ‘DURATION’ time.
c) Manual intervention turning OFF the boost charge facility.
Note: this is achieved by changing the ‘NOW’ parameter to No (‘N’) in the
battery boost menu screen (see steps 6 & 7 above).
8. Step back to the default screen, by continually pressing the ‘ESC’ button.

2.5.7 On-Generator test (if applicable)

The following test checks the operation of the generator parameters set-up earlier
(See paragraph [Link]) in the generator menu screen (See Figure 2-19).
The test is unnecessary if the generator parameters have not been selected – i.e.
the function parameters for the ‘GENERATOR’ options must be selected to Yes (‘Y’).
Any combination of the three functions can be selected.
1. To initiate this test, the generator must apply a voltage in the range 12-24Volts
(ac or dc) between pins 5 and 6 of the Alarm Interface Board terminal block
X5 when the generator is operating.
2. Start the generator.
3. On the default screen, check for the following alarms:
a) ‘INV: UNSYNCHRONIZED’
The UPS will not synchronise to the unstable generator supply
b) ‘CHARGER INHIBITED’
The battery current is inhibited due to the generator power being limited.
c) ‘REDUCED CURRENT LIMIT’
The rectifier current is inhibited due to the generator power being limited.
4. Stop the generator

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5. Verify that ‘NORMAL OPERATION’ is displayed on the default screen.

2.6 Commissioning conclusion (‘single module’)

1. The (‘single’) UPS module has now been commissioned and can be put into
normal service. Be sure that the commissioning records are completed and
filed appropriately.
2. If the password protection system is to be enabled ensure that the link is
removed from jumper X26 pins 7-8 on the UPS Logic Board.
Note: If the password protection system is enabled only those parameters
listed below are changeable without first entering the selected password:
• Time and Calendar
• ON/OFF UPS CONTROL (rectifier, inverter and bypass)
• Battery test (star, time/date stamp, repetition rate)
• Modem configuration and operation
3. For 1+1 systems, the commissioning procedure must be repeated for each
1+1 module. When both modules have been satisfactorily commissioned, con-
tinue with the commissioning procedure for the ‘1+1’ system outlined below.

2.7 Parallel System Start Up (‘1+1’ System)

Applies only to The procedures contained in paragraph 2.7 and paragraph 2.8 are used to commis-
1+1 sion two ‘1+1-configured’ modules as a ‘parallel-operating’ system. It is crucial
that both modules have passed the single module commissioning checks before
any attempt at paralleling is carried out.

2.7.1 Initialisation
1. Ensure that both modules are fully powered down.
2. On each module in turn:
a) Fit the 60 way flat ribbon cable between the Parallel Logic Board
(4520075B) connector X1 and UPS Logic Board (4550007H) connector
X7 – this cable was removed earlier in the commissioning procedure to
allow the modules to operate in their ‘single module’ mode.
b) Reconfigure the UPS Logic Board (4550007H) jumpers for parallel opera-
tion (See Table 2-13) – these were changed earlier in the commissioning
procedure to allow the modules to operate in their ‘single module’ mode.
c) Check that the Parallel Logic Board (4520075B) jumpers have been
selected in accordance with Table 2-10.

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Table 2-13: UPS Logic Board jumper configuration

Inverter operation in ‘Manual’ mode (Bypass preferred) = Closed

1-2
Inverter operation in ‘Auto’ mode (Inverter Preferred) = (Standard)
Inverter Bad voltage for 10 seconds
3-4 Off latch enabled = Closed (Standard)
X26 Off latch disabled = Open
5-6 Not Required
Security Password Over-ride.
7-8 Closed = Over-ride security Password
Open = Enable security Password (standard)
1-2 *G.V.C.O. to inverter logic = parallel module
X34
2-3 Micro V.C.O. to inverter logic = single module
1-2 Separate battery per module (1 for each rectifier)
X35
2-3 Common battery (parallel rectifiers)
1-2 Separate battery per module (1 for each rectifier)
X36
2-3 Common battery (parallel rectifiers)

Note: *X34 must be in position 1-2 for ‘1+1’ operation.

X26 must be in position 7-8 to override the password security control.

2.7.2 Parallel logic PCB calibration

Complete paragraph 2.7.2 for each module in turn, ensuring that only the module
under calibration is energised.
1. Ensure that switches Q1, Q2, Q3 on the UPS Logic Board are selected OFF –
i.e. to disable the rectifier, inverter, and bypass operation.
2. Ensure that all power isolators are OPEN, take particular care that the bypass
isolator Q2 is OPEN.
3. Close the rectifier power isolator Q1 to energise the control electronics.
Governing Voltage Controlled Oscillator (GVCO) calibration:
4. Connect a DVM to X8 pin 1 and check that the level is high (+5V) to ensure
that the G.V.C.O. is free running (0V is available at TP10).
5. Adjust R18 to obtain a 50Hz square wave at X8 pin 2. Note: for 60Hz opera-
tion connect jumper X7 to 1-2 and adjust R18 for 60.00Hz @ X8 pin 2.
Reverse/Forward current detector calibration: .
6. Connect a DVM to the lower end of R68.
7. Adjust R19 to obtain the appropriate voltage for the expected nominal output
current as shown in Table 2-14.
Table 2-14:

UPS Rated Voltage R68 Lower End Value

220/380V 5.90V
230/400V 6.20V
240/415V 6.45V

Software re-configuration:

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8. Using the software driver menu display screens enter the ‘SETUP’ menu (See
Figure 2-15).
9. Select and enter the ‘CONFIG’ screen.
[Link] the ‘ROTATE’ button select ‘PAR 1+1’ and press ‘SAVE’ to store the param-
eters into memory.
[Link] the ‘ESCAPE’ button return to the ‘DEFAULT’ alarms screen.

[Link] the procedures detailed in paragraph 2.7.2 are carried out individually
on both modules.

2.8 Testing the Complete Parallel System

2.8.1 Module starting

1. Ensure that the bypass input isolator Q2 remains OFF on both modules.
2. Ensure that the switches Q1, Q2 & Q3 on the UPS Logic Board are OFF.
3. Close the rectifier input isolator Q1 on each module.
4. Start the rectifier in each module by closing the UPS Logic Board switch Q3
and check for the correct battery float voltage on each modules’ ‘MEASURE-
MENT’ screen.

5. Close the appropriate battery isolators for the system configuration.

6. Start a selected inverter by closing switch Q2 on the module UPS Logic
Board and then close the module output isolator Q4 – the inverter should run
up and its output contactor K1 close.
Check for correct output voltages on the ‘MEASUREMENT’ screen.
7. Start the inverter in the second module by closing switch Q2 on the UPS
Logic Board – the second module’s inverter should run up and its output con-
tactor K1 close.
Check for correct output voltages on the ‘MEASUREMENT’ screen.
8. Using the current ‘MEASUREMENT’ screens or current clamp CTs on the output
critical busbar interconnecting cables, check for circulating currents between
the paralleled inverters.
d) The measured circulating current should be less than 10% of the modules’
kVA rating – e.g. 6 amps for a 60kVA unit.
e) Adjust the inverter φ displacement using R247 on the Inverter Logic Board
(4530025T) on one module to minimise the circulating current.
9. Close the bypass input isolators Q2 on each module.
[Link] the static bypass on each module by closing the switch Q1 on each
UPS Logic Board.
The inverters should now synchronise to the bypass supply.
[Link] the system to stabilise.
Check for ‘NORMAL OPERATION’ indicated on the ‘DEFAULT’ screen of each
module.

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2.8.2 Inverter bypass re-transfer checks

The UPS system can be configured to operate in two ways, i.e.:

Redundant module
Where the proposed rated load level is less than or equal to the nominal kVA of
one module. Either module operating is therefore capable of sustaining the load.

Non-redundant module
Where the proposed rated load level is greater than the nominal kVA of one
module but less than the sum of both. Both modules are therefore required to sus-
tain the load.

[Link] Redundant configuration system power checks

This paragraph applies to a ‘Redundant’ module system only. If the system under
test is configured as ‘Non-redundant’ then jump to paragraph [Link].
The static bypass thyristor switches contained within each module will operate to-
gether, always opening and closing in unison. However it is possible to have one
in a ‘BLOCKED’ state by selecting switch Q1 of the relevant UPS Logic Board to
OFF – simulating a ‘bypass disabled’ condition.

1. Ensure that jumper X6 0-1 is open on the Parallel Logic Board (4520075B)
for redundant operation.
2. Start both modules and ensure they operate as expected, with the inverters
paralleled and ‘NORMAL OPERATION’ displayed on both modules’ ‘DEFAULT’
screen.
3. Stop one module’s inverter by selecting OFF Q2 on its UPS Logic Board.
a) The inverter should stop and the module’s output contactor K1 open –
thereby disconnecting the module from the critical bus.
b) The remaining module should continue to operate and support the critical
bus supply.
4. Stop the second module’s inverter by selecting OFF Q2 on its UPS Logic
Board.
a) The second module’s inverter should stop and its output contactor K1
open, – thereby disconnecting the second module from the critical bus.
b) Critical bus power should now transfer to the bypass supply, without a
break – i.e. both modules’ bypass static switches should close.
5. Check for the appropriate default alarms on each module mimic display.
6. Start the inverter on one module by selecting ON Q2 on the relevant module’s
UPS Logic Board.
a) The inverter should run up and achieve synchronisation.
b) The critical bus should transfer to the inverter – i.e. the output contactor
(K1) should close in the running module only, and the static switches
should open in both modules.
7. Start the remaining module’s inverter by selecting ON Q2 on its UPS Logic
Board.
a) The inverter will run up and achieve synchronisation.

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b) Check that the LED H3 illuminates on the Parallel Logic Board during
‘slave’ mode operation.
c) The second module’s output contactor (K1) should close connecting the
inverter to the critical bus.
d) Check that the LED H3 extinguishes on the Parallel Logic Board, indicat-
ing ‘master’ mode operation.

[Link] Non-redundant configuration system power checks

This paragraph applies to ‘Non-redundant’ configured systems only. If the system
under test is configured as a ‘Redundant’ system then jump to paragraph 2.9.
The static bypass thyristor switches contained within each module will operate to-
gether, always opening and closing in unison. However it is possible to have one
in a ‘BLOCKED’ mode by selecting OFF switch Q1 of the relevant UPS Logic
Board, simulating a ‘bypass disabled’ condition.
1. Ensure that link X6 0-1 is closed on the Parallel Logic Board (4520075B) for
‘Non-redundant’ operation.
2. Start both modules and ensure they operate as expected, with the inverters
paralleled and ‘NORMAL OPERATION’ displayed on both modules’ ‘DEFAULT’
screen.
3. Stop one module inverter by selecting OFF switch Q2 on the UPS Logic
Board.
a) The inverter should stop and the module output contactor K1 open –
thereby disconnecting the module from the critical bus.
b) The output contactor (K1) should also open in the remaining module.
c) If available both modules’ static switches should close to connect the criti-
cal bus to the bypass supply.
d) Check on the appropriate module mimic displays for verification.
4. Turn OFF the remaining inverter by selecting OFF switch Q2 on its UPS
Logic Board.
a) The second module’s inverter should stop – the load is already on bypass.
5. Start the inverter on one module by selecting ON switch Q2 on the relevant
module’s UPS Logic Board.
a) The inverter should run up but its output contactor (K1) should remain
open.
b) The load will remain connected to the bypass waiting for the start of the
second module.
6. Start the second module’s inverter by selecting ON switch Q2 on its UPS
Logic Board.
a) The inverter will run up in slave mode – i.e. led H3 on the Parallel Logic
Board will illuminate until the module achieves synchronisation and paral-
lels with the existing inverter.
b) Both modules should now transfer the critical bus supply to inverter by
closing the output contactor (K1) and turning off the static switch in both
modules simultaneously.

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7. Check on the appropriate module mimic displays for verification.

8. Allow the system to stabilise.
Check for ‘NORMAL OPERATION’ indicated on the mimic ‘DEFAULT’ screen for
each module.

2.9 Commissioning conclusion (‘1+1’ system)

1. The (‘1+1’) parallel UPS system has now been commissioned and can be put
into normal service. Be sure that the commissioning records are completed
and filed appropriately.
2. If the password protection system is to be enabled (both modules) ensure that
the link is removed from jumper X26 pins 7-8 on the UPS Logic Board.
Note: If the password protection system is enabled only those parameters
listed below are changeable without first entering the selected password:
• Time and Calendar
• ON/OFF UPS CONTROL (rectifier, inverter and bypass)
• Battery test (star, time/date stamp, repetition rate)
• Modem configuration and operation

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Section 2:

2.10 Voltage and Frequency Conversion

The 7200 Series UPS leaves the manufacturer fully tested and adjusted to operate
at 400Vac / 50Hz with a 198 cell battery; however, but can be converted to 380V
or 415V, at either 50 or 60Hz. Such a conversion is effected by:
• changing the control power supply transformers primary tap voltages.
• entering the revised working parameters into the control system’s memory
via the Operator Control Panel ‘SETUP’ menus.
• amending the number of batteries, if required.
The module’s working voltage and frequency is set as a matter of course within
the commissioning procedure: the purpose of the following paragraphs is to pro-
vide a consolidated procedure for changing these parameters post commissioning
– i.e. to change the voltage/frequency of an already working module.
Note: Where reference is made to the “nominal” voltage, this should be taken as
the required equipment working voltage – e.g. 380/400/415 volts.

2.10.1 Rating considerations and battery sizing

If the module is to operate at 415V input/output its power capacity will increase
by approximately 10%. – i.e. A 60kVA unit will be increased to 66kVA.
The number of battery elements required to enable the unit to meet its design
specifications is shown in the table below.
Note: If additional elements are required they should be of the same type and ca-
pacity as those already in use.
Table 2-15: Number of battery elements

Nominal Operating Output Voltage Specified Nº of Battery Elements

380V AC 192 Cells

400V AC 198 Cells

415 V AC 204 Cells

2.10.2 Hardware conversion

1. Ensure that the module is completely powered down – i.e. all the UPS isola-
tors, including the battery circuit breaker, are open (OFF or in position ‘0’) –
if necessary transfer the load to the Maintenance Bypass supply.
2. Select the correct primary voltage tap on the Power Supply transformers T2
and T3, according to Table 2-16 below.

Table 2-16: Power supply transformers T2 and T3 voltage selection.

380V Operation 400V Operation 415V Operation

A3 - B A2 - B A1 - B

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2.10.3 Software conversion – Entering new voltage / frequency / battery data

Figure 2-25: ‘SETUP’ menu map (Issue 5.0 software)

MAIN MENU SCREEN

UPS MENU
SCREEN

SETUP MENU
SCREEN

VOLTAGE
MENU
SCREEN

FREQUENCY
MENU
SCREEN

BATTERY
MENU
SCREEN

Continued in
Figure 2-26

1. Inhibit the UPS power sections by selecting switches Q1, Q2, Q3 on the UPS
Logic Board to OFF.
2. Close the Bypass Isolator Q2.
a) The power supply and electronics will energise.
b) The Operator Control Panel display will power up.
c) The rectifier and inverter power sections will remain off.
3. From the default screen press ‘ENTER’ to access the main menu screen.

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4. Ensure that a link is fitted to jumper X26 pins 7-8 on the UPS Logic Board to
override the password protection system.
5. Select and enter ‘SETUP’ – the password screen will now be shown.

[Link] Setting the UPS working voltage parameters

1. From the setup screen, select and enter ‘VOLTAGE’ – this will access the volt-
age menu screen.
2. Select and enter ‘RATED VOLTS.’.
a) Press the ‘UP’ menu button repeatedly until the desired input/output work-
ing voltage is indicated.
b) Press ‘ENTER’ to save the selection and then press ‘ESC’ once to move back
to the voltage menu screen.
3. Select and enter ‘LOWER’.
a) Using the data entry method described above, enter the required input and
output voltage undervoltage thresholds.
Note: Standard settings are for -10% (input) and -10% (output).
b) Press ‘ENTER’ to save the selection then press ‘ESC’ once to move back to
the voltage menu screen.
4. Select and enter ‘UPPER’.
a) Using the data entry method described above, enter the required input and
output overvoltage thresholds.
Note: Standard settings are for +10% (input) and +10% (output).
b) Press ‘ENTER’ to save the selection then press ‘ESC’ once to move back to
the voltage menu screen.
5. Verify that the data shown on the voltage menu screen is correct and repeat
this procedure if necessary.
6. Press ‘ESC’ again to move back to the setup menu screen.

[Link] Setting the UPS frequency parameters

Note: go directly to paragraph [Link] if the frequency is not to be changed.
1. Select and enter ‘FREQUENCY’ – this will access the frequency menu screen.
2. Select and enter ‘NOMINAL’.
a) Press the ‘UP’ menu button repeatedly until the desired nominal frequency
is indicated.
b) Press ‘ENTER’ to save the selection then press ‘ESC’ once to move back to
the frequency menu screen.
3. Select and enter ‘SYNC WINDOW’.
a) Enter the required sync window limit.
Note: Standard setting is ‘2.0%’ – i.e. the inverter will sync to the bypass if
it is ±1Hz of 50Hz nominal.
b) Press ‘ENTER’ to save the selection then press ‘ESC’ once to move back to
the frequency menu screen.

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4. Select and enter ‘SLEWRATE’.

a) Enter the required slew rate (range 0.1 - 1.0 Hz/s).
Note: Standard setting is ‘0.10 Hz/s’ – i.e. the speed the inverter will track
a change in bypass frequency.
b) Press ‘ENTER’ to save the selection then press ‘ESC’ once to move back to
the frequency menu screen.
5. Verify that the data shown on the frequency menu screen is correct and repeat
this procedure if necessary.
6. Press ‘ESC’ again to move back to the setup menu screen.

[Link] Setting the Battery parameters

Figure 2-26: ‘SETUP’ – BATTERY MENU

Continued from
Figure 2-25 E@Cðððððð & ð[F1
F?<D175ððð$ ððF SETUP MENU SCREEN
6B5AE5>3Iðð% ðð8j
21DDâ35<<Cðððð!)(
BATTERY MENU SCREEN

21DDâ35<<Cðððð!)( GB9D5ðððððððððC1F5
31@139DIððð %"ð1X =?F5ðððððððððð5H9D
F?<D175á35<< 21DDâ35<<Cðððð!)(ðð

21DDâ35<<Cðððð!)( GB9D5ðððððððððC1F5
31@139DIððð %"ð1X =?F5ðððððððððð5H9D
F?<D175á35<< 31@139DIðððð %"ð1X

21DDâ35<<Cðððð!)( 5>4ð49Câðð!â&'ðfáU GB9D5ðððððððððC1F5

31@139DIððð %"ð1X 21Dâ<?Gððð!â("ðfáU =?F5ðððððððððð5H9D
F?<D175á35<< =1Hâðððððð"â$%ðfáU 5>4ð49Câðð!â&'ðfáU
2??CDð381B75

BATTERY VOLTAGE 5>4ð49Câðð!â&'ðfáU GB9D5ðððððððððC1F5

MENU SCREEN 21Dâ<?Gððð!â("ðfáU =?F5ðððððððððð5H9D
=1Hâðððððð"â$%ðfáU 21Dâ<?Gðð!â("ðfáU
2??CDð381B75

5>4ð49Câðð!â&'ðfáU GB9D5ðððððððððC1F5
21Dâ<?Gððð!â("ðfáU =?F5ðððððððððð5H9D
=1Hâðððððð"â$%ðfáU =1Hâðððððð"â$%ðfáU
2??CDð381B75

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21Dâ<?Gððð!â("ðfáU Continued in
=1Hâðððððð"â$%ðfáU
2??CDð381B75 Figure 2-27

1. From the setup menu select and enter ‘[Link]’ – this will access the bat-
tery menu screen (illustrated in Figure 2-26).
Setting the number of cells:
2. From the battery menu screen, select and enter ‘ [Link]’.
3. Following the data entry method described earlier, using the ‘UP’, ‘DOWN’
menu buttons, enter the number of cells contained in the battery string.

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7200 Series UPS Service Manual SECTION 2 - Installation and Commissioning
CHAPTER 2 - Commissioning Procedure

4. Press ‘ENTER’ to save the data to memory, then press ‘ESC’ once to return to
the battery menu screen.
Setting the Battery Capacity:
5. From the battery menu screen, select and enter ‘ CAPACITY’.
6. Using the ‘UP’, ‘DOWN’ menu buttons, enter the total battery A/Hr capacity.
(at the 10Hr rate C10).

7. Press ‘ENTER’ to save the data to memory, then press ‘ESC’ once to return to
the battery menu screen.
Setting the battery voltage characteristics:
From the battery menu screen, select and enter ‘VOLTAGE’ – this will take you to
the battery voltage menu, which is concerned with selecting the battery charging
characteristics.

Battery undervoltage trip setting

8. From the battery voltage menu, select and enter ‘END DIS.’.
a) Using the ‘UP’, ‘DOWN’ menu buttons, enter the specified ‘end-of-dis-
charge’ voltage – standard setting is 1.67V/cell.
Note: this is the ‘end-of-discharge’ voltage and is the voltage at which the
battery breaker is tripped.
b) Press ‘ENTER’ to save the data to memory, then press ‘ESC’ once to return to
the battery voltage menu screen.

Battery low voltage warning setting

9. From the battery voltage menu, select and enter ‘BAT LOW’.
a) Using the ‘UP’, ‘DOWN’ menu buttons, enter the specified ‘low battery volt-
age’ – standard setting is 1.82V/cell.
Note: this is the voltage at which ‘low-battery warning’ annunciates.
b) Press ‘ENTER’ to save the data to memory, then press ‘ESC’ once to return to
the battery voltage menu screen.

Battery overvoltage trip setting

10. From the battery voltage menu, select and enter ‘MAX’.
a) Using the ‘UP’, ‘DOWN’ menu buttons, enter the specified ‘max battery
voltage’ – standard setting is 2.45V/cell. This sets the ‘slow’ overvoltage
level which is effective only when the batteries are in the float charge
mode, and is the voltage at which, after 3 minutes, the battery breaker is
tripped, and the rectifier and inverter turned OFF.
b) Press ‘ENTER’ to save the data to memory, then press ‘ESC’ once to return to
the battery voltage menu screen.
Battery boost charge setting:

WARNING DO NOT apply BOOST CHARGE to sealed batteries

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SECTION 2 - Installation and Commissioning 7200 Series UPS Service Manual
CHAPTER 2 - Commissioning Procedure

Figure 2-27: Battery boost charge parameters

Continued from
Figure 2-26 BATTERY VOLTAGE MENU SCREEN
BATTERY BOOST MENU SCREEN

11. From the battery voltage menu, select and enter ‘BOOST CHARGE’ – this will
take you to the boost charge menu screen.
12. From the boost charge menu, select and enter ‘SETUP’ – this will take you to
the battery boost setup menu screen.
13. From the battery boost setup menu, select and enter ‘DURATION’.
a) Using the ‘UP’, ‘DOWN’ menu buttons, enter the required boost operation
time (in minutes) – factory setting is 600 mins.
b) Press ‘ENTER’ to save the data to memory, then press ‘ESC’ once to return to
the battery boost setup menu screen.
14. From the battery boost setup menu, select and enter ‘THRESHOLD’.
a) Using the ‘UP’, ‘DOWN’ menu buttons, enter the required current change-
over threshold – factory setting is 20% of the battery current limit.
Note: this is the level that the battery current must reach before boost
charge is enabled upon mains return.
b) Press ‘ENTER’ to save the data to memory, then press ‘ESC’ once to return to
the battery boost setup menu screen.
15. It is advisable to set the ‘NOW’ and ‘AUTOMATIC’ parameters to ‘NO’ at this
stage in the commissioning, and reset to ‘YES’ (if required) once the rectifier
has been fully commissioned.
Verification:
16. Press ‘ENTER’ to save the data to memory, then press ‘ESC’ once to return to
the battery voltage menu screen.
17. Verify that the data shown on the battery voltage menu screen is correct and
repeat this procedure if necessary.

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7200 Series UPS Service Manual SECTION 2 - Installation and Commissioning
CHAPTER 2 - Commissioning Procedure

Figure 2-28: Battery CHARGE MODE Selection (Issue 5.0 software)

Continued from
Figure 2-19

FUNCTION
MENU SCREEN

NEXT PAGE MENU

SCREEN

ON/OFF
MENU
SCREEN

CHARGE MODE
SELECTION SCREEN

2.10.4 Calibration conversions

[Link] Recalibrating the battery charging voltages

This part of the procedure calibrates the battery charging voltages using the ap-
propriate potentiometers on the Rectifier Logic Board and requires the rectifier to
be fully powered-up.
1. Connect a DC voltmeter across the battery cable connections (adjacent to the
battery fuse).

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SECTION 2 - Installation and Commissioning 7200 Series UPS Service Manual
CHAPTER 2 - Commissioning Procedure

2. Close the UPS input mains isolator (Q1).

3. Turn switch Q3 on the UPS Logic Board to ON – the rectifier should now
start and ramp up to float voltage, as indicated on the voltmeter.
Float charge voltage calibration:
4. On the Rectifier Logic Board:
a) Ensure led H3 (green) is illuminated.
b) Adjust R21 to obtain the required float charge voltage, indicated on the
DC voltmeter.
Manual charge voltage calibration:
5. Using standard screen navigation techniques, gain access to the charge mode
selection screen via the FUNCTION – NEXT PAGE – ON/OFF UPS CON-
TROL menu path (See Figure 2-28).

6. Scroll through the menu options and select manual charge mode (‘MAN’).
7. On the Rectifier Logic Board:
a) Ensure led H4 (yellow) illuminates (H3 extinguished).
b) Adjust R22 to obtain a charge voltage, indicated on the DC voltmeter,
appropriate to ‘forming’ open vented cells (if applicable). If sealed cells
are used then set this voltage to equal the float voltage set previously.
Boost charge voltage calibration:
8. Leave the charge mode selected to manual (‘MAN’), as instructed above.
9. On the Rectifier Logic Board:
a) Link-out pins 0-2 on jumper X9 to force the charger to the ‘Boost’ mode.
b) Ensure led H2 (green) illuminates (H4 should extinguish).
c) Adjust R20 to obtain the required boost charge voltage, indicated on the
DC voltmeter.
Note: If sealed cells are used then set this voltage to equal the float voltage
set previously.
Calibration completion:
10. Open the UPS input mains isolator Q1 and bypass isolator S2.
11. On the UPS Logic Board set S1, S2, S3 to ON to re-enable the UPS power
sections.
12. On the Rectifier Logic Board remove the link from pins 0-2 on jumper X9.
13. Disconnect and remove the DC Voltmeter.

[Link] Completion of UPS SETUP configuration

The setup menu parameters have now all been entered and stored in the control
system’s non-volatile memory.
1. Start the UPS following the normal start-up instructions and verify that it
now operates at the desired voltage and frequency.
2. If required, remove the link from jumper X26 pins 7-8 on the UPS Logic
Board to re-enable the password security system.

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 Section 2:

Chapter 3 - Converting single (pre Jan 1997) units

to 1+1 capability

3.1 Introduction
Series 7200 single module units manufactured prior to January 1997 will require
upgrading before they can operate in a 1+1 system configuration. This chapter
outlines the procedure to be followed before the units are commissioned.
Before the 1+1 paralleling option can be fitted the upgrade procedure requires me-
chanical changes to be made by fitting Modification Kit Part Nº 4641030E, which
then changes the unit part number as shown below.
Table 2-17:

Model Pre January 1997 Modification Kit Converted Unit

Rating kVA unit Part Nº Required Part Nº
30 5410303P 4641030E 5410305R
40 5410304Q 4641030E 5410307T
60 5410308U 4641030E 5410310W

3.1.1 Important Considerations

Caution This modification must be carried out only by a fully trained and authorised Liebert
engineer.

Allow approximately two hours for the modification of each module.

The mechanical relocation of existing PCB’s and control transformers must be
carried out prior to fitting the 1+1 parallel option kit Part N º 4645004A.
Step by step instructions are included with the conversion kit Part Nº 4641030E
but are not in the scope of this manual. However the basic mechanical differences
and repositioning of components is shown in Figure 2-29.

3.2 Conversion Procedure

1. Fit the conversion kit Part Nº 4641030E, follow the instructions supplied
with each kit.
2. Upgrade the PCB’s, refer to below.

Remove PCB Fit New PCB

PCB Description
Pre Jan. 97 Post Jan. 97
Inverter Logic 4530024S 4530025T
UPS Logic 4550004E 4550007H
Static Switch 4542041X 4542043Z

Units manufactured after January 1997 will have the new PCB’s factory fitted.

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SECTION 2 - Installation & Commissioning 7200 Series UPS Service Manual
CHAPTER 3 - Commissioning Procedure

Figure 2-29: Pre/Post modification mechanical layouts

4530025T
4550007H

Pre January 1997 unit

before conversion Pre January 1997 unit after conversion.
Factory supplied units post Jan 97

3. Check the software version on the UPS Logic Board (D35/D36) and Opera-
tor Logic PCB (D8). This must be Version 3.0 or later. If the software version
is incorrect, replace these devices according to the table below
Table 2-18: .

EEPROM Old Part Number New Part Number

D35 0837044A Rev [Link] 0837044A Rev D.00
D46 0837045B Rev [Link] 0837045B Rev D.00
D8 0837046C Rev [Link] 0837046C Rev D.00

On completion of the mechanical conversion, PCB replacement and software

upgrade, the converted unit should be commissioned as detailed in Chapter 2.

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 Commissioning Report Sheet

Section 2 : Commissioning Parameter Settings

Sample Commissioning Recordsheets System Details

Customer Site Details

Module Type/Rating

Module Part/Serial Number

SET UP MENU Parameters

Standard Range
Menu
Parameter Factory Min. Max
Selected Setting
Selection
Setting
UPS KVA VALUE 60kVA – –
UPS TYPE 3 Phase – –
CONFIGURATION Single – –

VOLTAGE NOMINAL INPUT VOLTAGE 230 220 240

INPUT UNDERVOLTAGE –10% –1% –99%
INPUT OVERVOLTAGE +10% +1% +99%
NOMINAL OUTPUT VOLTAGE 230 220 240
OUTPUT UNDERVOLTAGE –10% –1% –99%
OUTPUT OVERVOLTAGE +10% +1% +99%

FREQUENCY NOMINAL FREQUENCY 50 Hz 50Hz 60Hz

SYNC WINDOW 2% 0.5% 9%
SLEW RATE (SPEED) 0.1 Hz/Sec 0.1 1.0

BATTERY NUMBER OF CELLS 198 190 210

CAPACITY 85 AHr 000 499
END OF DISCHARGE VOLTS 1.67 Volts/cell 1.60 1.69
LOW BATTERY VOLTAGE 1.82 Volts/cell 1.70 1.89
MAX. BATTERY OVER VOLTAGE 2.40 Volts/cell 2.30 2.70
BOOST CHARGE ENABLE NO – –
BOOST CHARGE AUTO NO – –
BOOST CHARGE DURATION 0000 min. 0000 9999
BOOST CHARGE THRESHOLD 00 Amps 00 99

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MAINTENANCE MENU Parameters

Menu Standard Range

Selected Setting
Selection Parameter Factory Min Max
setting
PASSWORD PASSWORD 0000 0000 –

S.N. SERIAL NUMBER 0000 0000 –

12.00.00 CURRENT TIME AND DATE 12.00.00 –

01.01.96

LAST SER. LAST SERVICE TIME AND DATE 01.01.96 –

NEXT SER. NEXT SERVICE TIME AND DATE 01.01.96 –

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FUNCTION MENU Parameters

Standard Range
Menu Selected Setting
Parameter Factory Min Max
Selection
setting
Input Password To Gain Access To Function Selec- 0000 0000 0000 9999
tion Screen 0000 9999

BATTERY NOW NO – –
TEST AUTOMATIC NO – –
SETUP DURATION 00 Min 00 99
THRESHOLD 1.70 V/e 1.70 1.90
PERIOD 000 dd 000 999
START AT 01.01.96 – –

GENERATOR INV: SYNC INHIBIT NO – Requires

BAT: I INHIBIT NO – an alarm
interface
RECT: I INHIBIT NO – PCB
fitted

LANGUAGE ITALIAN Eng : Fr : Esp :

Deu.
PANEL TYPE MASTER. 0060 – –
SETUP GROUP UPS : NODE : 1:1 – –
PASSWORD 0000 0000 0000 9999
0000 9999

MODEM PC CONN LOCAL – –

CONNEC- RESET NO – –
TION

ON/OFF UPS INVERTER ON – –

BLOCK BYPASS ON – –
RECTIFIER ON – –
RECTIFIER FLO FLO MAN

RELOAD UPS RELOAD DATA NO DO NOT perform this test as part of the
DATA normal commissioning procedure unless
the UPS parameters have to be reset to
factory default values.

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MEASURMENT MENU Parameters

Standard
Selection Enter
Parameter Factory
Screen On Site Readings
setting
OUTPUT VOLTAGE A–B 400 Volt
B–C 400 Volt
C–A 400 Volt
A–N 230 Volt
B–N 230 Volt
C–N 230 Volt
CURRENT A 0 Amp
B 0 Amp
C 0 Amp
N 0 Amp
POWER A 0 kW
B 0 kW
C 0 kW
A 0 kVA
B 0 kVA
C 0 kVA
FREQUENCY Bypass Line 50 Hz
Inverter 50 Hz

INPUT VOLTAGE A–B 230 Volt

B–C 230 Volt
C–A 230 Volt

BATTERY VOLTAGE 460 Volt

CURRENT 0 Amp
CHARGE CAPACITY 100%

TEMPERATURE Tt (Transformer) –
Ta (Input air) –
To (Output air) –
Tb (Batt cabinet) –

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 Commissioning Report Sheet

Hardware Parameters

Rectifier Logic Board

Factory
Parameter Potentiometer Test Point Site Setting
setting
Rectifier Current Limit R17 X8 pin 7 Proportional kVA
Battery Current Limit R18 X8 pin 8 Proportional kVA
Battery Temperature Compensa- R121 X8 pin 5 2.98Vdc
tion
DC Float Voltage R21 DC Bus 449Vdc
DC Manual Voltage R22 DC Bus 449Vdc
DC Boost Voltage R20 DC Bus 449Vdc
DC Test Voltage R19 DC Bus 390Vdc

Inverter Logic Board

Factory
Parameter Potentiometer Test Point Site Setting
setting
150% Current limit R248 X10 pin 4 0.6Vdc
Inverter Tri-wave PWM ref- R241 Scope to LHS of R27 4Vp-p
erence (+2V to -2V)
Output Voltage R-N R246 Inv output terminal R-N 230Vac
Output Voltage S-N R244 Inv output terminal S-N 230Vac
Output Voltage T-N R245 Inv output terminal T-N 230Vac
Output Voltage R-S R242 Inv output terminal R-S 400Vac
Output Voltage S-T Adjust all 3 Inv output terminal S-T 400Vac
phases together
Output Voltage R-T Inv output terminal R-T 400Vac
Output Frequency R-T – Inv output terminal R-T 50Hz
Inverter/Bypass phase R247 Scope Bypass R-phase 0° Shift
shift and Inv R-phase.

UPS Logic Board

Factory
Parameter Potentiometer Test Point Site Setting
setting
5V Voltage reference R209 X20 pin 1 5.00Vdc
2.5V Voltage reference R212 V45 anode 2.50Vdc

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Operator Logic Board

Factory
Parameter Potentiometer Test Point Site Setting
setting
LCD Display Contrast R21 LCD Display N/A

Battery information

Parameter On-Site notes

Battery Type
Number of Cells
Float Voltage =
Ampere/Hr capacity
Battery Current Limit
Battery Breaker Size

ENGINEER’S NAME:
SIGNATURE:
DATE:

WITNESSED BY:
SIGNATURE
DATE:

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 Commissioning Report Sheet

S2-c2e.fm5 - Issue 3 Dated 09/11/98

 Section 3: Control Power Supplies

Chapter 1 - Control Power Generation & Distribution

1.1 Control power generation ......................................................................... 3-1
1.1.1 AC-DC Power Supply Board ....................................................... 3-2
1.1.2 DC-DC Power Supply Board ....................................................... 3-2
1.2 Control power distribution ....................................................................... 3-2

Chapter 2 - AC-DC Power Supply

2.1 Chapter overview ..................................................................................... 3-5
2.2 General description ................................................................................... 3-5
2.2.1 Circuit board functions ................................................................ 3-5
2.2.2 Input/output connections .............................................................. 3-5
2.3 Circuit description .................................................................................... 3-5
2.4 Calibration details ..................................................................................... 3-6

Chapter 3 - DC-DC Power Supply

3.1 Chapter overview ..................................................................................... 3-7
3.2 General description ................................................................................... 3-7
3.2.1 Circuit board functions ................................................................ 3-7
3.2.2 Input/Output connections ............................................................. 3-7
3.3 Circuit description .................................................................................... 3-8
3.3.1 Introduction .................................................................................. 3-8
3.3.2 Series chopper and filter .............................................................. 3-8
3.3.3 Inverter and transformer sections ................................................. 3-9
3.3.4 Fault detection ............................................................................ 3-10
3.3.5 Indications .................................................................................. 3-10
3.4 Calibration details ................................................................................... 3-10

S-3.FM5 - Issue 2 Dated 21/08/97 i

SECTION 3 - Control Power Supplies 7200 Series UPS Service Manual

ii S-3.FM5 - Issue 2 Dated 21/08/97

 Section 3:

Chapter 1 - Control Power Generation & Distribution

1.1 Control power generation

Two Power Supply Boards are fitted to the 7200 series UPS module; the AC-DC
Power Supply Board and the DC-DC Power Supply Board – as illustrated in
Figure 3-1 below.

Figure 3-1: Control Power – primary supply

Q2
Bypass STATIC
Supply SWITCH

F6 F7
Split bypass links

T3

Q1
F10 L1
Input
Mains F11 RECTIFIER INVERTER
Supply F12

F8 F9

F4 F5
T2
From T3

AC-DC Power DC-DC Power

Supply Board Supply Board
±12Vdc ±12Vdc

Rectifier Inverter
Logic Board Logic Board

±12Vdc Supplies to
all other circuit boards

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SECTION 3 - Control Power Supplies 7200 Series UPS Service Manual
CHAPTER 1 - Control Power Generation & Distribution

1.1.1 AC-DC Power Supply Board

The AC-DC Power Supply Board, which is described in detail in Chapter 2, is fed
from both the input mains and bypass supplies via transformers T2 and T3 respec-
tively, and is live when either of these two power sources are available (note that
the ‘split-bypass links’ are removed if a separate bypass supply is used).
This board produces ±12V and 0V outputs which are directly connected to the
Rectifier Logic Board; and from this board these power rails are also connected
to the remainder of the control circuit boards (except the Inverter Logic Board) as
described in paragraph 1.2) .
Transformers T2 and T3 are identical and have tapped primary windings to cater
for a range of mains supply voltages. The taps used are A1/B (415V); A2/B
(400V); A2/B (380V). The primary fuses (e.g. F6/F7 and F8/F9) are fitted in
‘ganged’ fuse-holders which also serves as an isolation switch to allow the trans-
formers to be replaced without having to shut-down the entire UPS.

1.1.2 DC-DC Power Supply Board

The DC-DC Power Supply Board, which is described in detail in Chapter 3, is fed
from the DC Busbar and is live whenever the rectifier is operative or the battery
circuit breaker is closed. The board therefore has to operate over a wide range of
input voltages varying between the battery boost voltage to the battery undervolt-
age trip level (approximately 240V to 700V).
This board produces ±12V and 0V outputs which are connected to the Inverter
Logic Board; and from this board these power rails are also connected to the re-
mainder of the control circuit boards.
The board’s input fuses (F5/F5) are fitted in ‘ganged’ fuse-holders which also
serves as an isolation switch to allow the board to be replaced without having to
shut-down the entire UPS. (Note: As the Inverter Logic Board is powered only
from the DC-DC Power Supply, the inverter will shut-down and the load transfer
to bypass if these fuses are opened.)

1.2 Control power distribution

The ±12V supply rails on the Rectifier Logic Board and Inverter Logic Board,
from the AC-DC Power Board and DC-DC Power Board respectively, are con-
nected together on the UPS Logic Board and distributed to the remaining control
boards as illustrated in Figure 1.2.
Note that the power rails on the Inverter Logic Board are isolated by blocking
diodes from the UPS Logic Board supply rails. This means that the Inverter Logic
Board is powered only by the DC-DC Power Supply Board, and loses its operat-
ing power when this supply is not available – i.e. without the DC Input (from the
DC Bus) the inverter cannot operate. The remaining circuit boards, including the
Rectifier Logic Board, are powered when either the AC-DC or DC-DC Power
Supply Boards are active.
Most of the boards also require other stabilised voltages, such as +5V, for their
correct operation. Where such voltages are required they are developed individu-
ally on the board in question by appropriate voltage regulators. The exception to
this is the Operator Control Panel, which obtains its regulated +5V power from an
isolated dc-dc converter circuit on the Operator Logic Board.

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7200 Series UPS Service Manual SECTION 3 - Control Power Supplies
CHAPTER 1 - Control Power Generation & Distribution

Figure 3-2: Control Power Supplies Distribution

±12V inputs from ±12V inputs from

AC-DC Power Supply DC-DC Power Supply

3 4 5 5 4 3

V45 V46 -12V

Rectifier Inverter +12V
0V Logic Logic
+12V -12V Board Board 0V

V15 V14

5-8 1-4 9-12 9-12 1-4 5-8

X2 X4

X1 X3
5-8 1-4 9-12 9-12 1-4 5-8

-12V

0V

+12V

UPS Logic Board

+12V -12V +12V -12V +12V -12V
0V 0V 0V +12V

5-8 1-4 9-12 5-8 1-4 9-12 1 3 1-4 5-8

X2 X5 X4 X8

X1 X9
5-8 1-4 9-12 1 3

Operator Logic
High Voltage Board
Interface Board 0V +5V

30-31 4
X13 X1
5-8 1-4 9-12 1-4 5-8

Static Switch I/O Interface

Driver Board Board
(Remote Options)

30-31 4

Operator Control
Panel

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SECTION 3 - Control Power Supplies 7200 Series UPS Service Manual
CHAPTER 1 - Control Power Generation & Distribution

3-4 s3-c1.fm5 - Issue 2 Dated 21/08/97

 Section 3:

Chapter 2 - AC-DC Power Supply

2.1 Chapter overview

This chapter describes the AC-DC Power Supply Board and should be read in
conjunction with circuit diagram SE-4503030-M.

2.2 General description

2.2.1 Circuit board functions

This board is responsible for providing the UPS control logic circuits, with the ex-
ception of the Inverter Logic Board and Inverter Driver Interface Board, with
their ±12V low voltage operating power supplies. The board is itself powered
from two supply sources; the first is derived from the UPS input mains supply and
the second is from the bypass mains supply. This means that the board is active
when either of these two supplies is present - see chapter 1.
Note: in installations not configured with a ‘split-bypass’ supply, the static bypass
supply and UPS input supply are fed from a common mains power source and
both supply sources to this board will fail in the event of an input mains failure.

2.2.2 Input/output connections

The AC-DC Power Supply board has three connectors, described below:
• M1 carries the board’s input supply derived from the UPS input mains
supply.
• M2 carries the board’s input supply derived from the bypass mains supply.
• CN1 carries the board’s output low voltage supplies (±12V) to the UPS
control circuit boards. These are initially connected to the Rectifier Logic
Board and from there to the UPS Logic Board where they are coupled
with the outputs from the DC-DC Power Supply, which is connected to the
UPS Logic Board via the Inverter Logic Board.

2.3 Circuit description

This board contains two straight-forward 3-phase rectifiers whose outputs are
connected in parallel, one being fed via M1 and the other by M2.
The supply to M1 is obtained via transformer T2 and FS8-FS9 (1A), connected to
the S-T phases of the input mains supply and present a nominal 30Vac input (see
the power schematics description in Section 1 Chapter 2). The transformer prima-
ry is tap-selectable to suit the system voltage (see paragraph 1.1.1 on page 3-2).
The supply to M2 is obtained via transformer T3 and FS6-FS7 (1A), connected to
the R-S phases of the bypass mains supply. This transformer is identical to T2,
and tapped in the same way as described above.
Note: the transformer supply fuses are fitted to ganged fuse-holders which enable
them to be used as a two-pole isolation switch.
The AC-DC Power Supply Board circuit diagram shows that each input supply
passes through a full-wave bridge rectifier, providing an unregulated DC power

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SECTION 3 - Control Power Supplies 7200 Series UPS Service Manual
CHAPTER 2 - AC-DC Power Supply

source smoothed by C1 and C2. Two 3-terminal regulators are used to convert this
raw supply into regulated ±12Vdc outputs at CN1 pins 3, 4 and 5.
Leds LS1 (+12V) and LS2 (-12V) indicate the presence of the 12V outputs. These
leds are turned on by transistor drivers and will begin to illuminate when the
power rails are greater than 10.5V (approximately).

2.4 Calibration details

This board is fully calibrated during the manufacturer’s bench testing procedure
and should not require further adjustment when being fitted to the main equip-
ment. The only adjustments are resistors TM1 and TM2, which are connected in
the voltage sense lines to the 3-terminal regulators and enable the output voltage
to be trimmed.

Caution If you need to alter these potentiometers make all adjustments very slowly.
Adjust TM2, the -12Vdc adjustment, first.

As the outputs from this board are effectively connected in parallel with the ±12V
outputs from the DC-DC Power Supply, always ensure that the DC-DC Power
Supply is inoperative when adjusting the AC-DC Power Supply output voltages.
This is achieved by opening the battery circuit breaker and turning off the rectifier.

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 Section 3:

Chapter 3 - DC-DC Power Supply

3.1 Chapter overview

This chapter describes the DC-DC Power Supply Board and should be read in
conjunction with circuit diagram SE-4503028-K.

3.2 General description

3.2.1 Circuit board functions

This board is primarily responsible for providing the Inverter Logic Board and In-
verter Driver Interface Boards with their ±12V low voltage operating power sup-
plies. It also provides a secondary power supply source for the remaining control
logic boards when the AC-DC Power Supply Board is inactive.
The DC-DC Power Supply Board is itself powered from the DC busbar, which
means that it is active at all times when the DC busbar is live: either via the recti-
fier when the UPS input mains supply is healthy, or from the batteries in the event
of a mains failure.

3.2.2 Input/Output connections

The DC-DC Power Supply board has two connectors, described below:
• The input power is connected via M1 (IDC Connector) and is at the nomi-
nal DC busbar voltage.
• The board’s outputs at CN1 are connected to X5 on the Inverter Logic
Board.

CN1 pins 1 & 2 carry a 36Vac output which passes straight through the Inverter
Logic Board to the Inverter Driver Interface Board (to provide an internally iso-
lated power supply for each inverter drive circuit).
CN1 pins 3, 4 and 5 carry the board’s +12Vdc, 0V and -12Vdc outputs respec-
tively. These are initially connected to the Inverter Logic Board and from there to
the UPS Logic Board where they are coupled with the ±12V outputs from the AC-
DC Power Supply, which is connected to the UPS Logic Board via the Rectifier
Logic Board.

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CHAPTER 3 - DC-DC Power Supply

3.3 Circuit description

3.3.1 Introduction

Figure 3-3: Block diagram

M1 Variable DC
Controlled DC (fixed)
Bus + Controlled AC (fixed) CN1
1 Series
Bus - Filter
3 Chopper 1 36Vac
2

3 +15Vdc
Push Pull Output Fixed 4 0V
Chopper PWM

Inverter Transformer Rectifier 5 -15Vdc

Current Feedback
Volts Feedback
Soft Start Output supply
Inverter Drive

LS1 present

TM1
LS2
Input supply
present Fault LS3 Fault
PWM Control Logic present
Detection

This board contains four major stages of operation:

1. A series-chopper circuit, working in conjunction with a filter, converts the
board’s input supply, from the DC busbar, into a Controlled DC supply rail.
Note: The input supply is variable according to the battery voltage as it
charges and discharges – i.e. over a working range of 240-700Vdc.
2. The Controlled (fixed) DC voltage is then converted into Controlled AC by
means of a simple push-pull inverter circuit which has a transformer-coupled
output stage for isolation.
3. The transformer provides two sets of outputs: one leaves the board as a low
voltage ac supply (36Vac nominal) and is used to provide an isolated power
supply for the Inverter Base Driver Boards: the other is rectified to provide
the general ±12Vdc LV control power supplies.

Note: In the following description, the terms ‘input voltage’ and ‘output voltage’
refer to the voltages entering and leaving the DC-DC power supply board and not
the UPS input and output voltages.

3.3.2 Series chopper and filter

Referring to the circuit diagram, the chopper section is designed around TR10,
which is switched ON and OFF by a PWM signal produced by a purpose-de-
signed integrated circuit (IC9). The PWM pattern produced by IC9 (and hence the
controlled dc voltage) is determined by control inputs derived from the input volt-
age, output voltage and output current, which are all monitored by error amplifiers
within IC9 whose outputs directly control its internal PWM pattern generator.

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The input and output voltage sense signals are resistively coupled to provide a
common voltage control input to IC9 pin 1. The input voltage is monitored
through CV1, R16, R15, R51 and CV2; and the output voltage is monitored by a
dedicated winding on the output transformer (4-6) and connected to CV2 via a
rectifier bridge comprising D9 and D10. Thus the voltage at CV2 is sensitive to
changes in both input and output voltage.
Resistor TM1 is connected in parallel with the voltage sense input to IC9 pin 1
and enables the output voltage to be calibrated.
When the UPS is first powered up the DC bus voltage is initially zero and increas-
es at a controlled rate as the rectifier phases forward (due to the Rectifier Logic
Board control features). To prevent the ‘sensed’ lack of DC voltage causing the
PWM generator to surge forward, a soft-start circuit is incorporated into the cir-
cuit design, built around TR9.
In addition to providing a control input to IC9 pin 1, the dc busbar voltage is also
connected to IC9 pin 12, which is its Vcc supply input. From this supply IC9 in-
ternally generates a stable 5V rail which it outputs at pin 14 to provide operating
power for the remaining integrated circuits. It also provide a stable reference volt-
age at pins 2 and 15 for the use of the IC9’s internal error amplifiers.
Note: IC9 can operate with its Vcc supply in the range 7-40Vdc, which more than
caters for the DC busbar voltage variation while the UPS is operating on battery
power – i.e. the power supply operating window is 240Vdc to 700Vdc on the DC
busbar.
The power supply’s output current is monitored by T1 which is a current trans-
former connected in series with the output transformer (T2) primary. T1 second-
ary is rectified by D15–D18 and a current-proportional voltage is developed
across burden resistor R13 which is fed back to IC9 pin 16 as an input to its inter-
nal current error amplifier where it alters the PWM output.

3.3.3 Inverter and transformer sections

The inverter circuit converts the controlled dc voltage rail into an alternating
waveform and basically comprises transformer T1 and fets TR7 and TR8.
One end of T1 primary is connected to the junction of C3 and C4 (in series with
the current sense transformer T2), and the other to the junction of TR8 and TR7.
When considering AC, these components effectively form a bridge, and current
will flow through T1 in either direction depending on whether TR8 or TR7 is
turned ON. The transistors’ drive signals are fixed at 20kHz and transformer cou-
pled in such a way that only one device is allowed to turn on at a time (i.e. they
are switched in anti-phase) thus AC current is set up in T1 primary.
T1 has three secondary windings; one provides a nominal 36Vac (@20kHz) out-
put, the second provides the ±12 Vdc outputs (after rectification) and the third
provides an output voltage feedback signal to the chopper voltage regulation cir-
cuit.
The 20kHz transistor drive signals are obtained from IC9. The frequency is con-
stant and determined by R39 and C22, which are connected to IC9 pins 5 and 6.
The oscillator output is applied to a phase splitter circuit (IC7) which provides
complementary signals through IC6, IC5, IC4 and driver transistors TR1–TR4 to
the driver transformer T3 primary. The passage of these signals can be interrupted
at IC6 by a logic low from the fault detection latch (IC8), in which case the power
supply outputs are immediately cut off.

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CHAPTER 3 - DC-DC Power Supply

3.3.4 Fault detection

Fault detection is achieved by IC10 which is configured as four comparator cir-
cuits.
One input to each comparator is connected to a 2.5V reference voltage derived
from voltage regulator IC2.
IC10b/c output pins 1 and 14 go low in the event of an overvoltage or overcurrent
condition respectively. This trips the latch formed by IC8, making IC8 pin 11 go
high to illuminate LS3 and pin 4 go low to inhibit the inverter driver signals. The
logic low at IC8 pin 4 is also taken to IC8 pin 9 to force pin 10 high and turn on
TR11. When this transistor is turned on it effectively short circuits C23 which
takes IC9 pin 4 to logic high (5V ref) and shuts down the ic operation.
IC10a pin 11 monitors the input (dc bus) voltage at the junction of R15 and R51,
and IC10d pin 5 monitors the output feedback voltage from T1 secondary. These
comparators operate for undervoltage conditions and their logic low output shuts
down IC9 via TR11 as described above.
IC10 pin 13 monitors the input voltage to detect an undervoltage (<230Vdc). In
such an event it latches OFF the drive signals and illuminates LS3. If CV2 is
opened the minimum operating voltage is increased to 290Vdc.
IC10 pin 2 monitors the output voltage to detect when the supply goes above
14.5V (approx.). In such an event it latches OFF the drive signals and illuminates
LS3.
During start-up these devices ‘enable’ the inverter driver logic by placing a logic
low at IC8 pin 6 when the input voltage rises above its ‘undervoltage’ threshold.

3.3.5 Indications
There are three leds on this board. LS3 is red and illuminates when a shutdown
signal has been generated by the fault detection logic. The other leds are both
green and are both lit during normal operation. LS1 signifies the presence of the
12Vdc outputs and LS2 shows the presence of the input supply.

3.4 Calibration details

This board is fully calibrated during the manufacturer’s final bench testing proce-
dure and should not require further adjustment when being fitted to the main
equipment. The only adjustment is TM1 which is used to calibrate the ±12V
output supply rails.

Caution If you need to alter this potentiometer make all adjustments very slowly.
As a parallel voltage source is applied to the control logic boards from the AC-DC
power supply board, when adjusting TM1 you should always monitor the DC-DC
Supply Board’s output voltage across the board’s output diode bridge and not at
the supply rails on the control logic boards.

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 Section 4: Rectifier Operation & Control

Chapter 1 - Rectifier Operating Principles

1.1 Introduction .............................................................................................. 4-1
1.2 SCR principles .......................................................................................... 4-1
1.2.1 Internal semiconductor structure .................................................. 4-2
1.2.2 SCR triggering mechanisms ........................................................ 4-3
1.2.3 SCR Turn-on characteristics ........................................................ 4-6
1.2.4 SCR Turn-off mechanisms .......................................................... 4-7
1.2.5 SCR turn-off characteristics ......................................................... 4-8
1.3 SCR Ratings ............................................................................................. 4-9
1.4 Phase control techniques ........................................................................ 4-11
1.4.1 Basic phase-control principles ................................................... 4-11
1.4.2 3-phase controlled rectifier ........................................................ 4-13
1.5 Rectifier construction ............................................................................. 4-14
1.6 Rectifier control system .......................................................................... 4-17
1.6.1 Control system overview ........................................................... 4-17
1.6.2 Charge mode selection ............................................................... 4-19
1.6.3 Input supply fault detection. ...................................................... 4-19
1.6.4 Input current limit ...................................................................... 4-19
1.6.5 Battery current limit ................................................................... 4-19
1.6.6 Battery temperature compensation ............................................ 4-19
1.6.7 Controlled start/stop ................................................................... 4-20
1.6.8 DC overvoltage and undervoltage fault detection ..................... 4-20
1.6.9 Battery Circuit Breaker .............................................................. 4-20

Chapter 2 - Rectifier Logic Board

2.1 Chapter overview ................................................................................... 4-21
2.2 General description ................................................................................. 4-21
2.2.1 Circuit board functions .............................................................. 4-21
2.2.2 Input/Output connections ........................................................... 4-21
2.2.3 Block diagram description ......................................................... 4-23
2.3 Detailed circuit description .................................................................... 4-26
2.3.1 Introduction ................................................................................ 4-26
2.3.2 Reference voltage generator ...................................................... 4-26
2.3.3 Battery temperature compensation ............................................ 4-27
2.3.4 Volts error amplifier .................................................................. 4-27
Battery current limit ......................................................... 4-29
Input current limit ............................................................ 4-29
Start/Stop control ............................................................. 4-30
2.3.5 Drive pulse generator ................................................................. 4-31
Analogue timing control circuit ....................................... 4-31
Digital signal processing .................................................. 4-33

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SECTION 4 - Rectifier Operation & Control 7200 Series UPS Service Manual

2.3.6 Start/Stop logic .......................................................................... 4-35

Input mains phase rotation error ...................................... 4-35
Input mains undervoltage ................................................. 4-35
ON/OFF control from UPS Logic Board ......................... 4-36
Control power supply failure detection ............................ 4-36
2.3.7 Control power supplies .............................................................. 4-36
2.4 Summary Information ............................................................................ 4-37

Chapter 3 - Rectifier Gate Drive Interface Board (4542040W)

3.1 Introduction ............................................................................................ 4-39
3.2 Rectifier SCR gate drive requirements ................................................... 4-39
3.3 Gate drive circuit .................................................................................... 4-40

Chapter 4 - Rectifier Snubber Board (4540043B)

4.1 Snubber requirements and characteristics .............................................. 4-41
4.2 Snubber board ......................................................................................... 4-42

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 Section 4:

Chapter 1 - Rectifier Operating Principles

1.1 Introduction
The 7200 series UPS employs a fully controlled, 3-phase SCR bridge rectifier to
provide a regulated DC busbar suitable for charging the UPS batteries and present
the inverter with a stable input voltage. This chapter describes the principles of
operation of an SCR device and its use in a phase-controlled rectifier circuit.

1.2 SCR principles

The Thyristor, or Silicon Controlled Rectifier (SCR), is a three-terminal device
which was first introduced to the power electronics industry in 1957. It is essen-
tially a solid-state switch which is normally triggered from its non-conducting
state (OFF condition) to its conducting state (ON condition) by a pulse applied be-
tween its gate and cathode terminals. In general, in its ON-state the SCR acts as a
unidirectional conducting device and blocks current flow in the reverse direction
(cathode-to-anode). In its OFF-state, it blocks current flow in both directions.

Figure 4-1: SCR principles (summary)

SCR – Three Terminal Device ANODE

An SCR is a three-terminal device which

can be considered to act as an GATE
CATHODE
electronically controlled switch.

SCR – Switch Analogy

SCR ON
current flow anode-cathode
That is, when an SCR is turned ON
(conducting) the forward voltage ANODE
drop between its Anode and
Cathode is small and can be
+
considered to be short-circuit for all
practical purposes. CATHODE
–
SCR OFF
no current flow
Alternatively, in its non-conducting
ANODE (OFF) state the SCR presents a
very high Anode/Cathode imped-
ance and can be considered to be
open circuit – like an open switch.
CATHODE

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CHAPTER 1 - Rectifier Operating Principles

1.2.1 Internal semiconductor structure

The SCR structure comprises four alternate ‘P’ and ‘N’ type semiconductor lay-
ers. Figure 4-2 shows how these layers can be ‘split’ to form a pair of intercon-
nected P-N-P and N-P-N transistors; annotated T1 and T2 in the diagram.

Figure 4-2: SCR – Regenerative transistor analogy

Anode A Anode B Anode C Anode IA D

P1 P1

T1 (PNP)
N1 N1 T1
N1 I2
Gate I1

T2 (NPN)
Gate P2 Gate P2
P2 Gate
N2 T2
N2 Ig
Cathode
Cathode Cathode Cathode

With reference to the transistor model above, the two transistors are connected in
a regenerative manner – i.e. ignoring the gate current (Ig), T2’s collector current
(I2) is drawn through T1 emitter-base junction (turning T1 on) and T1’s collector
current (I1) flows through T2 base-emitter junction (turning T2 on). This can be
expressed mathematically as I2 = αΤ2 x I1 (where αΤ2 is the current gain of T2)
and I1 = αΤ1 x I2 (where αΤ1 is the current gain of T1).
Regeneration occurs when the sum of the current gain of both transistors (αT1 and
αT2), also described as the ‘loop gain’ of the two transistors, is greater than unity;
at which point the transistors try to turn ON each other harder and harder until
both devices rapidly reach full saturation. This equates to the SCR being in its
conduction state, whereby the voltage drop across the device is approximately
1.0V and its anode current is determined only by the external voltage and load im-
pedance.
As with a normal transistor, the current gain αT1 and αT2 varies proportionally
with emitter current, and in the absence of any gate signal the only current initially
flowing through the transistors is a leakage current comparable to with the reverse
current of a diode. Under these conditions the value of the current gain associated
with each emitter falls to a very low figure, and the device is designed such that
the ‘loop gain’ is made less than unity, and the transistors remain non-conducting
– i.e. this is equivalent to the SCR’s non-conducting ‘forward blocking’ state. In-
deed, the fact that the two emitter-base pairs need be designed only for an average
value of α of 0.5, to produce the effective unity loop gain necessary to make con-
duction self-sustaining, makes it possible to use relatively thick base layers, and
hence obtain a much greater voltage blocking capability than in a practicable tran-
sistor.
In summary, the SCR can be triggered from its non-conducting to conducting
state by increasing the circulating current through T1 and T2 to the point where
the loop gain rise above unity. This may be accomplished by several means, some
of which are undesirable, as described below.

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1.2.2 SCR triggering mechanisms

Breakover voltage

Figure 4-3: SCR static characteristic with zero gate current

IA
Forward

Conducting

Holding
Current
Reverse
VAK
Forward
Avalanche Blocking
Breakdown Breakover
Voltage

Reverse

Figure 4-3 illustrates the static characteristics for the SCR anode current (IA) and
anode-cathode voltage (VAK) with zero gate current. This shows that in the reverse
direction the SCR characteristic is similar to that of a normal diode, in that very
little current flows as the reverse voltage increases until the reverse avalanche
breakdown point is reached, where-upon the current rapidly increase.
In the forward blocking region, increasing the forward voltage does not tend to
increase the leakage current until the point is reached where avalanche multipli-
cation begins to take place. Past this ‘breakover voltage’ point, the leakage current
increases quite rapidly until the total current through the device is sufficient to
raise the internal loop gain ≥ 1 whereupon the SCR switches to its conduction
state provided the anode current remains in excess of a minimum current known
as the ‘holding current’. When the anode current falls below the holding current
the loop gain falls below unity and the device will revert to its forward blocking
(non-conducting) state.
Albeit not necessarily destructive, this means of triggering the SCR is undesirable
(especially in phase-control applications) and usually avoided by employing a
device whose forward breakover voltage and peak inverse voltage ratings are well
outside the available circuit voltage. Additionally, external components may be
used to prevent spurious voltage spikes inadvertently triggering the device by this
means.

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CHAPTER 1 - Rectifier Operating Principles

Gate triggering

Figure 4-4: Effects of gate current on triggering

IA
Forward
Conducting

Ig2 > Ig1 > Ig0

Holding
Current Ig2 Ig1 Ig0

Reverse
VAK
Forward
Avalanche Blocking
Breakdown

Reverse

The usual method employed to trigger the SCR from the ‘blocking’ to the ‘con-
ducting’ state, is to inject sufficient current into the gate terminal (T2 base) to in-
crease the current in the main circuit by the modest amount required to raise the
loop gain to greater than unity. That is, the injected gate current (Ig) leads to an
increase in I2 which in turn leads to an increase in I1, which further increases I2....
and so on, until both transistors are saturated.
Figure 4-4 shows that for increasing magnitudes of gate current, the region of
characteristics between breakover current and holding current is narrowed and the
effective forward breakover voltage is reduced. For sufficiently high gate currents
the entire forward blocking region is removed and the V-I characteristics are es-
sentially identical to those of a P-N rectifier.
This is a very advantageous mode of operation, since it is possible to use a device
with a forward breakover voltage much higher than any voltage likely to be en-
countered in the circuit, and use only a moderate amount of trigger power to start
the high-conduction state.
Once the gate has been used to trigger the device into conduction it loses control
and can be removed without affecting the external circuit’s operation – i.e. once
the SCR is conducting, the anode current is determined solely by the external cir-
cuit’s voltage and impedance, and the only method of turning the device off is to
reduce this to below the SCR’s holding-current level. To minimise internal losses
and heating effects, it is usual therefore not to apply the gate current for much
longer than is necessary to assure the device turns on; for this reason the gate
signal normally takes the form of a current pulse of sufficient amplitude and du-
ration to ensure this condition is satisfied.

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Figure 4-5: Gate drive parameters spread

A Maximum
gate current
12 allowed

Maximum

Gate Voltage (V)

gate voltage
9 allowed
SAFE
OPERATING
AREA Maximum
gate power
6 dissipation
(V x I)

3 B
Minimum
gate voltage
allowed
Minimum 0.5 1.0 1.5 2.0
gate current
allowed Gate Current (A)

As can be seen from Figure 4-5, the spread of gate voltage versus gate current can
be quite wide for different load variations. The gate circuitry must therefore be
able to accommodate this variation and also allow for different sizes of SCR. Typ-
ical design values are for 6V and 1A pulses for 10µsec.

dV/dt triggering
As with all semiconductor devices, there are internal capacitive effects between
the various ‘P’ and ‘N’ layers, and between the electrodes. In the case of the SCR
these effects can turn-on the device inadvertently if the rate of change of voltage
applied to it are sufficient to raise the current flow to a level which raises the in-
ternal loop gain above unity:
– [Link] current flowing through the capacitor = CdV/dt and has the same effect
as injecting a gate current if allowed to increase to the appropriate level.
As with the breakover-voltage triggering mechanism described above, this
method of turning on the device is not generally used as it is uncontrollable and
is normally prevented by connecting additional components (known as snubbers)
across the device to limit the rate of such voltage changes (see paragraph 4.1 on
page 4-41).

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CHAPTER 1 - Rectifier Operating Principles

1.2.3 SCR Turn-on characteristics

Figure 4-6: SCR turn-on characteristics

VAK x IA
Power
Dissipation

0 t

VAK
90%

Voltage across
SCRs
10%
0 t

IA
90%

Anode
Current
10%
0 t
td tr

ton

Gate
Current
10%
0 t

As described previously, two basic conditions must be satisfied in order to turn

on an SCR. First, the device must be forward-biased – i.e. its anode must be pos-
itive with respect to its cathode; second, a suitable current pulse must be injected
into its gate terminal. When both these conditions are satisfied, the device will
turn ON and an anode-cathode current will flow through the device depending on
external circuit parameters.
In detail, the turning-on of an SCR in response to a gate trigger signal may be con-
sidered to take place in three phases. First, a delay occurs before any kind of sig-
nificant response is apparent. Secondly, under the direct influence of the gate
current, conduction is established in a small area adjacent to the gate. Finally, the
conducting area spreads with a fairly constant velocity, no longer influenced by
the gate, until the whole area is conducting.
Corresponding to the increase in conducting area, the resistance of the cell falls
from the near-infinite ‘blocking’ value, rapidly to a relatively high value while
conduction is concentrated in the gate region, and then relatively to a the steady
state value. The instantaneous voltage drop thus follows a waveform such as that
illustrated in Figure 4-6, resulting in an instantaneous power dissipation:
w = VAK x IA .

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Conventionally, as shown in Figure 4-6, the total switching time is divided into
the delay time (td) and the rise time (tr); these periods are arbitrarily delimited, for
the purpose of measurement, at the instants when the voltage across the SCR falls
to 90% and 10% of the initial blocking voltage. The rise-time (tr) is defined as the
time required for the anode voltage to drop from 90% to 10% of its forward block-
ing value. The rise of current as voltage across the SCR falls is determined largely
by the external circuit. In a purely resistive circuit the current will rise in the same
manner as the voltage falls; hence the term “rise time”. It is important that the in-
stantaneous current-voltage product during the turn on interval does not exceed
the device dissipation capability. For this reason, the rate of rise of anode current
(di/dt) must be limited. The “delay time” (td) is reduced as the gate current is in-
creased; however there are other considerations that affect the chosen gate signal,
as described later (see paragraph 3.2 on page 4-39).

1.2.4 SCR Turn-off mechanisms

To turn an SCR OFF its anode-cathode current must be reduced below the ‘hold-
ing current’ value, which is usually very small. This can be achieved by interrupt-
ing the current flow externally, by opening an switch for example, or by some
means reverse biasing the anode-cathode potential – i.e. making its anode nega-
tive with respect to the cathode.
The processes of turning off an SCR by reversing its anode-cathode voltage is
known as “commutation”; and can broadly be divided into two forms described
as either “natural” or “forced” commutation.

Figure 4-7: SCR Turn-off mechanism

Anode A Anode B
IA

P1 +
J1
N1 –
Gate J2
Gate P2 +
J3
N2 –
Cathode
Cathode

Referring to Figure 4-7, when an SCR is conducting, each its three semiconductor
junctions (J1-J3) are forward-biased and the two base regions (N1 & P2) are
heavily saturated with holes and electrons (stored charge).
When the SCR is commutated by the application of a reverse anode-cathode volt-
age, the holes and electrons in the vicinity of the two end junctions (J1 & J3) will
diffuse to the junctions and result in a reverse current in the external circuit. The
voltage across the SCR will remain at about 0.7V as long as an appreciable re-
verse current flows. After the holes and electrons in the vicinity of J1 and J3 have
been removed, the reverse current will cease; the junctions J1 and J3 will assume
a blocking state and the voltage across the SCR will then increase to a value de-
termined by the external circuit. However, recovery of the device is not complete,
since a high concentration of holes and electrons still exists in the vicinity of the
centre junction (J2). This concentration decreases by the process of recombina-
tion in a manner which is largely independent of the external bias conditions.
After the hole and electron concentration at J2 has decreased to a low value, J2

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will regain its blocking state and a forward voltage may then be reapplied to the
SCR without turning it back on. The time that elapses after the cessation of for-
ward current flow and before forward voltage may safely be applied is called the
SCR “turn-off” time (toff), and can typically range from 3µsec to 50µsec depend-
ing on the design and construction of the particular device.

1.2.5 SCR turn-off characteristics

Figure 4-8: SCR turn-off characteristics

Anode-Cathode
Current
trr
0

tfb
toff

Voltage across 0
SCRs

t1 t2 t3 t5 t7 t9 t10
t6
t4
t8

Figure 4-8 illustrates graphically the (some-what idealised) effects on the SCR
voltage and current of the turn-off mechanism described above. The total turn-off
time (toff) is the total time between the anode current falling to zero (t3) and the
device being capable of supporting a forward voltage (t8). This is shown to com-
prise two components. First the reverse recovery time (trr) (t3 to t6) followed by
the forward blocking time (tfb) (t6 to t8). These intervals are not constant, but are
a affected by several, mainly external, parameters.
For example the turn-off time will increase with:
• An increase in junction temperature.
• An increase in forward current amplitude (t1 to t2).
• An increase in the rate of decay of forward current (t2 to t3).
• A decrease in peak reverse current (t4).
• A decrease in reverse voltage (t5 to t7).
• An increase in the rate of reapplication of forward blocking voltage (t8 to
t9).
• An increase in forward blocking voltage (t9 to t10).
• An increase in external gate impedance.
• A more positive gate bias voltage.

‘Natural’ versus ‘forced’ commutation

As its title suggests, ‘natural’ commutation takes place automatically when the
voltage across the SCR reverses as part of the external circuit function – this is the
case in the phase-controller application, as the device is fed with the input a.c.

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mains supply and is ‘naturally’ reverse-biased on every negative half-cycle. As

this happens at 50Hz, the reverse voltage is maintained across the SCR for several
tens of milli-seconds and presents no commutation timing problems.
‘Forced’ commutation is used when the SCR is fed from a DC source, such as in
an inverter application. Under such circumstances the reverse voltage must be
generated by a dedicated commutation circuit which must present a reverse volt-
age pulse of sufficient magnitude and duration to ensure the device has time to
fully turn off under all rated load conditions. (Note: in the 7200 series UPS the
inverter section is transistor based so this does not apply).

1.3 SCR Ratings

Junction temperatures
Power losses in an SCR produces thermal energy (heat) which must be conducted
away from the junction region. Heat dissipation is achieved by mounting the SCR
on a suitable heatsink – the heat developed within the device then flows via the
device case and heatsink to the ambient air, and can be dispersed by fan extraction
if necessary.
The maximum operating junction temperatures are typically 125°C - 150°C.
Heat losses are a function of:
• ON-state conduction losses –
A product of the voltage drop across the device (about 1.5V) and the
amount of current flowing through it. This can be as high as 500W.

• OFF-state losses –
These losses are due to leakage current and are therefore very small.

• Switching losses –
The heat generated during turn-on and turn-off is a function of the voltage
across the device and the current flowing through the device at the time of
switching. These losses can be very large but exist for a very short dura-
tion only, as illustrated in the characteristic curves shown previously.

An upper temperature limit must be imposed to restrict mechanical failure and

prevent excessive temperatures to internal joints and leads (which may interfere
within the device package). When such a temperature limit is imposed (e.g.
125°C) it will have a direct affect on the device rated current capability.

Current ratings
Several rated current conditions can be stipulated in the device specification; and
thermal breakdown is likely if any one of these values are exceeded.
• Average current rating (IAV) –
This is the maximum average ON-state current the device may conduct
continuously.

• RMS Current rating (IRMS) –

This is the maximum RMS ON-state current the device may conduct con-
tinuously – i.e. this is the steady-state operating current.

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• Peak Current rating (IPK) –

This is the repetitive surge current the device may conduct at a specified
short pulse-width.

• I²t rating (I²t) –

This is the maximum forward non-repetitive surge current (i.e. Overload
current) capability, and is usually specified for one half cycle of 50Hz
operation.

Voltage ratings
• Maximum Forward Voltage (VFBO) –
This is the maximum forward voltage that can be applied across the device
(anode-to-cathode) without the device being forced to turn on.
There is always a small anode-to-cathode leakage current when a voltage
is applied to the device, and if the voltage is increased to the critical VFBO
the SCR will switch rapidly into full conduction. This is not dangerous to
the device itself, but may cause a short circuit within the rectifier if other
SCRs are already conducting when this false triggering occurs.

• Maximum reverse voltage (VRBO) –

This is the maximum reverse voltage that can be applied across the device
(cathode-to-anode) without the device being forced into reverse break-
down. If VRBO is exceeded it will lead to destructive breakdown, and the
SCR will not recover (that’s blown it!).

• Maximum rate-of-change (dv/dt) –

A very high rate of increase of forward (anode-to-cathode) cathode dv/dt
can turn on the SCR, even though there is no gate signal and VFBO is not
exceeded (see page 4-5).

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1.4 Phase control techniques

‘Phase control’ of the power rectifier is made possible by the fact that it contains
SCRs (Silicon Controlled Rectifiers - also called Thyristors), rather than straight-
forward power diodes.

1.4.1 Basic phase-control principles

Figure 4-9 shows a single SCR connected in a simple AC circuit and can be used
to illustrate the basic principles of phase control techniques.
Note: although a half wave rectifier circuit is shown, this circuit has no practical
use in the 7200 equipment but is used only to simplify explanation.

Figure 4-9: Simple half-wave rectifier circuit

Vin ( peak ) × 2
Vdc ( mean ) = ----------------------------------------
π

Vin(peak)
Vdc(mean)

Input
AC
+

Max Output
SCR gate permanently
RL
turned ON

Mean
DC

Input 0V
AC Min. Output
SCR gate permanently
RL turned OFF

The top diagram shows the situation where the SCR receives a permanent gate
drive signal – i.e. the gate is permanently positive with respect to the cathode. In
this condition the SCR passes current during the whole of the input AC waveform
positive half-cycles but blocks the negative half-cycles, as the anode-cathode are
reverse biased during the ‘reverse’ periods – i.e. the SCR is said to be ‘naturally
commutated’ at the end of each positive half-cycle. This results in a ‘half-wave
rectified’ voltage being developed across the load resistor, and the SCR can be
seen to be acting in the same manner as a normal rectifier diode. Note that in this
example the mean (d.c.) load voltage is approximately 0.45 times the input peak
voltage, and is shown as a dotted line superimposed on the output waveform.
In the lower diagram the SCR gate drive voltage is removed altogether and under
these circumstances the SCR is permanently turned off during both the positive

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and negative half-cycles of the input voltage waveform. In this case the mean
(d.c.) load voltage will of course be zero.
The two conditions described above illustrate how the ‘maximum’ and ‘mini-
mum’ load voltages are obtained. The description on the following page shows
how phase control techniques may be used to vary the mean load voltage to any
point between these two extremes.

Figure 4-10: Simple controlled rectifier; showing 45° and 90° output waveforms

SCR conducts only during the shaded Vdc(max)

period of the input positive half-cycle
Vdc(mean)

Input 0V
AC Output waveform at 45° delay –
RL Vdc(mean) is slightly less than the maximum
0 90 180 270 360 available dc voltage Vdc(max)

Gate ON

SCR turned ON by gate pulse

Vdc(max)

Vdc(mean)
Input
AC
0V
0 90 180 270 360 RL Output waveform at 90° delay –
Gate ON Vmean is even less than that achieved
at 45° delay

The examples on the previous page showed that the mean voltage, Vdc(mean),
produced by the simple half-wave rectifier circuit is at a maximum when the SCR
is turned on throughout the whole of its positive (forward biased) half cycle, and
at a minimum when the SCR gate is totally devoid of a drive signal.
When used in a phase-controlled circuit, the mean voltage, Vdc(mean), is varied
between these two extremes by applying the gate drive signal at a variable point
in its forward biased half-cycle – as illustrated in Figure 4-10. In the top diagram
the SCR gate is triggered when the input waveform is 45° into its positive half
cycle. The SCR therefore conducts during the period between 45° and 180° only
– i.e. it is not turned on between 0° and 45°, and is turned off by natural commu-
tation at 180°. As shown in the top waveform diagram, under these circumstances
the mean dc voltage Vdc(mean) is slightly less than maximum Vdc(max).
In the lower diagram the SCR gate trigger is delayed by a further 45°, to a total of
90°, which leads to a corresponding fall in mean output voltage, as shown.
This is the basic principle of a ‘phase-controlled’ rectifier – i.e. controlling the
mean DC voltage between its maximum and minimum limits by controlling the
variable phase delay between the point at which the SCR becomes forward biased
and the application of its gate drive signal.

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The terms “phase forward” and “phase back” are used in ‘power engineering’
fields to describe the action of advancing or retarding the gate drive signal respec-
tively – e.g. “phasing forward” the rectifier implies that the SCR is turned on ear-
lier in its forward conduction cycle and more energy is therefore allowed through
the rectifier, leading to an increased mean DC voltage.

1.4.2 3-phase controlled rectifier

The 7200 series UPS uses a three-phase controlled bridge rectifier, as shown in
Figure 4-11. The circuit is similar to a standard diode bridge rectifier but compris-
es 6 SCRs in place of the more usual diodes, and each SCR is phase controlled in
the manner described on the previous pages.

Figure 4-11: Basic three-phase bridge rectifier circuit

R+ S+ T+
Shaded area shows R+
SCR forward biased
period

0 90
Return path period: 30 150

first via S- SCR

then via T- SCR S– T– R– S–

R+ R+ S+ T+

R (load)
S– current
T– current R– S– T–

R–

Each SCR controls the rectifier conduction during one half cycle period of an
input cycle. Taking the R phase as an example, the top SCR (R+) controls the R
phase positive half cycle, and the lower SCR (R–) controls the negative half cycle.
Looking at the R phase positive half cycle (R+) in detail, the three-phase wave-
form diagram shows that this device is forward-biased only for a 120° period be-
tween 30° and 150° of the incoming R phase waveform. This is true of all six
SCRs and means that the bridge output voltage can be controlled over its full
range by controlling the individual SCR conduction angles between 30° and 150°.
In practice all six SCRs are controlled such that their conduction phase angles are
identical, therefore the rectifier load current is shared equally between all three
phases.
Note: in the practical 7200 circuit, the ‘load’ comprises the DC Busbar filter
(smoothing) capacitors, the batteries (when the battery circuit breaker is closed)
and the power inverter section. The rectifier SCRs are thus controlled at the phase
angle necessary to maintain the DC Bus voltage at the required battery charge
voltage while at the same time passing the power demanded by the inverter to
enable it to produce its correct output voltage over a wide load range.

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1.5 Rectifier construction

The rectifier power components and the static switch power components are as-
sembled on the same heatsink , as illustrated below.

Figure 4-12: Power rectifier construction

Connections to snubber boards

Bypass SCRs and gate drivers
STATIC BYPASS
MAINS FEED
RECTIFIER 3-Ph
MAINS FEED

Connections to snubber board

Input current CTs and gate driver

Rectifier SCRs

RECTIFIER OUTPUT
DC Busbar
Gate Driver (trigger) Snubber board
board

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Figure 4-13: Rectifier assembly wiring details

G2
Yellow

2 1
X6
Black Red

5
T8

K2
White V6
X3

2 1
X8
3
1 4

C
Black

G1
1

Yellow

2 1
X5
Red

K1

X7
G2
Yellow

4542040W
2 1
4540043B

X4
Black Red
5

K2
White V5
X2
3

B
Black

G1
1

Yellow

2 1
X3
Red

K1
G2

Yellow

2 1
X2
Black Red
5

T7
K2

White V4
X1
3

1 4
A

Black
G1
1

Yellow

2 1
X1
Red
59

58
57

K1

From Interface PCB

+

45900540 (X18)
-

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Depending on the module rating, the rectifier SCRs can take the form of ‘Twin-
pak’ or individual devices. As their name suggests, ‘Twinpak’ devices contain
two SCRs in a single moulded package (See Figure 4-14). As shown, the anode
of one device is internally connected to the cathode of the other, and brought out
to a power connection along with the remaining free anode and cathode. This then
forms a convenient package for the phase controlled rectifier application, with the
a.c. input connected to the common power connection and the DC Bus positive
and negative connections made to the appropriate anode and cathode, as shown.
Separate gate connections are provided, with connection G1 being internally con-
nected to the (+) SCR and G2 to the (–) SCR.
Where ‘single’ devices are used, their anode, cathode and gate connections are in-
dividually identified.
The gate drive signals take the form of a high frequency modulated waveform 2
which is produced by the Rectifier Logic Board and present whenever the partic-
ular SCR is due to be turned on. The gate signal is not required once the device is
turned on, in practice it is applied only for a short burst which avoids excessive
wear on the SCR gate material (see paragraph 3.2 on page 4-39).
The Rectifier Logic Board gate drive signals are connected via ribbon cables to
the Driver Interface Board which contains snubber components designed to
ensure ‘clean’ rectifier SCR switching, and is mounted on the rectifier assembly
itself. This board applies the drive signals to the SCR gate/cathode via twisted pair
cables – note that an auxiliary cathode connection is often provided on the SCR
device for connecting to the negative end of the gate drive cables.

Figure 4-14: ‘Twinpak’ SCR internal details

AC Input

+VE DC BUS

–VE DC BUS
+VE SCR Gate (G1) –VE SCR Gate (G2)

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1.6 Rectifier control system

Figure 4-15: Rectifier control system

Input Input
Rectifier Assembly DC Busbar
Isolator Fuses
filter capacitors DC Bus Pos
Input mains

Phase TO INVERTER
Input
Controlled SECTION
Choke
Rectifier
DC Bus Neg
+
-
Drive

DC Bus voltage sense

Battery current sense

Interface Bd.
Input voltage sense

Input current sense

Battery
Breaker

Battery
Rectifier Logic Board

Operator Logic Board UPS Logic Board Alarm Interface Board

(I/O Option)

Remote Alarms
Operator Control
Panel High Voltage ON GENERATOR
Interface Board

External Control Options

1.6.1 Control system overview

Figure 4-15 shows the control boards associated with the rectifier control together
with their major control signals.
The Rectifier Logic Board is central to the rectifier control system and is the board
ultimately responsible for generating the rectifier SCR gate drive signals at appro-
priate phase angles to effect the phase-control techniques described earlier in this
chapter. At its heart is a complex, analogue voltage regulation circuit which uses
the input voltage, input current, DC bus voltage and battery current sense signals
within a series of closed-control loops.
The control system offers the following features, each of which is functionally de-
scribed in the remainder of this chapter:
• charge mode selection – i.e. automatic and manually controlled switching
between float and boost charge modes (where applicable).
• adjustable input current limit and battery current limit functions.
• individually adjustable float, boost, and manual voltage reference levels.
• battery temperature compensation which reduces the DC bus voltage pro-
gressively if the battery cabinet temperature rises above 25°C.
• input supply fault detection.
• DC overvoltage and undervoltage fault detection.
• controlled start/stop features.

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[Link] Analogue control signals

Input mains voltage sense

The 3-phase input mains voltage is attenuated on the High Voltage Interface
Board and three line-line proportional sense signals are passed to the Rectifier
Logic Board where they provide zero-crossing reference signals for the phase-
control timing circuits and are also monitored by ‘input undervoltage’ and ‘input
phase sequence’ fault detection circuits.

Input current sense

The rectifier input current is detected by CTs fitted to the power rectifier assem-
bly. The signals produced by these CTs are rectified on the High Voltage Interface
Board and a single ‘input current sense’ signal, proportional to the total input cur-
rent, is connected to the ‘input current limit’ circuit on the Rectifier Logic Board
via the UPS Logic Board.
Note: the sensitivity of this signal is selected by jumpers on the High Voltage In-
terface Board.

DC Bus (battery) voltage sense

The DC busbar voltage is a function of the rectifier output when the rectifier is
operative, and a function of the battery voltage when the rectifier is inoperative
and the batteries are discharging. This voltage is attenuated on the High Voltage
Interface Board and a proportional ‘DC voltage sense’ signal is passed to the Rec-
tifier Logic Board where it provides a feedback input to the rectifier voltage reg-
ulation control loop.

Battery current sense

Battery current is sensed by a “Hall-effect” DCCT connected in the battery posi-
tive line. The signal produced by the CT is rectified on the High Voltage Interface
Board and a current-proportional signal is connected to the ‘battery current limit’
circuit on the Rectifier Logic Board via the UPS Logic Board. The sense signal is
polarity-sensitive – i.e. a positive signal indicates a charging current, and vice
versa.
Note: the sensitivity of this signal is selected by jumpers on the High Voltage In-
terface Board.

[Link] Digital control signals

Various digital signals are passed between the UPS Logic Board and all the other
boards connect to it. These can broadly be categorised as:
• alarm data generated on the Rectifier Logic Board and UPS Logic Board
which are passed to the Operator Control Panel via the Operator Logic
Board – also to the Alarms Interface Board (for remote indication) where
fitted.
• rectifier metering data generated on the UPS Logic Board and passed to
the Operator Control Panel – e.g. input voltage, battery volts current
metering.
• control data entered at the Operator Control Panel which is stored by the
UPS Logic Board – e.g. boost charge parameters, DC voltage monitor
threshold parameters; manual selection of Rectifier ON/OFF status and
immediate Boost Charge mode.
• external control options – e.g. remote stop, emergency shutdown, ‘on-gen-
erator’ input current limit.

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1.6.2 Charge mode selection

Although the float, boost, and manual charge operating voltage levels are individ-
ually adjustable by potentiometers on the Rectifier Logic Board, the selected
mode of operation is determined by digital command signals generated by the
UPS Logic Board and applied to the Rectifier Logic Board control logic (See par-
agraph 2.3.2).
The automatic boost mode parameters (boost voltage level and duration, and
changeover threshold) are entered via the Operator Control Panel and stored in the
UPS Logic Board micro system. Changeover from float charge to either boost or
manual charge modes can also be initiated manually from the Operator Control
Panel at any time.

1.6.3 Input supply fault detection.

The input voltage sense signal is applied to ‘undervoltage’ and ‘phase sequence’
fault detection circuits on the Rectifier Logic Board which shut down the rectifier
and provide error signals to the UPS Logic Board under fault conditions (See par-
agraph 2.3.6). On the Rectifier Logic Board, led H9 indicates an input undervolt-
age error and H8 a phase sequence error.

1.6.4 Input current limit

On the Rectifier Logic Board, if the input current sense signal exceeds the ‘current
limit’ threshold (adjustable between 100%-130%) it phases-back the rectifier, and
reduces the DC busbar voltage to a level which maintains the input current at its
set limit level (See paragraph [Link]); it also sends an ‘input overload’ signal to
the UPS Logic Board which initiates an alarm on the Operator Control Panel.
Note: if required, the input current limit level can be automatically reduced by
25% when the UPS is operating on a stand-by generator. This facility is enabled
from the Operator Control Panel and initiated by auxiliary contacts of the ‘On
Generator’ contactor which are connected to the UPS Logic Board via the Exter-
nal Alarms Board.
Led H6 illuminates on the Rectifier Logic Board when the input current limit cir-
cuit is active.

1.6.5 Battery current limit

A ‘battery current limit’ circuit on the Rectifier Logic Board operates in a similar
manner to the ‘input current limit’ circuit described above, and phases-back the
rectifier to reduce the DC busbar voltage if the battery charge current exceeds a
predefined ‘current limit’ threshold (See paragraph [Link]). It also sends a ‘bat-
tery current limit’ status signal to the UPS Logic Board where it is used by the
software controlled automatic boost charge changeover function.
Led H5 illuminates on the Rectifier Logic Board when the input current limit cir-
cuit is active.

1.6.6 Battery temperature compensation

This is an optional control input to the Rectifier Logic Board which progressively
reduces the DC busbar voltage as the battery cabinet temperature rises above
25°C and is included to prevent reduced battery life due to the effects of overheat-
ing. The temperature is monitored by a thermistor located in the battery cabinet
which produces a temperature-variable signal on the High Voltage Interface

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Board which is then passed to the Rectifier Logic Board via the UPS Logic Board
(See paragraph 1.6.6).

1.6.7 Controlled start/stop

The Rectifier Logic Board contains a start/stop control circuit which effectively
turns ON/OFF the rectifier SCR drive signals. This circuit is affected by several
circuits on the Rectifier Logic Board itself (e.g. input undervoltage or phase rota-
tion error) and also by a start/stop signal produced on the UPS Logic Board in re-
sponse to various monitored ‘system-wide’ control signals (See paragraph 2.3.6).

1.6.8 DC overvoltage and undervoltage fault detection

The UPS Logic Board uses DC voltage sense signal to detect various critical DC
busbar voltage levels. DC Over/Under voltage conditions instigate a rectifier
shutdown and trip the battery circuit breaker. Other conditions produce a warning
alarm only; such as the “Low Voltage” which warn the operator of an impending
DC undervoltage (and therefore battery trip) condition.
Note: the operating threshold of these conditions are programmable via the Oper-
ator Control Panel.

1.6.9 Battery Circuit Breaker

The battery circuit breaker is manually closed but can be electrically tripped by
the UPS Logic Board. The circuit breaker cannot be initially closed until the DC
bus voltage rises above the DC Undervoltage trip level. Once closed, it will be
tripped by the UPS Logic Board if:
• the DC bus voltage rises to the DC Overvoltage level.
• the DC bus voltage falls below the DC Undervoltage level (i.e. with the
mains failed and the batteries discharged to their trip level).
• the emergency stop circuit is activated.

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 Section 4:

Chapter 2 - Rectifier Logic Board

2.1 Chapter overview

This chapter contains a circuit description of the Rectifier Logic Board used
across the whole 7200 Series UPS model range, and should be read in conjunction
with circuit diagram SE-4520074-A (4 pages). Signal annotations shown on the
circuit diagrams are shown in italics in the following text – e.g. [IREC>.

2.2 General description

2.2.1 Circuit board functions

The board is responsible for providing the drive signals for the rectifier SCRs at
the appropriate phase angle necessary to produce the required DC Bus (battery
charging) voltage. In so doing, the board monitors the following UPS parameters
via the High Voltage Interface Board and UPS Logic Board (See Figure 4-15):
• Input voltage – for SCR synchronisation and mains failure detection.
• Input current – for SCR current protection.
• DC Bus (battery) voltage – closed-loop voltage regulation.
• Battery current – for battery protection.
• Battery temperature – for battery protection.
• System control signals from the UPS Logic Board microcontroller (Run/
Stop; Charge mode selection; ‘On Generator’; Current limit selection;
soft-start to reduce dc bus capacitors’ inrush current on start-up).

As part of its control function, the Rectifier Logic Board detects several abnormal
operating conditions and provides the UPS Logic Board control system with the
following error status signals:
• Rectifier overload.
• Input supply phase rotation error.
• Input supply undervoltage.
• Rectifier On/Off.
• Control power supply failure.

2.2.2 Input/Output connections

The Rectifier Logic Board has four connectors, described below:
• X1 – Output SCR gate drive signals to Rectifier Driver Interface Board
4542040-W
• X2 – System control signals to/from the UPS Logic Board 4550007-H
(See Table 4-1).
• X3 – Control power supplies input from AC-DC Power Supply Board
4503030-M.
• X4 – Interface to second rectifier control circuit in a 12-pulse rectifier sys-
tem (optional facility not used in standard module).

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Table 4-1: Connector X2 pinout details

PIN I/O Function

1-4 I/O 0V – ground reference for digital electronics

5-8 O +12V power supply to UPSLB

9-12 O -12V power supply to UPSLB

13-14 I/O Common – ground reference for analogue sense inputs

15 I VREC_AC – Input mains voltage sense signal – phases U-W (approx. 15Vp-p)

16 I VREC_BA – Input mains voltage sense signal – phases V-U (approx. 15Vp-p)

17 I VREC_CB – Input mains voltage sense signal – phases W-V (approx. 15Vp-p)

18 I IB – Battery current sense signal

19 Not in use

20 I
IREC – Rectifier input current sense signal (6 pulses/cycle)

21-23 Not in use

24 O IREC_T – Used in parallel systems only (not available)

25 I VB – DC Bus (battery) voltage feedback – 3Vdc @ 432Vbus

26 I T_BAT – Battery cabinet temperature sensor – 2.98Vdc @ 25°C

27 I IDC_1 – Not used in standard model (12 pulse rectifier option only)

28 I IDC_2 – Not used in standard model (12 pulse rectifier option only)

29 I DB – Used in parallel systems only (used for input current sharing control)

30 I DB_0 – Used in parallel systems only (used for input current sharing control)

31 Not in use

32 O OVL_REC – Signals rectifier overload error status to UPSLB (Overload = 1)

33 O BLK_REC – Signals rectifier OFF/ON status to UPSLB (OFF = 1 and ON = 0)

34 O SEQ – Signals input mains phase sequence error status to UPSLB (Error = 1)

35 O IN_LOW – Signals low input volts error status to UPSLB (Low Volts = 1)

36 I ON-REC – Rectifier Run/Stop selection from UPSLB micro (RUN = 1 and STOP = 0)

37 I STAT – Reduced current limit selection (‘On generator’ = 1)

38 I REC_A – Charge mode selection from UPSLB micro

39 I REC_B – Charge mode selection from UPSLB micro

40 Not in use

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2.2.3 Block diagram description

The following illustration shows the Rectifier Logic Board at its most basic func-
tional block diagram level – each of the blocks shown is described in more detail
in the remainder of this chapter.

Figure 4-16: Rectifier Logic Board basic block diagram

Mains volts sense

(3-phase) sync signal Drive Rectifier
SCR
Pulse Drive
Generator Pulses
DC Control
Input I sense
Volts voltage
Batt I sense Error
Bus Volts F/B Amplifier

control line
DC Reference

Start/Stop
voltage

Batt temp sense Reference

Charge Mode Voltage
Selection Generator Fault
(UPSLB)
Detection
Start/ Logic
Bi-directional
Control Stop
(UPSLB) Logic

Power
AC-DC Supply
Supply

Phase control principles

The board regulates the DC busbar (battery charging) voltage using standard
phase controlled techniques – i.e. by controlling the point at which each rectifier
SCR is turned on during its forward biased period. This is achieved by detecting
the point at which each SCR becomes forward biased and then applying a variable
time delay between this point and the production of its gate drive pulses. Maxi-
mum DC busbar voltage is obtained when the delay is very short, whereupon the
SCRs are allowed to conduct for the whole of their forward biased period. Con-
sequently, as the time delay is increased the SCRs conduct for a shorter period
leading to a reduced DC busbar voltage (See paragraph 1.4).

Drive pulse generator

This block has two major responsibilities. First, it contains a timing circuit which,
in conjunction with the ‘DC control voltage’ signal, controls the timing of the
SCR drive pulses relative to the mains voltage sense signals (i.e. it uses the mains
sense signals to synchronise each SCRs’ timing to the relevant forward biased
period of the incoming supply); second, it contains a signal conditioning circuit
which processes the resulting drive pulses to provide a modulated drive wave-
form.
The ‘DC control voltage’ directly controls the adopted SCR drive signals’ time
delay and therefore also the DC busbar voltage – i.e. increasing the ‘DC control
voltage’ reduces the time delay and results in a greater DC busbar voltage.

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Reference voltage generator

The ‘reference voltage generator’ provides the ‘volts error amplifier’ with its ‘DC
reference voltage’ input. This is seen as a voltage demand signal by the ‘voltage
error amplifier’ – in that it represents the DC busbar target voltage.
The ‘reference voltage generator’ can produce one of four ‘DC reference voltage’
levels equating to float charge, boost charge, manual charge, or test; as requested
by the processor on the UPS Logic Board. Note that although the charge mode is
selected by the UPS Logic Board, the respective ‘DC reference voltage’ for each
mode is individually adjustable by potentiometers on the Rectifier Logic Board
itself.
An analogue signal proportional to the battery temperature is also applied to the
‘reference voltage generator’ and can be used to reduce the ‘DC reference volt-
age’ by 1.5Vdc/°C as the battery temperature rises between 25°C and 35°C.
The test mode is used for fault-finding only and allows the DC busbar voltage to
be manually adjusted within the range 0V to 650Vdc.

Volts error amplifier

In the block diagram the primary output of the ‘voltage error amplifier’ is anno-
tated ‘DC control voltage’. This is the signal which directly controls the DC
busbar voltage via the time delay circuit in the ‘drive pulse generator’– see above.
The magnitude of the ‘DC control voltage’ is determined by a comparator within
the ‘volts error amplifier’ which compares the DC busbar voltage feedback signal
with the ‘DC reference voltage’ produced by the ‘reference voltage generator’
block. This basically forms a closed-loop control system, in that the error ampli-
fier constantly modifies the ‘DC control voltage’ in such a way as to make the rec-
tifier phase-forward or phase-back (as required) to maintain equilibrium between
the ‘DC reference’ and ‘DC bus feedback’ signal voltages.
The ‘volts error amplifier’ also monitors the input current and battery current
sense signals and reduces the ‘DC control voltage’ if either of these signals reach-
es a preset current limit threshold. Such an event reduces the DC busbar voltage
to maintain the particular current at its limiting value.

Start/Stop Logic
The ‘start/stop’ command signal produced by this circuit block is controlled by a
signal produced on the UPS Logic Board in response to it’s ‘system’ control logic,
and affects both the ‘volts error amplifier’ and ‘drive pulse generator’ blocks.
When the signal is in its ‘stop’ mode it totally inhibits the ‘drive pulse generator’s
outputs, effectively closing down the rectifier, and also clamps the ‘DC control
voltage’ to zero by inhibiting the ‘volts error amplifier’ output – thus demanding
zero DC busbar voltage. When the ‘start/stop’ signal enters its ‘start’ mode it im-
mediately releases the inhibit on the ‘drive pulse generator’ block, enabling the
output drive pulses to be produced; however, the clamp on the ‘volts error ampli-
fier’ is lifted gradually such that the ‘DC reference voltage’ is allowed to rise to
its operational level at a controlled rate.
The combined effects of these two operations ensure the power rectifier is stopped
and started in a controlled manner – providing an input current walk-in on start-
up to prevent undesirable input current surges damaging the power components.
This soft-start-controlled walk-in takes approximately 5 seconds to charge the dc
capacitor tray.

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The ‘fault detection’ block output is also connected to the start/stop control line
and has the same effects as the start/stop control signal applied from the UPS
Logic Board. It also applies an input to the ‘start/stop logic’ block which passes a
‘fault’ status signal back to the UPS Logic Board in response to certain detected
fault events – hence the start/stop line between the UPS Logic Board and Rectifier
Logic board is shown as bi-directional in the block diagram.

Fault detection logic

This block detects several abnormal/fault conditions on the Rectifier Logic Board
and, depending on the condition will:
• provide on-board led indication.
• send a fault signal to UPS Logic Board (via the Start/Stop Logic block).
• apply a ‘stop’ condition to the ‘start/stop’ control line.

Following is a list of the monitored conditions – see paragraph [Link] for a full
circuit description.

Table 4-2: Monitored faults

Stop Signals to
Condition Indication
Line? UPSLB

Battery current limit No CHG H5

Input current limit No OVL H6

Input mains undervoltage Yes IN_LOW H9

BLK_REC

Input mains phase sequence error Yes SEQ H8

BLK_REC

Control power supply monitor Yes BLK_REC H7

Control power supplies

The Rectifier Logic Board requires regulated ±12Vdc supplies for its operation.
These are obtained from the AC-DC Power Supply Board and will be present
whenever the UPS input mains supply (or static bypass supply in a split-bypass
system) is live. An on-board, three-terminal +5V regulator (N14) is driven from
the +12V supply to provide a regulated +5V supply voltage rail.
In the event of a mains failure the AC-DC Power Supply Board will become in-
active and the ±12V rails are provided by the DC-DC Power Supply Board via the
UPS Logic Board provided the batteries remain connected to the DC busbar – (see
section 3 of this manual for details of the control power supplies).

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2.3 Detailed circuit description

2.3.1 Introduction
The Rectifier Logic Board circuit diagram (SE-4520074-A) comprises 4 sheets.
With reference to the block diagram description in Figure 4-16, the drawings can
broadly be described as follows:
• Sheet 1 contains a ‘signal map’ showing the interconnection of the signals
passing between the other three sheets.
• Sheet 2 contains the:
– reference voltage generator circuit
– battery temperature compensation circuit
– volts error amp circuit
– battery current limit circuit
– input current limit circuit
– soft-start control amplifier
• Sheet 3 contains the timing portion of the ‘drive pulse generator’ circuit
together with the mains undervoltage (-15%) detection circuit
• Sheet 4 contains the:
– signal conditioning portion of the ‘drive pulse generator’ circuit
– ‘start/stop logic’ and ‘fault detection’ circuits
– ‘control power supplies’ and its power failure detection circuit

2.3.2 Reference voltage generator

(refer to diagram sheet 2)
This circuit is responsible for providing the ‘volts error amplifier’ with a ‘DC ref-
erence voltage’ which acts as a voltage demand signal, informing the ‘volts error
amplifier’ of the desired DC busbar (battery charging) voltage.
Four reference voltages are available: Test, Boost, Float, and Manual, which are
individually set by R19, R20, R21, R22 respectively. These resistors are connect-
ed in independent resistor chains which are fed from a stable +5V supply pro-
duced by a voltage regulator circuit comprising N6, R23 and R24. If the regulator
is working correctly its Vref input (junction R23/R24) will be at 2.5V.
A multiplexer i.c. (D1) is used to select one of the four reference voltages under
the control of the microprocessor on the UPS Logic Board (REC_A and REC_B
signals). The four pot wiper voltages at the multiplexer’s inputs 1X thru 4X are
connected to its X output according to the table below:

Table 4-3: Logic table for Q1 (4052)

Mode REC_A REC_B Output X = Output Y =

Manual 0 0 X1 Y1 (H4 Yellow)

Float 0 1 X2 Y2 (H3 Green)

Boost 1 0 X3 Y3 (H2 Green)

Test 1 1 X4 Y4 (H1 Yellow)

Notice that the multiplexer’s ‘Y’ channel provides on-board led indication of the
selected charger mode by switching the return path for leds H1-H4.

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As shown on sheet 4, the [REC_A/B> signals are obtained directly from the UPS
Logic Board via connector X2-38 and X2-39: however, these can be overridden
by links connected to X9 positions 1 & 2. This is a test facility, and enables the
bench/commissioning engineer to select any one of the four charger modes while
undertaking the board set-up procedures. X9 links 1 and 2 must be open during
normal UPS operation.
The selected reference voltage from Q1 (X) (pin13), which can be monitored at
test-point X8-6, is inverted by N4a and applied to the ‘volts error amplifier’ (N4b)
via R43 (22k) – this is the point annotated ‘DC reference voltage’ in Figure 4-16,
and is approximately 3.0Vdc when the dc bus is at 432Vdc. As the signal is in-
verted by N4a, the ‘DC reference voltage’ is always of a negative polarity – i.e.
the demanded DC bus voltage increases as the signal goes more negative. As a
guide, this (linear) signal has a sensitivity of around -7.24mV/V(bus demand).

2.3.3 Battery temperature compensation

Note: this is an ‘optional’ feature which is normally disabled in a standard module
A temperature sense signal, proportional to the battery cabinet temperature, is
connected via terminal X2-26 and jumper X5 (pins 2-3) to amplifier N2c, where
it is differentially summed with a variable voltage set by R121. The output from
N2c is then summed with the ‘reference voltage generator’ output (See paragraph
2.3.2) at N4a inverting input (test point X8-5).
The affected of the temperature sense signal is to reduce the ‘DC reference volt-
age’ by approximately 1.5Vdc per °C as the battery temperature increases above
25°C. This is done to prevent the batteries from being overcharged and so pro-
longs battery life.
That is, the temperature signal has no affect until it overcomes the threshold set
by R121, whereupon it progressively reduces the DC busbar voltage as the tem-
perature increases.
The circuit is calibrated by connecting jumper X5 to position (1-2) and adjusting
R121 to obtain 2.98V at test point X5-1 (equates to 25°C).
Note: this must be undertaken before the various charge levels are set.
If the facility is not required, leave jumper X5 in position (1-2). This connects the
reference voltage from R121 to both N2c inputs, where they self cancel.

2.3.4 Volts error amplifier

The earlier block diagram description states that the ‘volts error amplifier’ pro-
duces the ‘DC control voltage’ which ultimately controls the DC busbar voltage.
In practice the ‘volts error amplifier’ circuit comprises two amplifiers (circuit di-
agram sheet 2); N4b (which is the true error amplifier) and N3a (which is a unity
gain buffer amplifier). The output signal, analogous to the ‘DC control voltage’
signal in the block diagram, is annotated [MOD>.
N3a has five diode-coupled signals connected to its non-inverting input (pin 3)
obtained from:
• a fixed dc biasing circuit
• the error amplifier (N4b) output via V5
• the input current limit detector (N1d) via V3
• the battery current limit detector (N1a) via V4
• a soft-start signal from the ‘start/stop logic’ circuit (N4d) via V6
Each of these inputs can affect N3a’s [MOD> output, as described in detail below.

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Fixed bias
A fixed bias voltage of approximately +10.5Vdc is applied to N3a pin 3 by the
circuit comprising V1, R60, R55 and R63.
In the absence of all other inputs to N3a the magnitude of this signal would drive
N3a output [MOD>) to +10.5V which is sufficient to cause the ‘drive pulse gen-
erator’ circuit to turn on the rectifier SCRs with minimum delay – producing max-
imum DC busbar voltage. In practice, the inputs to N3a pin 3 from the voltage
error amplifier and current limit circuits therefore control the rectifier by pulling
down, or ‘clamping’, the voltage established by the fixed bias circuit: thereby re-
ducing the SCRs’ conduction to an angle which produces the desired DC busbar
voltage. Such clamping action is achieved by these circuits via their respective
coupling diodes (V3-V6).
Under normal operating conditions the current limit circuits are inactive and
diodes V3 and V4 are reversed biased and have no affect on N3a. The ‘DC control
voltage’ ([MOD>) is therefore usually controlled by the output from the voltage
error amplifier (N4b) alone.

Error amplifier (N4b)

N4b compares the ‘DC reference voltage’ produced by Q1/N4a (See paragraph
2.3.2) with a ‘DC busbar voltage feedback’ signal (approximately 3.0V at
432Vbus) which is connected to X2-25 and fed to the error amplifier via buffer
N2a and R42 (22k).
Note that the ‘DC reference voltage’ signal has a positive polarity due to the non-
inverting action of N2a (monitored at X8-1) while the ‘DC reference voltage’ pro-
duced at N4a pin 1 has a negative polarity. The error amp (N4b) therefore com-
pares the magnitude of these two signals differentially.

Error amplifier regulation circuit action

If the DC busbar falls below its required voltage the ‘DC busbar feedback’ signal
will be lower in amplitude than the ‘DC reference voltage’ and the voltage error
amplifier output will ramp in a positive direction, lifting the clamp (by V5) on
N3a non-inverting input. This allows the ‘DC control voltage’ ([MOD>) to in-
crease – so raising the DC Busbar voltage. This action will take place until the
‘DC busbar feedback’ signal increases to a level equal to the ‘DC reference volt-
age’ – at which point the output from N4b output will remain constant and cease
demanding an increase in DC busbar voltage.
If the DC busbar rises above the required voltage the circuit will respond with the
opposite polarity – i.e. if the ‘DC busbar feedback’ signal is higher than the ‘DC
reference voltage’ then N4b output will decrease and further clamp the input to
N31 with a resulting reduction in the ‘DC control voltage’ ([MOD>).
Due to the presence of C28 in its feedback path, the ‘volts error amplifier’ (N4b)
integrates any amplitude difference between its ‘DC busbar feedback (+)’ and
‘DC reference voltage (-)’ input signals, and so affects the rectifier’s regulation
speed of response. The circuit response can be selected by jumper X6 which
should be positioned (1-2) in modules rated at 60kVA and below (faster re-
sponse), and (2-3) in modules rated at 80kVA and above.

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[Link] Battery current limit

Battery current sense signal

Battery current is measured by a Hall-effect dc current sensor which produces a
dc voltage proportional to the battery current. This voltage is calibrated on the
High Voltage Interface Board (see paragraph 2.3.22 on page 7-11) and then
passes through the UPS Logic Board to enter the Rectifier Logic Board at X2-18
where it is buffered by N1c. The resulting sense signal appears as a positive volt-
age at test point X8-2.

Battery current limit circuit operation

From test point X8-2 the battery current sense signal is connected to a level de-
tector circuit (N1a) whose output pin 1 changes from logic high to low if the bat-
tery current exceeds the level set by R18. When this occurs it clamps the input to
the ‘volts error’ summing amplifier (N3a), via V4, reducing the ‘DC control volt-
age’ ([MOD>) which in turn reduces the DC busbar voltage – thereby reducing the
battery charge current. The reference voltage set by R18 can be monitored at test
point X8-8 and can be in the range 0V to -5V. This range is determined by a 5V
regulator circuit, based on N5, connected between the 0V and -12V power rails.
If the regulator circuit is operating correctly the junction of R12 and R13 will be
held at -2.5V. R18 is normally adjusted to obtain 0.1Vdc per amp of required cur-
rent limit at X8-8 for the 30kVA, 40kVA and 60kVA models respectively.
This circuit is dynamic in its operation – i.e. as the DC busbar voltage reduces so
too does the battery charge current. Ultimately, the circuit operation reduces the
DC busbar voltage to a level which sustains the battery charge current at the level
set by R18.
In practice the battery current limit circuit is only likely to become active when
the UPS input mains supply returns from a prolonged outage: whereupon the
heavily discharged batteries are certain to demand a high initial recharge current.
Under these circumstances the DC busbar voltage is initially restricted but will
gradually increase to its nominal value while maintaining the battery current at its
set limit level as the batteries regain their charge.

Battery current limit indication

Led H5 illuminates when the battery current limit circuit is active. The indication
circuit operates by detecting whether or not V4 is turned on. When V4 is conduct-
ing, the input to N3 pin 6 via R56 is approximately -0.6V with respect to the signal
applied via R57 to pin 5. These conditions force N3 pin 7 to switch high which
illuminates H5 and produce a logic high [CHG> signal, which is connected to the
UPS Logic Board, via X2-23, to inform it of the battery current limit status.

[Link] Input current limit

Input current sense signal

The UPS input current is sensed by current transformers (CTs) fitted to the recti-
fier assembly input R and T lines. The CTs’ outputs are rectified and normalised
on the High Voltage Interface Board (see paragraph 2.3.18 on page 7-10) and the
resulting dc voltage, which is proportional to the input current, is connected via
the UPS Logic Board to the Rectifier Logic Board X2-20. From here the sense
signal is buffered by N1b and can be measured as a positive voltage at test point
X8-3.

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Input current limit circuit operation

From test point X8-3 the input current sense signal is connected to a level detector
circuit (N1d) whose output pin 14 changes from logic high to low if the input cur-
rent exceeds the level set by R17. When this occurs it clamps the input to the
‘volts error’ summing amplifier (N3a), via V3, reducing the ‘DC control voltage’
([MOD>) which in turn reduces the DC busbar voltage – thereby reducing the input
current. The reference voltage set by R17 can be monitored at test point X8-7 and
can be in the range -0.5V to -5V. This range is determined by a 5V regulator cir-
cuit, based on N5, as described above for the battery current limit circuit. In prac-
tice R17 is adjusted to obtain 0.8Vdc at test point X8-7 in a 30kVA model; this is
increased to 1.2Vdc for 40kVA and 1.6Vdc for 60kVA models.
This circuit is dynamic in its operation – i.e. as the DC busbar voltage reduces so
too does the input current. Ultimately, the circuit operation reduces the DC busbar
voltage to a level which sustains the input current at the level set by R17.
When electronic switch D2 closes it increases the sensitivity of the input current
sense signal to N1d by connecting R35 in parallel with R49. This results in the
current sense signal reaching the set limit threshold at a reduced input current
level and effectively reduces the circuit’s operation by approximately 25%. This
reduced threshold is controlled by the [STAT> signal generated on the UPS Logic
Board and applied via X3-37 (see paragraph [Link] on page 7-46). This is used
to reduce the rectifier input current when the UPS is supplied from a stand-by gen-
erator.
Note: this signal is applied via the ‘optional’ Remote Alarms Board which pro-
vides an interface between the external ‘on generator’ signal and the UPS Logic
Board control logic.

Input current limit indication

Led H6 illuminates when the input current limit circuit is active. The indication
circuit operates by detecting whether or not V3 is turned on. When V3 is conduct-
ing, the input to N3c pin 9 via R58 is approximately -0.6V with respect to the
signal applied via R59 to pin 10. These conditions force N3 pin 8 to switch high
which illuminates H6 and produce a logic high [OVL> signal, which is connected
to the UPS Logic Board, via X2-32, to inform it of the input current limit status.

Parallel module operation

When two or more 7200 UPS modules are connected to a common battery a
system of input current sharing is employed to ensure that both modules share the
battery charging burden. Such a system monitors the input current from both
modules and employs a correction signal to either phase-forward or phase-back
the rectifiers as necessary.
In practice the monitored current is obtained from X2-24, which is connected to
the output of the input current sensing buffer amplifier (N1b); and the correction
signal is applied to X2-29, from where it applies an offset signal to the ‘volts error
amplifier’ (N4b) via buffer N2b. The correction signal can be monitored at test
point X8-4.

[Link] Start/Stop control

A start/stop control input is applied to the ‘volts error amplifier’ via diode V6.
This signal, annotated [STOP> (on sheet 1), goes high when the start/stop circuit
requires a rectifier shut-down, and vice-versa. In its ‘stop’ mode, this signal is in-
verted to a logic low at N4 pin 8 which is then buffered by N4d and applied as a
clamp to the ‘volts error amplifier’. This effectively phases-back the rectifier and

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demands zero DC busbar voltage.

Note: for a full description of the start/stop control logic see paragraph 2.3.6.
When the start/stop signal goes to its ‘start’ mode the [STOP> signal goes low and
the output from N4 pin 8 will switch high; however, this is not immediately re-
flected at the output of N4d pin 14 due to an R-C delay circuit (C19/R39) connect-
ed to its input in parallel with the start/stop signal. The effect of the R-C circuit is
to prevent the clamping effect of V6 on the ‘volts error amplifier’ from being re-
moved too quickly, as this could lead to a large inrush current as the rectifier en-
ergises the dc busbar filter capacitors. The presence of the R-C circuit thus leads
to a controlled power walk-in when the rectifier is started. Notice that the delay is
adjustable by means of jumper X7. When X7 is fitted 2-3 the time constant pro-
duces a ‘slow’ walk-in of approximately 5 seconds, but when fitted to position 1-
2 is connects R36 in parallel with R39 which speeds up the walk-in to 1 second.
In practice the link is normally fitted 2-3 (slow).

2.3.5 Drive pulse generator

(refer to diagram sheet 3)
The ‘drive pulse generator’ monitors sensing signals proportional to the UPS
input mains voltage together with the ‘DC control voltage’ ([MOD>) and produces
the rectifier SCR gate drive pulses at the conduction angle appropriate to obtain-
ing the desired DC busbar (battery charging) voltage.
This circuit can be divided into two areas:
• an analogue circuit based on a series of comparators (sheet 3) controls the
drive signal timing and thereby determines the adopted conduction angle
• a digital circuit based on a custom array gate (sheet 4) provides the neces-
sary signal processing.

The ultimate drive signals are despatched to the Gate Drive Interface Board via
transistors V37 to V42 and terminals of connector X1 shown on sheet 4.

[Link] Analogue timing control circuit

The drive signal timing is controlled by three comparator circuits (one per phase)
which compare sense signals proportional to the three phase input mains supply
with the variable ‘DC control voltage’ ([MOD>). In reality each comparator con-
tains two similar circuits: one to handle the timing for the positive SCR and the
other for the negative SCR in each phase – i.e. one deals with the positive half
cycle and the other with the negative half cycle of the incoming a.c. mains wave-
form. A full description of the comparators’ operation is given below.
Note: as all three phases are identical only the R phase is described in detail.

Input supply sensing (for synchronising SCR timing to the Input Supply)
The three phase input mains supply is sensed via an attenuator circuit on the High
Voltage Interface Board (see paragraph 2.3.3 on page 7-7) whose outputs pass
through the UPS Logic Board and are then connected to the Rectifier Logic Board
connector X2 pins 15, 16, 17 (sheet 3). On the High Voltage Interface Board the
mains sense signals are monitored by differential amplifiers on a line-to-line
basis; the input to the R phase control circuit at X2-15 ([VREC_AC>) is in fact de-
rived from the R-T phase and will in fact lag the R phase voltage by 90°. A further
lag of 180° is imposed by N12a, therefore the resulting output at N12 pin 1 is a
sine-wave which lags the ‘true’ mains R phase by 270°.

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Figure 4-17: R-Ph sense voltage phase details

R-Ph Positive Mains R-Ph
half cycle
[VREC_AC>

Mains delayed
by 270°
270° lag (N12 pin 1)

dead band

Figure 4-17 shows that due to the applied 270° phase shift the maximum and min-
imum levels of the sense signal at N12 pin 1 coincide with the changeover be-
tween ‘positive’ and ‘negative’ half cycles of the true incoming R-phase voltage
– i.e. the sense signal falls from max to min during the ‘true’ R-phase positive half
cycle and from min to max during the negative half cycle.
N8a buffers the R-phase sense voltage and passes it to N8b and N8c where it is
compared with the ‘DC control voltage’. N8b controls the positive R-phase SCR
(i.e. the SCR connected between the rectifier R phase input and the positive DC
busbar) while N8c controls the R-phase negative SCR.

DC Control voltage
The ‘DC control voltage’ ([MOD>), which is produced by the voltage error ampli-
fier and fully described in paragraph 2.3.4, was previously described as being a
DC busbar ‘volts demand’ signal, in that the bus voltage is ultimately proportional
to the [MOD> signal level.
Sheet 3 of the circuit diagram shows that [MOD> is inverted by N11a and connect-
ed to the non-inverting input of N8c (pin 10), then re-inverted back to its original
polarity by N11b and connected to N8b non-inverting input (pin 5). These two
sections of N11 are configured as comparators and compare the R-phase sense
voltage with the [MOD> signal, as described below.

Comparators’ operation
The R-phase drive gate drive generation circuit uses three comparators: N8b con-
trols the timing for the drive to the positive SCR, N8c controls the timing for the
drive to the negative SCR, and N8d provides ‘dead-band’ timing control to both
devices.
The outputs from the above comparators are annotated [A>, [B>, [C> on the dia-
gram and the their effects on the following digital drive circuit can be summarised
as follows:
• The R-phase positive SCR is turned on when [A> and [C> are both high
(logic 1).
• The R-phase negative SCR is turned on when [B> and [C> are both low
(logic 0).

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7200 Series UPS Service Manual SECTION 4 - Rectifier Operation & Control
CHAPTER 2 - Rectifier Logic Board

Considering the action of N8b: If the ‘DC control voltage’ ([MOD>) applied to
N8b pin 5 is very high, the R-phase sense signal on N8b pin 6 will fall below the
‘DC control voltage’ level very early with respect to the R phase positive zero-
crossover point. When this happens, the comparator’s output at N8b pin 7 switch-
es high, which has already been shown in the summary to be the state required to
turn on the R-phase positive SCR. Alternatively, if the ‘DC control voltage’
([MOD>) applied to N8b pin 5 is very low, then the R-phase sense signal on N8b
pin 6 will fall below the ‘DC control voltage’ level very late with respect to the R
phase positive zero-crossover point. This shows that as the ‘DC control voltage’
([MOD>) decreases, the R-phase positive SCR will be turned on later in its half
cycle and therefore produce a lower DC busbar voltage.
The negative SCR comparator (N8c) works in exactly the same way except that
the signal polarities are reversed – i.e. the [B> output from N8 pin 8 goes low, turn-
ing on the R-phase negative SCR, when the R-phased sense voltage applied to
N8c pin 9 rises above the ‘DC control signal’ at N8c pin 10. As has been previ-
ously described, the ‘DC control voltage’ at N8c pin 10 is an inverted version of
the [MOD> signal. Thus if the ‘volts error amplifier’ demands a greater DC busbar
voltage the ‘DC control signal’ will go more negative and will be ‘cut’ by the R-
phase sense signal earlier in its forward-biased (negative) half cycle and thereby
increase the R-phase negative SCR conduction angle
N8d acts as a delayed zero-crossing detector. This open-loop comparator moni-
tors the R-phase voltage sense signal via a C-R circuit which produces a time
delay of approximately 36° (@50Hz) – i.e. when the sense voltage traverses its
zero cross-over (ZCO) point in a positive direction N8d pin 14 ([C>) will provide
a negative pulse (holding off the R phase positive SCR) equal to about 36°: sim-
ilarly when the sense signal traverses the ZCO in a negative direction N8d will
produce a positive pulse of 36°. These pulses are gated with the main comparator
output signals [A> and [B> and provide a dead-band period while the pulses are
present. The SCR is thus allowed to conduct between 150° and 30°.
Note that the ‘DC control signal’ ([MOD>) is used by all three groups of compara-
tors, therefore the S and T phases adopt the same conduction angle as the R phase.

[Link] Digital signal processing

The digital signal processing aspect of the ‘drive pulse generator’ circuit is con-
trolled by D6 and its associated components shown on the diagram sheet 4. This
ASIC applies modulation and start/stop control to the comparators’ outputs (sig-
nals [A> to [I>), and provides further timing checks to ensure that the resulting
drive signals are suitable for driving the rectifier SCRs.

Signal summary
The following signal summary describes the relationship between the [A> – [I>
inputs and the drive output signals.
Note 1: the output drive waveforms will be modulated by a 19kHz oscillator con-
nected to D6 pin 7.
Note 2: the outputs all assume that the start/stop line (described in detail later) is
in its ‘start’ mode – i.e. outputs ‘enabled’.

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SECTION 4 - Rectifier Operation & Control 7200 Series UPS Service Manual
CHAPTER 2 - Rectifier Logic Board

Table 4-4: Drive logic table

Inputs Outputs

A B C R-Ph Positive SCR R-Ph Negative SCR

1 1 ON (U6-18 = 1)

0 0 ON (U6-19 = 1)

D E F S-Ph Positive SCR S-Ph Negative SCR

1 1 ON (U6-20 = 1)

0 0 ON (U6-21 = 1)

G H I T-Ph Positive SCR T-Ph Negative SCR

1 1 ON (U6-24 = 1)

0 0 ON (U6-25 = 1)

Modulating oscillator
A modulated high-frequency drive waveform is used to enable easy a.c. coupling
between the Rectifier Logic Board and the SCRs via the Drive Interface Board.
The modulating oscillator comprises a 555 timer, D5, which is set to operate at
approximately 19kHz. A series of mixer gates in the output stage of D6 uses this
signal to modulate the output drive signal and produces a composite signal which
appears as a 19kHz squarewave pulse-train corresponding to the duration of the
required SCR ‘TURN ON’ period.
D5 is reset by an output from D6 pin 14 which goes low each time D6 initiates an
SCR drive pulse at any of its six drive outputs. This ensures that every driver
output pulsetrain begins with a full-width pulse. Note that the output from D6 pin
14 is also fed back via D4e to pin 13 where it resets a series of latches concerned
with the internal drive signal timing. Thus only 10 pulses are modulated at the be-
ginning of the SCR trigger square-wave.

Start/Stop control
The ‘drive pulse generator’ circuit is controlled by the same start/stop control line
used to control the ‘volts error amplifier’ (See paragraph [Link]) to ensure that
the rectifier stops and starts in a controlled manner. The ‘stop/start’ logic is con-
tained within U6 and is described in detail below.

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7200 Series UPS Service Manual SECTION 4 - Rectifier Operation & Control
CHAPTER 2 - Rectifier Logic Board

2.3.6 Start/Stop logic

The ‘start/stop logic’ circuit is contained within D6 and has several inputs derived
from fault detection circuits on this board and on the UPS Logic Board. It produc-
es summary stop/start line which:
• ‘inhibits’/‘enables’ the production of the rectifier drive pulses within D6
• via the [STOP> output on D6 pin 34, reduces to zero the ‘DC control volt-
age’ produced by the ‘volts error amplifier’ when in the ‘stop’ mode (See
paragraph [Link])
• produces a ‘start/stop’ status signal at D6 pin 36 which is connected to the
UPS Logic Board via X2-33 (See paragraph [Link]). This signal is
annotated [BLK_REC> (Blocked Rectifier) and is logic high when the start/
stop line in the ‘stop’ mode. This informs the UPS Logic board that the
Rectifier Logic Board has detected a fault which results in the UPS Logic
Board turning OFF the ‘rectifier run’ command signal.
The ‘start/stop’ line is affected by the following fault detection and control sig-
nals.

[Link] Input mains phase rotation error

A phase sequence comparator within D6 monitors the R-phase and S-phase zero
crossover signals at D6 pins 4 and 44 (signals [C> and [F>) and produces and error
signal if these are not of the correct phase relationship.
If an error is detected:
• the ‘start/stop’ line is driven to its ‘stop’ mode
• led H8 illuminates to provide on-board indication of phase rotation error
• a logic high ‘error’ signal is produced at U6 pin 33 and passed to the UPS
Logic Board via X2-34 where it is processed by the system control logic

[Link] Input mains undervoltage

In addition to providing an input to the ‘drive pulse generator’ comparators, the
input mains 3-phase sense signals (sheet 3) are also connected to a full-wave rec-
tifier comprising V20-V25. The rectifier output is buffered by N11d whose output
is connected to a fixed comparator N11c. An undervoltage condition is sensed if
the sense signal at N11 pin 10 falls below the 4.5V threshold set at N11 pin 9, at
which point N11 pin 8 switches to a logic low. This equates to an undervoltage
error of 15%.
If an error is detected:
• the ‘start/stop’ line is driven to its ‘stop’ mode
• led H9 illuminates to provide on-board indication
• a logic high ‘error’ signal is produced at U6 pin 32 and passed to the UPS
Logic Board via X2-35 where it is processed by the system control logic

Note 1: R82 introduces a slight hysteresis into the detector so that the mains must
go above approximately -12% before the ‘mains OK’ signal is re-established.
This eliminates nuisance alarms on fast, spurious undervoltage conditions.
Note 2: there is very little capacitance so it will detect an undervoltage condition
on a phase drop.

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SECTION 4 - Rectifier Operation & Control 7200 Series UPS Service Manual
CHAPTER 2 - Rectifier Logic Board

[Link] ON/OFF control from UPS Logic Board

One function of the UPS Logic Board’s ‘system control logic’ is to provide the
Rectifier Logic Board with a general ON/OFF control signal (see paragraph 3.3.7
on page 7-29).
This signal, which is annotated [ON_REC>, is connected to the Rectifier Logic
Board X2-36 and goes low when in the OFF state. In this state:
• the ‘start/stop’ line is driven to its ‘stop’ mode
• led H10 illuminates to provide on-board indication

[Link] Control power supply failure detection

A purpose designed supply voltage supervisor i.c. (N13) monitors the +12V
power rail and flags an error if this falls below approximately 4.55Vdc. If the
+12V supply falls below this level N13 output pin 6 goes high which:
• drives the ‘start/stop’ line to its ‘stop’ mode
• illuminates H10 to provide on-board indication

2.3.7 Control power supplies

The Rectifier Logic Board is powered from the AC-DC Power Supply Board
which applies ±12V to X3 pins 3-5, as shown on sheet 4 of the circuit diagram.
Connector X11 is not used.
These inputs provide the general ±12V power rails for this board and are also con-
nected to the UPS Logic Board via X2 pins 1 to12, as shown. On the UPS Logic
Board these supplies are diode coupled with a similar set of supplies connected
via the Inverter Logic Board and then distributed to the remaining circuits boards.
A three-terminal +5V regulator (N14) is connected to the +12V rail and provides
the +5V supply required by some of the board’s integrated circuits. Note also that
D2 (diagram sheet 2) requires a -5V supply which is obtained by a simple zener-
regulator connected to the -12V rail.
Note: the cross-coupled diodes V45 splits the 12V rail into +12H and +12V. The
+12H rail is monitored by the ‘power supply monitor’ N13 only. H7 illuminates
if the AC-DC Power Supply is OFF – i.e. input mains failure. Upon mains return
N13 provides a power-up reset to the soft-start circuit to walk-in the rectifier con-
trol electronics. Thus during mains power failure the rectifier control electronics
are still energised via the DC-DC Power Supply but the soft-start is deactivated,
awaiting the mains return.

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CHAPTER 2 - Rectifier Logic Board

2.4 Summary Information

Table 4-5: Rectifier Logic Board configuration jumpers

Link
Jumper Function
Position

X5 1-2 Disable battery temperature/voltage compensation

(Standard)

2-3 Enable battery temperature/voltage compensation

X6 1-2 Increased DC regulation speed for units below 60kVA

2-3 Decreased DC regulation speed for units above 80kVA

X7 1-2 Fast walk-in: 1 Second

2-3 Slow walk-in: 5 Seconds

X9 0-1 open Rectifier in Auto mode (Standard)

0-2 open

0-1 closed Rectifier in Float mode

0-2 open

0-1 open Rectifier in Boost mode

0-2 closed

0-1 closed Rectifier in ‘Test’ mode

0-2 closed

0-3 closed Reduced input current limit forced on

open (Standard)

0-4 closed Rectifier forced on - Ignore UPS Logic

open UPS Logic control enabled (Standard)

0-5 open Disable driver IC - D6

closed Enable driver IC - D6 (Standard)

X10 1-2 Enable rectifier temperature monitor

2-3 Disable rectifier temperature monitor (Standard)

Table 4-6: Rectifier Logic Board potentiometer adjustment

Potentiometer Function
R17 Rectifier input current limit adjust (100 - 130%)
R18 Battery current limit adjust (0 - 25%)
R19 Battery test voltage adjust (0 - 550 volts)
R20 Battery boost voltage adjust (200 - 550 volts)
R21 Battery float voltage adjust (200 - 550 volts)
R22 Manual voltage adjust volts (10 - 550 volts)

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SECTION 4 - Rectifier Operation & Control 7200 Series UPS Service Manual
CHAPTER 2 - Rectifier Logic Board

Table 4-7: Rectifier Logic Board LED indications

LED Colour Function

H1 Amber Rectifier in Battery Test mode
H2 Green Rectifier in Boost mode
H3 Green Rectifier in Float mode
H4 Amber Rectifier in Manual mode
H5 Green Battery in current limit
H6 Red Rectifier in current limit

Table 4-8: Rectifier Logic Board test points

Test Point X8
X8 - 1 Battery volts reference feedback (3.26 ≈ 450V dc)
X8 - 2 Battery current feedback
X8 - 3 Rectifier current feedback
X8 - 4 Parallel rectifier compensation N/A
X8 - 5 Battery temperature compensation
X8 - 6 DC voltage reference
X8 - 7 Input current limit adjustment reference
X8 - 8 Battery current limit adjustment reference

Test Point X5
X5 - 1 Temperature compensation start point

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 Section 4:

Chapter 3 - Rectifier Gate Drive Interface Board (4542040W)

3.1 Introduction
A single Gate Drive Interface Board is used to interface the gate drive signals to
all six rectifier SCRs.
The board’s primary function is to provide the SCR gate drive signals with gal-
vanic isolation between their source (i.e. the low voltage control electronic envi-
ronment of the Rectifier Logic Board) and the noisy, high voltage environment of
the power rectifier SCR devices to which they are applied. This is achieved
through the means of suitable pulse transformers.

3.2 Rectifier SCR gate drive requirements

As described in chapter 1 of this section, for the successful gate triggering of an
SCR it is essential that the current supplied to the gate:
• occurs at a time when the main circuit conditions are favourable to the
SCRs’s conduction – i.e. the SCR must be forward biased.
• is of adequate duration – i.e. the gate pulse must not be removed until the
anode current has risen above its ‘holding current’ value, otherwise the
device would turn off.
• is of adequate amplitude and sufficiently short rise time to initiate a safe
but rapid turn-on process.

The pulse duration and timing criteria stipulated in the first two of the above con-
ditions are controlled by the Rectifier Logic Board – which is responsible for
managing the phase-control timing sequencing and producing the necessary drive
pulses etc. However, the ultimate pulse-shape and rise-time of the signal seen at
the SCR gate is also affected by the signal-coupling circuits on the Gate Drive In-
terface Board and the conduction path shown in Figure 4-18.
The rise-time as well as the delay time, tends to be reduced by a large gate drive
within the allowable gate dissipation ratings of the SCR. Therefore, in order to
minimize the turn-on switching dissipation, the gate should be driven quite hard,
towards its allowable gate dissipation curve (See Figure 4-5). Thus steep-fronted
gate pulses are desired for proper device operation.

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SECTION 4 - Rectifier Operation & Control 7200 Series UPS Service Manual
CHAPTER 3 - Rectifier Gate Drive Interface Board

3.3 Gate drive circuit

Figure 4-18: R-phase (+) SCR drive circuit details

DC Bus +

+12V Gate Drive Interface Board

X1 X7 X1
1 1 Yellow
1
2 2
Rectifier Gate drive 100n
Logic ribbon cables 1k
Board (maximum 3m)
22R V1 R+
3 3 2
V37 4 Red
4

R-ph
mains
0V
αmin (30°) αmax (150°)

SCR Conduction
period
R-

40kHz modulated signal Trigger pulses

DC Bus –

SCR gate current (IG)

Figure 4-18 illustrates the complete gate drive signal path for the R-phase positive
SCR (R+) – all other SCRs are similarly gated.
As has previously been explained, the Gate Drive interface Board contains a pulse
transformer to provide necessary signal isolation. To minimise the size of this
component the Rectifier Logic Board produces a modulated drive waveform
based on a 40kHz square-wave carrier – i.e. when the Rectifier Logic Board wants
to trigger the SCR it sends a 40kHz burst firing signal and the pulse transformer
“sees” the 40kHz signal as opposed to 50Hz. The chosen 40kHz modulation fre-
quency is sufficiently low so as not to be greatly affected by transmission losses
over the gate drive ribbon cables (to 3m) therefore the signal reaching the pulse
transformer maintains its fast rising edge.
When the Rectifier Logic Board requires to trigger the R+ SCR, the 40KHz
square-wave signal is applied to V37. When V37 turns on it connects the lower
end of the pulse transformer to 0V via a current limiting 22R resistor. A current
is induced in the pulse transformer secondary which makes the SCR gate potential
higher than the cathode – and triggers the SCR into conduction. Note that diode
V1 blocks reverse gate current in the event of ringing or voltage reversal of the
pulse transformer secondary and also reduces the SCR holding current.
Figure 4-18 shows that the trigger pulse is not applied for the complete possible
conduction period. In fact the “turn-on” envelope contains only 9 or 10 of the
40kHz trigger pulses. This prolongs the SCR life by avoiding excessive ‘wear’ on
the gate which would otherwise occur due to the additional heat generated by the
continued gate current after the SCR has turned on.

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 Section 4:

Chapter 4 - Rectifier Snubber Board (4540043B)

4.1 Snubber requirements and characteristics

Like all power semiconductor devices, SCRs are very intolerant of excessive volt-
ages; either steady voltages above their rating, or transient voltages which may
persist only for a few microseconds. Destructive breakdown or damage may
occur. Thus for reliable SCR operation, the use of overvoltage suppression tech-
niques are essential.
A transient can be defined by the rate of voltage rise with respect to time (dv/dt).
Potentially damaging transient voltages, with a dv/dt greater than 200V/µsec, can
be externally derived or produced internally by inherent SCR design operation.
One of the effects of high dv/dt transients is that they can cause the SCR to inad-
vertently turn-on (see page 4-5); and in the case of the rectifier application might
result in placing a short across the DC busbar, leading to a cascading failure of
other SCRs and rectifier components.

External sources
External transients are generated by the external supply and may be super-im-
posed on the normal AC supply source due to an input circuit breaker switching
operation or occasional lightening strikes.
Transients are also generated when energising and de-energising supply trans-
formers, which may exhibit ringing oscillations on their secondary windings
caused by the sudden application of voltage to secondary leakage reactance and
winding capacitance. Peak voltage of twice the normal value may be observed
when the transformer is energised; whilst de-energising may cause peak values as
high as ten times to be generated as the transformer flux is forced to decay rapidly
to zero.
Also, starting and stopping air conditioning units and motors might momentarily
alter the supply line impedance quite suddenly, and introduce voltage notching
sufficient to cause dv/dt SCR switching within the rectifier.

Internal sources
In general, the interruption of a current flow in a circuit may produce a potentially
dangerous transient voltage due to line inductance etc., unless alternative low re-
sistance discharge paths are provided. If unsuppressed, these transients will
appear within the circuit itself and may affect neighbouring circuits.
Excess di/dt (rate of change of current with respect to time) through the SCR may
cause internal failure due to excessive spot heating of the gate material. To slow-
down such di/dt changes, an inductor is connected in series with the rectifier input
augments the overall input supply inductance. Thus when turning-on an SCR, a
forward voltage step is applied which, when combined with the input circuit in-
ductance (L), causes an oscillatory peak voltage to appear across the device.
Similarly, when turning-off the SCR there is an abrupt interruption of the supply
current. During such commutation, the ‘outgoing’ SCR element does not block
reverse voltage immediately (see paragraph 1.2.5 on page 4-8). The commuta-

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SECTION 4 - Rectifier Operation & Control 7200 Series UPS Service Manual
CHAPTER 4 - Rectifier Snubber Board (4540043B)

tion voltage during the turn-off period causes a reverse current to flow until the
SCR blocks, at which time the reverse current stops suddenly. This rapid change
in current (which can be as high as 106 or 107 amps/second) can result in high re-
verse voltage spikes which can destroy the SCR device.
These rapid current changes also generate considerable radio frequency interfer-
ence (RFI); both radiated and conducted.

4.2 Snubber board

A simple R-C snubber circuit is usually employed to provide clamping of such
transient over-voltages. The snubber is connected across the device and if correct-
ly designed will limit both the amplitude and rate-of-rise of the voltage transient.
The R-C circuit is effectively a single-pole high-pass filter, tuned to a high fre-
quency relative to the transient dv/dt. That is, the capacitor blocks the 50Hz
supply voltage but will allow the higher-speed transient voltages through to the
resistor. The R-C time constant at fast dv/dt limits the rate of rise of the over-volt-
age and therefore also the magnitude. The resistor provides a discharge path for
any transient energy stored within the capacitor, thus the snubber is effective
against both external dv/dt and internal di/dt transient voltage spikes.

Figure 4-19: R-C Snubber filters transients

DC Bus +
Transient only
is allowed through
R-C filter

R+

R-ph
mains

100R
100W

0.1µf
R- 1kV

DC Bus –

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 Section 5: Inverter Operation & Control

Chapter 1 - Inverter Operating Principles

1.1 Introduction .............................................................................................. 5-1
1.2 Inverter operating principles – power block ............................................. 5-1
1.2.1 Inverter-phase ‘switch’ analogy ................................................... 5-1
1.2.2 DC-AC Conversion (Output AC voltage production) ................. 5-2
1.2.3 Pulse-width control of inverter voltage ........................................ 5-3
Generating a sine-wave 5-6
1.2.4 Pulse Width Modulation (PWM) control principles .................... 5-8
1.2.5 Inverter PWM duty cycle ........................................................... 5-10
1.2.6 Output filtering ........................................................................... 5-13
1.3 Inverter output detail .............................................................................. 5-15
1.3.1 Separately derived sources ......................................................... 5-18
1.4 Inverter IGBT transistor operation ......................................................... 5-19
1.4.1 Inverter transistor switching requirements ................................. 5-19
1.4.2 Insulated Gate Bipolar Transistor (IBGT) device ...................... 5-20
1.4.3 IGBT Device protection ............................................................. 5-22
1.4.4 IGBT Circuit design considerations ........................................... 5-23
1.5 Power Inverter Construction .................................................................. 5-26
1.6 Inverter control system ........................................................................... 5-28
1.6.1 Electronic control principle ........................................................ 5-28
1.6.2 Control system overview ........................................................... 5-29
1.6.3 Inverter voltage control .............................................................. 5-31
1.6.4 Inverter frequency control .......................................................... 5-32
1.6.5 Current protection ...................................................................... 5-32
1.6.6 Fault detection & Stop/Start control .......................................... 5-33
1.6.7 Control power supplies .............................................................. 5-33

Chapter 2 - Inverter Logic Board (4530025 T)

2.1 Chapter overview ................................................................................... 5-35
2.2 General description ................................................................................. 5-35
2.2.1 Circuit board functions .............................................................. 5-35
2.2.2 Input/Output connections ........................................................... 5-35
2.2.3 Block Diagram ........................................................................... 5-37
2.3 Detailed circuit description .................................................................... 5-39
2.3.1 Introduction ................................................................................ 5-39
2.3.2 Reference voltage generator ...................................................... 5-39
2.3.3 Volts error amplifier .................................................................. 5-45
2.3.4 PWM Modulator ........................................................................ 5-47
2.3.5 Current sensing and Current limit .............................................. 5-48
2.3.6 Drive pulse generator ................................................................. 5-49
2.3.7 Fault detection logic ................................................................... 5-50

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SECTION 5 - Inverter Operation & Control 7200 Series UPS Service Manual

2.3.8 Start/stop logic ........................................................................... 5-51

2.3.9 Power supply .............................................................................. 5-52
2.4 Summary Information ............................................................................ 5-53

Chapter 3 - Inverter Logic Board (4530024 S)

3.1 Chapter overview .......................................................................................55
3.2 General description .....................................................................................55
3.2.1 Circuit board functions ..................................................................55
3.2.2 Input/Output connections ...............................................................55
3.2.3 Block Diagram ...............................................................................57
3.3 Detailed circuit description ........................................................................59
3.3.1 Introduction ....................................................................................59
3.3.2 Reference voltage generator ..........................................................59
3.3.3 Volts error amplifier ......................................................................65
3.3.4 PWM Modulator ............................................................................67
3.3.5 Current sensing and Current limit ..................................................68
3.3.6 Drive pulse generator .....................................................................69
3.3.7 Fault detection logic .......................................................................70
3.3.8 Start/stop logic ...............................................................................71
3.3.9 Power supply ..................................................................................72
3.4 Summary Information ................................................................................73

Chapter 4 - Inverter Gate Driver Board

4.1 Chapter Overview ................................................................................... 5-75
4.2 General description ................................................................................. 5-75
4.2.1 Circuit board functions .............................................................. 5-75
4.2.2 Input/Output connections ........................................................... 5-76
4.3 Detailed circuit description .................................................................... 5-76
4.3.1 Power supplies ........................................................................... 5-76
4.3.2 Gate drive signal control logic ................................................... 5-76
4.3.3 Turning the inverter transistor ON ............................................. 5-78
4.3.4 De-saturation detector ................................................................ 5-78
4.3.5 Power supply monitor ................................................................ 5-80
4.3.6 Other connections ...................................................................... 5-80

ii S-5.FM5 - Issue 2 Dated 21/08/97

 Section 5:

Chapter 1 - Inverter Operating Principles

1.1 Introduction
The UPS inverter section converts the DC busbar voltage into a well regulated,
three-phase alternating voltage suitable for powering the critical load. As the DC
busbar voltage can vary typically between 432Vdc (when the batteries are on float
charge) and 320Vdc (the battery ‘end of discharge’ voltage) the inverter must be
controllable over this entire input voltage range to ensure that the critical load
voltage remains at the UPS nominal output voltage. The inverter control method
used in the 7200 Series UPS equipment is known as ‘pulse width modulation’
(PWM), and is described in simple terms in this chapter.
Liebert manufacture two designs of PWM inverter for use in large three-phase
UPS systems. In general, modules rated below 200kVA employ three independ-
ent, but identical, inverter phases operating at 120° with respect to each other to
produce the three-phase UPS output. Modules rated at 200kVA and above employ
a total of six inverter phases, with each UPS output phase obtained from two in-
verter phases operating in a ‘push-pull-like’ manner. These two types of inverter
configurations are described as being ‘single-ended’ and ‘double-ended’ respec-
tively.
Note: As the 7200 Series UPS range are currently all less than 200kVA they all
use a single-ended inverter design; however the double-ended design is also de-
scribed in this chapter for completeness of explanation.

1.2 Inverter operating principles – power block

1.2.1 Inverter-phase ‘switch’ analogy

Each inverter power block (also called an “inverter phase”) basically comprises
two IGBT transistors connected in series across the DC busbar, as shown in
Figure 5-1. In this diagram the transistor connected to the positive DC busbar is
identified as TRH (High) and the one connected to the negative DC busbar as
TRL (Low). The inverter output is taken from the junction of the two transistors.

Figure 5-1: Inverter phase switch analogy

DC BUS positive
Inverter power block

Pos. Bus
TRH

Gate drive waveforms O/P

180° output of phase

TRL

Neg. Bus

DC BUS negative

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SECTION 5 - Inverter Operation & Control 7200 Series UPS Service Manual
CHAPTER 1 - Inverter Operating Principles

When this circuit is used as a switch it has two stable states of interest:
1. When TRH is turned ON and TRL is OFF, the inverter output is effectively
connected to the positive DC busbar and is approximately equal to the posi-
tive busbar voltage.
2. Similarly, when TRH is turned OFF and TRL turned ON, the output is con-
nected to the negative DC busbar and is equal to the negative busbar voltage.

For this circuit to operate successfully as a switch, the transistors’ base drive sig-
nals must always be in anti-phase – i.e. one of the transistors must be OFF while
the other is ON. If both transistors are turned ON simultaneously they effectively
place a short circuit across the DC busbar and will cause the equipment to shut-
down, and possibly fail, due to a DC overload condition.

Basic inverter block output waveform

As the inverter power block operates as a switch, its output voltage takes the form
of a square-wave with a peak-to-peak amplitude equal to the DC busbar voltage,
and at a frequency determined directly by the transistors’ drive signal switching
rate (i.e. from the control electronics).
Note that the DC busbar is derived from the phase controlled rectifier and is in
practice approximately equidistant from ground (neutral) – e.g. if the bus voltage
is 450Vdc then the positive bus will be about +225Vdc with respect to neutral
(ground), and the negative bus about -225Vdc.

1.2.2 DC-AC Conversion (Output AC voltage production)

The above description showed that the basic inverter power block output takes the
form of an alternating (square) waveform; however, a substantial amount of con-
trol and power processing is necessary to convert this into a regulated sinusoidal
voltage suitable for presentation at the UPS output.

Figure 5-2: DC-AC Conversion (Step 1)

+ve Bus (450V) Block A Block B

ON ON ON ON

TR1 TR3

OFF OFF OFF OFF

A B
ON ON Output Transformer ON ON

TR2 TR4

OFF OFF OFF OFF

Output Filter
-ve Bus (0V)
To Load

Figure 5-2 illustrates two power inverter blocks connected together by a trans-
former: with inverter block A consisting TR1/TR2 and block B consisting TR3/
TR4. As described in paragraph 1.2.1, the drive signals to each pair of IGBTs
within an inverter block are always at 180° with respect to each other; however
the diagram in Figure 5-2 also shows that the relative polarity of the signals to the

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two inverter blocks are also in anti-phase – i.e. the drive signals to the ‘high’ tran-
sistors of Block A (TR1) and Block B (TR3) are in anti-phase, as are the signals
to the two remaining transistors (TR2 and TR4).
At the instant in time highlighted in Figure 5-2, TR1 & TR4 are both turned ON
and TR2 &TR3 are OFF. This leads to the left-hand side of the output transformer
primary winding being connected the positive DC bus (+450V) and the right-hand
side to the negative DC bus (0V), and current flows through the primary winding
in the direction A-to-B. Although at first glance this circuit may appear to present
a short-circuit across the DC busbar, the current flowing through the transformer
is limited by the impedance presented by the primary winding – which comprises
the impedance of the transformer itself, together with the reflected impedance of
the output filter and load (when connected).
When the control electronics reverse the transistor drive signals TR1 & TR4 turn
OFF and TR2 & TR3 turn ON. This reverses the polarity across the output trans-
former primary and, in this case, current now flows through the transformer from
B-to-A, as illustrated in Figure 5-3.

Figure 5-3: AC-DC Conversion (Step 2)

+ve Bus (450V) Block A Block B

ON ON ON ON

TR1 TR3

OFF OFF OFF OFF

A B
ON ON ON ON
Output Filter
TR2 TR4

OFF OFF OFF OFF

-ve Bus (0V)

Output to Load

Thus, by controlling the switching sequence of the two inverter blocks in relation
to each other it is possible to build-up a current flow through the transformer pri-
mary in either direction, which leads to an ‘alternating current’ being induced in
the transformer secondary and the production of an (alternating) secondary volt-
age. In practice the (‘output’) transformer is of a step-up design and its secondary
voltage represents the required UPS ‘output voltage’. The output amplitude is
controlled by using the ‘pulse-width modulation’ techniques described below,
working in conjunction with the output filter to obtain a good sinusoidal wave-
shape. The output filter comprises a capacitor network tuned with the output
transformer inductance to effectively remove the high frequency switching com-
ponents from the output waveform.

1.2.3 Pulse-width control of inverter voltage

Before discussing in depth the pulse-width modulation (PWM) methods em-
ployed to control the inverter output voltage, it is necessary to gain a basic under-
standing of the effects of varying the pulse-width of the inverter drive waveforms
together with the fundamental principles of the output filter. These are described
immediately below.

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Figure 5-4: Effects of varying drive signal M:S ratio

Bus +ve
2:1 Mark-Space
TRH
66%

TRL

Bus -ve

Bus +ve
1:1 Mark-Space
TRH

50%
TRL

Bus -ve

Bus +ve
1:2 Mark-Space

TRH

33%
TRL

Bus -ve

Basic control principles are best understood by considering the effects on the
output waveform of a single inverter power block when switching the inverter
transistors at a constant rate (‘modulation frequency’) but at various mark-space
ratios. This is illustrated in Figure 5-4 above, which shows the inverter output
waveform when TRH:TRL are turned on at ratios of 2:1, 1:1, and 1:2 respectively.
The top diagram illustrates the case where the inverter is operating at a constant
2:1 mark-to-space ratio – i.e. TRH ON period being twice that of TRL – which
results in a ‘mean’ output voltage (with respect to the negative DC busbar) ap-
proximately equal to 66% of the DC busbar voltage.
In the middle illustration the transistors are shown operating at a M:S of 1:1 (i.e.
equal ON and OFF periods). In this example the inverter output is a true square
wave and has a mean voltage approximately equal to 50% of the DC busbar volt-
age – once again with respect to the negative DC busbar.
A M:S ratio of 1:2 is shown in the lower illustration to produce a mean voltage of
approximately 33%.
Notice that in the above examples the inverter switching frequency is constant in
all three cases and the ‘mean’ output voltage is varied by changing the mark-to-
space ratio of the drive signals only.

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Basic filter principles

In the above examples the ‘mean’ output voltages are obtained by filtering the
variable m:s pulse waveforms. The filter works by absorbing energy (charging)
when the pulse is present (i.e. during the ‘mark’ period) and returning it back to
the circuit (discharging) when the pulse is absent (i.e. the ‘space’ period). This has
the effect of averaging-out the energy provided by each pulse over the complete
pulse period (e.g. P1, P2...), as shown below in Figure 5-5 – i.e. the ‘mean’ value
is the integral of the pulse width (shown shaded) taken over each complete pulse
period (P1, P2 ....).

Figure 5-5: Basic filter action

2:1 m:s waveform Positive bus

Mark 100%
Space 66%
Filter

0%

Negative bus
P1 P2 P3

The above 2:1 m:s waveform shows 3

pulses of mark+space period ‘P’. The A
waveform to the right illustrates the effects ‘mean’ voltage
of the filter on period 1 (P1) and shows
how part of the energy (A) absorbed during B A
the mark period is put back into the circuit
during the space period, leading to the
‘mean’ voltage shown.
P1

This waveform illustrates the same principles

at a 1:2 mark:space ratio. In this case less A
energy is stored during the ‘mark’ period
due to its shorter duration; therefore the ‘mean’
value is lower. ‘mean’ voltage
B A

P1

Note that in each of the above examples the ‘mean’ voltage produced is represented by the
area of the waveform’s ‘mark’ pulse – i.e. proportional to the width of the voltage pulse.

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[Link] Generating a sine-wave

From basic principles, a sine-wave can be developed by plotting the vertical com-
ponent of a vector as it is rotated through a complete circle.

Figure 5-6: Instantaneous value of a rotating vector

(π/2 rads)
90°

A rotation

V1
θ1 0
180°
(π rads) t1 360°
(2π rads)

270°
(2π/3 rads)

This is illustrated in Figure 5-6, which shows that when vector ‘A’ is rotated anti-
clockwise for time ‘t1’, its vertical component ‘V1’ can be described in trigono-
metrical terms as:
V1 = A sinθ1 – where θ1 is the angle of rotation (Equation 1).
When considering an electrical voltage waveform, the length of vector A repre-
sents the peak voltage and V1 represents the instantaneous voltage at time t1.
The relationship between the angle ‘θ1’ and time ‘t1’ is determined by the ‘angu-
lar velocity’ of the vector, which is usually represented in mathematical equations
by the greek letter omega (ω), where:
ω = 2πf rads/s (radians/second) (Equation 2).
– i.e. 2π is the number of radians travelled in one complete revolution, and f is the
frequency of rotation in revolutions-per-second (Hertz). For example: at 50Hz the
angular velocity of the vector is 2 × π × 50 = 100π radians per second.
Once the angular velocity (ω) of the vector is known, the instantaneous value of
θ1 at time t1 can be found by calculating the product of ωt. Using the previous
50Hz example; if time t1=2ms then θ1 equals 2 × π × 50 × 2 × 10–3 = 0.2π radians
(or 36°). By substituting 0.2π for θ1 and solving equation 1, the instantaneous
voltage ‘V1’ can be calculated as Asin0.2π which equals 0.588A – i.e. in electrical
terms, V1 = 0.588 x Vpeak.
Using the above principles, the instantaneous voltage V can be calculated at a par-
ticular time t using the general formula V=A sinωt where:
V = instantaneous voltage
A = peak voltage (length of the vector)
ω = the angular velocity – in radians/s (i.e. = 2πf)
t = instantaneous time (in seconds)

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Figure 5-7: Plotting a sinusoidal waveshape

90°

180° 0/ 360°
t8 t7 t6 t5 t4 t3 t2 t1 t0 t0 t1 t2 t3 t4 t5 t6 t7 t8
0° 90° 180°

270°

270° 360°
t9 t10 t11 t12 t13 t14 t15 t16
t0 t1 t2 t3 t4 t5 t6 t7 t8
0° 90°

The upper diagram in Figure 5-7 shows how a sinewave shape is developed by
plotting the instantaneous voltage amplitude at regular intervals as the vector is
rotated from 0° (t0) to 180° (t8) and transferring these values to a linear scale. The
lower diagram illustrates the formation of one complete cycle, which is obtained
by continuing with the plotted points from 180° (t8) to 360° (t16) to provide the
negative half cycle.
For reasons of clarity, the sampled intervals in the above diagrams are quite large
– i.e. only 16 samples are taken in the complete cycle. A much ‘cleaner’, more
accurate, waveform is produced if the sampling rate is increased: and in the prac-
tical 7200 series PWM control circuit the sine-wave is generated using 48 refer-
ence points per-cycle as opposed to the 16 points shown here.

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1.2.4 Pulse Width Modulation (PWM) control principles

Pulse-width modulation entails generating rectilinear output voltage pulses at a
repetition frequency considerably higher than the fundamental frequency (50Hz)
and modulating their duration so that the integrated value of each pulse is propor-
tional to the instantaneous value of the required fundamental component at the
time of its occurrence: that is, the pulse duration is modulated ‘sinusoidally’. This
is illustrated in Figure 5-8.
Figure 5-8A is an expanded view of the positive half-wave sinewave plotted in
Figure 5-7. Note that the voltage sampling rate shown is the same as the pulse rep-
etition rate and the instantaneous voltages at t0 to t8 coincide with the centre of
each pulse period: for example, the instantaneous voltage at time t1 coincides with
the centre of the period allocated for pulse 2 (P2).
Figure 5-8B shows the individual pulses P1-P9 superimposed on the instantane-
ous voltage plot and illustrates how varying pulse-widths are employed to ensure
that the ‘mean’ value of the pulse equals the plotted instantaneous value for the
particular pulse period. In each case the pulse amplitude is identical and compris-
es a ‘shaded’ and ‘hatched’ area – where the ‘shaded’ portion resents the ‘mean’
amplitude. For example, the ‘mean’ value resulting from the mark:space ratio of
the pulse during P3 equals the instantaneous voltage plotted at t2. This is shown
in more details in Figure 5-8C where the hatched portion at the top of pulse P3 is
shown to replace the space left at either side of the pulse – as described in the dis-
cussion of the basic filter principles Figure 5-5.
Note: to simplify explanation, the filter description in Figure 5-5 implied that the
drive pulse signal took the form of a mark followed by a space; however from the
control electronics point of view this is not the case, as shown in Figure 5-8. It is
true that the pulse repetition rate is constant, but the ‘variable’ pulse-width is con-
trolled by expanding and contracting the pulse about its centre point (known as
“double pulse-width modulation”). This does not affect the way in which the
output filter works, as the filter ‘sees’ only the presence or absence of pulses, and
stores and restores energy to the output circuit as previously described – i.e. the
output filter effectively ‘joins the dots’ by storing and shaping the pulse-width
modulated waveform to make the output envelope as near as possible to a sine-
wave.
A representative complete output cycle is shown in Figure 5-12.

The practical modulating frequency

As will be explained later, there are several considerations to be taken into ac-
count when deciding upon a modulating frequency, as this affects such things as
the generated output harmonics; inverter switching losses; and filter efficiency
and size. In general, Liebert-designed PWM inverters employ modulating fre-
quencies ranging from 2.4kHz to 9.6kHz.
In the 7200 UPS equipment the modulating frequency is fixed at 2.4kHz, which
therefore means that 48 switching pulses are used to produce each 50Hz (20ms)
output cycle – i.e. the output waveform is corrected every 7.5° (0.13 rad), leading
to a very accurate output waveform. The design specification is to produce a volt-
age sinewave with less that 5% THD for all rated input and load variations.

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Figure 5-8: PWM Control principles

P1 P2 P3 P4 P5 P6 P7 P8 P9

t0 t1 t2 t3 t4 t5 t6 t7 t8
0° 90° 180°

P1 P2 P3 P4 P5 P6 P7 P8 P9

t0 t1 t2 t3 t4 t5 t6 t7 t8
0° 90° 180°

P1 P2 P3 P4 P5 P6 P7 P8 P9

t0 t1 t2 t3 t4 t5 t6 t7 t8
0° 90° 180°

P1 P2 P3 P4 P5 P6 P7 P8 P9

t0 t1 t2 t3 t4 t5 t6 t7 t8
0° 90° 180°

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1.2.5 Inverter PWM duty cycle

The power delivered to the load by the inverter can be described mathematically
π⁄2
as the integral of the voltage & current (i.e. ∫0 VI dt ).

A PWM-controlled inverter provides load power each time it is turned on; there-
fore the power produced by the inverter during each output cycle is represented
by total area of the pulses contained in that cycle. Thus, when dealing with a
PWM waveform the integral equation above can be visualised by considering that
“the area of the output sinewave is equal to the sum of the areas of the individual
pulses used to generate the sinewave” (See Figure 5-9).

Figure 5-9: Output power derivation

The total amount of time the inverter IGBT devices are turned ON and delivering
load-power during each output cycle can be described in terms of the inverter’s
‘duty cycle’: and, as will be shown below, this varies in accordance with the avail-
able DC busbar voltage and the prevailing load current demand.

Figure 5-10: Typical inverter output section

Bus +ve (450Vdc – 320Vdc)
O/P Transformer O/P Filter
R S T
1:2 STEP-UP
R
R

S S Critical load
supply
(400VL-L)
T T
(200VL-L)
N

Bus -ve

The effects of the DC Busbar voltage on the PWM Duty cycle

Figure 5-10 illustrates a typical UPS output section set to operate at the standard
400V output voltage. The output transformer has a 1:2 voltage step-up ratio,
therefore the inverter must operate at 200VL-L.
200VL-L is equivalent to 115VL-N (i.e. 200 ⁄ ( 3 ) .) which is in turn equal to ap-
proximately 325Vp-p (i.e. 2 × 115 × 2 ). The inverter cannot produce a peak-to-
peak output voltage greater than the DC busbar voltage, therefore the output
waveform would clearly be clipped if the DC busbar falls below this 325V mini-
mum level.

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Figure 5-11: Effects of falling DC busbar voltage on the PWM duty-cycle

DC bus + (+225Vdc)
Combined area of pulses
equals the
area under output
sine-wave

DC busbar Inv output

450Vdc 326Vp-p

DC bus - (-225Vdc)

DC bus + (+225Vdc)

Combined area of pulses

still equals the
area under output
sine-wave
DC busbar Inv output
360Vdc 326Vp-p

DC bus - (-225Vdc)

In practice, the minimum DC busbar voltage is programmable and is usually set

to 1.67V per battery cell. The number of batteries connected to the busbar varies
according to the UPS working voltage. A standard 400V system employs 198
cells which leads to a minimum DC busbar voltage of 330V. Therefore, in a prac-
tical 400V system the DC busbar will vary between 450Vdc when the batteries
are being float charged and 330Vdc at the ‘end-of-discharge’ voltage – at which
point the inverter is shut-down and the load transferred to bypass (if available).
Note 1: Diagrams in this manual may indicate a minimum DC busbar voltage of
320V. This is in fact the minimum DC voltage at which the inverters are fully
rated and not necessarily the voltage at which the batteries are tripped off-line.
Note 2: The battery end-of-discharge voltage is also load dependant (see para-
graph 3.3.7 on page 7-29).
It has already been shown that in each output cycle the area of the sine-wave is
equal to the combined area of the associated PWM pulses; and also that the am-
plitude of the inverter pulses is equal to the DC busbar voltage. Therefore, when
the batteries are on-load, and the DC busbar voltage discharges from 450V to
330V, the width of the PWM pulses must increase proportionally as their ampli-
tude decreases in order to maintain a constant output voltage. This is illustrated in
Figure 5-11 which shows the effects on the PWM pulse-width as the DC busbar
reduces from 450V to 360V. Notice that this diagram shows that the peak, and
therefore r.m.s., value of the inverter output remains constant as the bus voltage

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falls. Once again, for reasons of clarity the illustration in Figure 5-11 uses only 16
PWM pulses-per-cycle rather that the 48 pulses used in the practical 7200 series
inverter.
With regards to the duty cycle: when the inverter is off-load and the DC busbar is
operating at its float charging voltage of around 450Vdc the sum of the inverter
conduction pulses amount to approximately 75° of the possible 180° forming each
half cycle a.c. conduction period. When the DC busbar is supported from the dis-
charging batteries the duty cycle increases to approximately 105° when the bat-
teries approach the end-of-discharge voltage of 330Vdc.

The effects of the Load demand on the PWM Duty cycle

The PWM wave-form duty cycle is directly affected by variations in the demand-
ed load current. For example, the previous paragraph illustrated that when oper-
ating off-load from the normal 450V busbar, the duty cycle is approximately 75°.
However, if the inverter is loaded under these conditions it would require that the
individual PWM pulse-widths are increased to maintain the output waveform
whilst allowing more power through to the load. In practice, at a nominal 450V
DC busbar the 7200 inverter duty cycle increases from 75° to approximately 80°
over the fully rated load range.
If the PWM duty cycle increase with falling DC busbar voltage and also with load
then the worst case conditions obviously occur when the inverter is operating near
the end-of-discharge voltage and at full load. Under these conditions the duty
cycle will increase to approximately 110°.
Note: as the duty cycle from no-load to full-load increases from 75° to 80°; and
the increase from float voltage to end-of-discharge voltage causes an increase of
70° to 105°, it can be seen that the duty cycle is affected more by changes in DC
busbar voltage than changes in load demand.

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1.2.6 Output filtering

Figure 5-12: One cycle of PWM control pattern

10 msec

15 msec

20 msec
5 msec
0 msec

20 msec
Bus +ve

TRH

0V

TRL

Variable m:s over 20 msec Bus -ve

50Hz sinewave obtained by

filtering the output
PWM pattern

Figure 5-12 illustrates the production of one PWM output cycle at 50Hz and
shows that the positive half cycle is created by beginning with a 1:1 ratio and then
increasing it to a higher ratio and back to 1:1 using a controlled pattern. The neg-
ative half cycle is produced in an identical manner; but in this case the ratio begins
at 1:1 and is then reduced to a lower ratio before returning to 1:1.
The sinusoidal output waveform is obtained be employing a filter which, in
simple terms, averages out the modulated waveform on a pulse-by-pulse basis and
thereby produces an output which rises and falls in a sinusoidal manner. In prac-
tice, this is achieved by a network of filter capacitors working in conjunction with
the inductance of output transformer to bypass the inverter modulation frequency
and its associated generated harmonics.

Figure 5-13: Filter current characteristics

Filter currents

Filter charging

Filter discharging
Output waveshape

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Figure 5-13 illustrates the filter action in detail. The diagram represents four
2.4kHz pulses at the beginning of the output positive half-wave and shows the ef-
fects of the charging and discharging filter currents during the presence and ab-
sence of the PWM pulses – i.e. the filter capacitors charge-up whilst a pulse is
present (storing energy) and then discharge when the pulse ceases (returning
energy into the output circuit to maintain the general output voltage waveshape).
As the PWM mark:space ratio gradually increases the resulting waveshape close-
ly resembles the required sine-wave.
Clearly, the charging and discharging filter currents are directly related to the
number of PWM pulses contained in the output cycle – i.e. the modulating fre-
quency. Where a fewer number of pulses are used per half-cycle, the overall
pulse-widths must increase to allow the filter to store a larger current during the
charge period in order to restore sufficient energy to the output circuit during the
discharge period to maintain the sinusoidal output waveshape; thus requiring
larger capacitors and inductors to handle the increased circulating power. How-
ever, although the required L-C components get smaller as the modulating is in-
creased, the inverter switching losses also increase and the overall inverter
conversion efficiency therefore reduces. The selected modulating frequency is
therefore a compromise between these two conflicting factors. An acceptable
mean is reached when using a frequency in the range 2.4kHz to 9.6kHz, and in
the 7200 series UPS an optimal frequency of 2.4kHz is used.

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Section 5:

1.3 Inverter output detail

Figure 5-14: Inverter output – basic block diagram

OUTPUT OUTPUT
POWER INVERTER TRANSFORMER FILTER
Bus +ve R R R
+450Vdc 1:2
S S
S
T T
0Vdc T
N N
Bus -ve
200Vac 400Vac

Bus +450Vdc

225Vdc
Ro
ta t
0V

i on
300Vdc

40

Neutral
V
2 30
225Vdc

DC Bus 0V

The inverter converts the DC primary source (nominal 450V DC busbar) to a bal-
anced 3-phase vector system on the UPS output. The inverter output is stepped-
up by a factor of 1:2 by the output transformer, which also provides galvanic iso-
lation; therefore an inverter output of 200V L-L is required to furnish the standard
400VL-L UPS output voltage –
Figure 5-14 contains a block diagram of the inverter output stage and a vector di-
agram which shows the relationship between the DC primary source (DC bus) and
the AC secondary objective (UPS output). The output neutral point is manufac-
tured by the output transformer’s star-connected secondary and is positioned ex-
actly at the mid-point of the DC primary source at all times – i.e. +225V or -225V
with respect to the nominal 0V or 450V DC input rails respectively. The neutral
is in fact floating about this mid-rail point and remains so as the busbar voltage
decreases towards 320V when powered from the discharging batteries.
As described earlier, (see "The effects of the DC Busbar voltage on the PWM Duty
cycle" on page 5-10), the mark:space ratio of the PWM drive signals are varied to
compensate for such DC busbar voltage fluctuations; however, as is evident from
Figure 5-14, a stage is reached whereby the available DC primary source is inad-
equate to sustain the output objective (even though the PWM duty has gone to
maximum). In the 7200 series equipment this occurs when the DC busbar falls

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below 290V. When this point is reached the output transformer will saturate and
cause flat-topping of the output voltage waveforms. Note that the inverter itself is
not affected and does not mind running on low input DC sources.
In practice, the inverter is turned off before the DC voltage reaches this absolute
minimum level. In the case of a 400V operating system the “end-of-battery” dis-
charge (DC undervoltage) threshold is set to approximately 330Vdc, as described
earlier in this chapter (See Figure 5-11).

Figure 5-15: Single-ended inverter output stage

Three
inverter
phases
Bus +ve (450Vdc – 320Vdc)
O/P Transformer O/P Filter
R S T
1:2 STEP-UP
R
R

S S Critical load
supply
(400VL-L)
T T
(200VL-L)
N

Bus -ve

Figure 5-16: ‘Double ended’ inverter output stage

Bus +ve
R-ph Main

S-ph Main

T-ph Main
R-ph Aux

S-ph Aux

T-ph Aux

Bus -ve
R S T

Output Transformer
R S T

Filter Capacitors

N R S T
To load via the Inverter-side static switch (contactor)

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Figure 5-15 illustrates the single-ended inverter output design, as employed in the
lower-rated 7200 Series product range, whereby the output transformer is con-
nected in a standard delta-star configuration. The output filter capacitors are con-
nected to the transformer secondary line-to-line and work in conjunction with the
transformer’s natural impedance to remove all remnants of the modulation fre-
quency from the output waveform and so leave a clean sinewave suitable for con-
necting to the load, via the inverter-side static switch (contactor).
A double-ended inverter output section, as employed in larger modules, is shown
in Figure 5-16. This design uses two power inverter blocks per output phase,
known as the ‘main’ and ‘auxiliary’ inverters. The transistors in each ‘inverter-
pair’ are switched in anti-phase with respect to each other – i.e. when the top tran-
sistor is turned on in the ‘main’ inverter the bottom transistor is turned on in the
‘auxiliary’ inverter (and vice-versa). This enables more power to be delivered to
the load, as described below.
An alternative way of increasing the output power, for a given busbar voltage, is
to use a number of IGBTs connected in parallel in each leg of the inverter power
block; however, due to difficulties with device matching, the inverter MTBF is
adversely affected as the number of parallel devices is increased. Using the
double-ended inverter topography means that no more than two parallel-connect-
ed devices are needed for the highest power rating offered in the 7200 UPS range.
As shown below, the power increase offered by a double-ended over a single-
ended inverter is equal to 3 – i.e. the relationship between a single-phase and
three-phase system.

Figure 5-17: ‘Single-ended’ versus ‘double-ended’ primary current path

Bus +ve Bus +ve

2 x 400A 2 x 400A
IGBTs IGBTs

800A
800A
I2
I1
ac

200Vac
0V

92kW 160kW
20

2 x 400A 2 x 400A
IGBTs IGBTs

Bus -ve Bus -ve

Single-ended – closed delta primary Double-ended – single phase primary

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CHAPTER 1 - Inverter Operating Principles

Figure 5-17 shows the comparative primary current flows in the ‘single-ended’
and ‘double-ended’ inverter output transformers. In the ‘single-ended’ circuit the
transformer primary windings effectively form a closed delta circuit, and the cur-
rent supplied by one inverter power block is always shared between two wind-
ings. In the case of the ‘double-ended’ circuit the output transformer primaries are
individually connected between the ‘main’ and ‘auxiliary’ power blocks of their
respective phases, effectively acting as three single-phase windings; therefore the
full current passes through each individual winding.

1.3.1 Separately derived sources

The inverter itself can be considered analogous to a generator in its own right. Full
noise rejection is achieved via the AC–DC–AC conversion, and the output trans-
former is double-wound, with isolation between primary and secondary. This im-
plies that there is no direct connection between the input mains and the inverter
output – i.e. it offers a separately derived power source.

Figure 5-18:

Bypass Mains
Supply

Input To Load
Mains
Supply

Rectifier Inverter Isolation Static Switch

Transformer
Battery

R
Perfectly balanced
3-phase bypass
source
230
40
0

Potential
T S
difference
between both R
neutrals
(10V - 1000V)
230
40
0

T S
Perfectly
balanced 3-phase
Inverter source

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The bypass supply is an alternative supply to which the load is transferred if the
inverter is switched off, or fails for any reason. A ‘no-break’ changeover is re-
quired during such transfers to ensure the load sees no interruption.
The 3-phase voltage (live wires RST) manufactured by the inverter are electron-
ically linked to the bypass 3-phase supply voltage (live wires RST) via the static
switch. The inverter neutral point is developed in the output transformer wye (zig-
zag) secondary, and if this point is not tied to the bypass neutral than a potential
difference may exist between the inverter and bypass power sources (it is possible
for this to extend from 10V right up to 1,000V).
To prevent this potential from appearing the output transformer neutral must be
directly tied to the bypass neutral. If this is not done the potential difference be-
tween both sources would induce a spike in the neutral during load transfers
which might damage the load equipment.

1.4 Inverter IGBT transistor operation

1.4.1 Inverter transistor switching requirements

When used in a power inverter environment, the inverter transistor is basically
acting as a power switch, and like all switches it ideally has two stable states:
1. When it acts as an ‘open switch’ the transistor is fully turned OFF and exhib-
its a high impedance. In this condition the collector current (Ic) is low (virtu-
ally zero) and the voltage across the collector and emitter (Vce) is very high
(almost equal to the DC bus voltage).
2. When it acts as a ‘closed switch’ the transistor is turned ON and exhibits a
low impedance. In this condition the transistor is in fact driven hard into satu-
ration. Its collector current is therefore high (as determined by the prevailing
load) and Vce low (equal to the saturation voltage of the device).

Since power is calculated as the product of the current flowing through the
device (Ic) and the voltage dropped across it (Vce), the transistor's power
dissipation (Ic x Vce) is very low in both its steady states – because Ic is very
small when the transistor is turned OFF, and Vce is very small when it is turned
ON . When the transistor switches from one state to the other, however, its
dissipated power rises to a peak and then returns to minimum as it traverses the
linear region of its particular load characteristic.
Transistors do not turn OFF and ON instantaneously; their turn ON and turn OFF
times are determined both by their internal construction and external circuit
influences. It is important, therefore, that transistors with fast switching times are
used in power inverter applications and sufficient drive power is used to ensure
the time taken to switch from one stable state to the other is as fast as possible, to
prevent the power dissipation reaching destruction level.
Note: as stated earlier, the 7200 series UPS uses a 2.4kHz switching frequency;
that is, the power IGBTs are each individually switched off/on at 2.4kHz. Thus
the IGBTs turn off and on 2400 times per second. Multiplying by minutes and
hours, this equates to 207.36 million on/off transitions per day. Considering that
there are 6 IGBT block (switching 300A @450Vdc) on smaller inverters, and
increasing to 24 blocks (switching 800A @ 450Vdc) on larger modules. This
leads to an enormous amount of power switching over the inverter’s design life
(10Yrs): hence annual preventive maintenance is highly recommended.

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CHAPTER 1 - Inverter Operating Principles

1.4.2 Insulated Gate Bipolar Transistor (IBGT) device

The 7200 series inverters use Insulated Gate Bipolar Transistors (IBGTs), which
combine the advantages of both FET and Bipolar transistor technologies to offer
a fast switching, high current device with a high gate impedance and low Vce
saturation voltage – these devices are described in detail below.
The IGBT is a voltage-driven element, but to turn it ON and OFF requires charg-
ing and discharging currents for the input capacity (CIES) because the IGBT has
a capacitance between adjacent terminals – as illustrated in Figure 5-19.

Figure 5-19: IGBT details

Collector

Collector

Gate

Gate
Emitter
RBE

C
CCG
Cies = CCG + CGE Emitter

CCE Coes = CCE + CCG

G
Cres = CCG

CGE E

Figure 5-20: IGBT high-speed switching surge voltages

Ic
High surge voltage
Vce (snubber required)
High critical rate-of-rise
of collector currents High critical rate-of-fall
(di/dt) of collector currents
(di/dt)

time

ton toff

Comparison of typical bipolar/IGBT device switching times

Parameter Bipolar IGBT

Turn on time (ton) 1 µsec 0.7 µsec

Turn off time (toff) 12 µsec 0.8 µsec

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The IGBT is a high-speed switching element. As the IGBT switches on and off a
large current at a high speed, the critical rate-of-rise (or fall) of collector currents
(di/dt) is considerably high and can result in the generation of high surge voltages
– as illustrated in Figure 5-20.

[Link] IGBT Switching characteristics

Figure 5-21: IGBT Switching waveform

EMITTER GATE
+15V

VGE
N°
P Rβ
+ -15V
- -
N° + + + + -
+ Ic
+ + 90%
N° + +

P°

10%

COLLECTOR tdon tf
tr tdoff
On-state electron/hole currents
within IGBT structure ton toff

Figure 5-21 illustrates the IGBT switching characteristic. The upper waveform
represents the idealised gate/emitter drive pulse (VGE); and the lower waveform
depicts the resulting collector current (Ic).
As can be seen from the lower waveform the total ‘turn-on’ time (ton) is the time
taken for the collector current to rise to 90%, and is made up of two components,
tdon + tr where:
tdon is the ‘tun-on delay time’ and is the time taken to attract electrons to the
region underneath the gate (i.e. holes migrate from the N-region to the P-
region) and is usually of the order of 250nsecs.

tr is the ‘rise time’ and is the time required for the collector current to increase
from 10% to 90% of its final value. This is directly proportional to the gate
impedance (i.e. the gate construction and internal input capacitance) and is
usually of the order of 500 nsecs.

The total ‘turn-off’ time is the time taken for the collector current to fall to 10%,
and is made up of two components, tdoff + tf where:
tdoff is the device ‘turn-off delay time’ and is the time taken to remove the
electrons from the region beneath the gate. This is usually of the order of
350nsecs.

tf is the device ‘fall time’ and is the time taken by the collector current to fall
to 10% of its initial value. This is the time taken to recombine the majority
carriers (holes) back to the N-region and is usually of the order of 350nsecs.

Propagation delay = ton + toff and is of the order of 1.5µs.

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[Link] IGBT Gating requirements

For ‘turn-on’ a positive gate voltage of 15V ±10% is recommended. This value is
sufficiently high to fully saturate the IGBT and minimise the on-state losses,
while it is sufficiently low to limit short-circuit current and its resulting stress. In
no case should a gate drive outside the range of 12V-20V be used for turn-on.
An IGBT will be off when its gate voltage is zero. However, in order to ensure
that the IGBT stays in its off-state when dv/dt noise is present in the collector
emitter voltage an off bias must be used. Use of reverse bias also decreases turn-
off losses. For H-series IGBTs an off bias of -15V is recommended.

[Link] RG Series Gate Resistance

Selecting the proper series gate resistor is very important as it has a significant
impact on the dynamic performance of the IGBT which is turned on and off by
charging and discharging the gate capacitance.
A smaller gate resistor will charge/discharge the gate capacitance faster, reducing
the switching times and switching losses. However, under short-circuit, or during
turn-off of the free-wheeling diode across the IGBT, the dv/dt applied to the IGBT
and its collector-to-gate capacitance can cause a current to flow in the gate circuit.
And if this current is large enough, the voltage developed across the gate resistor
can cause the IGBT to turn-on. Thus, while a smaller resistor offers enhanced rug-
gedness (rejection of dv/dt turn-on), they also provide less margin for gate noise
and can lead to oscillation problems in conjunction with the gate-emitter capaci-
tance and any parasitic inductance in the gate wiring. In addition, smaller gate re-
sistors allow faster turn-on di/dt of the IGBT and may cause an increased surge
voltage at forward recovery. Giving consideration to all the above effects, a resis-
tor value between 1R - 10R is recommended for the series gate resistance.

1.4.3 IGBT Device protection

[Link] Snubber circuit

Figure 5-22: Turn-off surge voltage

Ic VCE
Surge voltage ∆V

Ed

t
A snubber circuit is connected across the IGBT’s collector-emitter to suppress
any (potentially destructive) switching surge voltages which may otherwise occur
when the IGBT is turned off. The surge voltage is due to load inductance and the
recovery of the internal free-wheel diode, and its rate if rise (∆V) depends on the
turn-off speed.
The snubber usually comprises a capacitor (or resistor/capacitor network) which
is sized to keep the ∆V below the IGBT collector-emitter breakdown voltage. The
snubber activates when the collector-emitter voltage exceeds the DC power
source (i.e. Ed in the above diagram). The excess stored charge must be dissipated
before the IGBT begins its next turn-off operation, either through a resistor or
output circuit impedance.

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[Link] Desaturation detector

The IGBTs saturation voltage (VCE(sat)) is the voltage drop across the IGBT col-
lector-to-emitter when it is in the fully ON state. The saturation voltage is a func-
tion of the collector current (ICE), junction temperature (Tj) and gate-emitter
voltage (VGE) and is typically 2.5V - 4.0V at +15VGE and full ICE at Tj = 125°.
VCE(sat) increases proportionally with increases in ICE and Tj and is inversely pro-
portional to changes in VGE.
IGBT protection is incorporated by monitoring the voltage drop across the device
when it is ON and inhibiting the gate drive pulse if the monitored voltage rises the
permissible saturation voltage range. This function is provided by the individual
inverter Gate Driver Boards.

1.4.4 IGBT Circuit design considerations

[Link] Flywheel diode

Figure 5-23: Flywheel diode action

450V

Vsurge 800Vdc

On R1 Conducted back to
DC Caps via
flywheel diode

T1 (primary)
451V
450V
C1

R2

0V

0V

In the 7200 Series UPS inverter application, the IGBT is switching a PWM wave-
form into the output transformer primary. This primary is in fact a large inductor
and due to its magnetic properties will cause overshoot on the leading edge as
each pulse is applied. The size of the overshoot depends on both the transformer
and load inductance.
The IGBT’s internal flywheel diode will be forward biased once the overshoot ex-
ceeds the DC Busbar voltage by about 1V and, once it conducts, will pass the
excess energy due to the overshoot back into the DC busbar smoothing capacitors.
Since the diode has a fixed turn-on time, the surge voltage is suppressed by the
snubber network until the diode becomes forward biased.

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[Link] Device ratings

Voltage rating
From a design point of view, the maximum voltage applied to the device compris-
es four elements:
(Input volts(dc) x 2 ) + regen volts + surge volts + safety margin
From this it is desirable that the inverter input bus voltage should account for
about 50% - 60% of the IGBT rated voltage. The internal flywheel diode has the
same voltage rating as the IGBT.

Current rating
For safe operation the IGBT peak current must not exceed the device rating. In
general, the short-circuit rating of the inverter is set to 150%. Therefore, assuming
maximum current flows in such an overload event the desired steady-state current
should be approximately 50% - 60% of the maximum device rating.

(kVA) × Overload rate

The general formula is: I peak = Inverter
--------------------------------------------------------------------------- × 2 × 1.2
AC Volts (rms) × 3

(where 1.2 is the ripple factor)

Example: Select devices for 60kVA, 380V unit with 150% overload capacity:
60, 000 × 1.5
Current =  ------------------------------- × ( 2 × 1.2 ) = 232 Amps
380 × 3

Voltage = 500 (max DC) × 2 = 1000V

Nearest device to fit these ratings is 300A x 1200V

Note: The internal free-wheel diode is designed on the premise that a very short
current flows, so that steady state rating is regarded to be approximate half of that
of the main IGBT.

Junction temperature
IGBT power modules have a maximum rated junction temperature of 150°C. It is
therefore desirable to run the device under steady state at no more than 70% of its
maximum rating. Heat generated by the component is a mixture of both conduc-
tion and switching losses.
Conduction losses (Pss) occur while the device is ON and conducting current. The
total power dissipation during conduction is the product of the saturation voltage
Vsat (approximately 4V) and the on-state current (Ic) (max 300A).
Switching losses (Psw) is the power dissipated during the turn-on and turn-off
switching transitions:
Psw = Fpwm x (Esw(on) + Esw(off))
Where: Fpwm = Inverter switching frequency (2.4kHz)
(Esw(on) + Esw(off) = switch ON/OFF energy in joules/pulse
Total loss per device = Pss + Psw

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[Link] Parallel devices

In larger inverter power blocks two IGBTs may be connected in parallel in each
arm of the inverter. Under such circumstances it is desirable that the current is
shared between the two parallel-operating devices to within 10% of each other
and it is necessary to match the devices such that their Vce(sat) values are within
0.3V of each other.
To this end each device is ranked according to its Vce (sat) measurement, as shown
in the table below.

Table 5-4: IGBT Rankings

Type Vce(sat)

C 1.7 – 1.95

D 1.9 – 2.15

E 2.1 – 2.35

F 2.3 – 2.55

G 2.5 – 2.8

H 2.75 – 3.05

J 3.0 – 3.3

K 3.25 – 3.55

L 3.5 – 3.8

M 3.75 – 4.05

Note: IGBTs of different Vce(sat) values can be used in an inverter, but it is nec-
essary to use ranked devices in any parallel arm, and preferably in the complete
power block. Across power blocks, the output transformer inductance slows
down any possible fault current. Further-more, the maximum current allowed is
derated by 15% of both IGBT ratings (e.g. 2 x 300A = 600A x 0.85 = 510Amps).
Other influences on parallel device operation are:
• Inductance in the main circuit wiring –
minimised by using low-inductance symmetrical wiring.
• Driver wiring and differences in driver output impedance –
minimised by using twisted-pair conductors of short lengths.
• Equalisation of operating temperatures –
temperature equalisation assisted by using equal device mounting and
torque values.

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1.5 Power Inverter Construction

The power inverters are of modular design. The power components are mounted
on a heatsink assembly which is then affixed to the UPS back-wall. The inverter
modules fitted within the UPS are identical and interchangeable. That is, the R, S
and T inverter phases may be swapped over for troubleshooting if necessary and
an inverter module from any position in one UPS may be exchanged for any in-
verter module in another (provided that they are of the same power rating).
All the inverter modules are similarly constructed: in that the module contains:-
• The inverter IGBTs (transistors)
• An overtemperature-sensing thermostat fitted to the power block heatsink
– thermostats of all three (six) inverter phases are electrically connected in
series to provide a normally-closed circuit.
• Base Driver Board (See Chapter 4)
The Base Driver Board sits above the snubber capacitor and is fitted to
four mounting pillars. Connections between the base driver board and the
inverter transistors are made by tagged flying leads which are colour
coded as follows:

Black = Collector
White = Base
Red = Emitter

Flying leads are also used to connect the thermostat to Base Driver Board
terminals S and T.
Connection between the Base Driver Board and the Inverter Logic Board
is made by a ribbon cable which fits into a keyed socket connector (CN1).

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Figure 5-24: Power inverter construction (60kVA)

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CHAPTER 1 - Inverter Operating Principles

1.6 Inverter control system

1.6.1 Electronic control principle

The following overview of the electronic control methodology is provided before
the detailed explanation of the inverter control logic in order to bridge the gap be-
tween the previous description of the power objectives and the electronic control
source.
The control process used to manufacture the PWM waveform can be considered
as the reverse of that used by the power section to convert the PWM waveform
into a sinewave; as described in paragraph [Link].

Figure 5-25: PWM Signal production

(2.4kHz)
416µs Reference Waveform (VR) Carrier Waveform (Fc)

PWM
Waveform

20ms (50Hz)

The control mechanism compares a sinusoidal reference waveform with a tri-

wave carrier and produces a PWM pattern which changes state each time the ref-
erence waveform crosses the carrier, as shown in Figure 5-25.
In the 7200 equipment the tri-wave carrier amplitude is fixed, and its frequency
is governed at 2.4kHz. The reference waveform mimics the UPS output voltage
and therefore has a 50/60Hz base frequency.
As the above illustration shows, when the reference waveform (VR) rises above
the tri-wave (Fc) the output PWM pattern switches high, and vice-versa. Each
PWM pulse-width is therefore directly proportional to the instantaneous mean
value of the sinewave reference and is presented to the power IGBTs. The inverter
output therefore replicates the reference sinewave, and changes in output voltage
amplitude and frequency are achieved by altering the appropriate parameter of the
basic reference voltage waveshape (VR).

Carrier ratio (P)

The ratio of the carrier waveform frequency to the reference waveform frequency
determines the number of PWM pulses present per output cycle. In the 7200 series
UPS this equates to 2400/50 = 48. Therefore the inverter output will comprise 24
pulses in each of its output positive and negative half cycles.
Note: although the carrier frequency is said to be “fixed” it will in fact vary slight-
ly with the UPS base frequency as it tracks the bypass frequency as part of its syn-
chronisation control process. This results in 48 PWM pulses per cycle at all times.

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Another consideration, is that the carrier frequency must be divisible by the

number of output inverter phases (three in this case). This is necessary in order
that all three phases may be maintained at exactly 120° with respect to each other.
The selected carrier frequency (2.4kHz) also limits the size of the maximum pulse
allowed in the PWM pattern: f = 1--- therefore the maximum pulse width
1 t
= ------------ = 0.416ms
2400
The smallest permissible pulse is a function of the IGBT propagation delay (See
section 5 paragraph 1.4.2) and determined on the Base Driver Board. The delay
is of the order of 4µs.

1.6.2 Control system overview

Figure 5-26 shows the circuit boards associated with the inverter control system
together with their major control signals.
The Inverter Logic Board is central to the inverter control system and is the board
ultimately responsible for generating the inverter IGBT gate drive signals at the
appropriate pattern to effect the PWM control techniques described earlier in this
chapter. At its heart is a complex, analogue voltage regulation circuit which uses
the inverter voltage and inverter current sense signals within a series of closed-
control loops to maintain the required inverter voltage. It also contains a digital-
based frequency control system which synchronises the inverter frequency to the
bypass supply; and also maintains the inverter frequency at 50Hz (60Hz) when
the bypass supply is unavailable. Note that whilst individual voltage regulation
circuits are used for each phase, the frequency control logic applies to all three
phases to ensure their correct phase relationships are observed at all times.
The control system offers the following features, each of which is functionally de-
scribed in the remainder of this chapter:
• Output voltage limits selectable from the Operator Control Panel.
• Individual voltage regulation and current limit control on each phase.
• Overload protection of each inverter power circuit IGBT.
• Output overvoltage and undervoltage fault detection.
• Output frequency, synchronising window, slew-rate selectable from the
Operator Control Panel.
• Controlled start/stop features.
• Power supply monitor

[Link] Analogue control signals

Inverter voltage sense

The 3-phase inverter voltage is sensed at a point between the output transformer
and inverter-side static switch (contactor), and should therefore be at the nominal
UPS output voltage whenever the inverter is operating. The three independent
line-to-neutral sense signals are attenuated to 1% on the High Voltage Interface
Board and then passed to the Inverter Logic Board via the UPS Logic Board.
On the Inverter Logic Board the sense signals take the form of ‘voltage feedback’
inputs to the voltage regulation control loops.
On the UPS Logic Board, the sense voltage are converted to a digital form and
monitored by the board’s microprocessor system.

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Figure 5-26: Inverter control system

Bypass-side
Static Switch

Bypass
Supply

Inverter-side
Inverter Section filter Contactor
DC Bus Pos capacitors

Critical Load
3 Phase Output
Power Tfrmr
+ -
Inverter
DC Bus Neg
+ -
Inverter Base
Inverter current sense

Drive Bds.
Inverter voltage sense

Bypass voltage sense

Inverter Logic Board

Alarm Interface Board

(I/O Option)
UPS Logic Board
Operator Logic Board

Remote Alarms

Operator Control
High Voltage Panel
Interface Board

[Link] Analogue control signals

Inverter voltage sense

The 3-phase inverter voltage is sensed at a point between the output transformer
and inverter-side static switch (contactor), and should therefore be at the nominal
UPS output voltage whenever the inverter is operating. The three independent
line-to-neutral sense signals are attenuated to 1% on the High Voltage Interface
Board and then passed to the Inverter Logic Board via the UPS Logic Board.
On the Inverter Logic Board the sense signals take the form of ‘voltage feedback’
inputs to the voltage regulation control loops.
On the UPS Logic Board, the sense voltage are converted to a digital form and
monitored by the board’s microprocessor system.

Inverter current sense

The inverter output current is monitored by ‘Hall effect’ current sensors mounted
on the inverter S and T phases. These sense signals are attenuated on the High
Voltage Interface Board (by link selectable burden resistors) and then passed to
the Inverter Logic Board via the UPS Logic Board.

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Bypass voltage sense

The 3-phase bypass voltage is sensed at a point between the bypass isolator and
the bypass-side static switch, and should therefore be at the nominal mains volt-
age whenever the bypass switch is closed. The three independent line-to-neutral
sense signals are attenuated to 1% on the High Voltage Interface Board and then
passed to the UPS Logic Board.
On the UPS Logic Board, the bypass voltage sense signals are converted to a dig-
ital form and monitored by the board’s microprocessor system.

[Link] Digital control signals

Various digital signals are passed between the UPS Logic Board and all the other
boards connect to it. These can broadly be categorised as:
• alarm data generated on the Inverter Logic Board and UPS Logic Board
which are passed to the Operator Control Panel via the Operator Logic
Board – also to the Alarms Interface Board (for remote indication) where
fitted.
• inverter stop/start control signal generated on the UPS Logic Board in
response to other ‘system’ control parameters and applied to the Inverter
Logic Board as appropriate
• control data entered at the Operator Control Panel which is stored by the
UPS Logic Board – e.g. inverter voltage and frequency parameters.
• external control options – e.g. remote stop, emergency shutdown, sync
inhibit.

1.6.3 Inverter voltage control

Working voltage selection and basic control loop

The inverter voltage is controlled by an analogue circuit on the Inverter Logic
Board which instantaneously compares the inverter voltage sense signal with an
on-board generated sinusoidal reference voltage (See paragraph 2.3.2). Any error
detected between these two signals is applied to the PWM pattern generator in
such a manner as to make the inverter output waveform follow that of the refer-
ence sinusoid. This circuit therefore forms a closed-loop control mechanism
which produces a tightly regulated output voltage (See paragraph 2.3.3).
Independent circuits are employed for each of the output three phases; and poten-
tiometers are included in the ‘S’ and ‘T’ phase inverter voltage sense (feedback)
signals’ path to enable the voltage of all three phases to be manually balanced, if
necessary, to overcome the effects of component tolerances or excessively unbal-
anced load distribution.
The sinusoidal reference voltage amplitude can be selected to be one of three lev-
els, equating to 200V/220V/240V, as calibrated by a single potentiometer on the
Inverter Logic Board; however, the chosen level is selected by digital control sig-
nals generated on the UPS Logic Board in response to data entered via the Oper-
ator Control Panel (See Table 5-2).

Voltage error detection

All three inverter voltage sense signals are applied to a full-wave rectifier on the
UPS Logic Board and the resulting signal is digitised and monitored by software
controlled undervoltage and overvoltage detection functions. These are once
again programmable from the Operator Control Panel and are normally set to
±10%.

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In the event of a voltage error occurrence the UPS Logic Board will:
• send a STOP signal to the Inverter Logic Board to turn off the inverter.
• transfer the load to the bypass supply through the static switch operation.
• initiate the appropriate alarm indications on the Operator Control Panel.

1.6.4 Inverter frequency control

Reference voltage generator

As explained above, the closed-loop inverter voltage control circuit operation (on
the Inverter Logic Board) forces the inverter output to track the sinusoidal ‘refer-
ence voltage’. Therefore, the ‘reference voltage’ must also determine the inverter
frequency in addition to voltage.
The ‘reference voltage generator’ is a digital circuit which produces three synthe-
sised sinusoidal 50Hz(60Hz) waveforms – one per inverter phase (See paragraph
2.3.2). Its frequency is determined by a frequency reference signal produced by
the UPS Logic Board’s microprocessor system which is normally synchronised
to the bypass supply and reverts to the ‘base’ frequency (50/60Hz) when the
bypass supply is unavailable (See Figure 5-29) – note: synchronisation is main-
tained during normal operation to allow a ‘no-break’ load transfer to take place
between the inverter and bypass if necessary.
Although the actual reference voltage generator is situated on the Inverter Logic
Board, the previous paragraph shows that the UPS Logic Board microprocessor
provides the essential frequency control signals. The frequency control parame-
ters are therefore entered into the UPS Logic Board’s memory via the Operator
Control Panel. There include:
• base frequency selection – i.e. 50Hz or 60Hz.
• bypass sync window (normally ±2%) – i.e. the frequency extremities to
which the inverter is allowed to operate whilst tracking the bypass supply.
• tracking slew-rate (normally ±0.10Hz/s) – i.e. the maximum permissible
rate of change of inverter frequency whilst tracking the bypass supply.
Note that if the bypass frequency changes faster than the programmed
slew-rate then an “out of sync” error will be present during the periods of
non-synchronises operation.

External “Sync Inhibit”

In some installations a stand-by generator is used to provide an alternative input
(bypass) supply when the normal mains supply is unavailable. If such a generator
has unsuitable frequency regulation the inverter synchronisation function on the
UPS Logic Board may be inhibited by an external inhibit signal applied via the
one of the Remote Alarms Board options. This input would typically be slaved to
auxiliary contacts of the generator line contactor. Note that a ‘sync error’ condi-
tion will be prevalent while the synchronisation circuit is overridden.

1.6.5 Current protection

There are three forms of inverter current protection control:
• Inverter current limit –
the inverter output current sense signals are applied to a current limit cir-
cuit on the Inverter Logic Board which restrict the current on an individual
phase to approximately 150% of its nominal rating. If the phase current
reaches this level the phase voltage will be reduced to a level which sus-
tains this limit – i.e. if there is a short circuit on the critical bus then the

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inverter PWM pattern will be reduced to a minimum and the inverter will
deliver 150% current at a very low voltage in an attempt to clear the short
(See paragraph 2.3.5).

• IGBT overload protection –

Desaturation detection circuits built into each Inverter Gate Driver Board
inform the Inverter Logic Board of an overload condition on any of the
inverter IGBT devices which will then cause its internal start/stop control
logic to shut down the inverter operation (and subsequently transfer the
load to bypass).

• Output overload –
When the inverter is on-load the output current is monitored by the UPS
Logic Board and a software-controlled timer function provides an inverse
load/time shutdown facility which trips the inverter off-load – i.e. the
larger the overload the faster the trip action. The load profile is:
– 150% for 1 minute
– 125% for 10 minutes
– 110% for 1 hour
– 101% for 10 hours

1.6.6 Fault detection & Stop/Start control

The inverter is stopped and started in a controlled manner by a Stop/Start circuit
on the Inverter Logic Board which monitors the output from several on-board
fault detection circuits together with a ‘system-controlled’ general Stop/Start
command signal applied from the UPS Logic Board.
The fault conditions monitored on the Inverter Logic Board include:
• IGBT overload (from desaturation detector circuits on the Inverter Gate
Driver Boards)
• Disconnected ribbon cable on cards associated with the inverter control
circuits – as seen in Figure 5-26
• Inverter Logic Board power supply monitor

The general Stop/Start command signal applied from the UPS Logic Board is con-
trolled by various functions, such as:
• DC undervoltage (end of battery discharge)
• DC overvoltage
• Emergency stop
• Operator-selected start/stop commands from Operator Control Panel
• Inverter overvoltage

1.6.7 Control power supplies

The Inverter Logic Board and Gate Driver Boards are powered only from the DC-
DC Power Supply Board which is itself powered from the DC busbar. This means
that the inverter control circuit is active only when the DC busbar is ‘live’ – i.e. if
the power rectifier is operational or the battery circuit breaker is closed. The re-
maining circuit boards concerned with the inverter control function are powered
from either the AC-DC Power Supply Board or the DC-DC Power Supply Board
and are active when either supply is ‘live’.

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 Section 5: EP i.e. the larger

Chapter 2 - Inverter Logic Board (4530025 T)

Section 5:

2.1 Chapter overview

This chapter contains a circuit description of the Inverter Logic Board Part N º
4530025-T, which is used across the whole 7200 Series UPS model range, and
should be read in conjunction with circuit diagram SE-4530025-T (5 pages).
This is a direct replacement for PCB Part Nº 4530024-S which may be fitted to
modules manufactured prior to February 1997. Although there are only minor
differences between the two PCBs a full description of the Inverter Logic Board
Part Nº 4530024-S can be found in Section 5 Chapter 3.
Signal annotations shown on the circuit diagrams are shown in italics in the fol-
lowing text – e.g. [BLK-INV>.

2.2 General description

2.2.1 Circuit board functions

The Inverter Logic Board board is responsible for providing the drive signals for
the inverter IGBT transistors at the appropriate PWM (pulse width modulated)
pattern to produce the required inverter output voltage and frequency. In so
doing, the board monitors the following UPS parameters via the High Voltage In-
terface Board and UPS Logic Board:
• Inverter voltage – closed loop voltage regulation
• Inverter current – IGBT protection
• Bypass voltage – for inverter synchronisation
• System control signals from the UPS Logic Board micro (Run/Stop, Volt-
age/frequency selection, Current limit selection)
• Soft-start – 10 cycles to energise the output magnetics on start-up

As part of its control function, the board detects several abnormal operating con-
ditions and provides the UPS Logic Board control system with the following
error status signals:
• Inverter overload
• Inverter On/Off status
• Control power supply failure
• IGBT failure

2.2.2 Input/Output connections

The Inverter Logic Board has six connectors, described below:
• X1 – Output drive signals to Inverter Driver Board 4519015-H (R-phase)
• X2 – Output drive signals to Inverter Driver Board 4519015-H (S-phase)
• X3 – Output drive signals to Inverter Driver Board 4519015-H (T-phase)
• X4 – Control signals to/from UPS Logic Board (See Table 5-1)
• X5 – Power supply inputs from DC-DC Power Supply Board
• X6 – To Auxiliary Inverter Logic Board (used in large inverters only)

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Table 5-1: connector X4 (to UPS Logic Board) pinout details

PIN I/O Function

1-4 I/O 0V power supply rail

5-8 I/O +12V power supply rail

9 - 12 I/O -12V power supply rail

13 I Common – analogue feedback voltage ref

14 I Common – analogue feedback voltage ref

15 I [VI_A> Bypass A-ph volts sense from HVI Board – 8Vp-p

16 I [VI_B> Bypass B-ph volts sense from HVI Board – 8Vp-p

17 I [VI_C> Bypass C-ph volts sense from HVI Board – 8Vp-p

18 I [VIN_A> Inverter A-ph volts sense from HVI Board – 8Vp-p

19 I [VIN_B> Inverter B-ph volts sense from HVI Board – 8Vp-p

20 I [VIN_C> Inverter C-ph volts sense from HVI Board – 8Vp-p

21 I [IINV_A> Inverter A-phase current sense from HVI Board

22 I [IINV_B> Inverter B-phase current sense from HVI Board

23 I [IINV_C> Inverter C-phase current sense from HVI Board

24 I [XINV_OI> Mains error – load transfer to inverter = 1

25 I [DREF> Output voltage adjustment - used in parallel modules

26 I [DREF0> Output voltage adjustment - used in parallel modules

27 I [DV-A> Load sharing input for parallel modules only

28 I [DV-B> Load sharing input for parallel modules only

29 I [DV-C> Load sharing input for parallel modules only

30 I [DV-0> Load sharing input for parallel modules only (common)

31 I [INV_L> ‘Inverter on load’ commanded on UPS logic Board – Load-on-inverter = 1

32 O [OVL_INV> Inverter overload status to UPSLB micro (OVL = 0)

33 O [BLK_INV> Inverter On/Off status to UPSLB micro (Off = 1)

34 O [BACK> Frequency sync signal fed back to UPSLB micro – pulse

35 I [SYNC> Reference frequency produced by UPSLB micro – pulse

36 I [ON_INV> Inverter On/Off control from UPSLB micro (Off = 0)

37 I [INV_F> from UPSLB micro (Inv Freq - used in ref w/form gen) – 50Hz = 0 and 60Hz = 1

38 I [INV_A> from UPSLB micro - used in output volts selection

39 I [INV_B> from UPSLB micro - used in output volts selection

40 O Thermostats output to UPSLB (optional)

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2.2.3 Block Diagram

Figure 5-27 shows the Inverter Logic Board at its most basic functional block di-
agram level – the basic function of each of the blocks shown is described below,
with a more detailed, component level description provided in the remainder of
the chapter.

Figure 5-27: Inverter Logic Board basic block diagram

Inverter Current
Inverter I Overload (x3)
Current Limit
sense (x3)
Sense
PWM (x3)

Feed forward
Drive Inverter
PWM IGBT
Modulator Pulse Drive
Generator Pulses

voltages (x3)
AC Control
Parallel Current
share
(∆V Adj.) Volts
Error
Inverter Volts
F/B (x3) Amplifier
(actual)

control line
Start/Stop
Bypass Volts AC Reference
F/B (x3) voltages (x3)

Bypass Freq Frequency

Reference
Control
Output Volts Voltage
Tri-wave (x1)
Select Generator

Bi-directional Start/ Fault

Control Stop Detection
(UPSLB) Logic Logic

(UPSLB) Power ±12V

Supply ±5V
DC-DC Supply

Reference voltage generator

The ‘reference voltage generator’ produces three AC reference sine waves at
120° with respect to each other which act as voltage demand signals to the ‘volts
error amplifier’. These signals dictate the amplitude, frequency and waveshape of
the eventual inverter output voltage.

Volts error amplifier

This block compares the AC reference signals with voltage feedback signals de-
rived from the inverter output, and produces error signals proportional to any
detected amplitude difference. Three individual error amplifiers are contained in
this block, one for each phase, which means that each inverter phase is individu-
ally controlled. Note that the outputs from this block are annotated “AC control”
signals, as it is these signals that ultimately determine the adopted PWM pattern
which in turn directly determines the inverter output three phase voltage.

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In a parallel module (1+1) installation an additional input is applied to the volts

error amplifier to control the inter-module output current-sharing by effecting in-
dividual fine control over each inverter phase output voltage.
The error signal is produced by the Parallel Logic Board (see paragraph 2.5 on
page 8-31) and applied to the volts error amplifier as a ∆V adjustment.
The maximum voltage correction from this signal is ±5% of nominal inverter
output.

Current limit
AC signals proportional to the inverter output current are processed by the ‘in-
verter current sense’ circuit and fed to the ‘current limit’ block where they apply
a current limit function to the ‘drive pulse generator’ circuit if the current reaches
150%. Three independent circuits are contained in this block, one per phase, so
each output phase is individually controlled.

Modulator
This circuit modulates the AC control signals with a 2.4kHz tri-wave signal, pro-
duced by the ‘reference volts generator’, and generates three PWM waveforms.
Once again three independent circuits are used, one per phase.

Drive pulse generator

The ‘drive pulse generator’ converts the PWM signals into suitable IGBT base
drive signals. This block contains interlocking logic to prevent the simultaneous
triggering of both IGBTs in an inverter phase, a high frequency modulator, over-
load protection and general start/stop control of the output drive waveforms.

Start/stop logic and Fault detection

Numerous fault detection circuits are contained on the board. These control the
internal start/stop control lines to the ‘reference volts generator’ and ‘drive pulse
generator’, and also provide status signalling to the UPS Logic Board micro for
use by the system control logic. Signals from the UPS Logic Board to this (Invert-
er Logic) board also effect start/stop control in accordance with the system’s
control logic demands.

Power supply
The Inverter Logic Board is powered from the DC-DC Power Supply Board,
which is live whenever the power rectifier is operational or the batteries are con-
nected to the busbar via the battery circuit breaker.
This power source provides ±12V d.c. power rails which are then diode blocked
to the second supply source (from the AC-DC Power Supply board) the UPS
Logic Board – hence the board will be powered only from the DC-DC Power
Supply but once the mains fails (i.e. the AC-DC Power Supply is off) the DC-DC
Power Supply will keep all the circuit boards energised.
On-board 5V regulators, fed from the ±12V rails, provide stabilised ±5V power
rails for those devices that require it.

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2.3 Detailed circuit description

2.3.1 Introduction
The Inverter Logic Board circuit diagram (SE-4530025-T) comprises 5 sheets.
With reference to the block diagram in Figure 5-27, the drawings can broadly be
described as follows:
• Sheet 1 contains a ‘signal map’ showing the interconnection of the signals
passing between the other four sheets.
• Sheet 2 contains the reference voltage generator circuit
• Sheet 3 contains the:
– ‘volts error amplifier’ circuit
– ‘current limit’ circuit
– ‘PWM modulator’ circuit
• Sheet 4 contains the ‘current sense’ circuit and current limit detector
• Sheet 5 contains the:
– ‘drive pulse generator’ circuit
– ‘start/stop logic’ circuit
– ‘fault detection logic’ circuit

2.3.2 Reference voltage generator

(circuit diagram sheet 2)

Figure 5-28: Reference voltage generator block diagram

volts adj (R242)

[INV_A> Set
[BLK>
[INV_B> Volts
Stepped
V-peak waveform AC Reference
Resistor Voltage
Ladder

[REF_A>
[INV_F> Multiplexer Filter
Staircase
[S_TRI> [REF_B>
Pattern
Multiplexer Filter
Generator

φ Disp. adj
(R247)
C Phase [REF_C>
[O_BACK> Reference
Phase
Generator
Locked
[O_SYNC> Loop
Tri wave
Generator [TRI>
Freq-reference

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This circuit is responsible for producing three sinusoidal voltages, spaced at 120°
with respect to each other, which are then connected to the ‘volts error amplifier’
in the form of AC reference voltages. The voltages produced by this circuit can
thus be considered as ‘voltage demand’ signals, and represent the amplitude, fre-
quency and wave-shape desired at the inverter output voltage.

Multiplexer operation
The ‘reference voltage generator’ circuit’s operation is centred around D3 and
D4. These are 8-channel multiplexers whose 8 data lines are connected to various
points along a resistor ladder network (R1-R12), and whose 3 data-select lines are
clocked by the ‘staircase pattern generator’, ASIC D1. Each multiplexer output
(pin 3) is thus connected to one of 8 discrete voltage levels tapped along the re-
sistor ladder depending on the state of the data-select inputs.
In practice, the logic sequence of the signals to the three data-select inputs, from
D1, are such that a stepped waveform is produced at the multiplexers’ outputs
which takes the broad form of a full-wave rectified a.c. voltage – (See Figure 5-
28).
Voltage control. As the voltages at each stage of the stepped waveforms equal
the voltages present along the resistor chain, the stepped waveform peak voltage
is determined by the voltage at the top of the chain – i.e. the voltage at buffer N2c
pin 8. This is controlled by the circuit block annotated ‘set volts’ in Figure 5-28
and described in detail below.
Waveshape control. The AC reference voltage waveshape is determined solely
by the sequential logic within D1 and cannot be adjusted.
Frequency control. The AC reference voltage frequency is determined by the
clock frequency applied to the ‘staircase pattern generator’ (D1 pin 43), as this
controls the rate at which the multiplexers step through their sequence. This is
controlled by a phase locked loop which is normally synchronised to the bypass
supply frequency – described later (See Figure 5-29).
Set volts & Resistor ladder
As described above, the ‘set volts’ circuit (See Figure 5-28) provides a controlled
voltage at the top of the resistor ladder which thereby determines the peak value
of the AC reference voltages – and thus also the inverter output voltage.
It is possible to select one of three output working voltages: 380V, 400V and
415V. This is achieved by two signals from the UPS Logic Board annotated
[INV_A> and [INV_B> which are connected to the data-select inputs of D7, which is
a dual 4-channel multiplexer. The inputs to the ‘X’ channel (‘1X’ to ‘4X’) of D7
are connected to regulated DC voltages which represent the various UPS working
voltages. These are selected by the [INV_A> and [INV_B> to appear at the ‘X’
output as follows:

Table 5-2: Working voltage selection (D7)

[INV_A> [INV_B> Channel Volts

0 0 X1 380V

0 1 X2 400V

1 0 X3 415V

1 1 X4 Manual Set

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The voltages applied to ‘1X’, ‘2X’ and ‘3X’ are produced by a resistor network
connected across a variable regulated dc power rail which is itself connected be-
tween the 0V and -12V supply rails; the voltages are therefore of a negative
polarity. In practice, R242 is adjusted to obtain approximately -4V across N4; this
voltage is then divided by R54 - R57. The response of the inverter voltage control
loop is such that the signal at D7 ‘X’ output has a sensitivity of approximately
92Vac/V – e.g. a voltage of approximately -4.5V is required to produce an invert-
er output voltage of 415Vac. R242 thus provides the means of calibrating the
output voltage when the UPS is operating.
Note: R242 adjusts the voltage of all three phases. Further resistors are provided
which individually adjust the B and C phase line voltages and can be used to bal-
ance the output line voltages if necessary – described later (see page 5-45).
The ‘manual’ mode is elected by the UPS Logic Board in response to the operator
input and is designed to be used in a ‘test’ environment. When this mode is select-
ed the output voltage can be varied by means of R243 (0-600Vac), which is
connected between the -5V rail and ground, and whose wiper voltage is connect-
ed to D7 ‘X4’.
The selected voltage at D7 output (pin 13) is inverted to a positive voltage by N3b
and buffered by N2c before it is applied to the top of the resistor ladder network
(this voltage can be monitored at test point X8-4 where it has a sensitivity of ap-
proximately 0.01Vdc/Vac output. e.g. a level of 4.1Vdc is equivalent to 400Vac
on the inverter output).
An output from the ‘start/stop logic’, annotated [BLK> on the circuit diagram, re-
duces N3b voltage to zero when the inverter is being commanded OFF. This
reduces the voltage at the top of the resistor ladder to zero which thus results in a
“zero voltage” demand to the inverter voltage regulation circuit.
[BLK> goes high when in the stop/start logic is in its ‘STOP’ mode which clamps
the input to N2 pin 10 to 0V via V41. When this signal switches to its ‘START’
mode (low), V41 turns off but the voltage rise at N2 pin 10 is slugged by R50/C14
to restrict the rate of increase of the inverter demand voltage. This soft-start
action takes approximately 10 cycles to complete and is designed to slowly ener-
gise the output magnetics and thus reduce the inverter start-up surge current.
Note: The inputs to the ‘set volts’ circuit from X4 pins 25/26 and amplifier N3a
are not used, and play no part in the stop/start function.

Staircase pattern generator

The ‘staircase pattern generator’ is based on D1, which contains a complex series
of synchronous logic gates and timers and produces two sets of signals which are
connected to the multiplexer data-select inputs – e.g. output A1-C1 are connected
to multiplexer D4 and outputs A2-C2 to multiplexer D3. The sequence of these
outputs, which is determined solely by D1’s internal logic, produce stepped sig-
nals at the multiplexer outputs which resemble a full-wave rectified waveform.
Two frequency-related signals are applied to D1. An input to D1 pin 44, annotat-
ed [INV-F>, controls one of D1’s internal dividers and sets the inverter nominal
base frequency. This signal, which is logic high for 60Hz operation and low for
50Hz, is produced on the UPS Logic Board in response to inputs from the Oper-
ator Control Panel. The input to D1 pin 43 is a 288kHz clock signal, produced by
a phase-locked-loop (PLL) circuit, which controls D1’s internal operation.
Note: The PLL determines the inverter free running frequency and is normally
synchronised to the bypass supply (See Figure 5-29).

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In addition to the multiplexer data-select signals described above there are several
other frequency-related outputs from D1.
• The outputs from pins 31 (D2) and 36 (D1) are square-waves at the nomi-
nal base frequency which determine the zero-crossover points of the
inverter output and S phases respectively. These are connected to the filter
section – described later (see page 5-44).
• The output from pin 40 is a 2.4kHz square-wave which is converted to a
tri-wave by the ‘tri-wave generator, described below, for further use by the
‘PWM Modulator’ (See paragraph 2.3.4). The frequency of this signal is
determined by the logic levels at pin 1 (S2) and pin 2 (S3), as selected by
X-15 links 1 and 2 – detailed on sheet 1 of the circuit diagram.

Table 5-3:

X15(0-1) S2 X15(0-2) S3 Frequency Usage

Open (0) Open (0) 1.2kHz N/A

Closed (1) Open (0) 2.4kHz All models

Open (0) Closed (1) 4.8kHz N/A

Closed (1) Closed (1) 9.6kHz N/A

• The output from D1 pin 28 (ST2), annotated [S_TRI>, is connected to the

‘drive pulse generator’ block where it modulates the ultimate output drive
waveform (See paragraph 2.3.6). Once again the frequency of this signal
is controlled by links on X15. Normally, it is a 2.4kHz square-wave.

• The output from D1 pin 27 (PLL), annotated [O_BACK> (test point X8-5)
via D99, is connected to the UPS Logic Board via a variable resistor
(R247) – shown on sheet 5 of the diagram (See Figure 5-29). This signal is
a square-wave at the nominal base frequency coinciding with the zero-
crossover point of the A-phase AC reference voltage (i.e. the actual
inverter frequency at the moment). On the UPS Logic Board a phase-com-
parator function within the microcontroller compares this signal with a
similar signal derived from the bypass supply R-phase and is thus able to
detect an out-of-phase conditions. R247, located in the [O_BACK> line,
allows any residual phase displacement between the inverter and bypass
R-phase waveforms to be nulled once the two sync signals are phase-
locked.

• The output from D1 pin 21 [O_SYNC> is connected to one of the phase

locked loop (PLL) phase comparators’ inputs. The square-wave signal at
this point is a synchronizing frequency as selected by the PLL software
routine on the UPS logic board. This can be at the bypass frequency, the
previous frequency or base frequency as shown in Flow Chart 7-4 & Flow
Chart 7-5 in Section 7 Chapter 7. Due to the phase locked loop action
(described below) this signal is aligned with the A-phase inverter zero-
crossover point.

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Figure 5-29: Frequency synchronisation control

X2
D42 D53 Bypass supply R-phase
62 15 5
F-IN 18 voltage sensing
F-INM

X3 X4
63 16 4 [O_BACK>
BACK
34 34
BACKM

D17 INV-F INV-F 44

15 D1
37 37
DATA 50 /60 Hz
(Selected from Frequency
MICROCONTROLLER

BUS 27
Operator Panel) Divider
Staircase
(PORT 2)

Generator
R247
43
phase
align
288kHz

CLK
2-3 = Single
1-2 = Parallel (nominal)

50/60Hz
4
D59 14 X34
1 Phase
9
Locked

F Correction
2 VCO
Loop
15 3
64 D10 14 13
5 13 Phase
35 35
SYNCM SYNC 12 Comparator
Pulses proportional to Master Freq D6 3
phase error between reference for [I_SYNC>
Inverter & Bypass mains Inverter Osc Phase
error signal
UPS Logic Board Inverter Logic Board

Phase locked loop (PLL)

A PLL (D6) provides the clock signal for the ‘staircase pattern generator’ and
thereby has direct control over the inverter output frequency. This is a standard
type 4046 i.c. which contains two types of phase comparators (only one of which
is used) and a voltage controlled oscillator (VCO) centred at 288kHz.
One of the phase comparator’s inputs (D6 pin 14) is driven by a square-wave fre-
quency reference signal, annotated [SYNC>, which is produced by the UPS Logic
Board microprocessor system. That is, this signal relates to the error between the
inverter and bypass frequency, as calculated by the microprocessor, which then
adds a percentage gain correction under its slew rate program. The signal is then
presented to the PLL phase comparator – e.g. if there is an instant change to the
bypass frequency from 50Hz to 51Hz, the microprocessor detects an error of 1Hz.
This error is then divided by the slew rate e.g 0.1Hz/Sec, and the [SYNC> signal
is modified from 50Hz to 51Hz in increments of 0.1 over a 10 second period.
The other phase comparator input, to D6 pin 3) is driven by a 50/60Hz output
from the ‘staircase pattern generator’ (D1 pin 26) which is described above. If the
comparator’s input signals are out of phase the phase comparator output (D6 pin
13) will either add or subtract voltage to C2 (depending on the phase relationship)
and apply an error correction signal to the VCO’s control input (D6 pin 9) – i.e.
the VCO frequency is effectively made to track the frequency reference signal.

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For example – if the bypass frequency rises slightly, the following actions will
take place:
1. The sync control function on the UPS Logic Board will increase the [SYNC>
signal frequency by an appropriate amount, determined by the microproces-
sor under the control of the slew rate programme.
2. When the PLL compares the [SYNC> signal with the base frequency signal
from the ‘staircase pattern generator’ it will detect that the [SYNC> signal is of
a slightly higher frequency and the output from D6 pin 13 will exhibit logic
high pulses equal to the periods of phase difference.
3. The pulses at D6 pin 13 are filtered and applied to the VCO control input at
D6 pin 9 in the form of a dc correction voltage and will cause an increase in
the VCO output at pin 4.
Note: 2.5 volts at D6 pin 9 equates to a centre frequency of 288kHz, as set by
C1, R33 and R34. An increase in voltage at pin 9 will cause the RC charge
rate to increase, with as subsequent increase in VCO frequency. A decease in
the voltage at pin 9 will cause the VCO frequency to reduce.
4. This increases the ‘staircase pattern generator’ clock rate which then
increases the inverter frequency along with the base frequency signal pro-
duced at D1 pin 27.
5. When the base frequency signal at D1 pin 27 has risen to match that of the
[SYNC> signal, the phase comparator within the PLL ceases to detect any
phase error and the correction voltage at pin 13 will stop changing. The VCO
control voltage will thus remain constant and the inverter will be maintained
at its current frequency and in sync with the bypass supply.

Filter & C-phase reference generator

The filter sections convert the full-wave rectified stepped waveforms produced
by the ‘multiplexers’ into sinusoidal AC reference signals suitable for connecting
to the ‘volts error amplifier’ – (See Figure 5-27).
Two filter sections are used; one processes the A-phase AC reference signal and
the other for the B-phase.
Considering the A-phase circuit: the stepped waveform produced by the A-phase
multiplexer (D4) is buffered by N1a and connected to D5 pin 13. This signal is
also inverted by N1d and connected to D5 pin 12. D5 is an electronic switch con-
trolled by the output from D1 pin 36 – which was previously described as a
squarewave signal at the nominal base frequency, coinciding with the A-phase
zero crossing points. If D5 is switched by this signal then the signal at its output
pin 14 will be a stepped sine-wave comprising both halves of the signals present
at its pins 12 and 13. This stepped waveform is then filtered by N2a which pro-
duces a smooth sinusoidal AC reference voltage [REF_A> and can be monitored at
test point X8-1 as an 8V peak-to-peak sinewave.
The B-phase circuit operates in an identical manner but displaced by 120° – i.e.
[REF_B> lags [REF_A> by 120°.

The C-phase signal, [REF_C>, is produced by N2d which differentially sums the
other two phases with 0V. Theoretically, in a three phase system the instantane-
ous sum of all three voltages equals zero: therefore by subtracting the A and B
phase signals from 0V the output from N2 pin 14 is equivalent to the C-phase AC
reference signal, [REF_C> – i.e. A + B + C = 0 ∴ C = -(A + B).

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Tri-wave generator
The square-wave signal from D1 pin 40 is connected to an integrator circuit
(N3b/c) via adjustable resistor R241. This resistor allows the peak value of the tri-
wave signal to be calibrated and is adjusted to obtain a 4V peak-to-peak triangu-
lar waveform at the left hand side of R2 (i.e. ±2V peak).
The tri-wave output from N3 pin 8, annotated [TRI>, is connected to the ‘PWM
modulator’ (diagram sheet 3).

2.3.3 Volts error amplifier

(circuit diagram sheet 3)

Figure 5-30: Volts error amplifier & modulator block diagram

line volts adj

Inv volts F/B
[VINV_X>
Volts
AC Reference volts Error
[REF_X> D8
Amplifier
[VI_X>
Bypass volts F/B

[RIF>

Current
[IINV_X>
Feed/fwd
PWM waveform
AC Control volts to output driver

PWM
[TRI> [MOD_X>
Modulator
Tri-wave

Each block shown is triplicated – one block per inverter phase

Note: As an almost identical circuit is used for each phase the following descrip-
tion refers to the ‘A’ phase only, with any differences between this and the ‘B’
and ‘C’ phase highlighted.
The purpose of the ‘volts error amplifier’ is to compare the inverter output volt-
age feedback signal with the AC reference voltage created by the ‘reference volts
generator’ (See paragraph 2.3.2) and provide an appropriate AC control signal to
the ‘PWM modulator’ – i.e. if the ‘volts error amplifier’ detects an error between
the inverter output voltage feedback signal and the AC reference voltage it modi-
fies the AC control voltage to change the PWM pattern in such a way as to restore
a balanced condition; therefore effectively making the inverter voltage closely
track the AC reference voltage.

Inverter voltage feedback signal

The inverter A-phase output feedback voltage is sensed at the output side of the
output transformer (i.e. at nominal system output volts), attenuated to approxi-
mately 1% on the High Voltage Interface Board and connected to the Inverter
Logic Board at X4-18. The signal ([VINV_A>) is amplified slightly as it passes

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through N5a to N5b, which acts as the ‘error amplifier’, and can be measured at
test point X9-8 as an ac voltage in the range 4.5V to 5.0V (about 14Vp-p) depend-
ing on the system working voltage. Calibration resistor R246 allows for
individual A-N line voltage adjustment.
Note: Calibration resistors are also included in the ‘B’ phase and ‘C’ phase feed-
back inverter volts feedback signal paths which enables those two phases to be
individually balanced to the ‘A’ phase during board set-up. R224 adjusts the B
phase and R245 the C phase.

AC Reference voltage signal

The A-phase AC reference signal is connected to the error amplifier (N5b) via an
electronic switch comprising part of multiplexer D8. This switch is controlled by
a signal annotated [RIF> which is normally ‘low’, leaving the switch in the posi-
tion shown on the circuit diagram. When [RIF> goes high the switch changes over
and replaces the AC reference voltage input into the error amplifier (N5b) with a
signal derived from the R-phase bypass voltage [VI_A> connected to X4-14 which
makes the inverter voltage track the voltage on the bypass supply line.

Bypass voltage sense signal

[VI_A> is connected via an attenuator circuit on the High Voltage Interface Board
which is identical to that connected in the inverter output feedback signal path.
The bypass voltage sense signal at test point X9-5 therefore has the same sensi-
tivity as the inverter feedback voltage at X9-8 (about 14Vp-p).
When the inverter is first started, [RIF> goes high and energises D8 which then
connects the bypass voltage sense signal [VI_A> to the ‘volts error amplifier’ ref-
erence input – thereby replacing the AC reference voltage as the voltage demand
signal. The inverter voltage will thus rise to equal the bypass voltage. Once the in-
verter voltage has stabilised at the ‘bypass’ level the output contactor will close
to put the inverter on-load. At this point [RIF> reverts to a logic low and D8 deen-
ergises to select the AC reference voltage as the voltage demand signal. This is
done to prevent arcing across the inverter output contactor when it closes and
therefore increases its operating life and reliability.

Volts error amplifier

N5b sums the AC reference voltage and the inverter voltage feedback signal and
its output takes the form of a sinusoidal voltage representing the reference signal
superimposed with a signal representing any detected error. This is then filtered
by N5c and connected to N5d where it is processed in conjunction with an A-
phase current-derived signal.
Note: A third input to N5b from N9a is used only when the module is operating
as part of a multi-module parallel system and provides a means for implementing
load sharing control. In a ‘single module’ installation this circuit is not used and
the inputs to X4 pins 27-30 are left open circuit.

Current feed-forward
N5d sums the volts error amplifier output from N5c with a signal proportional to
the output current, annotated [IMN_A>. This is a ‘feed-forward’ signal which calls
for an increased inverter voltage as the current increases and improves the overall
inverter voltage regulation characteristics. The output from N5d is connected to
the ‘PWM modulator’ in the form of the AC control voltage, as depicted in Figure
5-27, where it directly controls the generated PWM pattern.

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All three AC control signals are summed by N9d and its output is connected back
to the feed-forward amplifier in all three phases. As, in a three phase system, the
sum of all three phase voltage should equate to 0V, this provides a virtual neutral
reference point for all three amplifiers which prevents the AC control signals
drifting with respect to each other and also ensures that no harmful dc voltages
are generated in the output transformer windings.
Note: In a module fitted with a double-ended (12-pulse) inverter (optional config-
uration generally reserved for larger modules) the AC control voltage is
connected to the Auxiliary Inverter Logic Board via X6-9 and buffer N10a. In a
standard module connector X6 is not used.

2.3.4 PWM Modulator

The A-phase PWM pattern is generated by N11, which is configured as a differ-
ential comparator whose inverting input is driven by the variable (sinusoidal) AC
control voltage and non-inverting input by a fixed frequency (2.4kHz), fixed volt-
age (±2V) tri-wave signal generated by the ‘reference voltage generator’.
N11 generates the PWM pattern by detecting when the fixed tri-wave voltage is
cut by the AC control voltage as illustrated below.

Figure 5-31: PWM Pattern production

Tri-wave (fixed)
N11
PWM pattern
AC control voltage
(variable)

Tri-wave (fixed)

AC control signal
(low)

3
PWM pattern

AC control signal
(high)

Tri-wave (fixed)
1

PWM pattern
3

The upper waveform diagram depicts the condition where the AC control voltage
is low with respect to the tri-wave (equal to about 25% of the tri-wave peak volt-
age) and illustrates that this results in a PWM pattern with a mark-to-space (m:s)

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ratio of approximately 3:1. The lower diagrams shows the situation when the AC
control signal is increased to about 75% of the tri-wave peak voltage and illus-
trates the output m:s now equals 1:3. This shows that the m:s ratio of the output
waveform can be varied by varying the AC control signal; and if this signal is
varied in a sinusoidal manner then the output waveform will represent a sinusoi-
dally modulated PWM pattern.
This pattern is processed by the ‘drive pulse generator’ and applied to the inverter
IGBT transistors such that for each individual inverter phase the ‘high’ IGBT is
turned on when the PWM signal is high – and vice versa.
Note: if a 12-pulse inverter is fitted (option on larger modules only) the three AC
control signals and tri-wave signal [TRI> are connected to the Auxiliary Inverter
Logic Board via the four sections of N10 (buffers) and connections X6 pins 9 to
12 – i.e. the Auxiliary board contains its own ‘PWM modulator’ and ‘drive pulse
generator’ stages.

2.3.5 Current sensing and Current limit

(circuit diagram sheet 4)

Current sensing
The inverter current is sensed by Hall-effect CT’s fitted between the inverter and
output transformer. In modules above 200 kVA a CT is fitted to each phase but
only two CTs are used in modules at or below this rating, fitted to the S and T
phases only. In the latter case the phase current is calculated from the other two
(monitored) phases.
The CTs’ sense signals are calibrated by jumpers on the High Voltage Interface
Board which determines the overall burden resistance (See section 7 paragraph
2.3.24) and then connected to X4 pins 21 to 23 on the Inverter Logic Board via
the UPS Logic Board.
In the lower-rated modules, where only two CTs are fitted, the A-phase current is
calculated by N15a which sums the B and C phase current sense signal (via jump-
ers X16-1 and X16-2) with 0V. As in a three-phase circuit the instantaneous sum
of all three currents equals zero then the output from N15a pin 1 represents the A-
phase current – i.e. A + B + C = 0 ∴ C = -(A + B). In installations using three
CTs, X16 jumpers 1 and 2 should be ‘open’ and jumper 3 must be ‘made’. This
connects the A-phase signal directly to N15a in the same manner employed by
the other two phases.
As all three phases are identical in operation the following description refers to
the A-phase only.
N15 effectively buffers the current sense signal and the output on N15a pin 1 (test
point X10-1 shows approximately 0.2Vp-p signal when the inverter is on no-load)
is in-phase with the output phase current. From N15a this signal is inverted and
amplified by N15b whose output [IMN-A> is connected to the ‘current feed-for-
ward’ circuit in the AC control voltage line – described earlier.

Current limit
The output from N15a is also rectified by N15c/N15d (zero gain) whose output
pin 14 provides a positive full-wave rectified signal representing the inverter A-
phase current which is then applied to a comparator circuit comprising N18. The
comparator’s operating threshold is set by R248 which is connected across a 4.7V
zener regulator and adjusted to present +0.6Vdc at N18 non-inverting input –

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available at test point X10-4. This represents 150% of the rated inverter load cur-
rent, and if the current sense signal to N18 inverting input exceeds this level then
the output from N18 pin 7 ([BLK_A>) will switch to a logic low level and apply an
inhibiting input to the ‘drive pulse generator’ (described below) which prevents it
from turning on the A-phase inverter transistors. This effectively limits the in-
verter peak current to the set 150% threshold.
Note that the inverter is not shut down during the above event; but the current
limit action will take place during each pulse of the 2.4kHz PWM drive signal –
i.e. sub-cycle operation. This effectively reduces the PWM pattern and therefore
the inverter output voltage will fall to the level necessary to restrict the current to
its 150% level. Taken to its extreme, if there is a short-circuit on the critical bus
then the inverter PWM pulses will be reduced to a minimum and the inverter will
deliver full (150%) current at very low voltage in an attempt to clear the short.

2.3.6 Drive pulse generator

(circuit diagram sheet 5)
This circuit, which comprises a complex series of gated latches within D11 to-
gether with driver transistors V42 to V47, performs signal conditioning on the
PWM pulsetrains produced by the ‘PWM modulators’ to make them suitable
drive signals for the inverter IGBT transistors.
Note: these signals are connected to the IGBTs via the Inverter Driver Boards
(one per phase) which provide further signal conditioning.

D11 internal gates

Those gates within D11 concerned with the ‘drive pulse generator’ function com-
prise three independent channels controlled by the PWM modulated signals
[MOD_A>, [MOD_B>, [MOD_C>, in conjunction with [STRI>.

Taking the A-phase circuit as an example; the drive control inputs to D11 are
[MOD_A> and [STRI> and the outputs from D11 are taken from pin 36 (drive to the
A-phase inverter low IGBT [PAL>) and 37 (high IGBT [PAH>).
[PAL> switches high, turning on the ‘low’ IGBT via V42, when [MOD_A> is low
and [STRI> goes low. This condition is latched until [MOD_A> is high and [STRI>
goes high, whereupon [PAL> returns low, turning off the ‘low’ IGBT, and [PAH>
goes high, turning on the ‘high IGBT via V43.
There are two means by which the drive pulse logic can be inhibited within D11.
The first occurs if an overload is detected, in which case the [BLK_A>, BLK_B>,
[BLK_C> signals described earlier will inhibit the particular channel being over-
loaded – (See paragraph 2.3.5). The second is by means of a general ‘stop/start
logic’ block within D11 which handles signals from the UPS Logic Board and
from the local ‘fault detection logic’ and provides a controlled stop/start function
– (See paragraph 2.3.8).

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2.3.7 Fault detection logic

(circuit diagram sheet 5)
Circuits on the Inverter Logic Board monitor the following faults:
• Inverter current limit
• Inverter overload (from desaturation detector on driver interface boards)
• Ribbon cable discontinuity
• Inverter stack thermostat overtemperature
• Power supply monitor

Each of these facilities are described below

Inverter current limit

The ‘inverter current limit’ circuit is shown on the diagram sheet 4 and described
in detail in paragraph 2.3.5. This circuit provides three inputs to D11 annotated
[BLK_A>, [BLK_B> and [BLK_C> which go low if an overload is detected on the as-
sociated phase. In the event of a phase current rising to the current limit level the
following occurs within D11:
1. The drive signals to the affected phase(s) are inhibited, as described above.
2. A summary current limit signal (logic low) is produced at D11 pin 21 if any
one of the three phase currents reach the current limit level. This is inverted to
a high by D10b and connected to the UPS Logic Board via X4-32 as an
inverter overload status alarm signal [OVL_INV>, where it is used for display
purposes only (code 33). From D10b pin 10 the signal is also passed back
through D11 pins 20 to 19 and illuminates H14 to provide an on-board indica-
tion that the inverter overload circuit is activate. Note that the signal to D10b
is slugged by V23/R300/R237/C141 on removal of the overload to allow the
inverter conditions time to stabilise before the overload status is reset.
3. The [BLK_A>, [BLK_B> and [BLK_C> signals are buffered within D11 and out-
put at pins 31, 32 and 33 respectively. These are passed to the Auxiliary
Inverter Logic Board in a 12-pulse inverter installation via connector X6 pins
13, 14 and 15 (used in large module only).

Inverter Vce(sat) (from desaturation detector on driver interface boards)

A circuit on the Inverter Driver Board (See paragraph 4.3.4) detects an inverter
IGBT fault (short or open circuit) by sensing when the particular device is desat-
urated during its ‘ON’ period. These boards thus provide six fault signals back to
the Inverter Logic Board via pins 3/4 and 13/14 of connectors X1 (A-phase) X2
(B-phase) and X3 (C-phase) respectively. The fault signal applied to these inputs
take the form of a logic low on fault, but this is inverted to a high by a section of
D9 and diode-coupled to a single input at D11 pin 8 [DIS> which is therefore high
if a desaturation condition is detected on any inverter IGBT and drives the Start/
stop logic within D11 to its stop mode (see below).
Note: the Vce(sat) signals produced by the various sections of D9 illuminate
LEDs H5 to H10 to positively identify the location of the faulty IGBT transistor.

Ribbon cable discontinuity

A system of verifying that the ribbon cables connecting the Inverter Logic Board
to the three Inverter Driver Interface Boards is implemented by the connections
to X1 to X3 pins 5/8. Pins 5 and 8 of the respective connectors are linked together
on the Inverter Driver Interface Boards and so present a short-circuit which pulls

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D11 pin 9 ([COI>) low if the cables are all correctly in place. However, if one of
the cables are disconnected while the inverter is operating [COI> will rise to a
logic high and drive the Start/stop logic within D11 to its stop mode (see below).
Note: this signal is buffered within D11 and produces a logic high output at D11
pin 18 which illuminates H13 if a fault occurs.
X12 provides a means of overriding this circuit for test purpose only when it is
made 0-2 – this jumper should always be OPEN during normal operation.

Inverter stack thermostat overtemperature

A facility exists in which thermostats fitted to the power inverter heatsinks can
provide an overtemperature status signal to the UPS Logic Board. The thermo-
stats provide a normally-closed circuit between X1-5 and X3-8 and produce a
logic low signal at X4-40, which is connected to the UPS Logic Board. If any
thermostat opens (at a temperature above 90°C) then this chain is broken and X4-
40 is pulled high via R100 and V24.
Where this option is not used (standard), a jumper should be fitted to X12 posi-
tion 0-1 to override the overtemperature fault signal which would otherwise
appear. Reposition this jumper to OPEN when the option is used.

2.3.8 Start/stop logic

This circuit is based on a multi-input logic gate within D11 which monitors the
‘fault detection logic’ circuits described above, together with several control
inputs from the UPS Logic Board, and either enables or disables the ‘drive pulse
generator’ outputs (also within D11) in response to the input signals’ status.

Start/stop logic circuit outputs

Three ‘start/stop’ status outputs are also produced by D11, as described below:
• D11 pin 7 goes high on stop and is the source of the [BLK> signal to the
‘reference voltage generator’ circuit. When the ‘stop/start logic’ is in its
stop mode this signal reduces the ‘reference voltage generator’ output to
zero and thus demands zero output voltage.
• D11 pin 28 goes high on stop and sends a status signal to the UPS Logic
Board via X4 pin 33 to request the micro to disable the inverter run signal.
• D11 pin 34 goes high on stop and sends a status signal to the Auxiliary
Inverter Logic Board (12-pulse inverter only); thus ensuring that where
this option is used both the main and auxiliary boards are stopped and
started by a common control signal.

Start/stop logic circuit inputs

The ‘start/stop logic’ within D11 is driven by the following D11 inputs:
1. Inverter Vce(sat) error (detected by desaturation detector on Inverter Driver
Interface Boards) – logic high to D11 pin 8 forces the stop mode (See para-
graph 2.3.7).
2. Connector discontinuity (led H13 illuminated) – logic high to D11 pin 9
forces the stop mode (See paragraph 2.3.7).
3. A system start/stop control input to D11 pin 13 from the UPS Logic Board,
via X4-36, which is low on stop and high on start, provides the means of
allowing the UPS Logic Board to shut down the inverter in response to certain
system events – e.g. DC overvoltage, low battery, OFF selected from the
Operator Panel, emergency shutdown, etc. This input also drives led H12 via

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D11 pin 17 (inverts the signal at pin 13) and illuminates the led when the sig-
nal is demanding the inverter to be turned OFF.
4. If a 12-pulse inverter is installed (option) the output from the ‘start/stop’ cir-
cuit on the Auxiliary Inverter Logic Board is connected to D11 pin 14 via
X6-18 and is logic high on stop. This ensures that both main and auxiliary
Inverter Logic Boards react to a common ‘Start/stop’ line (see also the output
from D11 pin 34 described above).
5. A power supply monitor circuit based on N22 applies a logic high input to
D11 pin 16, placing the ‘stop/start’ circuit in its stop mode if the 12V supply
rail falls below 10Vdc. This circuit also holds off the inverter operation when
the UPS is first powered up until the 12V rail rises above this level to allow
the power supply time to stabilise before initiating the PWM drive signals.
Led H11 illuminates when this circuit is demanding a stopped condition.
6. The transfer to inverter command [INV_L> generated on the UPS Logic Board
is connected to D11 pin 12. This is clocked through D11 to enable the [RIF>
signal. This re-references the inverter voltage to the bypass voltage just before
the inverter is about to take over the load, which prevents any voltage drop
appearing across the output contactor when it is instructed to close (See para-
graph 2.3.3).
The inverter voltage is referenced to the bypass voltage level for approxi-
mately 220ms before is it switches back to its normal reverence voltage: this
more than adequately covers the output contactor closure time, which is
approximately 50ms. Note that this function is disabled by the ‘mains fail’
signal [MNS_KO> to D11 pin 11 in the event of a mains failure; thus if the load
is transferred to the inverter when there is no bypass to the UPS, then the
inverter will remain referenced to its normal reference voltage at all times.

2.3.9 Power supply

(circuit diagram sheet 5)
This board receives its control power supply from the DC-DC Power supply
Board only, via connector X5. Pins 3, 4 and 5 carry regulated +12V, 0V and -12V
power rails which form the Inverter Logic Board’s main supply inputs; and pins
1 and 2 carry an isolated 36Vac supply which is used by the Inverter Driver Inter-
face Boards and connected via connectors X1, X2 and X3, as shown.
A 5V regulator, N21, provides a regulated +5V rail from the +12 supply.
The ±12V rails are diode-coupled to the ±12V rails on the UPS Logic Board via
V14 and V15, as shown on sheet 5 of the diagram. Thus in the event of mains fail-
ure (i.e. the AC-DC Power Supply is inactive) the DC-DC Supply will maintain
the control power to all the electronic circuit boards.

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2.4 Summary Information

Table 5-4: Inverter Logic Board configuration jumpers

Jumper Link Position Function

open Enable thermostat detector (Standard)

0-1
closed Override thermostat detector (Test only)

open Enable disconnected cable detector (Standard)

0-2
closed Override disconnected cable detector (Test only)

0-3 Voltage select Manual inv Testing only Open

X12 closed = standard
0-4 override adj R243
6 links-override
0-5 Frequency select override
control inputs
0-6 Force Inv ON => ignore all blocks from UPS logic
board as shown
0-7 Ignore Inv ‘On Load’ signal on main circuit
diagram
0-8

0-5 1200Hz

0-1 2400 Hz (Standard) PWM modulating

X15 0-2 4800Hz frequency selec-
tion
0-1
9600Hz
0-2

0-1 C-phase current monitor signal selection (where only 2 CTs are
0-2 fitted to the inverter phases – standard to 7200 range)
X16
C-phase current monitor signal selection (where 3 CTs are fitted
0-3
to the inverter phases – used in larger modules)

Table 5-5: Inverter Logic Board potentiometer adjustments

Potentiometer Function
R241 Amplitude of triangle wave adjustment
R242 Inverter voltage reference setting
R243 Manual inverter voltage adjustment (0 to 500V)
R244 Phase B to Neutral adjustment
R245 Phase C to Neutral adjustment
R246 Phase A to Neutral adjustment
R247 Phase displacement adjustment Inverter to Bypass
R248 150% Inverter Current Limit

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Table 5-6: Inverter Logic Board LED indications

LED Colour Function

H1 Green 380V operation
H2 Green 400V operation
H3 Green 415V operation

Manual operation Range 0 - 500 Volts ( Clock-

H4 Amber
wise = minimum)
H5 to H10 Red Transistor saturation, (R+, R– : S+, S– : T+, T–.)
H11 Red PCB power supply failure
H12 Red Inverter off from UPS Logic Board
H13 Red Ribbon cable monitor block
H14 Red Inverter in 150% current limit (Active)

Table 5-7: Inverter Logic Board test points

Test Point X8
X8 - 1 Inverter ref. A (8Vp-p)
X8 - 2 Inverter ref. B (8Vp-p)
X8 - 3 Inverter ref. C (8Vp-p)
X8 - 4 Inverter DC ref.
X8 - 5 Inverter pulse for φ displacement
X8 - 6 φ displacement error pulse

Test Point X9
X9 - 8 Inverter feedback A
X9 - 7 Inverter feedback B
X9 - 6 Inverter feedback C
X9 - 5 Bypass A 8V p-p
X9 - 4 Bypass B 8V p-p
X9 - 3 Bypass C 8V p-p
X9 - 2
Not Used
X9 - 1

Test Point X10

X10 - 1 Current φ A (0.2V p - p No Load)
X10 - 2 Current φ B (0.2V p - p No Load)
X10 - 3 Current φ C (0.2V p - p No Load)
X10 - 4 0.6V Current limit

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 Section 5: EP i.e. the larger

Chapter 3 - Inverter Logic Board (4530024 S)

Section 5:

3.1 Chapter overview

This chapter contains a circuit description of the Inverter Logic Board 4530024S,
which was used across the whole 7200 Series UPS model range prior to February
‘97 when it was superceeded by 4530025T – see chapter 2. This chapter should
be read in conjunction with circuit diagram SE-4530024-S (5 pages).
Signal annotations shown on the circuit diagrams are shown in italics in the fol-
lowing text – e.g. [BLK-INV>.

3.2 General description

3.2.1 Circuit board functions

The Inverter Logic Board board is responsible for providing the drive signals for
the inverter IGBT transistors at the appropriate PWM (pulse width modulated)
pattern to produce the required inverter output voltage and frequency. In so
doing, the board monitors the following UPS parameters via the High Voltage In-
terface Board and UPS Logic Board:
• Inverter voltage – closed loop voltage regulation
• Inverter current – IGBT protection
• Bypass voltage – for inverter synchronisation
• System control signals from the UPS Logic Board micro (Run/Stop, Volt-
age/frequency selection, Current limit selection)
• Soft-start – 10 cycles to energise the output magnetics on start-up

As part of its control function, the board detects several abnormal operating con-
ditions and provides the UPS Logic Board control system with the following
error status signals:
• Inverter overload
• Inverter On/Off status
• Control power supply failure
• IGBT failure

3.2.2 Input/Output connections

The Inverter Logic Board has six connectors, described below:
• X1 – Output drive signals to Inverter Driver Board 4519015-H (R-phase)
• X2 – Output drive signals to Inverter Driver Board 4519015-H (S-phase)
• X3 – Output drive signals to Inverter Driver Board 4519015-H (T-phase)
• X4 – Control signals to/from UPS Logic Board (See Table 5-8)
• X5 – Power supply inputs from DC-DC Power Supply Board
• X6 – To Auxiliary Inverter Logic Board (used in large inverters only)

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Table 5-8: connector X4 (to UPS Logic Board) pinout details

PIN I/O Function

1-4 I/O 0V power supply rail

5-8 I/O +12V power supply rail

9 - 12 I/O -12V power supply rail

13 I Common – analogue feedback voltage ref

14 I Common – analogue feedback voltage ref

15 I [VI_A> Bypass A-ph volts sense from HVI Board – 8Vp-p

16 I [VI_B> Bypass B-ph volts sense from HVI Board – 8Vp-p

17 I [VI_C> Bypass C-ph volts sense from HVI Board – 8Vp-p

18 I [VIN_A> Inverter A-ph volts sense from HVI Board – 8Vp-p

19 I [VIN_B> Inverter B-ph volts sense from HVI Board – 8Vp-p

20 I [VIN_C> Inverter C-ph volts sense from HVI Board – 8Vp-p

21 I [IINV_A> Inverter A-phase current sense from HVI Board

22 I [IINV_B> Inverter B-phase current sense from HVI Board

23 I [IINV_C> Inverter C-phase current sense from HVI Board

24 I [XINV_OI> Mains error – load transfer to inverter = 1

25 I [DREF> Output voltage adjustment - used in parallel modules

26 I [DREF0> Output voltage adjustment - used in parallel modules

27 I [DV-A> Load sharing input for parallel modules only

28 I [DV-B> Load sharing input for parallel modules only

29 I [DV-C> Load sharing input for parallel modules only

30 I [DV-0> Load sharing input for parallel modules only (common)

31 I [INV_L> ‘Inverter on load’ commanded on UPS logic Board – Load-on-inverter = 1

32 O [OVL_INV> Inverter overload status to UPSLB micro (OVL = 0)

33 O [BLK_INV> Inverter On/Off status to UPSLB micro (Off = 1)

34 O [BACK> Frequency sync signal fed back to UPSLB micro – pulse

35 I [SYNC> Reference frequency produced by UPSLB micro – pulse

36 I [ON_INV> Inverter On/Off control from UPSLB micro (Off = 0)

37 I [INV_F> from UPSLB micro (Inv Freq - used in ref w/form gen) – 50Hz = 0 and 60Hz = 1

38 I [INV_A> from UPSLB micro - used in output volts selection

39 I [INV_B> from UPSLB micro - used in output volts selection

40 O Thermostats output to UPSLB (optional)

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3.2.3 Block Diagram

Figure 5-32 shows the Inverter Logic Board at its most basic functional block di-
agram level – the basic function of each of the blocks shown is described below,
with a more detailed, component level description provided in the remainder of
the chapter.

Figure 5-32: Inverter Logic Board basic block diagram

Inverter Current
Inverter I Overload (x3)
Current Limit
sense (x3)
Sense
PWM (x3)

Feed forward
Drive Inverter
PWM IGBT
Modulator Pulse Drive
Generator Pulses

voltages (x3)
AC Control
Inverter Volts Volts
F/B (x3) Error
(actual) Amplifier

control line
Start/Stop
Bypass Volts AC Reference
F/B (x3) voltages (x3)

Bypass Freq Frequency

Reference
Control
Output Volts Voltage
Tri-wave (x1)
Select Generator

Bi-directional Start/ Fault

Control Stop Detection
(UPSLB) Logic Logic

(UPSLB) Power ±12V

Supply ±5V
DC-DC Supply

Reference voltage generator

The ‘reference voltage generator’ produces three AC reference sine waves at
120° with respect to each other which act as voltage demand signals to the ‘volts
error amplifier’. These signals dictate the amplitude, frequency and waveshape of
the eventual inverter output voltage.

Volts error amplifier

This block compares the AC reference signals with voltage feedback signals de-
rived from the inverter output, and produces error signals proportional to any
detected amplitude difference. Three individual error amplifiers are contained in
this block, one for each phase, which means that each inverter phase is individu-
ally controlled. Note that the outputs from this block are annotated “AC control”
signals, as it is these signals that ultimately determine the adopted PWM pattern
which in turn directly determines the inverter output three phase voltage.

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Current limit
AC signals proportional to the inverter output current are processed by the ‘in-
verter current sense’ circuit and fed to the ‘current limit’ block where they apply
a current limit function to the ‘drive pulse generator’ circuit if the current reaches
150%. Three independent circuits are contained in this block, one per phase, so
each output phase is individually controlled.

Modulator
This circuit modulates the AC control signals with a 2.4kHz tri-wave signal, pro-
duced by the ‘reference volts generator’, and generates three PWM waveforms.
Once again three independent circuits are used, one per phase.

Drive pulse generator

The ‘drive pulse generator’ converts the PWM signals into suitable IGBT base
drive signals. This block contains interlocking logic to prevent the simultaneous
triggering of both IGBTs in an inverter phase, a high frequency modulator, over-
load protection and general start/stop control of the output drive waveforms.

Start/stop logic and Fault detection

Numerous fault detection circuits are contained on the board. These control the
internal start/stop control lines to the ‘reference volts generator’ and ‘drive pulse
generator’, and also provide status signalling to the UPS Logic Board micro for
use by the system control logic. Signals from the UPS Logic Board to this (Invert-
er Logic) board also effect start/stop control in accordance with the system’s
control logic demands.

Power supply
The Inverter Logic Board is powered from the DC-DC Power Supply Board,
which is live whenever the power rectifier is operational or the batteries are con-
nected to the busbar via the battery circuit breaker.
This power source provides ±12V d.c. power rails which are then diode blocked
to the second supply source (from the AC-DC Power Supply board) the UPS
Logic Board – hence the board will be powered only from the DC-DC Power
Supply but once the mains fails (i.e. the AC-DC Power Supply is off) the DC-DC
Power Supply will keep all the circuit boards energised.
On-board 5V regulators, fed from the ±12V rails, provide stabilised ±5V power
rails for those devices that require it.

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3.3 Detailed circuit description

3.3.1 Introduction
The Inverter Logic Board circuit diagram (SE-4530024-S) comprises 5 sheets.
With reference to the block diagram in Figure 5-32, the drawings can broadly be
described as follows:
• Sheet 1 contains a ‘signal map’ showing the interconnection of the signals
passing between the other four sheets.
• Sheet 2 contains the reference voltage generator circuit
• Sheet 3 contains the:
– ‘volts error amplifier’ circuit
– ‘current limit’ circuit
– ‘PWM modulator’ circuit
• Sheet 4 contains the ‘current sense’ circuit and current limit detector
• Sheet 5 contains the:
– ‘drive pulse generator’ circuit
– ‘start/stop logic’ circuit
– ‘fault detection logic’ circuit

3.3.2 Reference voltage generator

(circuit diagram sheet 2)

Figure 5-33: Reference voltage generator block diagram

volts adj (R242)

[INV_A> Set
[BLK>
[INV_B> Volts
Stepped
V-peak waveform AC Reference
Resistor Voltage
Ladder

[REF_A>
[INV_F> Multiplexer Filter
Staircase
[S_TRI> [REF_B>
Pattern
Multiplexer Filter
[FRFB> Generator

C Phase [REF_C>
Reference
Phase
Generator
[ISYNC> Locked
Loop
Tri wave
Freq-reference Generator [TRI>

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This circuit is responsible for producing three sinusoidal voltages, spaced at 120°
with respect to each other, which are then connected to the ‘volts error amplifier’
in the form of AC reference voltages. The voltages produced by this circuit can
thus be considered as ‘voltage demand’ signals, and represent the amplitude, fre-
quency and wave-shape desired at the inverter output voltage.

Multiplexer operation
The ‘reference voltage generator’ circuit’s operation is centred around D3 and
D4. These are 8-channel multiplexers whose 8 data lines are connected to various
points along a resistor ladder network (R1-R12), and whose 3 data-select lines are
clocked by the ‘staircase pattern generator’, ASIC D1. Each multiplexer output
(pin 3) is thus connected to one of 8 discrete voltage levels tapped along the re-
sistor ladder depending on the state of the data-select inputs.
In practice, the logic sequence of the signals to the three data-select inputs, from
D1, are such that a stepped waveform is produced at the multiplexers’ outputs
which takes the broad form of a full-wave rectified a.c. voltage – (See Figure 5-
33).
Voltage control. As the voltages at each stage of the stepped waveforms equal
the voltages present along the resistor chain, the stepped waveform peak voltage
is determined by the voltage at the top of the chain – i.e. the voltage at buffer N2c
pin 8. This is controlled by the circuit block annotated ‘set volts’ in Figure 5-33
and described in detail below.
Waveshape control. The AC reference voltage waveshape is determined solely
by the sequential logic within D1 and cannot be adjusted.
Frequency control. The AC reference voltage frequency is determined by the
clock frequency applied to the ‘staircase pattern generator’ (D1 pin 43), as this
controls the rate at which the multiplexers step through their sequence. This is
controlled by a phase locked loop which is normally synchronised to the bypass
supply frequency – described later (See Figure 5-34).
Set volts & Resistor ladder
As described above, the ‘set volts’ circuit (See Figure 5-33) provides a controlled
voltage at the top of the resistor ladder which thereby determines the peak value
of the AC reference voltages – and thus also the inverter output voltage.
It is possible to select one of three output working voltages: 380V, 400V and
415V. This is achieved by two signals from the UPS Logic Board annotated
[INV_A> and [INV_B> which are connected to the data-select inputs of D7, which is
a dual 4-channel multiplexer. The inputs to the ‘X’ channel (‘1X’ to ‘4X’) of D7
are connected to regulated DC voltages which represent the various UPS working
voltages. These are selected by the [INV_A> and [INV_B> to appear at connected to
the ‘X’ output as follows:

Table 5-9: Working voltage selection (D7)

[INV_A> [INV_B> Channel Volts

0 0 X1 380V

0 1 X2 400V

1 0 X3 415V

1 1 X4 Manual Set

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The voltages applied to ‘1X’, ‘2X’ and ‘3X’ are produced by a resistor network
connected across a variable regulated dc power rail which is itself connected be-
tween the 0V and -12V supply rails; the voltages are therefore of a negative
polarity. In practice, R242 is adjusted to obtain approximately -4V across N4; this
voltage is then divided by R54 - R57. The response of the inverter voltage control
loop is such that the signal at D7 ‘X’ output has a sensitivity of approximately
92Vac/V – e.g. a voltage of approximately -4.5V is required to produce an invert-
er output voltage of 415Vac. R242 thus provides the means of calibrating the
output voltage when the UPS is operating.
Note: R242 adjusts the voltage of all three phases. Further resistors are provided
which individually adjust the B and C phase line voltages and can be used to bal-
ance the output line voltages if necessary – described later (see page 5-65).
The ‘manual’ mode is elected by the UPS Logic Board in response to the operator
input and is designed to be used in a ‘test’ environment. When this mode is select-
ed the output voltage can be varied by means of R243 (0-600Vac), which is
connected between the -5V rail and ground, and whose wiper voltage is connect-
ed to D7 ‘X4’.
The selected voltage at D7 output (pin 13) is inverted to a positive voltage by N3b
and buffered by N2c before it is applied to the top of the resistor ladder network
(this voltage can be monitored at test point X8-4 where it has a sensitivity of ap-
proximately 0.01Vdc/Vac output. e.g. a level of 4.1Vdc is equivalent to 400Vac
on the inverter output).
An output from the ‘start/stop logic’, annotated [BLK> on the circuit diagram, re-
duces N3b voltage to zero when the inverter is being commanded OFF. This
reduces the voltage at the top of the resistor ladder to zero which thus results in a
“zero voltage” demand to the inverter voltage regulation circuit.
[BLK> goes high when in the stop/start logic is in its ‘STOP’ mode which clamps
the input to N2 pin 10 to 0V via V41. When this signal switches to its ‘START’
mode (low), V41 turns off but the voltage rise at N2 pin 10 is slugged by R50/C14
to restrict the rate of increase of the inverter demand voltage. This soft-start
action takes approximately 10 cycles to complete and is designed to slowly ener-
gise the output magnetics and thus reduce the inverter start-up current.
Note: the inputs to the ‘set volts’ circuit from X4 pins 25 / 26 and amplifier N3a
are used in a multi-module parallel-operating system only and play no part in a
single module installation.

Staircase pattern generator

The ‘staircase pattern generator’ is based on D1, which contains a complex series
of synchronous logic gates and timers and produces two sets of signals which are
connected to the multiplexer data-select inputs – e.g. output A1-C1 are connected
to multiplexer D4 and outputs A2-C2 to multiplexer D3. The sequence of these
outputs, which is determined solely by D1’s internal logic, produce stepped sig-
nals at the multiplexer outputs which resemble a full-wave rectified waveform.
Two frequency-related signals are applied to D1. An input to D1 pin 44, annotat-
ed [INV-F>, controls one of D1’s internal dividers and sets the inverter nominal
base frequency. This signal, which is logic high for 60Hz operation and low for
50Hz, is produced on the UPS Logic Board in response to inputs from the Oper-
ator Control Panel. The input to D1 pin 43 is a 288kHz clock signal, produced by
a phase-locked-loop (PLL) circuit, which controls D1’s internal operation.
Note: The PLL determines the inverter free running frequency and is normally
synchronised to the bypass supply (See Figure 5-34).

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In addition to the multiplexer data-select signals described above there are several
other frequency-related outputs from D1.
• The outputs from pins 31 (D2) and 36 (D1) are square-waves at the nomi-
nal base frequency which determine the zero-crossover points of the
inverter output and S phases respectively. These are connected to the filter
section – described later (see page 5-64).
• The output from pin 40 is a 2.4kHz square-wave which is converted to a
tri-wave by the ‘tri-wave generator, described below, for further use by the
‘PWM Modulator’ (See paragraph 3.3.4). The frequency of this signal is
determined by the logic levels at pin 1 (S2) and pin 2 (S3), as selected by
X-15 links 1 and 2 – detailed on sheet 1 of the circuit diagram.

Table 5-10:

X15(0-1) S2 X15(0-2) S3 Frequency Usage

Open (0) Open (0) 1.2kHz N/A

Closed (1) Open (0) 2.4kHz All models

Open (0) Closed (1) 4.8kHz N/A

Closed (1) Closed (1) 9.6kHz N/A

• The output from D1 pin 28 (ST2), annotated [S_TRI>, is connected to the

‘drive pulse generator’ block where it modulates the ultimate output drive
waveform (See paragraph 3.3.6). Once again the frequency of this signal
is controlled by links on X15. Normally, it is a 2.4kHz square-wave.

• The output from D1 pin 27 (D3), annotated [FRFB> (test point X8-5), is
connected to the UPS Logic Board via a variable resistor (R247) – shown
on sheet 5 of the diagram (See Figure 5-34). This signal is a square-wave
at the nominal base frequency coinciding with the zero-crossover point of
the A-phase AC reference voltage. On the UPS Logic Board a phase-com-
parator function within the microcontroller compares this signal with a
similar signal derived from the bypass supply R-phase and is thus able to
detect an out-of-phase conditions. R247, located in the [FRFB> line, allows
any residual phase displacement between the inverter and bypass R-phase
waveforms to be nulled once the two sync signals are phase-locked.

• The output from D1 pin 26 (D4) is connected to one of the phase locked
loop (PLL) phase comparators’ inputs. The square-wave signal at this
point is at the nominal base frequency and produced by dividing down the
288kHz clock signal at pin 13. Due to the phase locked loop action
(described below) this signal is aligned with the A-phase inverter zero-
crossover point.

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Figure 5-34: Frequency synchronisation control

X2
D42 D53 Bypass supply R-phase
62 15 5
F-IN 18 voltage sensing
F-INM

X3 X4 phase
63 4 align
16 BACK FRFB
34 34
BACKM R247

D17 INV-F INV-F 44

15 D1
37 37
DATA 50 /60 Hz 27
(Selected from Frequency
MICROCONTROLLER

BUS 26
Operator Panel) Divider
Staircase
(PORT 2)

Generator

43

50/60Hz
288kHz

CLK
(nominal)
4
D59 Phase
9
Locked

F Correction
VCO
Loop

64 5 15 14 13
SYNC Phase
35 35
SYNCM Master Freq SYNC Comparator
Pulses proportional to reference for Phase D6 3
phase error between Inverter Osc error signal
Inverter & Bypass mains

UPS Logic Board Inverter Logic Board

Phase locked loop (PLL)

A PLL (D6) provides the clock signal for the ‘staircase pattern generator’ and
thereby has direct control over the inverter output frequency. This is a standard
type 4046 i.c. which contains two phase comparators (only one of which is used)
and a voltage controlled oscillator (VCO). One of the phase comparator’s inputs
(D6 pin 14) is driven by a square-wave frequency reference signal, annotated
[SYNC>, which is synchronised to the bypass supply and produced on the UPS
Logic Board; the other input is driven by a 50/60Hz output from the ‘staircase
pattern generator’ (D1 pin 26) which is described above. If these two signals are
out of phase the phase comparator output (D6 pin 13) will either switch high or
low (depending on the phase relationship) and apply an error correction signal to
the VCO’s control input (D6 pin 9) – i.e. the VCO frequency is effectively made
to track the frequency reference signal. For example – if the bypass frequency
rises slightly, the following actions will take place:
1. The sync control function on the UPS Logic Board will increase the [SYNC>
signal frequency by an appropriate amount.
2. When the PLL compares the [SYNC> signal with the base frequency signal
from the ‘staircase pattern generator’ it will detect that the [SYNC> signal is of
a slightly higher frequency and the output from D6 pin 13 will exhibit logic
high pulses equal to the periods of phase difference.

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3. The pulses at D6 pin 13 are filtered and applied to the VCO control input at
D6 pin 9 in the form of a dc correction voltage and will cause an increase in
the VCO output at pin 4.
4. This increases the ‘staircase pattern generator’ clock rate which then
increases the inverter frequency along with the base frequency signal pro-
duced at D1 pin 26.
5. When the base frequency signal at D1 pin 26 has risen to match that of the
[SYNC> signal, the phase comparator within the PLL ceases to detect any
phase error and the correction voltage at pin 13 will stop changing. The VCO
control voltage will thus remain constant and the inverter will be maintained
at its current frequency and in sync with the bypass supply.

Filter & C-phase reference generator

The filter sections convert the full-wave rectified stepped waveforms produced
by the ‘multiplexers’ into sinusoidal AC reference signals suitable for connecting
to the ‘volts error amplifier’ – (See Figure 5-32).
Two filter sections are used; one processes the A-phase AC reference signal and
the other for the B-phase.
Considering the A-phase circuit: the stepped waveform produced by the A-phase
multiplexer (D4) is buffered by N1a and connected to D5 pin 13. This signal is
also inverted by N1d and connected to D5 pin 12. D5 is an electronic switch con-
trolled by the output from D1 pin 36 – which was previously described as a
squarewave signal at the nominal base frequency, coinciding with the A-phase
zero crossing points. If D5 is switched by this signal then the signal at its output
pin 14 will be a stepped sine-wave comprising both halves of the signals present
at its pins 12 and 13. This stepped waveform is then filtered by N2a which pro-
duces a smooth sinusoidal AC reference voltage [REF_A> and can be monitored at
test point X8-1 as an 8V peak-to-peak sinewave.
The B-phase circuit operates in an identical manner but displaced by 120° – i.e.
[REF_B> lags [REF_A> by 120°.

The C-phase signal, [REF_C>, is produced by N2d which differentially sums the
other two phases with 0V. Theoretically, in a three phase system the instantane-
ous sum of all three voltages equals zero: therefore by subtracting the and B phase
signals from 0V the output from N2 pin 14 is equivalent to the C-phase AC refer-
ence signal, [REF_C> – i.e. A + B + C = 0 ∴ C = -(A + B).

Tri-wave generator
The square-wave signal from D1 pin 40 is connected to an integrator circuit
(N3b/c) via adjustable resistor R241. This resistor allows the peak value of the tri-
wave signal to be calibrated and is adjusted to obtain a 4V peak-to-peak triangu-
lar waveform at the left hand side of R2 (i.e. ±2V peak).
The tri-wave output from N3 pin 8, annotated [TRI>, is connected to the ‘PWM
modulator’ (diagram sheet 3).

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3.3.3 Volts error amplifier

(circuit diagram sheet 3)

Figure 5-35: Volts error amplifier & modulator block diagram

line volts adj

Inv volts F/B
[VINV_X>
Volts
AC Reference volts Error
[REF_X> D8
Amplifier
[VI_X>
Bypass volts F/B

[RIF>

Current
[IINV_X>
Feed/fwd
PWM waveform
AC Control volts to output driver

PWM
[TRI> [MOD_X>
Modulator
Tri-wave

Each block shown is triplicated – one block per inverter phase

Note: As an almost identical circuit is used for each phase the following descrip-
tion refers to the ‘A’ phase only, with any differences between this and the ‘B’
and ‘C’ phase highlighted.
The purpose of the ‘volts error amplifier’ is to compare the inverter output volt-
age feedback signal with the AC reference voltage created by the ‘reference volts
generator’ (See paragraph 3.3.2) and provide an appropriate AC control signal to
the ‘PWM modulator’ – i.e. if the ‘volts error amplifier’ detects an error between
the inverter output voltage feedback signal and the AC reference voltage it modi-
fies the AC control voltage to change the PWM pattern in such a way as to restore
a balanced condition; therefore effectively making the inverter voltage closely
track the AC reference voltage.

Inverter voltage feedback signal

The inverter A-phase output feedback voltage is sensed at the output side of the
output transformer (i.e. at nominal system output volts), attenuated to approxi-
mately 1% on the High Voltage Interface Board and connected to the Inverter
Logic Board at X4-18. The signal ([VINV_R>) is amplified slightly as it passes
through N5a to N5b, which acts as the ‘error amplifier’, and can be measured at
test point X9-1 as an ac voltage in the range 4.5V to 5.0V (about 14Vp-p) depend-
ing on the system working voltage.
Note: Calibration resistors are included in the ‘B’ phase and ‘C’ phase feedback
inverter volts feedback signal paths which enables those two phases to be individ-
ually balanced to the ‘A’ phase during board set-up. R224 adjusts the B phase and
R245 the C phase.

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AC Reference voltage signal

The A-phase AC reference signal is connected to the error amplifier (N5b) via an
electronic switch comprising part of multiplexer D8. This switch is controlled by
a signal annotated [RIF> which is normally ‘low’, leaving the switch in the posi-
tion shown on the circuit diagram. When [RIF> goes high the switch changes over
and replaces the AC reference voltage input into the error amplifier (N5b) with a
signal derived from the R-phase bypass voltage [VI_A> connected to X4-14 which
makes the inverter voltage track the voltage on the bypass supply line.

Bypass voltage sense signal

[VI_A> is connected via an attenuator circuit on the High Voltage Interface Board
which is identical to that connected in the inverter output feedback signal path.
The bypass voltage sense signal at test point X9-4 therefore has the same sensi-
tivity as the inverter feedback voltage at X9-1 (about 14Vp-p).
When the inverter is first started, [RIF> goes high and energises D8 which then
connects the bypass voltage sense signal [VI_A> to the ‘volts error amplifier’ ref-
erence input – thereby replacing the AC reference voltage as the voltage demand
signal. The inverter voltage will thus rise to equal the bypass voltage. Once the in-
verter voltage has stabilised at the ‘bypass’ level the output contactor will close
to put the inverter on-load. At this point [RIF> reverts to a logic low and D8 deen-
ergises to select the AC reference voltage as the voltage demand signal. This is
done to prevent arcing across the inverter output contactor when it closes and
therefore increases its operating life and reliability.

Volts error amplifier

N5b sums the AC reference voltage and the inverter voltage feedback signal and
its output takes the form of a sinusoidal voltage representing the reference signal
superimposed with a signal representing any detected error. This is then filtered
by N5c and connected to N5d where it is processed in conjunction with an A-
phase current-derived signal.
Note: A third input to N5b from N9a is used only when the module is operating
as part of a multi-module parallel system and provides a means for implementing
load sharing control. In a ‘single module’ installation this circuit is not used and
the inputs to X4 pins 27-30 are left open circuit.

Current feed-forward
N5d sums the volts error amplifier output from N5c with a signal proportional to
the output current, annotated [INV_A>. This is a ‘feed-forward’ signal which calls
for an increased inverter voltage as the current increases and improves the overall
inverter voltage regulation characteristics. The output from N5d is connected to
the ‘PWM modulator’ in the form of the AC control voltage, as depicted in Figure
5-32, where it directly controls the generated PWM pattern.
All three AC control signals are summed by N9d and its output is connected back
to the feed-forward amplifier in all three phases. As, in a three phase system, the
sum of all three phase voltage should equate to 0V, this provides a virtual neutral
reference point for all three amplifiers which prevents the AC control signals
drifting with respect to each other and also ensures that no harmful dc voltages
are generated in the output transformer windings.
Note: In a module fitted with a double-ended (12-pulse) inverter (optional config-
uration generally reserved for larger modules) the AC control voltage is
connected to the Auxiliary Inverter Logic Board via X6-9 and buffer N10a. In a
standard module connector X6 is not used.

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3.3.4 PWM Modulator

The A-phase PWM pattern is generated by N11, which is configured as a differ-
ential comparator whose inverting input is driven by the variable (sinusoidal) AC
control voltage and non-inverting input by a fixed frequency (2.4kHz), fixed volt-
age (±2V) tri-wave signal generated by the ‘reference voltage generator’.
N11 generates the PWM pattern by detecting when the fixed tri-wave voltage is
cut by the AC control voltage as illustrated below.

Figure 5-36: PWM Pattern production

Tri-wave (fixed)
N11
PWM pattern
AC control voltage
(variable)

Tri-wave (fixed)

AC control signal
(low)

3
PWM pattern

AC control signal
(high)

Tri-wave (fixed)
1

PWM pattern
3

The upper waveform diagram depicts the condition where the AC control voltage
is low with respect to the tri-wave (equal to about 25% of the tri-wave peak volt-
age) and illustrates that this results in a PWM pattern with a mark-to-space (m:s)
ratio of approximately 3:1. The lower diagrams shows the situation when the AC
control signal is increased to about 75% of the tri-wave peak voltage and illus-
trates the output m:s now equals 1:3. This shows that the m:s ratio of the output
waveform can be varied by varying the AC control signal; and if this signal is
varied in a sinusoidal manner then the output waveform will represent a sinusoi-
dally modulated PWM pattern.
This pattern is processed by the ‘drive pulse generator’ and applied to the inverter
IGBT transistors such that for each individual inverter phase the ‘high’ IGBT is
turned on when the PWM signal is high – and vice versa.

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Note: if a 12-pulse inverter is fitted (option on larger modules only) the three AC
control signals and tri-wave signal [TRI> are connected to the Auxiliary Inverter
Logic Board via the four sections of N10 (buffers) and connections X6 pins 9 to
12 – i.e. the Auxiliary board contains its own ‘PWM modulator’ and ‘drive pulse
generator’ stages.

3.3.5 Current sensing and Current limit

(circuit diagram sheet 4)

Current sensing
The inverter current is sensed by Hall-effect CT’s fitted between the inverter and
output transformer. In modules above 60 kVA a CT is fitted to each phase but
only two CTs are used in modules at or below this rating, fitted to the S and T
phases only. In the latter case the phase current is calculated from the other two
(monitored) phases.
The CTs’ sense signals are calibrated by jumpers on the High Voltage Interface
Board which determines the overall burden resistance (See section 7 paragraph
2.3.24) and then connected to X4 pins 21 to 23 on the Inverter Logic Board via
the UPS Logic Board.
In the lower-rated modules, where only two CTs are fitted, the A-phase current is
calculated by N15a which sums the B and C phase current sense signal (via jump-
ers X16-1 and X16-2) with 0V. As in a three-phase circuit the instantaneous sum
of all three currents equals zero then the output from N15a pin 1 represents the A-
phase current – i.e. A + B + C = 0 ∴ C = -(A + B). In installations using three
CTs, X16 jumpers 1 and 2 should be ‘open’ and jumper 3 must be ‘made’. This
connects the A-phase signal directly to N15a in the same manner employed by
the other two phases.
As all three phases are identical in operation the following description refers to
the A-phase only.
N15 effectively buffers the current sense signal and the output on N15a pin 1 (test
point X10-1 shows approximately 0.2Vp-p signal when the inverter is on no-load)
is in-phase with the output phase current. From N15a this signal is inverted and
amplified by N15b whose output [IINV-A> is connected to the ‘current feed-for-
ward’ circuit in the AC control voltage line – described earlier.

Current limit
The output from N15a is also rectified by N15c/N15d (zero gain) whose output
pin 14 provides a positive full-wave rectified signal representing the inverter A-
phase current which is then applied to a comparator circuit comprising N18. The
comparator’s operating threshold is set by R246 which is connected across a 4.7V
zener regulator and adjusted to present +0.6Vdc at N18 non-inverting input –
available at test point X10-4. This represents 150% of the rated inverter load cur-
rent, and if the current sense signal to N18 inverting input exceeds this level then
the output from N18 pin 7 ([BLK_A>) will switch to a logic low level and apply an
inhibiting input to the ‘drive pulse generator’ (described below) which prevents it
from turning on the A-phase inverter transistors. This effectively limits the in-
verter peak current to the set 150% threshold.
Note that the inverter is not shut down during the above event; but the current
limit action will take place during each pulse of the 2.4kHz PWM drive signal –
i.e. sub-cycle operation. This effectively reduces the PWM pattern and therefore
the inverter output voltage will fall to the level necessary to restrict the current to

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its 150% level. Taken to its extreme, if there is a short-circuit on the critical bus
then the inverter PWM pulses will be reduced to a minimum and the inverter will
deliver full (150%) current at very low voltage in an attempt to clear the short.

3.3.6 Drive pulse generator

(circuit diagram sheet 5)
This circuit, which comprises a complex series of gated latches within D11 to-
gether with driver transistors V42 to V47, performs signal conditioning on the
PWM pulsetrains produced by the ‘PWM modulators’ to make them suitable
drive signals for the inverter IGBT transistors.
Note: these signals are connected to the IGBTs via the Inverter Driver Boards
(one per phase) which provide further signal conditioning.

D11 internal gates

Those gates within D11 concerned with the ‘drive pulse generator’ function com-
prise three independent channels controlled by the PWM modulated signals
[MOD_A>, [MOD_B>, [MOD_C>, in conjunction with [STRI>.

Taking the A-phase circuit as an example; the drive control inputs to D11 are
[MOD_A> and [STRI> and the outputs from D11 are taken from pin 36 (drive to the
A-phase inverter low IGBT [PAL>) and 37 (high IGBT [PAH>).
[PAL> switches high, turning on the ‘low’ IGBT via V42, when [MOD_A> is low
and [STRI> goes low. This condition is latched until [MOD_A> is high and [STRI>
goes high, whereupon [PAL> returns low, turning off the “‘low’ IGBT, and [PAH>
goes high, turning on the “high” IGBT via V43.

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The other two inverter phases are controlled in an identical manner with their re-
spective drive signals shown annotated [MOD_B>, [PBL>, [PBH> for the B-phase
and [MOD_C>, [PCL>, [PCH> for the C-phase.
Note: [STRI> is common to all three phases.
There are two means by which the drive pulse logic can be inhibited within D11.
The first occurs if an overload is detected, in which case the [BLK_A>, BLK_B>,
[BLK_C> signals described earlier will inhibit the particular channel being over-
loaded – (See paragraph 3.3.5). The second is by means of a general ‘stop/start
logic’ block within D11 which handles signals from the UPS Logic Board and
from the local ‘fault detection logic’ and provides a controlled stop/start function
– (See paragraph 3.3.8).

3.3.7 Fault detection logic

(circuit diagram sheet 5)
Circuits on the Inverter Logic Board monitor the following faults:
• Inverter current limit
• Inverter overload (from desaturation detector on driver interface boards)
• Ribbon cable discontinuity
• Inverter stack thermostat overtemperature
• Power supply monitor

Each of these facilities are described below

Inverter current limit

The ‘inverter current limit’ circuit is shown on the diagram sheet 4 and described
in detail in paragraph 3.3.5. This circuit provides three inputs to D11 annotated
[BLK_A>, [BLK_B> and [BLK_C> which go low if an overload is detected on the as-
sociated phase. In the event of a phase current rising to the current limit level the
following occurs within D11:
1. The drive signals to the affected phase(s) are inhibited, as described above.
2. A summary current limit signal (logic low) is produced at D11 pin 21 if any
one of the three phase currents reach the current limit level. This is inverted to
a high by D10b and connected to the UPS Logic Board via X4-32 as an
inverter overload status alarm signal [OVL_INV>, where it is used for display
purposes only (code 33). From D10b pin 10 the signal is also passed back
through D11 pins 20 to 19 and illuminates H14 to provide an on-board indica-
tion that the inverter overload circuit is activate. Note that the signal to D10b
is slugged by V23/R300/R237/C141 on removal of the overload to allow the
inverter conditions time to stabilise before the overload status is reset.
3. The [BLK_A>, [BLK_B> and [BLK_C> signals are buffered within D11 and out-
put at pins 31, 32 and 33 respectively. These are passed to the Auxiliary
Inverter Logic Board in a 12-pulse inverter installation via connector X6 pins
13, 14 and 15 (used in large module only).

Inverter Vce(sat) (from desaturation detector on driver interface boards)

A circuit on the Inverter Driver Board (See paragraph 4.3.4) detects an inverter
IGBT fault (short or open circuit) by sensing when the particular device is desat-
urated during its ‘ON’ period. These boards thus provide six fault signals back to
the Inverter Logic Board via pins 3/4 and 13/14 of connectors X1 (A-phase) X2

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(B-phase) and X3 (C-phase) respectively. The fault signal applied to these inputs
take the form of a logic low on fault, but this is inverted to a high by a section of
D9 and diode-coupled to a single input at D11 pin 8 [DIS> which is therefore high
if a desaturation condition is detected on any inverter IGBT and drives the Start/
stop logic within D11 to its stop mode (see below).
Note: the Vce(sat) signals produced by the various sections of D9 illuminate
LEDs H5 to H10 to positively identify the location of the faulty IGBT transistor.

Ribbon cable discontinuity

A system of verifying that the ribbon cables connecting the Inverter Logic Board
to the three Inverter Driver Interface Boards is implemented by the connections
to X1 to X3 pins 5/8. Pins 5 and 8 of the respective connectors are linked together
on the Inverter Driver Interface Boards and so present a short-circuit which pulls
D11 pin 9 ([COI>) low if the cables are all correctly in place. However, if one of
the cables are disconnected while the inverter is operating [COI> will rise to a
logic high and drive the Start/stop logic within D11 to its stop mode (see below).
Note: this signal is buffered within D11 and produces a logic high output at D11
pin 18 which illuminates H13 if a fault occurs.
X12 provides a means of overriding this circuit for test purpose only when it is
made 2-3 – this jumper should always be position 1-2 during normal operation.

Inverter stack thermostat overtemperature

A facility exists in which thermostats fitted to the power inverter heatsinks can
provide an overtemperature status signal to the UPS Logic Board. The thermo-
stats provide a normally-closed circuit between X1-5 and X3-8 and produce a
logic low signal at X4-40, which is connected to the UPS Logic Board. If any
thermostat opens (at a temperature above 90°C) then this chain is broken and X4-
40 is pulled high via R100 and V24.
Where this option is not used, a jumper should be fitted to X13 position 2-3 to
override the overtemperature fault signal which would otherwise appear. Reposi-
tion this jumper to 1-2 when the option is used.

3.3.8 Start/stop logic

This circuit is based on a multi-input logic gate within D11 which monitors the
‘fault detection logic’ circuits described above, together with several control
inputs from the UPS Logic Board, and either enables or disables the ‘drive pulse
generator’ outputs (also within D11) in response to the input signals’ status.

Start/stop logic circuit outputs

Three ‘start/stop’ status outputs are also produced by D11, as described below:
• D11 pin 7 goes high on stop and is the source of the [BLK> signal to the
‘reference voltage generator’ circuit. When the ‘stop/start logic’ is in its
stop mode this signal reduces the ‘reference voltage generator’ output to
zero and thus demands zero output voltage.
• D11 pin 28 goes high on stop and sends a status signal to the UPS Logic
Board via X4 pin 33 to request the micro to disable the inverter run signal.
• D11 pin 34 goes high on stop and sends a status signal to the Auxiliary
Inverter Logic Board (12-pulse inverter only); thus ensuring that where
this option is used both the main and auxiliary boards are stopped and
started by a common control signal.

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Start/stop logic circuit inputs

The ‘start/stop logic’ within D11 is driven by the following D11 inputs:
1. Inverter Vce(sat) error (detected by desaturation detector on Inverter Driver
Interface Boards) – logic high to D11 pin 8 forces the stop mode (See para-
graph 3.3.7).
2. Connector discontinuity (led H13 illuminated) – logic high to D11 pin 9
forces the stop mode (See paragraph 3.3.7).
3. A system start/stop control input to D11 pin 13 from the UPS Logic Board,
via X4-26, which is low on stop and high on start, provides the means of
allowing the UPS Logic Board to shut down the inverter in response to certain
system events – e.g. DC overvoltage, low battery, OFF selected from the
Operator Panel, emergency shutdown, etc. This input also drives led H12 via
D11 pin 17 (inverts the signal at pin 13) and illuminates the led when the sig-
nal is demanding the inverter to be turned OFF.
4. If a 12-pulse inverter is installed (option) the output from the ‘start/stop’ cir-
cuit on the Auxiliary Inverter Logic Board is connected to D11 pin 14 via
X6-18 and is logic high on stop. This ensures that both main and auxiliary
Inverter Logic Boards react to a common ‘Start/stop’ line (see also the output
from D11 pin 34 described above).
5. A power supply monitor circuit based on N22 applies a logic high input to
D11 pin 16, placing the ‘stop/start’ circuit in its stop mode if the 12V supply
rail falls below 10Vdc. This circuit also holds off the inverter operation when
the UPS is first powered up until the 12V rail rises above this level to allow
the power supply time to stabilise before initiating the PWM drive signals.
Led H11 illuminates when this circuit is demanding a stopped condition.
6. The transfer to inverter command [INV_L> generated on the UPS Logic Board
is connected to D11 pin 13. This is clocked through D11 to enable the [RIF>
signal. This re-references the inverter voltage to the bypass voltage just before
the inverter is about to take over the load, which prevents any voltage drop
appearing across the output contactor when it is instructed to close (See para-
graph 3.3.3).
The inverter voltage is referenced to the bypass voltage level for approxi-
mately 220ms before is it switches back to its normal reverence voltage: this
more than adequately covers the output contactor closure time, which is
approximately 50ms. Note that this function is disabled by the ‘mains fail’
signal [MNS_KO> to D11 pin 11 in the event of a mains failure; thus if the load
is transferred to the inverter when the mains have failed then the inverter will
remain referenced to its normal reference voltage at all times.

3.3.9 Power supply

(circuit diagram sheet 5)
This board receives its control power supply from the DC-DC Power supply
Board only, via connector X5. Pins 3, 4 and 5 carry regulated +12V, 0V and -12V
power rails which form the Inverter Logic Board’s main supply inputs; and pins
1 and 2 carry an isolated 36Vac supply which is used by the Inverter Driver Inter-
face Boards and connected via connectors X1, X2 and X3, as shown.
A 5V regulator, N21, provides a regulated +5V rail from the +12 supply.

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The ±12V rails are diode-coupled to the ±12V rails on the UPS Logic Board via
V14 and V15, as shown on sheet 4 of the diagram. Thus in the event of mains fail-
ure (i.e. the AC-DC Power Supply is inactive) the DC-DC Supply will maintain
the control power to all the electronic circuit boards.

3.4 Summary Information

Table 5-11: Inverter Logic Board configuration jumpers

Link
Jumper Function
Position

1-2 Enable disconnected cable detector (Standard)

X12
2-3 Override disconnected cable detector (Test)

1-2 Enable thermostat detector (Standard)

X13
2-3 Override thermostat detector (Test)

5 links – override control inputs from UPS Logic Board as

X14
shown on main circuit diagram

0-5 1200Hz

0-1 2400 Hz
X15 0-2 4800Hz PWM modulating frequency selection

0-1
9600Hz
0-2

1-2 C-phase current monitor signal selection (where only 2 CTs

0-2 are fitted to the inverter phases – standard to 7200 range)
X16
C-phase current monitor signal selection (where 3 CTs are
2-3
fitted to the inverter phases – used in larger modules)

Table 5-12: Inverter Logic Board potentiometer adjustments

Potentiometer Function
R241 Amplitude of triangle wave adjustment
R242 Inverter voltage reference setting
R243 Manual inverter voltage adjustment (0 to 500V)
R244 Phase B to Neutral adjustment
R245 Phase C to Neutral adjustment
R246 150% Inverter Current Limit
R247 Phase displacement adjustment Inverter to Bypass

Table 5-13: Inverter Logic Board LED indications

LED Colour Function

H1 Green 380V operation
H2 Green 400V operation
H3 Green 415V operation

H4 Amber Manual operation Range 0 - 500 Volts ( Clock-

wise = minimum)

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LED Colour Function

H5 to H10 Red Transistor saturation, (R+, R– : S+, S– : T+, T–.)
H11 Red PCB power supply failure
H12 Red Inverter off from UPS Logic Board
H13 Red Ribbon cable monitor block
H14 Red Inverter in 150% current limit (Active)

Table 5-14: Inverter Logic Board test points

Test Point X8
X8 - 1 Inverter ref. A (8V p - p)
X8 - 2 Inverter ref. B (8V p - p)
X8 - 3 Inverter ref. C (8V p - p)
X8 - 4 Inverter DC ref.
X8 - 5 Inverter pulse for φ displacement
X8 - 6 φ displacement error pulse

Test Point X9
X9 - 1 Inverter feedback A
X9 - 2 Inverter feedback B
X9 - 3 Inverter feedback C
X9 - 4 Bypass A 8V p-p
X9 - 5 Bypass B 8V p-p
X9 - 6 Bypass C 8V p-p

Test Point X10

X10 - 1 Current φ A (0.2V p - p No Load)
X10 - 2 Current φ B (0.2V p - p No Load)
X10 - 3 Current φ C (0.2V p - p No Load)
X10 - 4 0.6V Current limit

Test Point X11

X11 - 1 Inverter pulse plus correction for UPS Logic PCB
X11 - 2 Block pulse A
X11 - 3 Block pulse B
X11 - 4 Block pulse C
X11 - 5 PWM A
X11 - 6 PWM B
X11 - 7 PWM C
X11 - 8 Square pulse enable

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 Section 5:

Chapter 4 - Inverter Gate Driver Board

4.1 Chapter Overview

This chapter contains a circuit description of the Inverter Gate Driver Board used
across the whole 7200 UPS model range and should be read in conjunction with
circuit diagram SE-4519015-H.

4.2 General description

Details of the IGBT and its drive requirements are described on page 5-19.

4.2.1 Circuit board functions

Figure 5-37: Inverter Gate Driver Board Block Diagram

CN1

3 Desaturation
Desaturation
4 Fault Signal
Monitor
C
Generator

Drive Control Output G

1 Signal Logic Drive
2 Demodulator Chip IC2 Pulses
E

Power Supply Power

for High Supply
Transistor Monitor
M1

S 1
9
10 Power Thermostat
19 Supply 2
Transformer
Connections
20
T 3

Power Supply Power

for High Supply
Transistor Monitor

Drive Control Output

11 Signal Logic Drive G
12 Demodulator Chip IC52 Pulses E

13 Desaturation
Desaturation
14 Fault Signal C
Monitor
Generator

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CHAPTER 4 - Inverter Gate Driver Board

The Gate Driver Board is responsible for processing the modulated PWM
transistor drive signals produced by the Inverter Logic Board, making them
suitable for driving the inverter power transistors. It also provides galvanic
isolation of the drive signals and power supply, which is necessary to keep the
high voltage environment surrounding the power inverter transistors away from
the low voltage environment of the electronic control boards.
Three driver boards are used (one per power inverter phase) with each board
containing two identical, but electrically separate, circuits to drive the two
transistors contained in the inverter power block. These channels are easily
observed on the circuit diagram and described in detail below (See Figure 5-37).

4.2.2 Input/Output connections

Each of the three driver boards is connected to the Inverter Logic Board by means
of a ribbon cable to connector CN1. This cable carries the power supplies, drive
signals and fault detection signals for both ‘high’ and ‘low’ transistors in the par-
ticular inverter phase. The connections between the Gate Driver Board and the in-
verter IGBTs are made by hard-wired terminations rather than being socketed –
note that in each case the connections are colour-coded:
• Black = Collector
• White = Gate
• Red = Emitter.
Thermostats can be fitted to the inverter heatsinks as an optional facility. Where
these are used, they are hard-wired to the Inverter Gate Driver Board terminals S
and T; then connected to the control system via connector M1.

4.3 Detailed circuit description

4.3.1 Power supplies

Two independent (and isolated) sets of power supplies are produced on the Gate
Driver Board – one for each inverter drive channel. The supplies are obtained
from the 30Vp-p (20 kHz) output on the DC-DC Power Supply Board which is
connected to T1 primary via CN1 pins 9/10 and 19/20. T1 has two isolated
secondaries which are connected to identical power supply circuits.
T1 secondary voltage is first rectified by a diode bridge to provide a raw +15V
power rail which is then connected to a standard three-terminal +5V voltage
regulator (IC4/IC54). Notice that the supply used by the circuit driving the
inverter ‘high’ transistor is annotated ‘0VH’, ‘5VH’ and ‘15VH’, while the ‘low’
transistor channel is annotated ‘0VL’, ‘5VL’ and ‘15VL’.

4.3.2 Gate drive signal control logic

At the heart of the gate drive circuit control is a purpose-designed integrated
circuit – identified as IC2 in the ‘high’ transistor channel and IC52 in the ‘low’
channel. As both drive channels are identical in operation, the following
description concentrates on the ‘high’ channel (IC2) only.
The inverter transistor drive signals are produced at IC2 pins 12 and 13, and
connected to the transistor via drivers TR1-TR4. The inverter transistor is turned
ON by making its gate positive with respect to its emitter, and turned OFF by
reversing this polarity – note that just leaving the gate open circuit is insufficient
to turn OFF the device.

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The circuit diagram shows that the gate terminal is connected to the junction of
driver transistors TR1 and TR3; and the emitter terminal is similarly connected to
the junction of TR2 and TR4. TR1 to TR4 thus form a bridge across the 15V
power rail. To turn ON the inverter transistor, drivers TR1 and TR4 must be
turned ON, and to turn the inverter transistor OFF, drivers TR2 and TR3 must be
turned ON. Regarding the control logic chip IC2, this means that IC2 pin 13 has
to be logic high and pin 12 logic low in order to turn the inverter transistor ON
with the opposite logic states being necessary to turn it OFF.
Note: links CV2/3 and CV52/53 must remain OPEN when this board is fitted to
the 7200 Series UPS range. Fitting these links increases the gate drive signal
power which is necessary when the board is used with inverters of a higher power
level.

Figure 5-38: IC2 Internal Details

1
19

2 2 3

14
3
a 4
b 6
c
9 d 18
5
8

a 8
b
c 13
d

a 10
b
c 12
d
11
4
17
13
12
16
6

Figure 5-38 shows IC2's internal logic functions. The internal gates have been
identified numerically as an aid to description (gate 1 to gate 13), although these
are of course inaccessible.
The Inverter Logic Board generates the required inverter PWM pattern and, in its
output stage, modulates the resultant variable mark-to-space gate drive signals
with a high frequency carrier signal (See paragraph 2.3.4). This composite drive

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waveform is then connected to the Gate Driver Board at CN1 pins 1 and 2. As
such, the signal can be interpreted that the inverter transistor is to be turned ON
when the carrier signal is present and turned OFF when it is not.
The first circuit that the drive signals meets on the Gate Driver Board is a
demodulator, comprising D5-D8 and C10, which converts the drive signal back
into its basic PWM logic pattern. This signal is isolated by opto-coupler OP1 and
connected to IC2 pin 2.

4.3.3 Turning the inverter transistor ON

It has already been stated that IC2 pin 13 must be `high' and pin 12 `low' in order
to turn ON the inverter transistor. Referring to Figure 5-38, this means that the
four inputs to gates 8 and 10 must all be logic high. As will be shown later, the
input to gates 8d and 10d from gate 12 is normally high, and will go low only if
the Gate Driver Board 5V power supply fails. The input to gates 8a and 10a from
gate 11 is also normally high and will go low if the ‘de-saturation’ monitor circuit
detects an inverter transistor overload. Under normal circumstances therefore,
the main control inputs of interest are those applied to gates 8 and 10 pins b and c.
When the input drive signal demands the inverter transistor to be turned ON the
output from OP1 applies a logic low to IC2 pin 2. This is inverted by gate 1 to a
logic high at IC2 pin 19, and by gate 2 to a logic high at gates 8c and 10c.
When IC2 pin 19 goes high it drives IC2 pin 3 high after a 4µs time delay which
is due to R7/C6. This delay is designed to give the inverter low transistor
sufficient time to turn OFF before the high transistor is eventually switched ON
and is directly related to the IGBT propagation delay time (see paragraph [Link]
on page 5-21).
When IC2 pin 3 goes high it places a high on gates 8b and 10b making IC2 pin 13
go high and pin 12 low –i.e. the conditions needed to turn ON the inverter high
transistor.

4.3.4 De-saturation detector

The de-saturation detector circuit monitors the voltage across the inverter
transistor (Vce) during its turn ON period. This voltage is normally be very low
(i.e. less than 4V); but will increase if the load current demand becomes
excessive and makes the transistor de-saturate, or if the transistor is open circuit.
The de-saturation circuit, shown in detail in Figure 5-39, comprises a fixed
voltage divider chain (R2, R3, R4 and R6) connected to the +15VH power rail –
the `hot' end of R6 is connected to IC2 pin 9, which is the ‘de-saturation’ input to
the controller chip. The inverter transistor collector voltage is diode-coupled into
the divider chain via D9 and R20 – i.e. D9 provides a means of clamping the
junction of R2 and R3.
Note that although the de-saturation circuit monitors the Vce of the inverter IGBT,
the monitored signal is not connected directly to the transistor's emitter terminal.
Instead, the detector uses the 0VH line which is connected to the inverter transis-
tor emitter via TR4 when the transistor is turned ON – i.e. the de-saturation detec-
tor monitors the combined Vce of the inverter ‘high’ transistor and Vds of TR4.
Under `normal' circumstances (i.e. when the inverter is not being overloaded) the
monitored transistor collector voltage is sufficiently low to clamp the R2/R3 junc-
tion at a voltage seen as a logic low (<<0.8Vdc) by IC2 pin 9. The resistor values
have been chosen means that this condition is satisfied when the monitored volt-
age is approximately 3.7V (assuming 0.7V drop across D9 when it is turned ON).

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7200 Series UPS Service Manual SECTION 5 - Inverter Operation & Control
CHAPTER 4 - Inverter Gate Driver Board

Figure 5-39: Desaturation detector

DC BUS POSITIVE

+15VH

R2
D9
R20
R?

RES IGBT
R3

Gate Driver Board

R4
INV
desat OUT
IC2 TR4

R6

0VH

DC BUS NEGATIVE

A fault is registered by IC2 when its pin 9 rises to logic high (>>2.0Vdc), which
occurs if the monitored voltage rises above approximately 10.3Vdc. This is
assumed to be the point at which the inverter transistor is operating in a
potentially dangerous de-saturated condition.
Another condition that has to be taken into consideration when monitoring for
de-saturation is the transistor ‘turn-on’ time. A transistor does not change from
being fully OFF to fully ON instantaneously; therefore, when the transistor is
initially turned ON there is certain to be a brief interval where its collector-
emitter voltage will exceed the level detected as a de-saturated condition. For this
reason, the de-saturation monitor circuit allows the transistor 8µs to attain a
saturated state after it has been instructed to turn ON (i.e. 12 µs from the
application of the gate drive pulse to IC2 pin 2).

The circuit works as follows:

Within IC2, gate 4 forms the de-saturation detector gate. Gate 4d is held
permanently high due to IC8 pin 8 being pulled down to 0V by R5 (SH1 not
fitted). Gate 4b goes high as soon as a gate drive signal is applied to IC2 pin 2
(low) and gate 4a goes high 4µs later when IC2 pin 3 goes high. This means that
a logic high output is produced at IC2 pin 18 if the input to gate 4c, from IC2 pin
9, goes high. The input to IC2 pin 9 comes from the de-saturation detector circuit
as previously described.
Put another way, IC2 pin 18 goes high only when the inverter is receiving a gate
drive signal and its collector-emitter voltage is greater than the saturation level.
When IC2 pin 18 goes high it sets off an 8µs time delay effected by R10/C7;
however, if the de-saturation signal to IC2 pin 9 returns to a logic low within 8µs,
then IC2 pin 18 will return to a logic low and reset the time delay circuit.

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SECTION 5 - Inverter Operation & Control 7200 Series UPS Service Manual
CHAPTER 4 - Inverter Gate Driver Board

If the de-saturation signal remains high long enough to allow the 8µs time delay
to operate fully, it will eventually apply a logic high to IC2 pin 4, with the
following effects:
1. It forces gate 11 output high which, after being inverted by gates 7 and 9,
applies a logic low to gates 8a and 10a, inhibiting the inverter transistor drive
signals at IC2 pins 12 and 13.
2. Via gate 5, IC2 pin 18 is latched into a logic high state -i.e. IC2 pin 4 is pre-
vented from returning to a logic low due to the return-to-normal of the de-sat-
uration fault signal at gate 4 output (which will naturally occur if the
transistor is turned OFF).
3. IC2 pin 17 is driven high, which provides a permanent charging path for C7
through R9, which reinforces the logic high fault input to IC2 pin 4.
4. IC2 pin 16 is driven high which turns OFF LS2 (normally illuminated) and
turns ON LS1, indicating that a fault has been detected. The logic high is also
opto-coupled by OP2 to CN1 pins 3 and 4 which provides a signal back to the
Inverter Logic Board to inhibit the gate drive signals to the faulty inverter
transistor (See paragraph 2.3.7).
5. The culmination of these action clearly latch the de-saturation shutdown cir-
cuit mechanism until all power is removed from the Gate Driver Board.

4.3.5 Power supply monitor

IC1 monitors the 15V power rail: its output on pin 6 changes from a normally
logic low to a logic high if the 15V rail falls below 12.00Vdc. This is not only
used as a power failure detector, but also serves to prevent the board from issuing
gate drive pulses on power up until the 15V rail has developed fully and had time
to stabilise.
In the event of a power supply fault, IC2 pin 6 going high causes a logic high at
IC2 pin 16 which affects LS1 and LS2, and signals the fault to the Inverter Logic
Board in the same way as the de-saturation circuit previously described. It also
inhibits the drive signals at IC2 pins 13 and 12 by putting a logic low to gates 8
and 10 via gate 12.
Note that effect of the low voltage error signal on gate 11 blocks the de-saturation
error signal on pin 4 passing through gate 11. This prevents any spuriously
detected de-saturation errors from locking-up the circuit on initial power-up.

4.3.6 Other connections

There are two other groups of connections on this circuit board which are not
directly concerned with the transistor driver function.
The link between CN1 pins 6 and 7 (16 and 17) form part of the normally-closed
ribbon connector serial link which enables the Inverter Logic Board to detect
when a cable is disconnected. Thus the Inverter Logic Board will shut down the
inverter if CN1 were to be disconnected while the inverter was operational.
Finally, connector M1 pins 1 and 3, and terminals S and T, are concerned with
the thermostat connections. These are probably best understood by referring to
the inverter power schematic diagram.

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 Section 6: Static Switch Operation & Control

Chapter 1 - Static Switch Principles

1.1 Introduction .............................................................................................. 6-1
1.2 Static switch construction ......................................................................... 6-2
1.3 Static switch control system ..................................................................... 6-4
1.3.1 Control system overview ............................................................. 6-4
1.3.3 Control power supplies ................................................................ 6-7

Chapter 2 - Static Switch Driver Board (4542043 Z)

2.1 Chapter overview ..................................................................................... 6-9
2.2 General description ................................................................................... 6-9
2.2.1 Circuit board functions ................................................................ 6-9
2.2.2 Input/Output connections ............................................................. 6-9
2.2.3 Block Diagram ........................................................................... 6-10
2.3 Detailed circuit description .................................................................... 6-11
2.3.1 Introduction ................................................................................ 6-11
2.4 Summary information ............................................................................. 6-15

Chapter 3 - Static Switch Driver Board (4542041 X)

3.1 Chapter overview .......................................................................................17
3.2 General description .....................................................................................17
3.2.1 Circuit board functions ..................................................................17
3.2.2 Input/Output connections ...............................................................17
3.2.3 Block Diagram ...............................................................................18
3.3 Detailed circuit description ........................................................................19
3.3.1 Introduction ....................................................................................19
3.4 Summary information .................................................................................23

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SECTION 6 - Static Switch Operation & Control 7200 Series UPS Service Manual

ii S-6.FM5 - Issue 2 Dated 21/08/97

 Section 6:

Chapter 1 - Static Switch Principles

1.1 Introduction
The static switch assembly is responsible for controlling the transfer of critical
load power between the bypass mains supply and the inverter output supply.

Figure 6-1: Static switch power block

Static Switch
Assembly

Bypass Static Switch

Mains
Supply Bypass-Side

Static Switch
UPS Logic
Driver
Board
Board

Inverter Static Switch Critical

Output Load
Supply Inverter-Side Supply

In order to perform this function, the static switch assembly contains two 3-phase
switching circuits; one is connected between the UPS output switch and the
bypass mains supply, and the other between the UPS output switch and the invert-
er supply (See Figure 6-1). For reasons of clarity, these are referred to in this
manual as the “bypass-side” and “inverter-side” static switches respectively.

Bypass-side static switch

The bypass-side static switch comprises a pair of inverse-parallel-configured
SCRs connected in series with each bypass mains supply line (See Figure 6-2).

Figure 6-2: Bypass-side static switch

U
To
Bypass V Critical
Mains Load
Supply W

Static Switch Driver Board

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SECTION 6 - Static Switch Operation & Control 7200 Series UPS Service Manual
CHAPTER 1 - Static Switch Principles

When the static switch control logic decides to connect the load to the bypass
mains supply it signals the Static Switch Driver Board to trigger all six SCRs si-
multaneously; thus allowing passage of the bypass supply a.c. mains through to
the critical load – i.e. all six SCRs receive a gate drive signal for the whole time
that the ‘bypass-side’ is required to be turned on.

Inverter-side static switch

The term “static switch” might be considered a misnomer when describing the
‘inverter-side’ circuit; as in a standard 7200 module this normally comprises a
straightforward three-phase circuit breaker connected in series with the inverter
output. If necessary, provision has been made to allow this contactor to be re-
placed with a solid state circuit (as used in the bypass-side static switch) as the
product is developed.
The contactor is controlled by the Static Switch Driver Board.

1.2 Static switch construction

The static switch power components and the rectifier power components are as-
sembled on the same heatsink , as illustrated below.

Figure 6-3: Static switch assembly wiring details

4542043Z

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7200 Series UPS Service Manual SECTION 6 - Static Switch Operation & Control
CHAPTER 1 - Static Switch Principles

Figure 6-4: Static switch construction

Connections to snubber boards

Bypass SCRs and gate drivers
STATIC BYPASS
MAINS FEED
RECTIFIER 3-Ph
MAINS FEED

RECTIFIER OUTPUT

Gate Driver (trigger) Snubber board

board
4542043Z

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SECTION 6 - Static Switch Operation & Control 7200 Series UPS Service Manual
CHAPTER 1 - Static Switch Principles

Figure 6-5: System control overview

Load
U-Phase U-Phase
Mains Inverter

ON ON

Transfer Logic

PCB Logic Boards

Mains-side switch enable Transfer Control Inverter-side switch enable

a) Bypass voltage OK (±10%) Transfer Mains-to-Inverter a) Inverter voltage OK (±10%)

a) Sync OK (Inv/Mains ±9° with
b) No bypass frequency error b) No inverter frequency error
respect to each other
c) No Open-circuit bypass SCR c) No Overload timeout
b) Inverter voltage OK (±10%)
150% (1 min)
d) Bypass Disable Switch “ena- 125% (10 min)
c) Parallel condition satisfactory
bled” – i.e. not in “inhibit” position. 110% (1 Hr)
(1+1 system only)
101% (9 Hrs)
e) Permission to close static
(a) + (b) + (c) = OK to transfer
bypass gained from Parallel Logic d) Inverter Disable Switch “ena-
Board (in 1+1 system only) bled” – i.e. not in “inhibit” position.
Transfer Inverter-to-Mains
a) Critical bus volts fail (±10%) e) Permission to close output
contactor gained from Parallel
b) Sync OK = No break Logic Board (in 1+1 system only)
Sync not OK = 1 cycle break

Transfer Lockout
a) More than 8 transfer attempt in
1 minute = load locked on bypass

1.3 Static switch control system

1.3.1 Control system overview

Figure 6-6 illustrates the basic static switch control circuit.
The decision making logic which determines whether to close the ‘bypass-side’
or ‘inverter-side’ static switch is contained on the UPS Logic Board under soft-
ware control – (see chart 7-12 on page 7-183) – and provides the Static Switch
Driver Board with independent “load on bypass” and “load on inverter” com-
mand signals. The Static Switch Driver Board processes these signals and pro-
vides suitable outputs to control the ‘bypass-side’ SCRs and ‘inverter-side’
contactor.

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7200 Series UPS Service Manual SECTION 6 - Static Switch Operation & Control
CHAPTER 1 - Static Switch Principles

Figure 6-6: Static switch control system

Bypass-side
Static Switch

Bypass
Mains
Supply

Bypass voltage
Output voltage sense
Bypass

sense
Supply
Output current sense

High Voltage UPS Logic Static Switch

Interface Board Board Driver Board

Operator Logic Board

K1 Auxiliary sense
Inverter current sense

Inverter voltage sense

Operator Control
Panel

DC Bus Pos

Critical Load
3 Phase Output
Power Tfrmr
Inverter
DC Bus Neg
Inverter-side
Contactor (K1)

[Link] Analogue control signals

Inverter voltage sense

The 3-phase inverter voltage is sensed at a point between the output transformer
and inverter-side static switch (contactor), and should therefore be at the nominal
UPS output voltage whenever the inverter is operating. The three independent
line-to-neutral sense signals are attenuated to 1% on the High Voltage Interface
Board and then passed to the UPS Logic Board where they are converted to a dig-
ital form and monitored by the board’s microprocessor system.
Note: these same signals also pass straight through the UPS Logic Board to the
Inverter Logic Board where they serve as the output voltage feedback signals.

Bypass mains voltage sense

The 3-phase bypass mains voltage is sensed at a point between the bypass supply
isolator and the ‘bypass-side’ static switch, and should therefore be at the nominal
mains voltage whenever the bypass switch is closed. The three independent line-
to-neutral sense signals are attenuated to 1% on the High Voltage Interface Board
and then passed to the UPS Logic Board where they are converted to a digital
form and monitored by the board’s microprocessor system.

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SECTION 6 - Static Switch Operation & Control 7200 Series UPS Service Manual
CHAPTER 1 - Static Switch Principles

Output (critical load) voltage sense

The 3-phase UPS output voltage is sensed immediately ahead of the output isola-
tor (on the hot side of the output contactor K1) and therefore accurately represents
the voltage offered to the critical load. The three independent line-to-neutral sense
signals are attenuated to 1% on the High Voltage Interface Board and then passed
to the UPS Logic Board where they are converted to a digital form and monitored
by the board’s microprocessor system.

Output (critical load) current sense

The output current is sensed by three individual current transformers (CTs) locat-
ed immediately ahead of the output isolator (on the hot side of the output current
transformers) and therefore monitors the critical load current. These current sense
signals are calibrated by jumpers fitted to the High Voltage Interface Board and
then passed to the UPS Logic Board where they are summed and converted to a
digital form and monitored by the board’s microprocessor system.

[Link] Digital control signals

UPS Logic Board

Various digital signals affecting the static switch operation are passed between
the UPS Logic Board and the other boards connect to it. These can broadly be cat-
egorised as:
• static switch status and alarm data generated on the UPS Logic Board and
passed to the Operator Control Panel via the Operator Logic Board – also
to the Alarms Interface Board (for remote indication) where fitted.
• transfer control logic signals passed to the Static Switch Driver Board.
• metering data generated on the UPS Logic Board and passed to the Opera-
tor Control Panel.
• control data entered at the Operator Control Panel which is stored by the
UPS Logic Board – e.g. manual load transfer selection.
• external control options – e.g. emergency shutdown, ‘on-generator’ sync-
inhibit, isolator status.

Static Switch Driver Board

In addition to the transfer control signals obtained from the UPS Logic Board, the
Static Switch Driver Board also receives a status signal from auxiliary contacts of
the ‘inverter-side’ contactor to detect its operational status.

1.3.2 Transfer control philosophy

Under normal circumstances the UPS Logic Board will request the Static Switch
Driver Board to connect the load to the inverter supply – i.e. ‘bypass-side’ open
and ‘inverter-side’ closed.
This situation will be maintained unless an inverter fault renders it incapable of
providing the required load supply parameters (e.g. ‘low battery voltage’, inverter
over/under voltage, inverter overload shutdown) or it is manually selected OFF
(from Operator Control Panel or UPS Logic Board ‘inverter enable’ switch) etc.
Note: if the cause of the transfer clears when the load is ‘on-bypass’ the load will
automatically transfer back to the inverter-side after a brief period to allow the in-
verter control time to re-establish itself. For example, a fault on an inverter phase
may cause an erroneous overload to be detected, or the output volts to dip below
the ‘undervoltage’ threshold, and initiate a load transfer to bypass. However, once

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7200 Series UPS Service Manual SECTION 6 - Static Switch Operation & Control
CHAPTER 1 - Static Switch Principles

the load is removed from the inverter its output will return to normal and request
the load to be returned to the inverter.
This type of fault could cause the load to “tick-tock” between the inverter and by-
pass; and to overcome this problem the transfer control logic permanently trans-
fers the load to bypass if more than 8 transfers occur within 60 seconds.

Bypass-to-inverter transfer mechanism

When the load is transferred from bypass to inverter the signal to close the ‘in-
verter-side’ contactor is applied 150ms before the ‘bypass-side’ SCR drive sig-
nals are removed. This is to allow time for the contactor to close before the bypass
SCRs are turned OFF. In practice the contactor should close well within 50ms.;
consequently, there will be an overlap period where both ‘sides’ of the static
switch are closed simultaneously, and the inverter and bypass voltages are effec-
tively connected in parallel. Once the contactor is closed an auxiliary contact sig-
nals the bypass SCRs to open immediately. This type of transfer is referred to as
a “closed transfer” as the load is transferred without a supply break.
Note: if the contactor does not close, as indicated by the auxiliary contact, the
UPS Logic Board will re-establish the ‘load-on-bypass’ command before the
150ms time-out period, keeping the load on bypass.
Before the transfer control logic will allow a closed transfer from bypass to invert-
er it must verify that the inverter voltage is synchronised to the bypass supply. If
this condition is not met then the transfer action is prohibited. Also, as this is a
“controlled” transfer (i.e. not initiated by a fault condition) the inverter voltage
regulation circuit is momentarily increased to matched the bypass voltage while
the transfer takes place – once the load is ‘on-inverter’ the inverter reverts to its
nominal voltage. This is to limit any volts difference across the ‘inverter-side’
contactor while it is being closed, and so prolong contactor life.

Inverter-to-bypass transfer mechanism

A load transfer from inverter to bypass can be initiated by manual selection (con-
trolled transfer) or by a fault condition (uncontrolled); however the results are
similar in that a “closed transfer”, as described above, will take place providing
the two supplies are synchronised. That is, the ‘bypass-side’ SCRs are requested
to turn ON before the ‘inverter-side’ contactor is de-energised, thus effecting a
no-break transfer.
If the inverter is not synchronised to the bypass supply when the load transfer is
requested then the ‘inverter-side’ contactor is opened before the ‘bypass-side’
SCRs are turned ON and the load will experience a slight power-break of up to 1
cycle. This type of transfer is referred to as an “open transfer”, and protects the
load from out-of-phase voltage differences which could put twice the phase volt-
age potential on the critical load busbar.

1.3.3 Control power supplies

All circuit boards concerned with the static switch control function are powered
from either the AC-DC Power Supply Board or the DC-DC Power Supply Board
and are active when either supply is ‘live’.

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SECTION 6 - Static Switch Operation & Control 7200 Series UPS Service Manual
CHAPTER 1 - Static Switch Principles

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 Section 6:

Chapter 2 - Static Switch Driver Board (4542043 Z)

2.1 Chapter overview

This chapter contains a circuit description of the Static Switch Driver Board cur-
rently used across the whole 7200 Series UPS model range, and should be read in
conjunction with circuit diagram SE-4542043-Z (1 page).
Part N º SE-4542043-Z is a direct replacement for Part Nº SE-4542041-X which
may be fitted to units manufactured prior to February 1997. Although there are
only minor differences between the two boards a full explanation of the Static
Switch Driver Board Part Nº SE-4542041-X can be found in Section 6 Chapter 3.

2.2 General description

2.2.1 Circuit board functions

This board is responsible for providing the ‘bypass-side’ static switch SCRs with
their gate drive signals when the UPS Logic Board requests Load-on-bypass, and
for energising the ‘inverter-side’ contactor when it requests Load-on-inverter. In
so doing, the board contains interlocking controls to prevent simultaneous opera-
tion of both circuits: thereby controlling the load transfer characteristics.
It also provides the necessary galvanic signal isolation between the low-voltage
environment of the control electronics and the high-voltage environment sur-
rounding the bypass SCR devices and ‘inverter-side’ contactor.

2.2.2 Input/Output connections

The Static Switch Driver Board has eleven connectors, all of which are described
below:
• X1 to X6 – Output gate drive signals to static switch SCRs
• X7 – Not used
• X8 – DC supply for the ‘inverter-side’ contactor
• X9 – Switched energising supply for the ‘inverter-side’ contactor
• X10 – ‘inverter-side’ contactor auxiliary contacts (used for contactor sta-
tus monitoring)
• X13 – Ribbon cable to the UPS Logic Board: carrying control logic sig-
nals and power supplies etc.

WARNING TAKE EXTREME CARE WHEN WORKING ON THIS BOARD IN SITU.

The ‘inverter-side’ contactor energising supply at connectors X8 and X9 is ob-

tained from the DC Busbar and is at a potentially dangerous DC voltage whenever
the rectifier is operating or the UPS battery circuit breaker is closed.
Similarly, mains a.c. voltage is present on the SCR drive connectors at all times
when the load is on ‘inverter’ or ‘bypass”.

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SECTION 6 - Static Switch Operation & Control 7200 Series UPS Service Manual
CHAPTER 2 - Static Switch Driver Board (4542043 Z)

2.2.3 Block Diagram

The following illustration shows the Static Switch Driver Board at its most basic
functional block diagram level – the function of each of the blocks shown is de-
scribed in the following text.

Figure 6-7: Static Switch Driver Board basic block diagram

DC Bus Contactor Inverter

Volts Switching Contactor
Logic

control
switch
Contactor
Auxiliary Transfer
Interlock
Load-on-inverter Logic
Load-on-bypass

Modulator Mixer
Oscillator Gate

Static
Supply Output Switch
Monitor Driver SCR
Circuit Gates
+12V
Power +12V
Control Power –12V
Supply
Supply +5V

Transfer interlock logic

The ‘transfer interlock logic’ is at the heart of the board’s operation. It determines
whether the ‘inverter-side’ contactor is closed or the static bypass SCRs are
turned on; and in so doing, it controls the load transfer operation between the in-
verter and bypass supplies.
There are three inputs to this static logic block. The ‘load-on-inverter’ and ‘load-
on-bypass’ signals are produced on the UPS Logic Board and are the primary load
transfer request inputs. The interlocking function also employs a signal derived
from auxiliary contacts of the ‘inverter-side’ contactor which confirms the con-
tactor’s status.

Contactor switching logic

The ‘contactor switching logic’ block contains a solid-state switching circuit
which is controlled by the ‘transfer interlock logic’ and connects the DC busbar
(battery) voltage through to the ‘inverter-side’ contactor’s closing coil.

Mixer gate
The ‘mixer gate’ combines the load-on-bypass command signal from the ‘transfer
interlock logic’ with a 30kHz modulating signal to provide the ‘output driver cir-
cuit’ with a modulated drive waveform. This type of drive signal is used to mini-

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CHAPTER 2 - Static Switch Driver Board (4542043 Z)

mise the size of the transformers in the ‘output driver circuit’, which are necessary
to provide signal isolation.
Note that the ‘mixer gate’ output is inhibited by the ‘supply monitor’ circuit if it
detects a ‘low’ control power supply voltage: this also provides a reset pulse on
initial power-up.

Modulation oscillator
This is a free running oscillator of approximately 30kHz which provides a modu-
lating signal to the ‘mixer gate’ as described immediately above.

Output driver circuit

This circuit contains three pairs of power drivers which are all driven by the mod-
ulated signal from the ‘mixer gate’. Each pair of drivers is connected in a push-
pull configuration across the output transformers’ primary windings to provide
adequate drive power.

Supply monitor
The ‘supply monitor’ senses the voltage on the +12V control power rail and
serves two functions: first, it provides reset signal to the ‘mixer gate’ to prevent it
turning on the static switch SCRs during power-up, until the supply rail has had
chance to stabilise. Second, it inhibits the mixer gate if it detects that the +12V
rail falls below 8V.

Power Supply
±12V power rails are connected to this board from the UPS Logic Board via X13
pins 1-12. These are connected to a voltage regulator circuit which provides a sta-
bilised +5V rail which is required by the board’s electronic devices.

2.3 Detailed circuit description

2.3.1 Introduction
This description, which refers to the ‘circuit blocks’ shown in Figure 6-7, should
be read in conjunction with diagram SE-4542043-Z.

‘inverter-side’ contactor control

The ‘inverter-side’ contactor is energised by the high DC voltage present on the
DC busbar. The full bus voltage is applied to X8 pins 1-3 and the coil is connected
to X9 pins 1-3. Note that the positive supply is directly connected via pins 3 and
the contactor is controlled by switching the bus negative supply to X9 pin 1.
The contactor is energised by a logic ‘high’ [INV-L> signal applied to X13 pin 15
from the UPS Logic Board. This signal turns on V32 which, via opto-isolator
V41, then turns on V31 and thus connects the contactor coil negative side to the
negative DC busbar supply at X8-1. The contactor should close within 50ms.
Note: the supply to V31 gate is obtained from the positive DC bus (battery) volt-
age present at X8 pins 3 via V41, R23 and R24; however it is limited to 13V by
zener V21. V12 and V13 are flywheel diodes to protect V41 and V31.
When the contactor closes, its auxiliary contacts short out X10 pins 1-2 which
then pulls D5-8 to a logic ‘low’ and informs the ‘transfer interlock logic’ of the
contactor’s status. The contactor should take between 60-100ms to open.

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CHAPTER 2 - Static Switch Driver Board (4542043 Z)

Static switch SCR control

The ‘bypass-side’ SCRs are controlled by the ‘transfer interlock logic’ circuit
output at D5 pin 12 (best monitored at X11: 0-3 which should be made). When
this point goes ‘high’ it drives N2 pin 7 ‘high’ which then takes D2 pin 2 and 3
high, which ‘triggers’ the SCRs, vi the driver FET’s V2 and V11.
D2 is annotated ‘mixer gate’ in the block diagram (See Figure 6-7) and turns on
the static switch SCRs when its outputs (D2 pins 6 & 9) are high. The input to D2
pin 2 and 3 is connected to the output of N3, which is a power supply monitor,
and goes ‘low’ to inhibit the SCR drive signal in the event of a power failure (and
during initial power-up). The input to D2 pin 1 and 5 is a 30kHz square wave
signal provided by D1, which is a free running oscillator: thus, provided there is
no problem with the power rails, when the output from N2 pin 7 goes ‘high’ it ‘en-
ables’ D2 to pass the 30kHz modulating signal through to the output driver gates
of V2 and V11.
Note: V2 and V11 are supplied from the -12V rail to provide suitable output
switching levels to the isolating pulse transformers driving the power SCRs.

Output driver circuit

The 30kHz output from the ‘mixer gate’ (D2 pins 6 & 9) are connected to the
gates of V2 & V11, which are the output line driver devices. Taking V2 as an ex-
ample: when the 30kHz drive signal to D2 pin 6 is ‘high’ FET V2 turns on. This
connects the -12V through to T1, T3 and T5 primaries with the +12V rail. When
the 30kHz drive signal is ‘low’ D2 outputs go to a high impedance state; thus the
±12V output at V2 is switched on and off at a 30kHz rate.
As can be seen on the circuit diagram, V2 and V11 output is connected to the
SCRs’ gate drive connectors via pulse transformers T1 to T6 which provide the
necessary signal isolation. Suppression capacitors C34 and C35 protect the driver
FETs from the transformers’ reactive currents.

Transfer interlock logic

Figure 6-8: Transfer interlock logic

D6
1
3
2
D5
V10 D6
R48 1 2 12
D5 11
470k
[MNS-L> R28 C6
13
3 4
1 = Load 330n
on 470k
Bypass

[INV-L> U5 U5

1 = Load 5 6 11 10
on
D6 1 = Turn on
Inverter D5
D6 8 bypass SCRs
D5 5 10 13 12
Contactor 4 9
Aux Fdbk 9 8 6

1 = Contactor
Open 1 = Close
Output
Contactor

As explained in the previous paragraphs, the ‘transfer interlock logic’ controls the
signal which initiates the static switch SCR driver circuit – i.e. the output from
D5-12 turns on the static switch when ‘high’ and vice versa.

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7200 Series UPS Service Manual SECTION 6 - Static Switch Operation & Control
CHAPTER 2 - Static Switch Driver Board (4542043 Z)

This circuit is controlled by three inputs shown in the diagram above. These are:
• [INV-L> which goes ‘high’ when the UPS Logic Board is requesting load-
on-inverter (i.e. contactor closed).
• [MNS-L> which goes ‘high’ when the UPS Logic Board is requesting load-
on-bypass (i.e. static switch SCRs turned on).
• Auxiliary contacts from the ‘inverter-side’ contactor which is logic ‘low’
when the contactor is closed and vice versa.

The [INV-L> and [MNS-L> signals are mutually exclusive – i.e. the control system
on the UPS Logic Board prevents it from requesting both conditions simultane-
ously. The following paragraphs described the circuit action when the load is
transferred between one power source and the other.
Load transfer from bypass to inverter - When the UPS Logic Board re-
quires a load transfer to inverter it simultaneously drives the [MNS-L> ‘low’ and
the [INV-L> ‘high’.
1. Prior to the transfer, the load is on the bypass supply, which means that D6
pin 10 is ‘low’ (turning on the bypass SCRs).
2. The ‘low’ [MNS-L> signal is inverted to a ‘high’ at D5 pin 4 which takes D6
pin 1 high.
3. The same ‘high’ [MNS-L> signal is also inverted to a ‘low’ at D5-2, however
R28/C6 applies a 150ms time delay on this signal before it reaches D6 pin 12.
This is to hold on the bypass SCRs until the ‘inverter-side’ contactor has had
time to close (contactor should close within 50ms).
4. After 150ms D6 pins 1 & 2 will both be ‘high’ and this will drive D6 pin 3
‘low’ which drives D6 pin 10 ‘high’ and D5 pin 12 ‘low’ – turning off the
bypass SCRs.
5. The ‘high’ [INV-L> signal:
a) is inverted twice, at D5-6 and D5-10, and applies a ‘high’ at D6 pin 5.
However this has no immediate effect on the circuit.
b) turns on V32, which switches on the ‘inverter-side’ contactor energising
supply (see earlier ‘output contactor control’ earlier in this section).
6. When the ‘inverter-side’ contactor closes it applies a ‘low’ to D5-9 which is
inverted to a ‘high’ at D5-8 and D6 pin 6.
7. With D6 pins 5 and 6 now both ‘high’, the output at D6 pin 4 goes ‘low’
which drives D6 pin 10 ‘high’ and D6 pin 11 ‘low’, which then turns off the
bypass SCRs. That is, if the ‘inverter-side’ contactor has closed it will open
the bypass SCRs immediately and doesn’t wait 150ms.

Note 1: the above description shows that when transferring normally from ‘by-
pass’ to ‘inverter’ the bypass SCRs are held on until the ‘inverter-side’ contactor
is closed (auxiliary contacts closed), therefore the load is transferred without a
supply break – i.e. closed transfer.
Note 2: Once the UPS Logic Board software decides to transfer to inverter, the
bypass SCRs are held on for a 150ms period. The contactor, if OK, should close
within 50ms. If this is the case, as indicated by the contactor auxiliary contacts,
the bypass SCRs are opened immediately. If this is NOT the case then the UPS

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CHAPTER 2 - Static Switch Driver Board (4542043 Z)

Logic Board software will re-establish the load on bypass command and remove
the load on inverter request to close the ‘inverter-side’ contactor.
Note 3: The load on inverter request is given 5 seconds to achieve its objective,
otherwise the micro will annunciate an alarm (#41) [Output: No Voltage] on the
Operator Control Panel and will not attempt further transfers.
Load transfer from inverter to bypass - When the UPS Logic Board re-
quires a load transfer to bypass it simultaneously drives the [MNS-L> ‘high’ and
the [INV-L> ‘low’.
1. Prior to the transfer, the load is on the inverter supply, which means that D5
pin 12 is ‘low’ (turning off the bypass SCRs).
2. The ‘high’ [MNS-L> signal is:
a) inverted to a ‘low’ at D5 pin 4 which takes D6 pin 1 ‘low’.
b) inverted to a ‘high’ at D5 pin 2 which takes D6 pin 2 ‘low’.
Note: that in this instance there is no delay on the signal reaching D6 pin 2
as the time delay is bypassed by V10.
3. A logic ‘low’ at either of D6 pins 1 or 2 will drive D6 pin 8 high; however this
has no immediate effect on the circuit (step 4a below).
4. The ‘low’ [INV-L> signal:
a) is inverted twice, at D5-6 and D5-10, and applies a ‘low’ at D6 pin 5
which results in a ‘high’ at D6 pin 9.
b) turns off V32, which switches off the ‘inverter-side’ contactor energising
supply (see ‘output contactor control’ earlier in this section).
5. With logic highs at D6 pin 8 (step 3) and pin 9 (step 4a), the output from D8
pin 10 now switches ‘low’ and D5 pin 12 ‘high’ which is the state necessary
to turn on the bypass SCRs.
6. When the ‘inverter-side’ contactor opens it applies a ‘high’ to D5-9 which is
inverted to a ‘low’ at D5-8 and D6 pin 6 which then holds D6 pin 9 ‘high’ and
reinforces (overrides) the effect of the [INV-L> signal on D6 pin 5.

Note: the above description shows that when transferring normally from ‘invert-
er’ to ‘bypass’ the bypass SCRs are turned on immediately the [INV-L> signal re-
quests the ‘inverter-side’ contactor to open, therefore the load is transferred
without a supply break – i.e. closed transfer. The contactor should open within 60-
100ms.

Power supplies
The devices on this board require various operating voltages. The main ±12V
supply rails are provided by the UPS Logic Board and connected via X13 pins 1
to 12. +12V and 0V are then connected to a simple three-terminal regulator which
provides a +5V supply rail, as shown.
Note that D1 and D2 are both 5V operating devices but are fed from the -12V and
0V power rails. This is to shift their output signal levels to that required to switch
the ‘output drivers’ (V2 and V11).

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CHAPTER 2 - Static Switch Driver Board (4542043 Z)

Power supply monitor

N3 monitors the +12V rail and -12V rail and its output pin 5 goes ‘low’ if the
+12V falls below approximately 6.8V or the -12 falls below approximately
-10.6V. This inhibits the ‘mixer gate’ D2 and the output line driver devices and
so prevents the bypass SCRs from being turned on. Power supply failure could
cause intermittent SCR triggering and, in the worst case, present a half-wave load
supply. The power supply monitor avoids such occurrences.

2.4 Summary information

Table 6-1: Static Switch Driver Board configuration jumpers

Link
Jumper Function
Position

open Enable load on inverter command (Standard)

0-1
closed Disable load on inverter command

open Enable load on bypass command(Standard)

0-2
closed Disable load on bypass command

open Disables bypass fire command

X11 0-3
closed Enable bypass fire command (Standard)

0-4 N/A Not used

open Test static switch temperature monitor

0-5 Inhibit static switch temperature monitor
closed
(standard)

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CHAPTER 2 - Static Switch Driver Board (4542043 Z)

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 Section 6:

Chapter 3 - Static Switch Driver Board (4542041 X)

3.1 Chapter overview

This chapter contains a circuit description of the Static Switch Driver Board
4542041X which was used across the whole 7200 Series UPS model range prior
to February ‘97, when it was superseded by Part No. 4542043Z (see Chapter 2).
This chapter should be read in conjunction with circuit diagram SE-4542041-X
(1 page).

3.2 General description

3.2.1 Circuit board functions

This board is responsible for providing the ‘bypass-side’ static switch SCRs with
their gate drive signals when the UPS Logic Board requests Load-on-bypass, and
for energising the ‘inverter-side’ contactor when it requests Load-on-inverter. In
so doing, the board contains interlocking controls to prevent simultaneous opera-
tion of both circuits: thereby controlling the load transfer characteristics.
It also provides the necessary galvanic signal isolation between the low-voltage
environment of the control electronics and the high-voltage environment sur-
rounding the bypass SCR devices and ‘inverter-side’ contactor.

3.2.2 Input/Output connections

The Static Switch Driver Board has eleven connectors, all of which are described
below:
• X1 to X6 – Output gate drive signals to static switch SCRs
• X7 – Not used
• X8 – DC supply for the ‘inverter-side’ contactor
• X9 – Switched energising supply for the ‘inverter-side’ contactor
• X10 – ‘inverter-side’ contactor auxiliary contacts (used for contactor sta-
tus monitoring)
• X13 – Ribbon cable to the UPS Logic Board: carrying control logic sig-
nals and power supplies etc.

WARNING TAKE EXTREME CARE WHEN WORKING ON THIS BOARD IN SITU.

The ‘inverter-side’ contactor energising supply at connectors X8 and X9 is ob-

tained from the DC Busbar and is at a potentially dangerous DC voltage whenever
the rectifier is operating or the UPS battery circuit breaker is closed.
Similarly, mains a.c. voltage is present on the SCR drive connectors at all times
when the load is on ‘inverter’ or ‘bypass”.

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SECTION 6 - Static Switch Operation & Control 7200 Series UPS Service Manual
CHAPTER 3 - Static Switch Driver Board (4542041 X)

3.2.3 Block Diagram

The following illustration shows the Static Switch Driver Board at its most basic
functional block diagram level – the function of each of the blocks shown is de-
scribed in the following text.

Figure 6-9: Static Switch Driver Board basic block diagram

DC Bus Contactor Inverter

Volts Switching Contactor
Logic

control
switch
Contactor
Auxiliary Transfer
Interlock
Load-on-inverter Logic
Load-on-bypass

Modulator Mixer
Oscillator Gate

Static
Supply Output Switch
Monitor Driver SCR
Circuit Gates

±12V
Control Power Power +5V
Supply
Supply
-7V

Transfer interlock logic

The ‘transfer interlock logic’ is at the heart of the board’s operation. It determines
whether the ‘inverter-side’ contactor is closed or the static bypass SCRs are
turned on; and in so doing, it controls the load transfer operation between the in-
verter and bypass supplies.
There are three inputs to this static logic block. The ‘load-on-inverter’ and ‘load-
on-bypass’ signals are produced on the UPS Logic Board and are the primary load
transfer request inputs. The interlocking function also employs a signal derived
from auxiliary contacts of the ‘inverter-side’ contactor which confirms the con-
tactor’s status.

Contactor switching logic

The ‘contactor switching logic’ block contains a solid-state switching circuit
which is controlled by the ‘transfer interlock logic’ and connects the DC busbar
(battery) voltage through to the ‘inverter-side’ contactor’s closing coil.

Mixer gate
The ‘mixer gate’ combines the load-on-bypass command signal from the ‘transfer
interlock logic’ with a 30kHz modulating signal to provide the ‘output driver cir-
cuit’ with a modulated drive waveform. This type of drive signal is used to mini-

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CHAPTER 3 - Static Switch Driver Board (4542041 X)

mise the size of the transformers in the ‘output driver circuit’, which are necessary
to provide signal isolation.
Note that the ‘mixer gate’ output is inhibited by the ‘supply monitor’ circuit if it
detects a ‘low’ control power supply voltage: this also provides a reset pulse on
initial power-up.

Modulation oscillator
This is a free running oscillator of approximately 30kHz which provides a modu-
lating signal to the ‘mixer gate’ as described immediately above.

Output driver circuit

This circuit contains three pairs of power drivers which are all driven by the mod-
ulated signal from the ‘mixer gate’. Each pair of drivers is connected in a push-
pull configuration across the output transformers’ primary windings to provide
adequate drive power.

Supply monitor
The ‘supply monitor’ senses the voltage on the +12V control power rail and
serves two functions: first, it provides reset signal to the ‘mixer gate’ to prevent it
turning on the static switch SCRs during power-up, until the supply rail has had
chance to stabilise. Second, it inhibits the mixer gate if it detects that the +12V
rail falls below 8V.

Power Supply
±12V power rails are connected to this board from the UPS Logic Board via X13
pins 1-12. These are connected to two voltage regulator circuits which provide
stabilised +5 and -7V supply rails which are required by several of the board’s de-
vices.

3.3 Detailed circuit description

3.3.1 Introduction
This description, which refers to the ‘circuit blocks’ shown in Figure 6-9, should
be read in conjunction with diagram SE-4542041-X.

‘inverter-side’ contactor control

The ‘inverter-side’ contactor is energised by the high DC voltage present on the
DC busbar. The full bus voltage is applied to X8 pins 1-3 and the coil is connected
to X9 pins 1-3. Note that the positive supply is directly connected via pins 3 and
the contactor is controlled by switching the bus negative supply to X9 pin 1.
The contactor is energised by a logic ‘high’ [INV-L> signal applied to X13 pin 15
from the UPS Logic Board. This signal turns on V32 which, via opto-isolator
V41, then turns on V31 and thus connects the contactor coil negative side to the
negative DC busbar supply at X8-1. The contactor should close within 50ms.
Note: the supply to V31 gate is obtained from the positive DC bus (battery) volt-
age present at X8 pins 3 via V41, R23 and R24; however it is limited to 13V by
zener V21. V12 and V13 are flywheel diodes to protect V41 and V31.
When the contactor closes, its auxiliary contacts short out X10 pins 1-2 which
then pulls D5-8 to a logic ‘low’ and informs the ‘transfer interlock logic’ of the
contactor’s status. The contactor should take between 60-100ms to open.

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CHAPTER 3 - Static Switch Driver Board (4542041 X)

Static switch SCR control

The ‘bypass-side’ SCRs are controlled by the ‘transfer interlock logic’ circuit
output at D6 pin 11 (best monitored at X12-3 which should be made). When this
point goes ‘high’ it drives N3 pin 7 ‘high’ which then takes D2 pin 4 and D3/D4
pins 7 and 16 high, which ‘triggers’ the SCRs.
D2 is annotated ‘mixer gate’ in the block diagram (See Figure 6-9) and turns on
the static switch SCRs when its output (D2 pin 6) is high. The input to D2 pin 3
is connected to the output of N4, which is a power supply monitor, and goes ‘low’
to inhibit the SCR drive signal in the event of a power failure (and during initial
power-up). The input to D2 pin 5 is a 30kHz square wave signal provided by D1,
which is a free running oscillator: thus, provided there is no problem with the
power rails, when the output from N3 pin 7 goes ‘high’ it ‘enables’ D2 to pass the
30kHz modulating signal through to the output driver gates of D3 and D4.
Note: D1 and D2 are supplied from the -7V and -12V power rails to shift their
output switching levels to that required for driving the output line drivers D3/D4.

Output driver circuit

The 30kHz output from the ‘mixer gate’ (D2-8) is connected to the gates of Q3/
Q4, which are the output line driver devices. Taking D4a as an example: when the
30kHz drive signal to D4-1 is ‘high’ the two drivers within D4a turn on. This con-
nects the -12V at D4-2 through to D4-3 and +12V (from N3 output) at D4-7
through to D4-6. When the 30kHz drive signal is ‘low’ D4 outputs go to a high
impedance state; thus the ±12V outputs at D4 pins 3 and 6 are switched on and
off at a 30kHz rate.
As can be seen on the circuit diagram, D4 outputs are connected to the SCRs’ gate
drive connectors via pulse transformers T1 and T2 which provide the necessary
signal isolation. V3 to V4 are flywheel diodes and protect the driver devices from
the transformers’ reactive currents.

Transfer interlock logic

Figure 6-10: Transfer interlock logic

D5

1 2
[MNS-L> D6
1
1 = Load 3
V10
on 2
Bypass D5

3 4
R29
C6
330n
470k

D6
8 D6
10 12
9 11 1 = Turn on
[INV-L>
D5 D5 13 bypass SCRs
1 = Load
on 5 6 11 10 D6
Inverter 5
4
6
D5
Contactor
9 8
Aux Fdbk
1 = Contactor 1 = Close
Open Output
Contactor

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CHAPTER 3 - Static Switch Driver Board (4542041 X)

As explained in the previous paragraphs, the ‘transfer interlock logic’ controls the
signal which initiates the static switch SCR driver circuit – i.e. the output from
D6-11 turns on the static switch when ‘high’ and vice versa.
This circuit is controlled by three inputs shown in the diagram above. These are:
• [INV-L> which goes ‘high’ when the UPS Logic Board is requesting load-
on-inverter (i.e. contactor closed).
• [MNS-L> which goes ‘high’ when the UPS Logic Board is requesting load-
on-bypass (i.e. static switch SCRs turned on).
• Auxiliary contacts from the ‘inverter-side’ contactor which is logic ‘low’
when the contactor is closed and vice versa.

The [INV-L> and [MNS-L> signals are mutually exclusive – i.e. the control system
on the UPS Logic Board prevents it from requesting both conditions simultane-
ously. The following paragraphs described the circuit action when the load is
transferred between one power source and the other.
Load transfer from bypass to inverter - When the UPS Logic Board re-
quires a load transfer to inverter it simultaneously drives the [MNS-L> ‘low’ and
the [INV-L> ‘high’.
1. Prior to the transfer, the load is on the bypass supply, which means that D6
pin 11 is ‘high’ (turning on the bypass SCRs).
2. The ‘low’ [MNS-L> signal is inverted to a ‘high’ at D5 pin 2 which takes D6
pin 1 high.
3. The ‘low’ [MNS-L> signal is also inverted to a ‘high’ at D5-4, however R29/C6
applies a 150ms time delay on this signal before it reaches D6 pin 2. This is to
hold on the bypass SCRs until the ‘inverter-side’ contactor has had time to
close (contactor should close within 50ms).
4. After 150ms D6 pins 1 & 2 will both be ‘high’ and this will drive D6 pin 3
‘low’ which drives D6 pin 10 ‘high’ and D6 pin 11 ‘low’ – turning off the
bypass SCRs.
5. The ‘high’ [INV-L> signal:
a) is inverted twice, at D5-6 and D5-10, and applies a ‘high’ at D6 pin 5.
However this has no immediate effect on the circuit.
b) turns on V32, which switches on the ‘inverter-side’ contactor energising
supply (see earlier ‘output contactor control’ earlier in this section).
6. When the ‘inverter-side’ contactor closes it applies a ‘low’ to D5-9 which is
inverted to a ‘high’ at D5-8 and D6 pin 6.
7. With D6 pins 5 and 6 now both ‘high’, the output at D6 pin 4 goes ‘low’
which drives D6 pin 10 ‘high’ and D6 pin 11 ‘low’, which then turns off the
bypass SCRs. That is, if the ‘inverter-side’ contactor has closed it will open
the bypass SCRs immediately and doesn’t wait 150ms.

Note 1: the above description shows that when transferring normally from ‘by-
pass’ to ‘inverter’ the bypass SCRs are held on until the ‘inverter-side’ contactor
is closed (auxiliary contacts closed), therefore the load is transferred without a
supply break – i.e. closed transfer.

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CHAPTER 3 - Static Switch Driver Board (4542041 X)

Note 2: Once the UPS Logic Board software decides to transfer to inverter, the
bypass SCRs are held on for a 150ms period. The contactor, if OK, should close
within 50ms. If this is the case, as indicated by the contactor auxiliary contacts,
the bypass SCRs are opened immediately. If this is NOT the case then the UPS
Logic Board software will re-establish the load on bypass command and remove
the load on inverter request to close the ‘inverter-side’ contactor.
Note 3: The load on inverter request is given 5 seconds to achieve its objective,
otherwise the micro will annunciate an alarm (#41) [Inverter: No Voltage] on the
Operator Control Panel and will not attempt further transfers.
Load transfer from inverter to bypass - When the UPS Logic Board re-
quires a load transfer to bypass it simultaneously drives the [MNS-L> ‘high’ and
the [INV-L> ‘low’.
1. Prior to the transfer, the load is on the inverter supply, which means that D6
pin 11 is ‘low’ (turning off the bypass SCRs).
2. The ‘high’ [MNS-L> signal is:
a) inverted to a ‘low’ at D5 pin 2 which takes D6 pin 1 ‘low’.
b) inverted to a ‘low’ at D5-4 which takes D6 pin 2 ‘low’.
Note: that in this instance there is no delay on the signal reaching D6 pin 2
as the time delay is bypassed by V10.
3. A logic ‘low’ at either of D6 pins 1 or 2 will drive D6 pin 8 high; however this
has no immediate effect on the circuit (step 4a below).
4. The ‘low’ [INV-L> signal:
a) is inverted twice, at D5-6 and D5-10, and applies a ‘low’ at D6 pin 5
which results in a ‘high’ at D6 pin 9.
b) turns off V32, which switches off the ‘inverter-side’ contactor energising
supply (see earlier ‘output contactor control’ earlier in this section).
5. With logic highs at D6 pin 8 (step 3) and pin 9 (step 4a), the output from D8
pin 10 now switches ‘low’ and D6 pin 11 ‘high’ which is the state necessary
to turn on the bypass SCRs.
6. When the ‘inverter-side’ contactor opens it applies a ‘high’ to D5-9 which is
inverted to a ‘low’ at D5-8 and D6 pin 6 which then hold D6 pin 9 ‘high’ and
reinforces (overrides) the effect of the [INV-L> signal on D6 pin 5.

Note: the above description shows that when transferring normally from ‘invert-
er’ to ‘bypass’ the bypass SCRs are turned on immediately the [INV-L> signal re-
quests the ‘inverter-side’ contactor to open, therefore the load is transferred
without a supply break – i.e. closed transfer. The contactor should open within 60-
100ms.

Power supplies
The devices on this board require various operating voltages. The main ±12V
supply rails are provided by the UPS Logic Board and connected via X13 pins 1
to 12. These are then connected to two simple three-terminal regulators which
provide +5V and -7V supply rails, as shown.
Note that D1 and D2 are both 5V operating devices but are fed from the -12V and
-7V power rails. This is to shift their output signal levels to that required to switch

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CHAPTER 3 - Static Switch Driver Board (4542041 X)

the ‘output drivers’ (D3 and D4). The -7V rail also offsets the output from N3 to
the ‘mixer gate’ input.

Power supply monitor

N4 monitors the +12V rail and -12V rail and its output pin 6 goes ‘low’ if the
+12V falls below approximately 6.8V or the -12 falls below approximately
-10.6V. This inhibits the ‘mixer gate’ and the output line driver devices (via V11)
and so prevents the bypass SCRs from being turned on. Power supply failure
could cause intermittent SCR triggering and, in the worst case, present a half-
wave load supply. The power supply monitor avoids such occurrences.

3.4 Summary information

Table 6-2: Static Switch Driver Board configuration jumpers

Link
Jumper Function
Position

X11 1-2 Inhibit static switch temperature monitor

2-3 Enable static switch temperature monitor (Standard)

0-1 OPEN Enable load on inverter command (Standard)

0-1 CLOSED Disable load on inverter command

0-2 OPEN Enable load on bypass command(Standard)

X12
0-2 CLOSED Disable load on bypass command

0-3 OPEN Disables bypass fire command

0-3 CLOSED Enable bypass fire command (Standard)

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CHAPTER 3 - Static Switch Driver Board (4542041 X)

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 Section 7: UPS System Control

Chapter 1 - UPS System Control Principles

1.1 Introduction .............................................................................................. 7-1

Chapter 2 - High Voltage Interface Board

2.1 Chapter overview ..................................................................................... 7-5
2.2 General description ................................................................................... 7-5
2.3 Detailed description .................................................................................. 7-7
2.3.1 X1 Low voltage signals to/from the UPS Logic Board. .............. 7-7
2.3.2 X2 (Page 2) – DC bus (battery) voltage sense ............................. 7-7
2.3.3 X3 (Page 2) – Rectifier input voltage sense ................................. 7-7
2.3.4 X4 (Page 2) – UPS output voltage sense ..................................... 7-7
2.3.5 X5 (Page 2) – Inverter output voltage sense ................................ 7-7
2.3.6 X6 (Page 2) – Bypass voltage sense ............................................ 7-8
2.3.7 X7 (Page 1) – Power switch auxiliary contacts ........................... 7-8
2.3.8 X8 (Page 1) – Interface to external connection block .................. 7-8
2.3.9 X9 (Page 2) – Battery cabinet temperature .................................. 7-9
2.3.10 X10 (Page 2) – Input air temperature sensor ............................. 7-9
2.3.11 X11 (Page 2) – Inverter output air temperature sensor .............. 7-9
2.3.12 X12 (Page 2) – Transformer cubicle air temperature sensor ..... 7-9
2.3.13 X13 (Page 1) – Inverter assembly thermostats ........................ 7-10
2.3.14 X14 (Page 1) – Not in use ........................................................ 7-10
2.3.15 X15 (Page 1) – Battery fuse monitor ....................................... 7-10
2.3.16 X16 (Page 1) – Not in use (linked out) .................................... 7-10
2.3.17 X17 (Page 1) – Not in use (linked out) .................................... 7-10
2.3.18 X18 (Page 1) – Rectifier current sensing ................................. 7-10
2.3.19 X19 (Page 1) – Output current monitoring W-ph .................... 7-10
2.3.20 X20 (Page 1) – Output current monitoring V-ph ..................... 7-10
2.3.21 X21 (Page 1) – Output current monitoring U-ph ..................... 7-11
2.3.22 X22 (Page 1) – Battery current monitoring ............................. 7-11
2.3.23 X23 (Page 1) – Inverter current monitoring U-ph ................... 7-11
2.3.24 X24 (Page 1) – Inverter current monitoring V-ph ................... 7-11
2.3.25 X25 (Page 1) – Inverter current monitoring W-ph .................. 7-11
2.3.26 X26 (Page 1) – Not in use ........................................................ 7-11
2.3.27 X27 (Page 1) – Not in use ........................................................ 7-11
2.4 Summary information ............................................................................. 7-12

Chapter 3 - UPS Logic Board (4550007 H)

3.1 Chapter overview ................................................................................... 7-13
3.2 General description ................................................................................. 7-13
3.2.1 Circuit board functions .............................................................. 7-13
3.2.2 Input/Output connections ........................................................... 7-14
3.2.3 Block Diagram ........................................................................... 7-20

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SECTION 7 - UPS System Control 7200 Series UPS Service Manual

3.3 Detailed circuit description .................................................................... 7-23

3.3.1 Introduction ................................................................................ 7-23
3.3.2 Basic microcontroller system ..................................................... 7-24
3.3.3 Data bus, address bus and control bus buffers ........................... 7-26
3.3.4 Ni-Cad Battery back-up controller ............................................. 7-26
3.3.5 Reset generator ........................................................................... 7-27
3.3.6 System RAM and ROM memory addressing ............................ 7-28
3.3.7 Basic system control logic (D88) ............................................... 7-29
D88 Status signals to processor system ........................... 7-31
D88 Reset circuit [RES_EXT> ........................................ 7-32
Major control signal outputs ............................................ 7-32
Load transfer control ........................................................ 7-34
3.3.8 CAN bus communications drivers and control logic ................. 7-35
3.3.9 Real-time clock (RTC) ............................................................... 7-35
3.3.10 Data bus buffers ‘chip select’ decoding ................................... 7-37
3.3.11 Data bus input buffers .............................................................. 7-38
3.3.12 Data bus output buffers ............................................................ 7-45
3.3.13 Frequency sensing and control signals .................................... 7-55
Frequency control principles ............................................ 7-55
Frequency sync control and operation ............................. 7-56
Non-Sync detection and alarm ......................................... 7-58
External ‘sync inhibit’ ...................................................... 7-58
3.3.14 Analogue signal processing ..................................................... 7-59
Bypass voltage signal processing ..................................... 7-59
Inverter voltage sensing ................................................... 7-60
Battery (bus) voltage sensing ........................................... 7-61
Battery current sensing .................................................... 7-61
Output voltage sensing ..................................................... 7-62
Output current sensing ..................................................... 7-63
Analogue signal monitoring multiplexers 7-64
3.3.15 Power supplies ......................................................................... 7-65
3.3.16 External communications ......................................................... 7-67
3.3.17 On board 7-segment indications summary .............................. 7-68
3.4 Summary information ............................................................................. 7-72

Chapter 4 - UPS Logic Board (4550004 E)

4.1 Chapter overview ................................................................................... 7-75
4.2 General description ................................................................................. 7-75
4.2.1 Circuit board functions .............................................................. 7-75
4.2.2 Input/Output connections ........................................................... 7-76
4.2.3 Block Diagram ........................................................................... 7-81
4.3 Detailed circuit description .................................................................... 7-84
4.3.1 Introduction ................................................................................ 7-84
4.3.2 Basic microcontroller system ..................................................... 7-85
4.3.3 Data bus, address bus and control bus buffers ........................... 7-88
4.3.4 Ni-Cad Battery back-up controller ............................................. 7-88
4.3.5 Reset generator ........................................................................... 7-89
4.3.6 System RAM and ROM memory addressing ............................ 7-90

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7200 Series UPS Service Manual SECTION 7 - UPS System Control

4.3.7 Basic system control logic ......................................................... 7-92

D22 Functional description .............................................. 7-92
D23 Functional description .............................................. 7-94
4.3.8 CAN bus communications drivers and control logic ................. 7-96
4.3.9 Real-time clock (RTC) ............................................................... 7-96
4.3.10 Data bus buffers ‘chip select’ decoding ................................... 7-98
4.3.11 Data bus input buffers .............................................................. 7-99
4.3.12 Data bus output buffers .......................................................... 7-105
4.3.13 Frequency sensing and control signals .................................. 7-113
Frequency control principles .......................................... 7-113
Frequency sync control and operation ........................... 7-114
Non-Sync detection and alarm ....................................... 7-116
External ‘sync inhibit’ .................................................... 7-116
4.3.14 Analogue signal processing ................................................... 7-117
Bypass voltage signal processing ................................... 7-117
Inverter voltage sensing ................................................. 7-118
Battery (bus) voltage sensing ......................................... 7-119
Battery current sensing .................................................. 7-119
Output voltage sensing ................................................... 7-120
Output current sensing ................................................... 7-121
Analogue signal monitoring multiplexers ...................... 7-122
4.3.15 Power supplies ....................................................................... 7-123
4.3.16 External communications ....................................................... 7-125
4.3.17 On board 7-segment indications summary ............................ 7-126
4.4 Summary information ........................................................................... 7-130

Chapter 5 - Operator Logic Board

5.1 Chapter overview ................................................................................. 7-133
5.2 General description ............................................................................... 7-133
5.2.1 Circuit board functions ............................................................ 7-133
5.2.2 Input/Output connections ......................................................... 7-134
5.2.3 Block Diagram ......................................................................... 7-135
5.3 Detailed circuit description .................................................................. 7-137
5.3.1 Introduction .............................................................................. 7-137
5.3.2 Basic microcontroller system ................................................... 7-138
5.3.3 Data bus, address bus and control bus buffers ......................... 7-139
5.3.4 Reset generator ......................................................................... 7-140
5.3.5 Alarm buzzer ............................................................................ 7-140
5.3.6 Address decoding – D10 .......................................................... 7-140
5.3.7 System RAM and ROM memory addressing .......................... 7-141
5.3.8 Interface to the Operator Control Panel ................................... 7-142
5.3.9 Interface to the CAN Bus ......................................................... 7-143
5.3.10 Serial (modem) Interface ....................................................... 7-144
5.3.11 RS232 & RS485 Interface ..................................................... 7-144
5.3.12 Power Supply ......................................................................... 7-145
5.4 Summary information ........................................................................... 7-146

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SECTION 7 - UPS System Control 7200 Series UPS Service Manual

Chapter 6 - Operator Control Panel

6.1 Section overview .................................................................................. 7-149
6.2 General description ............................................................................... 7-149
6.2.1 Circuit board functions ............................................................ 7-149
6.2.2 Input/Output connections ......................................................... 7-149
6.3 Detailed circuit description .................................................................. 7-150
6.3.1 LED Display indication ........................................................... 7-150
6.3.2 Operator input switches ........................................................... 7-151
6.3.3 LCD Display Panel .................................................................. 7-151

Chapter 7 - System software

7.1 Introduction .......................................................................................... 7-153
7.2 Program structure and execution .......................................................... 7-153
7.2.1 Initialisation/Reset ................................................................... 7-156
7.2.2 Rectifier ON/OFF subroutine .................................................. 7-158
7.2.3 Inverter OFF/ON Sub-routine .................................................. 7-160
7.2.4 Frequency synchronisation control .......................................... 7-162
7.2.5 Battery circuit breaker control ................................................. 7-168
7.2.6 Low Battery Pre-alarm ............................................................. 7-172
7.2.7 Battery undervoltage trip threshold ......................................... 7-174
7.2.8 Battery Boost charge ................................................................ 7-176
7.2.9 Battery Test .............................................................................. 7-178
7.2.10 Load transfer control logic ..................................................... 7-180

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 Section 7: UPS System Control

Chapter 1 - UPS System Control Principles

1.1 Introduction
Previous descriptions in this manual show that the UPS can broadly be divided
into three major areas, each of which is largely independently controlled – i.e:
• the rectifier – (See section 4)
• the inverter – (See section 5)
• the static switch – (See section 6)

However, a study of these sections show that there is also a degree of commonal-
ity concerning certain of their control functions; for example, the way in which
their required analogue sense signals are processed and applied, and their operat-
ing parameters set from the Operator Control Panel.
The chapters in this section (7) describe those boards concerned with servicing the
control requirements of all three of the major power sections mentioned above,
and as such are the boards that bring together the control functions of the entire
UPS system – hence the section title UPS System Control. A block diagram show-
ing the relationship between the System Control boards and the other UPS control
areas is shown in Figure 7-1.

High Voltage Interface Board

Analogue signal processing. The High Voltage Interface Board is responsible
for processing the analogue sense signals obtained from various parts of the UPS
power sections – as illustrated in Figure 7-1. It attenuates, and where necessary
isolates, the sensed signals to levels acceptable to the low voltage operating envi-
ronment of the other control boards, and in certain instances also provides a
means of signal calibration. The board’s output are then passed to the major con-
trol logic boards via the UPS Logic Board, which is at the heart of the System Con-
trol function.
Digital signal processing. This board also monitors various digital status sig-
nals and passes them once again to the UPS Logic Board, where they are used by
the decision-making processes in its microcontroller’s software. For example,
Figure 7-1 shows inputs from the power switch auxiliaries; but not shown are var-
ious external inputs from circuits such as the Emergency Stop facility, battery
cabinet thermostats etc.

Operator Control Panel & Operator Logic Board

These two boards provide the digital interface between the Operator and the UPS
Logic Board and permit two-way data communication – i.e. metering data gener-
ated on the UPS Logic Board are processed on the Operator Logic Board and then
presented to the Operator Control Panel; conversely, parameter settings and
manual control inputs entered at the Operator Control Panel are passed through
the Operator Logic Board processing circuits to the UPS Logic Board where they
impinge on the microcontroller’s decision-making operation.

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 Maintenance Bypass
Isolator

7-2
Bypass
Isolator

Bypass Mains
Bypass-side
Static Switch

Q2 Aux
Q3 Aux
Static Switch
Input Rectifier Control DC Busbar Inverter Control Control Output
Input filter filter

Bypass voltage sense

Isolator Fuses capacitors Isolator
capacitors
SECTION 7 - UPS System Control

Phase 3 Phase Output

Input
Controlled Power Tfrmr
Choke
Rectifier Inverter

Input mains
Critical Load

Inverter-side
Drive (Trigger) Inverter Base
CHAPTER 1 - UPS System Control Principles

Contactor
Interface Bd. Drive Bds.
Drive (Trigger)
Interface Bd.

Rectifier Logic Inverter Logic Static Switch

Board Board Driver Board

CBbat Aux

Q1 Aux
Input voltage sense
Input current sense
DC Bus voltage sense
Battery current sense
Inverter current sense
Output voltage sense
Output current sense
Q4 Aux

Inverter voltage sense

Inverter voltage sense
Figure 7-1: UPS Control system block diagram

Alarm Interface Board Remote Alarms

(I/O Option) ON GENERATOR

Operator Logic Board
UPS Logic Board
Parallel Logic
Board (1+1 only)

CBbat Aux
Q1 Aux Inverter current sense
Operator Control
Q2 Aux Inverter voltage sense
Panel Q3 Aux Parallel Control Bus
High Voltage Bypass voltage sense
Input voltage sense Output voltage sense
Input current sense
Interface Board
Output current sense
7200 Series UPS Service Manual

DC Bus voltage sense Q4 Aux System Control

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Battery current sense Battery Breaker Trip
7200 Series UPS Service Manual SECTION 7 - UPS System Control
CHAPTER 1 - UPS System Control Principles

Alarm Interface Board

Several forms of Alarm Interface Board are available to allow remote indication
of the alarms generated on the UPS Logic Board (refer to the Options Section of
this manual). These boards also permit the connection of certain basic external
controls; such as on-generator, sync inhibit, second stage current limit etc.

UPS Logic Board

As is evident from reading the earlier part of this chapter, the UPS Logic Board
is central to the whole System Control function.
This board, which is micro-controller driven, accepts various analogue and digital
inputs from the High Voltage Interface Board, Operator Control Board and Alarm
Interface Board (optional) and provides the necessary control and alarms signals
used by the remainder of the UPS control areas. It also monitors various alarm and
status signals from the rectifier, inverter and static switch control sections and
produces appropriate alarms and control logic signals.
The board is software-driven and a description of the software functions and flow-
charts are provided at the end of this section (see Chapter 7).
In a 1+1 configured system the UPS Logic Board is also fed with various control
and status signals from the Parallel Logic Board pertaining to the parallel-control
functions (See section 8).

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SECTION 7 - UPS System Control 7200 Series UPS Service Manual
CHAPTER 1 - UPS System Control Principles

7-4 s7-c1.fm5 - Issue 2 Dated 21/08/97

 Section 7:

Chapter 2 - High Voltage Interface Board

2.1 Chapter overview

This chapter contains a circuit description of the High Voltage Interface Board
used across the whole model 7200 Series UPS range and should be read in con-
junction with circuit diagram SE-4590054-O (2 pages).
Signal annotations shown on the circuit diagrams are shown in italics in the fol-
lowing text – e.g. VINV_A.

2.2 General description

The purpose of this board is to provide an interface between the high voltage en-
vironments of the UPS power circuitry and the low voltage environment of the
system control boards. The high voltage sense signals taken from various parts of
the power circuitry are therefore attenuated on this board before being applied to
their appropriate control circuits.
In addition to providing signal attenuation the board also contains calibration fa-
cilitates for those signals which are power-related. This allows the board to be
used across the entire model range providing the calibration links are set appro-
priately.
All the low-voltage signals are connected to the UPS Logic Board via socket X1
and ribbon cable W8: the remaining IDC connectors (X2 to X27) carry the high
voltage signals.
Table 7-1on the following page provides an overview of each connectors’ func-
tion and this is followed by a more detailed circuit description.

Power supplies
The ±12V control power rails required by the board’s op-amps are obtained from
the UPS Logic Board and connected via X1 pins 1-12 as shown on the circuit di-
agram page 2.

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SECTION 7 - UPS System Control 7200 Series UPS Service Manual
CHAPTER 2 - High Voltage Interface Board

Table 7-1: Connector summary

X1 Low voltage signals to/from the UPS Logic Board.

X2 DC bus (battery) voltage sense inputs.

X3 Rectifier input voltage sensing inputs

X4 UPS output voltage sensing inputs

X5 Inverter output voltage sensing inputs

X6 Bypass voltage sensing inputs

X7 Power switch auxiliary contacts

X8 Interface to customer connection block X8

X9 Battery cabinet temperature

X10 Input air temperature sensor inputs

X11 inverter output air temperature sensor inputs

X12 Transformer cabinet air temperature sensor inputs

X13 Inverter assembly thermostats (n/c)

X14 Not in use

X15 Battery fuse monitor

X16 Not in use (linked out) – inverter fuse fail

X17 Not in use (linked out) – rectifier fuse fail

X18 Rectifier input current monitor

X19 Output current monitoring W-ph

X20 Output current monitoring V-ph

X21 Output current monitoring U-ph

X22 Battery current monitoring

X23 Inverter current monitoring U-ph (12 pulse inverter only)

X24 Inverter current monitoring V-ph (6 pulse & 12 pulse inverter)

X25 Inverter current monitoring W-ph (6 pulse & 12 pulse inverter)

X26 Not in use – 12 pulse rectifier DC current ½ bridge

X27 Not in use – 12 pulse rectifier DC current ½ bridge

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7200 Series UPS Service Manual SECTION 7 - UPS System Control
CHAPTER 2 - High Voltage Interface Board

2.3 Detailed description

The remainder of this chapter contains a detailed description of the circuits asso-
ciated with each of the above connectors.

2.3.1 X1 Low voltage signals to/from the UPS Logic Board.

X1 carries various signals between the High Voltage Interface Board and the UPS
Logic Board, each of which is described in detail below. It also carries ±12V
power supplies from the UPS Logic Board to the High Voltage Interface Board to
provide it with general control power supply rails and also power the DCCT de-
vices used to monitor the battery current and inverter output current.

2.3.2 X2 (Page 2) – DC bus (battery) voltage sense

The DC Bus (battery) voltage is monitored at connector X2, attenuated by N4d
and connected to the UPS Logic Board via X1-27. The attenuation factor is ap-
proximately 136:1 – i.e. V_B has a sensitivity of approximately 7.3mV per V(bat-
tery) and is therefore approximately 3.255Vdc. at a nominal float charge of 446V.

2.3.3 X3 (Page 2) – Rectifier input voltage sense

The input mains line voltage is connected to connector X3, attenuated by three
sections of N4 and connected to the UPS Logic Board via X1 terminals 24,25,26.
Each section of N4 monitors the input voltage on a line-to-line basis; for example
N4a inputs are connected to the input U (Vrec-A) and V (Vrec-B) phases. The at-
tenuation factor is approximately 75:1 – i.e. VREC_AB has a sensitivity of ap-
proximately 13.3mV per Vl-l (input volts) and therefore equals 5.8Vrms (15Vp-p)
when the input mains voltage is at a nominal 400Vac.
Note: the input voltage is applied to X3 only when the input power switch Q1 is
closed and the main input power fuses are healthy.

2.3.4 X4 (Page 2) – UPS output voltage sense

The UPS output voltage is connected to connector X4, attenuated by three sec-
tions of N3 and connected to the UPS Logic Board via X1 terminals 21,22,23.
Each section of N3 monitors the output voltage on a line-to-neutral basis; for ex-
ample N3a inputs are connected to the output neutral (Vout-0) and U phase
(Vout-A). The attenuation factor is approximately 100:1 – i.e. VO_A has a sensi-
tivity of approximately 10mV per Vl-n (output) and therefore equals 2.2Vrms
(8Vp-p) when the UPS output voltage is at a nominal 220Vac.
Note: the output voltage is connected to X4 from the ‘live’ side of the output
power switch Q4 and is present when the inverter output contactor is closed (load
on inverter) OR the bypass static switch is closed (load on bypass) but not when
the load is running on the maintenance bypass and the UPS is shut down.

2.3.5 X5 (Page 2) – Inverter output voltage sense

The inverter output voltage is connected to connector X5, attenuated by three sec-
tions of N2 and connected to the UPS Logic Board via X1 terminals 18,19,20.
Each section of N2 monitors the inverter voltage on a line-to-neutral basis; for ex-
ample N2a inputs are connected to the inverter neutral (Vinv-0) and U phase
(Vinv-A). The attenuation factor is approximately 100:1 – i.e. VINV_A has a sen-
sitivity of approximately 10mV per Vl-n (inverter) and therefore equals 2.2Vrms
(8Vp-p) when the inverter voltage is at a nominal 220Vac.

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SECTION 7 - UPS System Control 7200 Series UPS Service Manual
CHAPTER 2 - High Voltage Interface Board

Note: the inverter voltage is connected to X5 from the junction of the output trans-
former and inverter output contactor and is present only when the inverter is op-
erating. When the inverter output contactor is closed (load on inverter) the voltage
applied to X5 is identical to the output voltage sense signals applied to X4 (see
above) – these two signal groups can therefore be considered as monitoring either
side of the inverter output contactor.

2.3.6 X6 (Page 2) – Bypass voltage sense

The UPS bypass voltage is connected to connector X6, attenuated by three sec-
tions of N1 and connected to the UPS Logic Board via X1 terminals 15,16,17.
Each section of N1 monitors the bypass voltage on a line-to-neutral basis; for ex-
ample N1a inputs are connected to the bypass neutral (Vin-0) and U phase (Vin-A).
The attenuation factor is approximately 100:1 – i.e. VI_A has a sensitivity of ap-
proximately 10mV per Vl-n (bypass) and therefore equals 2.2Vrms (8Vp-p) when
the UPS output voltage is at a nominal 220Vac.
Note: the bypass voltage is connected to X4 from the ‘switched’ side of the bypass
power switch Q2 and is present when the switch is closed (normal).

2.3.7 X7 (Page 1) – Power switch auxiliary contacts

Each of the UPS power switches has an auxiliary contact which signals the switch
status to the UPS Logic Board via the High Voltage Interface Board Q7. In each
case the auxiliary contact is open when the main switch is open, and one side is
connected to 0V which is available at X7-5. When the power switches are closed
they therefore pull their respective status signals at X1 terminals 43-46 to 0V
which is interpreted as logic low by the switch monitoring circuits on the UPS
Logic Board. Conversely, when the power switches are open the outputs to X1
terminals 43-46 are pulled up to +4.7V and interpreted as logic high.

2.3.8 X8 (Page 1) – Interface to external connection block

X8 is connected to the customer terminal block (X3) by means of the wires iden-
tified in Figure 7-1 below:

Figure 7-2: Connection between X8 and customer T.B

X3
1
2
3 X8
4 1
5 79 2
6 3
7 81 4
8 82 5
9 77 6
10 76 7
11
12 HVI Board

Customer T.B

Battery circuit breaker “enable”

A +5V battery circuit breaker “enable” signal is generated on the UPS Logic
Board and connected to the High Voltage Interface Board X1-54 from where it
passes directly through X8-2 to the customer T.B. X3-6. From here, the signal is
taken via external wiring to the trip circuit on the Battery Circuit Breaker Control-
ler Board. The battery circuit breaker will “trip” if this “enable” supply is re-
moved (note that X8-5 provides the enable signal 0V return path).

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CHAPTER 2 - High Voltage Interface Board

Battery circuit breaker auxiliary

Auxiliary contacts of the battery circuit breaker ‘make’ the circuit between X8
terminals 4 and 5 (0V) when the breaker is closed. This is fed as a logic low ‘cir-
cuit breaker closed’ status signal (SW_BAT) to the UPS Logic Board via X1-53.
When the circuit breaker is open SW_BAT is pulled up to 4.7V due to V11.

Emergency Stop
The emergency stop circuit is connected in a ‘normally-closed’ fashion between
the customer T.B. terminals 10 and 11. This is connected via wires 76 and 77 to
X8 terminals 6 and 7 and then passed to the UPS Logic Board via X1-52 in the
form of a logic low ESD signal. When the emergency stop circuit is open, ESD is
pulled up to 4.7V due to V10.
If the emergency stop facility is not used then a link must be fitted between ter-
minals 10 and 11 on the customer T.B. in order for the UPS to operate.
Note: when the emergency stop circuit is activated it shuts down the UPS power
sections and isolates the load but does not disconnect the UPS input power source
(unless an optional external mains circuit breaker is used) therefore the UPS con-
trol logic will maintain its operating control power from the input mains supply if
it is still available.

2.3.9 X9 (Page 2) – Battery cabinet temperature

The battery cabinet temperature is monitored by an LM355A temperature sensor
which produces a temperature-proportional voltage of 10mV/°C. This is buffered
on the High Voltage Interface Board and the resulting T4 signal is connected to
the UPS Logic Board via X1-60 and is ultimately used by the Rectifier Logic
Board to reduce the regulated battery float charge voltage by 1V per degree cen-
tigrade of increase in battery temperature.

2.3.10 X10 (Page 2) – Input air temperature sensor

The input air temperature is monitored by an LM355A temperature sensor which
produces a temperature-proportional voltage of 10mV/°C. This is buffered on the
High Voltage Interface Board and the resulting T3 signal is connected to the UPS
Logic Board via X1-59. The UPS Logic Board uses this signal to present the
actual input cooling air-flow temperature on the appropriate Operator Control
Panel metering display window.

2.3.11 X11 (Page 2) – Inverter output air temperature sensor

The inverter output air temperature is monitored by an LM355A temperature
sensor which produces a temperature-proportional voltage of 10mV/°C. This is
buffered on the High Voltage Interface Board and the resulting T2 signal is con-
nected to the UPS Logic Board cooling air-flow temperature on the appropriate
Operator Control Panel metering display window.

2.3.12 X12 (Page 2) – Transformer cubicle air temperature sensor

The transformer cubicle air temperature is monitored by an LM355A temperature
sensor which produces a temperature-proportional voltage of 10mV/°C. This is
buffered on the High Voltage Interface Board and the resulting T1 signal is con-
nected to the UPS Logic Board via X1-57. This signal is ultimately used by the
Rectifier Logic Board to reduce the regulated battery float charge voltage by 1V
per degree centigrade of increase in transformer temperature (between 25°C and
35°C).

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SECTION 7 - UPS System Control 7200 Series UPS Service Manual
CHAPTER 2 - High Voltage Interface Board

2.3.13 X13 (Page 1) – Inverter assembly thermostats (normally closed)

The thermostats fitted to the inverter heatsink provide a normally closed circuit
between X13 pins 1 and 2, and open only if the temperature rises above 90°C. The
TH status signal to the UPS Logic Board via X1-51 is therefore normally low, and
rises to 4.7V (due to V9) following an inverter overtemperature event.
If an overtemperature condition occurs an “inverter overtemperature” alarm is
immediately activated (alarm #34) and the inverter is shut down after one minute
if the condition is still present – “overtemp shutdown” (alarm #62) annunciated.
The shut-down condition is latched, and the reset button must be pressed to restart
the inverter and cancel the alarm.

2.3.14 X14 (Page 1) – Not in use

2.3.15 X15 (Page 1) – Battery fuse monitor

The battery fuse contains a micro-switch failure detection device which provides
a normally closed circuit between X15 pins 1 and 2. The FUS_BAT status signal
to the UPS Logic Board via X1-50 is therefore normally low, and rises to 4.7V
(due to V8) following a fuse failure. Alarm #54 annunciates a fuse failure event.

2.3.16 X16 (Page 1) – Not in use (linked out)

2.3.17 X17 (Page 1) – Not in use (linked out)

2.3.18 X18 (Page 1) – Rectifier current sensing

Two CTs mounted on the U and V phases of the rectifier assembly provide input
current sense signals to X18 pins 1-3. These signals are rectified by V12-V17 and
the resulting dc voltage (IREC_I) is developed across a selectable burden resistor
and fed to the UPS Logic Board via X1-35. The appropriate resistance is selected
by a three-position jumper identified as X40 which should be set to position 0-3
in all cases of 30kVA, 40kVA and 60kVA models. This signal is used by the Rec-
tifier Logic Board to limit the maximum input current allowed through the recti-
fier in order to protect the rectifier SCRs.

2.3.19 X19 (Page 1) – Output current monitoring W-ph

A CT mounted on the UPS output W phase provides a current sense signal to X19
pins 1-3. The resulting voltage (IO_C) is developed across a selectable burden re-
sistor and fed to the UPS Logic Board via X1-34. The appropriate resistance is
selected by a three-position jumper identified as X39 which should be set to po-
sition 0-3 in all cases of 30kVA, 40kVA and 60kVA models. This signal is used
by the UPS Logic Board to initiate an overload warning (alarm #66) and overload
latches (alarm #62), and also to initiate the overload timer.

2.3.20 X20 (Page 1) – Output current monitoring V-ph

A CT mounted on the UPS output V phase provides a current sense signal to X20
pins 1-3. The resulting voltage (IO_B) is developed across a selectable burden re-
sistor and fed to the UPS Logic Board via X1-33. The appropriate resistance is
selected by a three-position jumper identified as X38 which should be set to po-
sition 0-3 in all cases of 30kVA, 40kVA and 60kVA models. This signal is used
by the UPS Logic Board to initiate an overload warning (alarm #66) and overload
latches (alarm #62), and also to initiate the overload timer.

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CHAPTER 2 - High Voltage Interface Board

2.3.21 X21 (Page 1) – Output current monitoring U-ph

A CT mounted on the UPS output U phase provides a current sense signal to X21
pins 1-3. The resulting voltage (IO_A) is developed across a selectable burden re-
sistor and fed to the UPS Logic Board via X1-32. The appropriate resistance is
selected by a three-position jumper identified as X37 which should be set to po-
sition 0-3 in all cases of 30kVA, 40kVA and 60kVA models. This signal is used
by the UPS Logic Board to initiate an overload warning (alarm #66) and overload
latches (alarm #62), and also to initiate the overload timer.

2.3.22 X22 (Page 1) – Battery current monitoring

A DCCT mounted in the battery positive line provides a current sense signal to
X22 pin 2 (pins 1 and 3 carry the ±12V operating power supply to the DCCT de-
vice). The signal voltage (IO_A) is developed across a selectable burden resistor
and fed to the UPS Logic Board via X1-31. The appropriate resistance is selected
by a three-position jumper identified as X31 which should be set to position 0-2
in standard 30kVA, 40kVA and 60kVA models and 0-3 in a 60kVA model. The
sense signal is used by the Rectifier Logic Board to limit the maximum battery
charge current (to protect the battery), and also by the UPS Logic Board to calcu-
late the percentage capacity and remaining autonomy time.

2.3.23 X23 (Page 1) – Inverter current monitoring U-ph

Not used – the inverter U-phase current is not monitored in a standard 7200 Series
UPS model.

2.3.24 X24 (Page 1) – Inverter current monitoring V-ph

A DCCT mounted in the inverter output V-phase line provides a current sense
signal to X24 pin 2 (pins 1 and 3 carry the ±12V operating power supply to the
DCCT device). The signal voltage (IINV_B) is developed across a selectable
burden resistor and fed to the UPS Logic Board via X1-29. The appropriate resist-
ance is selected by a three-position jumper identified as X33 which should be set
to 0-2 in standard 40kVA models and 0-3 in a 30kVA and 60kVA models.
This signal is used by the Inverter Logic Board to:
• regulate the PWM drives in order to sustain the inverter output during load
changes (i.e. act as a feed-forward control).
• introduce a 150% inverter current limit (achieved by blocking the PWM
signal and reducing the inverter voltage) in order to limit the maximum
current drawn through the inverter and protect the inverter IGBT devices.

2.3.25 X25 (Page 1) – Inverter current monitoring W-ph

A DCCT mounted in the inverter output W-phase line provides a current sense
signal to X25 pin 2 (pins 1 and 3 carry the ±12V power supply to the DCCT de-
vice). The signal voltage (IINV_C) is developed across a selectable burden resistor
and fed to the UPS Logic Board via X1-30. The appropriate resistance is selected
by a three-position jumper identified as X34 which should be set to position 0-2
in standard 40kVA models and 0-3 in a 30kVA and 60kVA models.
This signal is used in the same way as the V-phase signal described above.

2.3.26 X26 (Page 1) – Not in use

2.3.27 X27 (Page 1) – Not in use

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CHAPTER 2 - High Voltage Interface Board

2.4 Summary information

Table 7-2: High Voltage Interface Board configuration links

Link
Jumper Function
Position

— 0-1

X31 0-2 30 kVA CT burden selection

X31 : X32 : X33 : X34 : X35 : X37 : X38 0-3
: X39 : X40

— 0-1

X31 : X32 : X33 : X34 0-2 40 kVA CT burden selection

X35 : X36 : X37 : X38 : X39 : X40 0-3

— 0-1

— 0-2 60 kVA CT burden selection

X31 :X32 : X33 : X34 : X35 : X36 : X37 : 0-3
X38 : X39 : X40

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 Section 7: UPS System Control

Chapter 3 - UPS Logic Board (4550007 H)

3.1 Chapter overview

This chapter contains a circuit description of the current UPS Logic Board used
across the whole 7200 Series UPS model range, and should be read in conjunction
with circuit diagram SE-4550007-H (7 pages).
Part N º SE-4550007-H is a direct replacement for Part Nº SE-4550004-E which
may be fitted to units manufactured prior to February 1997. Though their are only
minor differences in the two PCBs a full explanation of the UPS Logic Board Part
Nº SE-4550004-E can be found in Section 7 Chapter 4.
Signal annotations shown on the circuit diagrams are shown in italics in the fol-
lowing text – e.g. [CLKOUT>.

3.2 General description

3.2.1 Circuit board functions

Figure 7-3: UPS Logic Board connections

Rectifier Inverter Static Switch

Logic Board Logic Board Driver Board
X2 X4 X13

X1 X3 X5
Parallel X2
UPS Logic Board X7 Control
Logic
X3
X2 X8 X6 X4

X1 X1 X2 X9 Operator
High Voltage External Operator Control
I/face Board Alarm Options Logic Board Panel

The position of the UPS Logic Board with respect to the other control boards
places it at the heart of the UPS control operation and its functional responsibili-
ties can be broadly summarised as follows:
• Motherboard –
One of the most basic functions provided by the UPS Logic Board is to act
as a ‘motherboard’ for signals travelling directly between any of the other
circuit boards connected to it: e.g. the input voltage sense signals passes
directly from the High Voltage Interface Board to the Rectifier Logic

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CHAPTER 3 - UPS Logic Board (4550007 H)

Board.
• System control –
The UPS Logic Board contains a microprocessor-based control system
which reads various status signals derived on the other circuit boards and
produces several ‘system’ control logic signals: e.g. ‘stop/start’ signals to
the Rectifier/Inverter Logic Boards, and ‘transfer command’ signals to the
Static Switch Interface Board.
• Alarms control –
The UPS Logic Board acts as an assembly point for alarm signals gener-
ated on the various other boards, together with those generated on the UPS
Logic Board itself, and controls their distribution to the Operator Control
Panel and External Alarms Options under microprocessor supervision.
• Operator programming interface –
The UPS Logic Board microprocessor enforces the programmable system
operating parameters selected by the operator, via the Operator Logic
Board, onto the ‘system’ control logic
• Static Switch transfer control –
The UPS Logic Board contains decision-making logic which controls the
load transfer events between the inverter and static bypass supplies.

3.2.2 Input/Output connections

The UPS Logic Board has eight connectors (See Figure 7-3) whose connections
are summarised below.
• X1 – System control and monitoring signals to/from the Rectifier Board
4520074-A (See Table 7-3).
• X2 – System control and monitoring signals to/from the High Voltage
Interface Board 4590054-O (See Table 7-4).
• X3 – System control and monitoring signals to/from the Inverter Logic
Board 4530025-T (See Table 7-5).
• X4 – Power supply to Operator Logic Board 4550005-F (see circuit dia-
gram sheet 7).
• X5 – System control and monitoring signals to/from the Static Switch
Driver Board 4542043-Z (See Table 7-6).
• X6 – Data/logic to/from Operator Logic Board 4550005-F (see circuit dia-
gram sheet 7).
• X7 – System control and monitoring signals to/from the Parallel Logic
Board 4520075-B. (See Table 7-1)
• X8 – Alarm outputs to optional external (remote) alarm display boards
(see relevant external alarm interface board in the Options section of this
manual).

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CHAPTER 3 - UPS Logic Board (4550007 H)

Table 7-3: Connector X1 (To Rectifier Logic Board)

PIN I/O Function

1-4 I 0V – ground reference for digital electronics

5-8 I +12V power supply derived from AC-DC Power Supply Board

9-12 I -12V power supply derived from AC-DC Power Supply Board

13-14 I/O Common – ground reference for analogue sense signals

15 O VREC_AC: Input mains voltage sense signal (phases U-W) –

through connection from HVI Board – (15Vp-p)

16 O VREC_BA: Input mains voltage sense signal (phases V-U) –

through connection from HVI Board – (15Vp-p)

17 O VREC_CB:Input mains voltage sense signal (phases W-V) –

through connection from HVI Board – (15V p-p)

18 O IB: Battery current sense signal – through connection from HVI

Board – battery current limit control

19 – Not used in standard modules

20 O IREC: Rectifier input current sense signal – through connection

from HVI Board – input current limit control

21-23 – Not used in standard modules

24 I IREC_T: Used in parallel systems only (not available)

25 O VB: DC Bus (battery) voltage feedback – through connection from

HVI Board (-3.225Vdc @446V DC Bus)

26 O T_BAT: Battery cabinet temperature sensor – through connection

from HVI Board (2.98V @ 25°C)

27 O IDC_1: Not used in standard model (12 pulse rectifier only)

28 O IDC_2: Not used in standard model (12 pulse rectifier only)

29 O DB: Used in parallel systems only (input current sharing)

30 O DB_0: Used in parallel systems only (input current sharing)

31 – Not used in standard modules

32 I OVLREC: Rectifier overload error status (Overload = 1)

33 I BLKREC: Rectifier OFF/ON status (OFF = 1, ON = 0)

34 I SEQREC: Input mains phase sequence error status (Error = 1)

35 I IN_LOW: Low input volts 20% error status (Error = 1)

36 O ON_REC: Rectifier Run(1)/Stop(0) command from UPSLB micro

37 O XRADD_1: Reduced current limit from UPSLB micro (On Gen = 1)

38 O REC_A: Charge mode selection from UPSLB micro

39 O REC_B: Charge mode selection from UPSLB micro

40 – Not used in standard modules

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CHAPTER 3 - UPS Logic Board (4550007 H)

Table 7-4: Connector X2 (To High Voltage Interface Board)

PIN I/O Function

1-4 – 0V – ground reference for digital electronics

5-8 O +12V supply to HVI Board

9-12 O -12V supply to HVI Board

13-14 – Common – ground reference for analogue sense signals

15-17 I VI-A, VI-B, VI-C: Bypass sense voltages for U-V-W phases respec-
tively. Approximately 1% of bypass L-N voltage

18-20 I VINV-A, VINV-B, VINV-C: Inverter sense voltages for U-V-W

phases. Approximately 1% of inverter L-N voltage (8Vp-p)

21-23 I VO-A, VO-B, VO-C: UPS output sense voltages for U-V-W phases
respectively. Approximately 1% of UPS output L-N voltage (8Vp-p)

24-26 I VREC-AC, VREC-BA, VREC-CB: Input mains sense voltages.

Approximately 1.3% of input L-L voltage –
e.g. approx. range 5V - 5.5V (15Vp-p) for 380-415V nominal input

27 I V-B: DC Bus (Battery) volts sense signal. Approximately 0.7% of

the DC Bus voltage (+3.225Vdc @446V DC Bus)

28-30 I IINV-A, IINV-A, IINV-C: Inverter current sense (150% phaseback)

31 I I-B: Battery current sense signal (Batt I limit and current display)

32-34 I IO-A, IO-B, IO-C: Output current – O/load alarm/timer/display

35 I IREC-1: Input current sense signal (dc)

36-42 – Not used in standard modules

43 I SW-REC: Rectifier Input Switch auxiliary contact status

44 I SW-IN: Static Bypass Switch auxiliary contact status

45 I SW-BYP: Maintenance Bypass Switch auxiliary contact status

46 I SW-OUT: Output Switch auxiliary contact status

47 – Not used in standard modules

48 I FUSINV: Inverter fuse monitor (not used in standard module)

49 I FUSREC: Rectifier fuse monitor (not used in standard module)

50 I FUSBAT: Battery fuse monitor

51 I TH: Inverter thermostat contact status

52 I ESD: Emergency shutdown

53 I SW-BAT: Battery isolator auxiliary contact status

54 O BATTRP: Battery isolator trip signal

55-56 – Not used in standard modules

57-60 I T1, T2, T3, T4: Temperature sensing monitoring signals

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CHAPTER 3 - UPS Logic Board (4550007 H)

Table 7-5: Connector X3 (Inverter Logic Board)

PIN I/O Function

1-4 I 0V power supply rail

5-8 I +12V power supply derived from DC-DC Power Supply Board

9 - 12 I -12V power supply derived from DC-DC Power Supply Board

13 – Common

14 – Common

15-17 O [VI-A>, [VI-B>, [VI-C>: Bypass volts sense signals

– through connection from HVI Board

18-20 O [VIN-A>, [VIN-B>, [VIN-C>: Inverter volts sense signals

– through connection from HVI Board

21-23 O [IINV_A>, [IINV_B>, [IINV_C>: Inverter current sense signals

– through connection from HVI Board

24 O [XINVOI>: Mains error – load transfer to inverter (H)

25 O [DREF>: Output voltage adjustment - used in parallel modules

26 O [DREF0>: Output voltage adjustment - used in parallel modules

27-30 O [DV-A>, [DV-B>, [DV-C>, [DV-0>: Load sharing signals used for par-
allel modules only

31 O [INV-L>: Transfer load to inverter command from processor system

32 I [OVL-INV>: Inverter overload status to processor system (OVL = L)

33 I [BLK-INV>: Inverter On/Off status to processor system (Off = H)

34 I [BACK>: Inv. frequency back to processor system from Inverter

Logic Board

35 O [SYNC>: Produced by processor system to Inverter Logic Board

36 O [ON-INV>: Inverter On/Off control from processor system (Off = L)

37 O [INV-F>: from processor system (Inv Freq)

38-39 O [INV_A>, [INV_B>: from processor system - used in output volts

selection

40 I Inverter thermostat status signals (optional)

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CHAPTER 3 - UPS Logic Board (4550007 H)

Table 7-6: Connector X5 (Static Switch Driver Board)

PIN I/O Function

1-4 O 0V power supply rail

5-8 O +12V power supply rail

9 - 12 O -12V power supply rail

13 I XSTAI1: Not used in standard module. Details required as to what

is connected to SSDB connector X7

14 I XSTAI2: Output contactor (inverter output) auxiliary contact status

– low = contactor closed

15-16 O INV-L: Transfer load to inverter command from processor system

17-18 O MNS-L: Transfer load to bypass command from processor system

19 – XSTAD1: Not used in standard module.

20 – XSTAD2: Not used in standard module.

Table 7-1: Connector X7 (See Table 8-2)

PIN I/O Function

1-4 – 0V – ground reference for digital electronics

5-8 O +12V supply to HVI Board

9-10 O -12V supply to HVI Board

11-13 – VO-A, VO-B, VO-C: UPS output sense voltages for U-V-W phases
respectively. Approximately 1% of UPS output L-N voltage (8Vp-p)

14 I Common – ground reference for analogue sense signals

VI-A, VI-B, VI-C: Bypass sense voltages for U-V-W phases respec-
tively. Approximately 1% of bypass L-N voltage

15-17 I IO-A, IO-B, IO-C: Output current – O/load alarm/timer/display

18 I I_B_P:

19 COMM_P:

20-22 DV-A, DV-B, DV-C:

23 DV-0:

24 IREC-T:

25 DB:

26 DB-0:

27-28 0V – ground reference

29-30 +5V – Supply to

31 PAOU10:

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CHAPTER 3 - UPS Logic Board (4550007 H)

Table 7-1: Connector X7 (See Table 8-2)

PIN I/O Function

32 INV_DIS:

33 SW-OUT:

34 SWBYP:

35 I_BST_BAT:

36 I_TST_BAT:

37 MNS_DIS:

38 BLK_SEL:

39 OFF_INV:

40 C_L_INV:

41 RES_EXT:

42 V-AUX:

43 O_BLK_SW:

44 O_MNS_L_SS:

45 O_MNS_D_SS:

46 TST_BAT:

47 BST_BAT:

48 MNS_SYN_KO:

49 O_MNS_DIS:

50 SYN_INV_OK:

51 PAR_REC:

52 INV-L:

53 FRQ_SYN:

54 FRQ_PAR:

55 FRQ_MNS:

56 BACK:

57 INV_OK:

58 CON_SEL:

59 I_SW_BYP:

60 XSTAIZ:

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 3.2.3

7-20
ON
ON OFF
On Bypass
OFF
Bypass SCR control Inverter Run
ON
Block Diagram

On Inverter D23
OFF
Reset Inverter contactor
20MHz Rectifier Run
Power control ON
Clock
X28 OFF

S5
Reset
SECTION 7 - UPS System Control

S1
Bypass On/Off
S2 D22
Inverter On/Off
S3
Rectifier On/Off
CHAPTER 3 - UPS Logic Board (4550007 H)

Address X
X1 Rectifier
P0 Logic Bd

Output H.V.I Board

l
RAM EPROM CS X2
tro
Buffer
C on
Output CAN P3
Display Interface Da
ta X3 Inverter
P4 Input Logic Bd
Buffer
P2 SBS Board
X5
Data X

P1 Parallel
X7
MUX Logic
Figure 7-4: UPS Logic Board basic block diagram

A/D D43
Analogue Signal
Converters D48 Analogue X8 Alarm
P5 D49 Buffering Board
7200 Series UPS Service Manual

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7200 Series UPS Service Manual SECTION 7 - UPS System Control
CHAPTER 3 - UPS Logic Board (4550007 H)

[Link] System overview

Processor system
The UPS Logic Board control system is based on a type 80C166 microcontroller,
as shown in Figure 7-4. This device contains six ports through which it commu-
nicates with peripheral circuits/devices, together with several ‘system control
lines’. It also contains an internal A/D converter, four programmable timers and
internal ROM & RAM.
The ports are configured by an initialisation routine performed by the system soft-
ware on power-up and can be summarised as follows.
• Port 0
This port is configured as a 16-bit bi-directional data bus <D0...D15>
• Port 1
This port is configured as the first 16-bits of an 18-bit address bus
<A0...A15> the other two address lines are provided by port 4.
• Port 2
The lower half of this port <P2-0...P2-7> carries various synchronising/tim-
ing signals and the upper half <P2-8...P2-15> comprises the CAN data bus,
which carries the data to/from the Operator Logic Board
• Port 3
This 16-bit port is configured as a mixture of inputs and outputs generally
concerned with controlling the CAN Bus data exchange.
• Port 4
The lower two lines only are utilised on port 4. These form the upper two
address lines <A16...A17> the lower address lines <A0...A15> are provided
by port 1.
• Port 5
The lower ten lines of this port <P5-0...P5-9> are configured to act as inputs
to the internal A/D converter.
• System control lines
In addition to the I/O ports the microcontroller also has the general control
I/O lines normally associated with a microprocessor-based system; such as
a system clock, reset, and Read/Write control.

Memory
The microcontroller uses both internal and external memory. 2 X 126k of battery-
backed RAM and 2 X 516k of EPROM are fitted to the board as standard which
holds the system operating software. Facilities are included on the board to allow
alternative memory configurations to be used as described later.

Data buffers
The 16-bit data bus is connected to various control circuit boards via input and
output data buffers, as shown in Figure 7-4, which are controlled by individual
‘chip select’ enable lines to direct the data flow to/from the appropriate source, as
required by the system control software.

Analogue signal processing

The microcontroller monitors various analogue signals which are connected to
the UPS Logic Board from the peripheral boards. These signals are processed by
suitable analogue circuitry, buffered where necessary, and applied to the micro-
controller’s A/D inputs via a series of multiplexer devices.

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CHAPTER 3 - UPS Logic Board (4550007 H)

Primary output control signals

Although the micro-controller produces numerous control logic signals, its pri-
mary outputs can be considered to be:
• Inverter Start/Stop
Signal to the Inverter Logic Board which determines whether or not the
inverter section is ‘enabled’ or ‘inhibited’.
• Rectifier Start/Stop
Signal to the Rectifier Logic Board which determines whether or not the
rectifier section is ‘enabled’ or ‘inhibited’.
• Load on inverter
Signal which controls the ‘inverter-side’ contactor (K1) and connects the
inverter output to the load.
• Load on bypass
Signal which controls the static switch and connects the load to the static
bypass supply.
Note: the ‘load on inverter’ and ‘load on bypass’ signals are interlocked
such that they cannot be activated simultaneously.

As shown on the block diagram, these signals are produced by a dedicated logic
block which is controlled by the data bus together with individual switches which
allow each of the above functions to be manually overridden.

Operator Interface
The microcontroller is connected to the Operator Logic Board via the CAN Bus,
which is a bi-directional serial communications link that enables the operator to
program several operational parameters into the micro-controller and also enables
various alarms and indications to be displayed on the Operator Control Panel.

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3.3 Detailed circuit description

3.3.1 Introduction
The UPS Logic Board circuit diagram (SE-4540007-H) comprises 7 sheets. With
reference to the block diagram description (See Figure 7-4), the drawings can
broadly be described as follows:
• Sheet 1 contains a ‘signal map’ identifying the functions covered on the
remaining pages. It also contains a summary chart detailing the various
configuration jumpers.
• Sheet 2 contains the
– basic microcontroller system
– data bus, address bus and control line buffers
– Ni-Cad battery back-up controller
– reset generator
• Sheet 3 contains the
– system RAM and ROM memory and its associated configuration links
– Inverter/Rectifier Start/Stop control logic
– load transfer control logic
– CAN bus communications drivers and control logic
– Real-time clock (RTC)
• Sheet 4 contains the
– data bus input buffers
– data bus output buffers
– on-board 7-segment indication circuit
• Sheet 5 contains analogue signal processing circuits for the
– input voltage sense signals
– inverter voltage sense signals
– DC (battery) bus voltage sense signal
– Battery current sense signal
it also contains reference voltage generators; power supply monitors; and
inverter overvoltage and input overvoltage fault detection circuits.
• Sheet 6 contains analogue signal processing circuits for the
– output voltage sense signals
– output current sense signals
it also contains the analogue signal multiplexers (for the A/D inputs), out-
put overvoltage and overcurrent fault detection circuits.
• Sheet 7 contains the
– input/output signal identifications details
– serial communications (RS485) driver and port
Note: On the diagrams, a ‘negative’ symbol at the end of a signal’s annotation in-
dicates that the signal is ‘active low’ – e.g. [RD> = [RD->.
As with all micro-based system, the microcontroller’s operation is determined by
the program held in the system’s memory: and as this is hidden to the service en-
gineer there is very little that can be done to ascertain that the board is working
correctly apart from checking the validity of its input and output signals, and other
signals generated on the board which are required by the central processor system.
The following description deals with the board on this basis, and should provide
sufficient information to determine whether or not the board is functioning cor-
rectly when it comes to troubleshooting. A full software description is beyond the
scope of this manual.

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3.3.2 Basic microcontroller system

(circuit diagram sheet 2)

Figure 7-5: Micro system control signals

Power Supply

20 READY 96 Ready
Clock XTAL1
CLKOUT 97 Clock out
Reset 27

Control Bus
RSTIN 25 Address latch enable
ALE
Power 29 BHE 92 Bus high enable
Fail NMI
RSTOUT 96 Reset out
Vref (+5V) 54
VAREF RD 26 Read

WR 95 Write
D42

Caution When monitoring the signals described in this section it is best done with control
power only – i.e. with the UPS power sections shut down and the circuit boards
live via the control power supply. The signals entering the left of the above dia-
gram are constant and can be monitored with a meter/oscilloscope; those shown
on the right of the diagram are not constant and best monitored with a logic probe.
The logic sequence/timing of these signals depend upon various circuit conditions
and cannot therefore be accurately defined; however, for field test purposes, the
presence of a ‘variable switching’ logic signal at these points would generally in-
dicate that the basic processor control bus is serviceable and the system software
is running.

Power supply
The microcontroller is powered from the general +5V rail which is provided by a
three-terminal 5V regulator (N1) shown on diagram sheet 7.

System clock (XTAL1)

A dedicated crystal-controlled clock generator (E2) provides a system clock
signal which is connected to the microcontroller (D12) pin 20. This signal is a
20MHz squarewave switching between +5V and 0V.

System reset (RSTIN)

On power-up, a 1 second logic low reset pulse, [RSTIN->, is applied to D42 pin 27
from the ‘reset generator’ circuit. This can also be manually applied for trouble-
shooting purposes by temporarily bridging jumper X28 (See paragraph 3.3.5).
The [RSTIN-> pulse forces the processor to restart its operation from the beginning
of its operating program which forces it to run through its initialisation routine.

Non-Maskable Interrupt (NMI)

When the input to D42 pin 29 (NMI) goes low it instructs the system software to
interrupt its present operation and execute a power-down routine to save critical
data.
The source of this input is determined by X17 which is normally ‘made’ 2-3 and
selects the power failure detection circuit output [PFO> as the controlling signal –
this circuit is shown on diagram sheet 5 (See paragraph [Link]).

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Reference voltage (VAREF)

The input to D42 pin 54 (VAREF) is a +5V reference voltage used by the internal
A/D converters to compute the digital values for all analogue signals – e.g volts/
current/VA etc. An adjustable reference voltage generator (N45 pin 8) (See par-
agraph [Link]), shown on diagram sheet 5, provides this input ([VREF>) via X20
which is normally ‘made’ 1-2.

Clock out (CLKOUT)

This output is a 20MHz squarewave synchronised to the processor clock input and
is used by the RAM/ROM memory address decoding logic D33 (See paragraph
3.3.6) shown on the diagram sheet 3. This is to ensure that when the processor
wishes to read from/write to memory the memory access is synchronised to the
internal microprocessor action – i.e. it ensures that the accessed memory address
is relevant to the current processor’s requirements.

Address latch enable (ALE)

This output goes high to enable the address bus to be latched into the RAM/ROM
memory address decoding logic D33 shown on the diagram sheet 3 – (See para-
graph 3.3.6).

Bus high enable (BHE)

The logic state of this output indicates whether the processor is internally enabling
its ‘high’ or ‘low’ byte data bus – i.e. it indicates if the micro wishes to read from
(or write to) the lower byte (D0....D7) or the higher byte (D8....D15). [BHE-> is
low when the high byte is being accessed, and vice versa, and is used by the RAM/
ROM memory address decoding logic shown on the diagram sheet 3 – (See par-
agraph 3.3.6).

Reset out (RSTOUT)

[RSTO-> is controlled by the reset input signal, [RSTIN->, and goes high while the
input rest signal is applied. This signal is synchronised to the system clock and
returns high an integral number of clock pulses after the input reset signal is re-
moved. The [RSTO-> signal is used by the RAM/ROM memory address decoding
logic shown on the diagram sheet 3 (See paragraph 3.3.6); and a buffered version,
[RSTOX->, is connected to the data bus output buffers as shown on diagram sheet
4 via jumper X25 (2-3) – (See paragraph 3.3.12).

Ready (Ready)
This input, when low, inserts wait states in the processor’s operation; thus slowing
it down. It is driven by the RAM/ROM memory address decoding logic shown on
the diagram sheet 3 – (See paragraph 3.3.6) – and holds off the processor’s oper-
ation until the appropriate address latching has taken place, thus effectively ex-
tending the read/write times when slower memory elements are being used.

Read (RD)
This output goes low when the processor wishes to read the data from the device
or memory location currently addressed by the address bus.

Write (WR)
This output goes low when the processor wishes to write data to the device or
memory location currently addressed by the address bus.

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3.3.3 Data bus, address bus and control bus buffers

(circuit diagram sheet 2).

Data bus buffer

Two type ACT245 octal bus transceivers (D32 & D36) are employed as bi-direc-
tional protection buffers between the microcontroller (D0....D15) and the data bus
(DX0....DX15). D32 buffers the ‘low’ byte (D0....D7) and D36 the ‘high’ byte;
however both are controlled by a common data direction signal – i.e. the micro-
controller’s [RD-> output – therefore the data direction of all 16 data bus lines are
controlled by a single signal.
These devices are described in appendix A (See paragraph A.1).
When the microcontroller drives its [RD-> output low it sets the data direction
through the buffers from B-to-A, which allows the data bus contents through to
the microcontroller’s data inputs. At other times, when [RD-> is high, data flows
through the buffers from A-to-B, allowing the micro to place data onto the data
bus, which can then be written to a peripheral circuit as required.

Address bus buffer

The address bus is also buffered by two ACT245 devices (D38 & D41) but, unlike
the data bus described above, in this case the data direction is fixed by connecting
pin 1 of each device to a permanent +5V supply. Thus the address bus data always
flows through the devices in the A-to-B direction and used to select a memory lo-
cation – the buffered address bus is annotated (AX0....AX17).
Note: AX16 & AX17 are buffered by the control bus buffer described below.

Control bus buffer

The control bus signals [RD->, [WR->, [BHE->, [RSTO-> are all buffered by D47.
This device is configured with fixed data direction A-to-B, in the same manner as
the address bus buffer described above, by the application of a fixed +5V supply
at D47 pin 1. The buffered control signals [RDX->, [WRX->, [BHEX->, [RSTOX-> are
used by various circuits distributed throughout the circuit diagrams.
In all cases the above mentioned buffers have pull-up resistors connected to their
input and output pins – e.g. resistor packs R307, R309 etc.

3.3.4 Ni-Cad Battery back-up controller

(circuit diagram sheet 2).
A 3.6V 280mAh Ni-Cad battery is fitted to the UPS Logic Board to back-up the
RAM contents and maintain the RTC time-keeping operation when the UPS is
turned OFF; when fully charged the battery offers a back-up period of up to 4 to
5 months.
The charger circuit is activated by the [OUTBAT> signal which is produced by the
processor via D25 pin 19 (diagram sheet 4). When [OUTBAT> goes high it turns
on V152 which then turns on V151 to supply the battery charge current via led
H8, R32 and V73. The charge voltage is limited to 4.7V by zener V14.
Note: the battery can be disabled for shipping/storage by opening jumper X31.
The battery is connected to the RAM memory devices and Real Time Clock
device – shown on diagram sheet 3 – via V32 and the battery supply annotated
[VRAM>. Thus, if the board’s power supply is turned off (i.e. UPS fully powered
down) the programmable parameters held in RAM (e.g. kVA, working voltage

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and frequency, battery charging parameters and display language) are main-
tained; and the real-time clock keeps running. It is not therefore necessary to re-
program these parameters following every start-up.
Note: Jumper X31 must be made in order to enable this function.
The [VBATT> output is not connected to other parts of the circuit, but it is moni-
tored by the microcontroller’s analogue input [AN9> via D44, which is a quad an-
alogue switch. [VBATT> is switched through D44 pin 2, by [FL-12> when it goes
high; this is controlled by a ±12V supply rail monitor circuit (diagram sheet 5)
which inhibits the [VBATT> sense signal if the ±12V power rails are invalid, thus
preventing an erroneous battery voltage fault being detected by the micro under
these conditions.
Note: the other three gates within D44 are not used and their inputs are tied to 0V.

[OUTBAT> signal details

The micro-controller monitors the NiCad battery voltage (3.6V nom) via AN9
and its internal A/D converter (as described above) and turns on the Ni-Cad
charger, by driving the [OUTBAT> signal high, if the Ni-Cad voltage falls below
2.8V. When the charger is active, the [INTERNAL BATTERY LOW] message is
displayed on the Operator Control Panel (alarm #76) and led H8 illuminates.
Once the battery is recharged to 3.6V the charger is turned off by the [OUTBAT>
signal returning low and the alarm message is cancelled. Thus the Ni-Cad battery
is charged only when necessary and is not permanently trickle-charged.
Note: the NiCad charger may be active for several hours when the UPS is first
commissioned (depending on the initial battery charge state) – jumper X31 must
be fitted to ‘enable’ the battery back-up facility.

3.3.5 Reset generator

(circuit diagram sheet 2).
A purpose-designed Supply Voltage Supervisor (N24) provides the micro with a
1 second sec logic low [RSTIN-> reset signal on power-up. This signal, which is
applied to the micro pin 27, can also be initiated manually by temporarily making
jumper X28 (1-2). The [RSTIN> signal also resets the RAM chip select signals pro-
duced by D19a/d (shown on circuit diagram sheet 3) and points the micro to its
initialisation routines.

Caution Using X28 to activate the reset circuit during normal UPS operation will crash the
unit, because the ‘run’ signals to the rectifier, inverter and static switch will be dis-
abled for the 1 second reset period.

On power-up (reset) the micro-controller receives initialisation data from D20

which is an EEPROM used to store the Emerson/Liebert/SICE software passport
identification. Amongst other things this configures the micro’s programmable
ports P0-P5 to the parameters required to operate in this application. Without this
security interlock the micro-controller will be inactive. An inverse output, [V-
AUX>, goes high on reset and is connected to D22 and D23 in the ‘Inverter/Recti-
fier Start/Stop control logic’ and ‘Load transfer control logic’ (circuit diagram
sheet 3). This resets the logic latches (Emergency Stop, DC Overvolts, etc.) and
re-applies the ‘run’ signals to the rectifier, inverter and static switch.
Note: the reset time is determined by R157/C97, and begins when the +5V supply
rail reaches 3.6V on initial power-up.

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3.3.6 System RAM and ROM memory addressing

(circuit diagram sheet 3).
The system memory comprises 2 x 512k EPROMs (D35 & D46) and 2 x 128k
RAM chips (D28 & D40). All these devices have an 8-bit data bus output; how-
ever, the EPROMs have a 16-bit address input while the RAM chips have a 17-
bit address facility.

Random Access memory (RAM)

This is the read/write memory store; sometimes referred to as the temporary
store. Any data fed in from the peripheral devices or produced during the execu-
tion of the main program will be temporarily held in RAM – e.g. UPS setup pa-
rameters such as kVA, nominal voltages/frequency, serial number, passwords,
etc. This is a ‘volatile’ location, meaning that when power is lost to the component
all data is also lost; thus the need for the on-board back-up Ni-Cad battery.

Read Only Memory (ROM)

This memory contains the ‘operating system program’, or firmware, which is ba-
sically a sequence of instructions to be carried out by the micro-controller in order
to make it perform the actions required of it. Upon power-up the micro is pointed
to the first instruction as part of its reset initialisation, and from then on it steps
through the programmed instructions in a sequence dictated by various events and
monitored conditions.
ROM is ‘non-volatile’, which means that it does not lose its memory contents in
the event of a loss of power.

Address decoding – D33 / D19

The ‘output enable’ pins of all four memory devices are controlled by the control
bus [RD-> line, therefore when this line goes low the processor can read the data
held at the current address from any of the devices. The purpose of the ‘address
decoding’ circuit is to enable the microcontroller to select which of the EPROM
or RAM devices it wishes to communicate with at any given time. The memory
devices’ ‘chip select’ inputs are controlled by a circuit comprising an ASIC i.c.
(D33) and two gates of D19.
D33’s inputs are connected to A0, A14....A17, and several control bus signals –
as described in paragraph 3.3.2. – which are all controlled by the microcontroller.
The output signals, [CSEP1L->, [CSEP1H->, [CSRA1L->, and [CSRA1H->, adopt logic
states determined directly by these processor-controlled inputs and are synchro-
nised to the processor operation by the 20MHz [CLKOUT> signal.
When low, [CSEP1L-> and [CSEP1H-> enable the EPROM devices via their ‘chip
enable’ inputs (pin 20), while [CSRA1L-> and [CSRA1H-> perform a similar func-
tion on the RAM chips.
The [READY> output from D33 is fed back to the micro to inform it that the appro-
priate addresses have been loaded into D33’s internal latches (See paragraph
3.3.2).
As D19 provides the ‘chip select’ inputs to the RAM devices it is powered from
the battery-backed RAM supply to prevent RAM data corruption on UPS power
down.
Note: jumper X14 provides a test facility for bench testing only and all links
should be open during normal operation.

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AX15 & AX16 configuration links

The UPS Logic Board has been designed to facilitate future software upgrades by
including configuration links to permit the addressing of alternative memory de-
vices. These links affect the routing of the AX15 and AX16 address lines, and the
standard configuration is shown below in Figure 7-6.
In the standard configuration the signals annotated [PIN29EP> and [PIN3EP> are
connected to the EPROMs’ A14 and A15 inputs and are therefore driven by the
AX15 and AX16 address lines respectively. The [PIN31RAM> signal (AX16) is
connected to the A15 input of both RAM devices and the [PIN3RAM> signal
(AX15) is connected to the RAM ‘write enable’ inputs.

Figure 7-6: AX15 & AX16 decoding configuration links

X19 X13
1 1
2 2
[PIN31RAM>
3 3

[AX16>
X22 X21
1 1
2 2
[PIN3EP> [PIN3RAM>
3 3

X23 X24
5 5
4 4
3 3
[AX15>
2 2
[PIN29EP> [PIN29RAM>
1 1
[WRX–>

3.3.7 Basic system control logic (D88)

The term ‘Basic System Control Logic’ is used here to described the signals gen-
erated by the UPS Logic Board which control the rectifier and inverter ‘start/stop’
commands; battery circuit breaker ‘trip’, and the ‘load transfer’ control between
inverter and static bypass.
These functions are controlled by a single ASIC device annotated D88 which is
shown on sheet 3 of the diagram and also in greater detail in Figure 7-7. D88 also
provides the processor system with various status signals, as illustrated in the
block diagram.
The following description begins by identifying D88’s input logic signals, and
continues by explaining their influences on the individual output control signals.

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Figure 7-7: Basic system control logic (internal detail)

X2-52
ESD_I 09 D88
29 M_ESD
D26-5

R97 SCR_OPN 28
N15-8

R86
N15-14
32 M_SCR_OP
D26-4
Z39
0V BAT_MA 08
D34-12
20 M_BAT_MA
D26-6

R112

R111

R113
26 BAT_MA_D
27 SCR_OP_D
24 ESD_D

MRESET 43

C64
C63

652
V-AUX 44 39
N24-6
16 0V
D21-2 ALM_RES
RES_EXT
X7=41

25 BLK_MNS
SEQ_MNS 13 D26-3
D26-7
BLK_BYP_M 01
MNS_KO 11
D55-9

D21-16 IBOPEN 12
34 BAT_TRP X2-54

BLK_INV_M 02
33 ON_INV
X3-36

INV_ON 17
D21-5
OFF_INV 05
X7-39
C_L_INV 06
X7-40
L_INV 14 36 INV_L
D21-9 D51-8

INV_DIS 07
X7-32
SYN_KO 18
D54-6

B-INV 31 38 MNS_L
D1-4 D51-6
L_MAINS 41
D21-12

37 ON_REC X1-36
BLK_REC_M 04
REC_ON 40
D21-15

R320
Block
Q3 Rectifier

R320
Block
Inverter
Q2

R320 Block
Bypass
Q1

R320 Manual
S1 RESET

+5V 0V

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[Link] D88 Status signals to processor system

Emergency shutdown [M_ESD>

The ‘emergency shutdown’ signal [ESD_I> to D88-9 is driven by external circuitry
and connected via X2-52 (sheet 7) as a logic high when the emergency shutdown
is applied.
This drives pin 29 ([M_ESD>) high which is connected to the processor system via
D26-5 where it initiates alarm #63 [CUT-OFF: EMERGENCY] (See paragraph
[Link]) and also provides a latching input back to D88 pin 24 ([ESD_D>) which
holds pin 29 in its high state until the reset circuit is activated – the latching signal
is debounced by R112/C63.
The high [ESD_D> input to D88 pin 24:
• turns off the ‘bypass enable’ signal ( [BLK_MNS> = 0) D88 pin 25.
• trips the battery circuit breaker ([BAT_TRP> = 0) D88-34
• turns OFF (stops) the rectifier ([ON_INV> = 0) D88-33
• turns OFF (stops) the inverter ([ON_REC> = 0) D88-37

Static switch SCR open [M_SCR_OP>

The ‘static switch SCR open’ signal [SCR_OPN> to D88-28 is produced by N15-
8 or N5-14 (sheet 6) as a logic high when the detection circuits ‘sees’ a voltage
drop across one of the static bypass SCRs.
This drives pin 32 ([M_SCR_OP>) high (provided the ‘load on mains’ ([MNS_L>)
output to D88-38 is also high) which is connected to the processor system via
D26-4 where it annunciates alarm #15 [BYP: SCR FAILURE] (See paragraph
[Link]) and also provides a latching input back to D88 pin 27 ([SCR_OP_D>)
which holds pin 32 in its high state until the reset circuit is activated – the latching
signal is debounced by R111/C62.
In addition to latching the output on pin 32, the logic high [SCR_OP_D> input also
blocks the static switch by forcing high the [BLK_MNS> output at D88-25 (see de-
tails of [BLK_MNS> below).

DC Overvoltage – fast
The ‘DC Fast Overvoltage’ signal ([BAT_MA>) to D88-8 is produced by N13-8
(sheet 5) and is logic high when a DC busbar (battery) overvoltage condition
(>620V) is present.
This drives pin 20 ([M_BAT_MA>) high which is connected to the processor system
via U26-6 where it initiates alarm #58 [DC BUS: FAST OVERVOL.] (See para-
graph [Link]) and also provides a latching input back to D88 pin 26
([BAT_MA_D>) which holds pin 20 in its high state until the reset circuit is activat-
ed – the latching signal is debounced by R113/C64.
The logic high latching signal to pin 20 ([M_BAT_MA>) also:
• trips the battery circuit breaker ([BAT_TRP> = 0) D88-34
• turns OFF (stops) the rectifier ([ON_INV> = 0) D88-33
• turns OFF (stops) the inverter ([ON_REC> = 0) D88-37

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[Link] D88 Reset circuit [RES_EXT>

There are three sources of reset signal applied to D88:
• D88-16 receives a logic high reset signal from the microcontroller via the
data bus output buffer D21-2 (See paragraph [Link]). This is a software
reset programmable via the Operator Control Board
• D88-44 receives a logic high reset pulse when the board is powered up
(See paragraph 3.3.5)
• D88-43 is driven high when the manual reset button (S1) is pressed

Common functions
In each case, a logic high activation on any of the above inputs:
• resets the ‘Emergency shutdown’, ‘Bypass SCR open’ and ‘DC overvolt-
age’ latches described above.
• provides a [RES_EXT> reset signal at D88-39 which is applied via X7-41 to
the Parallel Logic Board in a ‘1+1’ configured system.

[V_AUX> signal functions

In addition to the common functions described above the [V_AUX> signal also:
• applies a reset signal directly to the Parallel Logic Board – via X7-42.
• resets (turns off) the static bypass – ([BLK_MNS> = 1) D88-25.
• resets (opens) the battery circuit breaker– ( [BAT_TRP> = 0) D88-34.
• resets (turns off) the inverter – ([ON_INV> = 0) D88-33.
• resets (turns off) the rectifier – ([ON_REC> = 0) D88-37.

The [V_AUX> ‘power-up’ reset signal to D88-44 also resets the [BLK_MNS> output
from D88-25, described immediately above.

[Link] Major control signal outputs

Static bypass inhibit [BLK_MNS>

The [BLK_MNS> output from D88 pin 25 goes high when D88 detects any condi-
tion which requires the load to be prevented from being connected to the static
bypass supply. This output is fed to the microcontroller via the data bus buffer
U26-3 where it initiates alarm #16 [BYP:HARDWARE BLOCK.] (See paragraph
[Link]) and is also connected to the ‘load-on-bypass’ control logic within D88
where it inhibits the ‘load-on-bypass’ command [MNS_L> output from D88 pin 38.
The [BLK_MNS> signal can be driven high, disabling the static bypass, by any one
of the following conditions:
• ‘Emergency shutdown’ latch set – ([ESD_D> = 1) D88-24 (see above).
• ‘Bypass SCR open’ latch set – ([M_SCR_OP> = 1) D88-27 (see above).
• 1 second Power-up reset pulse ([V_AUX> =1) D88-44 (see above).
• Static bypass mains phase sequence error ([SEQ_MNS> = 1) D88-13. This
is derived from D27a on diagram sheet 5 (see paragraph [Link] on page
7-56).
• ‘Manual block’ applied from switch Q1 – ([BLK_MNS_M>) = 1) D88-1.
• ‘Mains error’ signal – ([MNS_KO>) = 1) D88-11. This is produced by the
processor system under software control and applied via data bus buffer
D55 (see paragraph [Link] on page 7-50).

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Battery circuit breaker trip [BAT_TRP>

A logic low [BAT_TRP> output from D88-34 trips the battery circuit breaker via
X2-54 (sheet 7), which is connected to the High Voltage Interface Board (See sec-
tion 7 paragraph 2.3.8).
The [BAT_TRP> signal can be driven low by any one of the following inputs:
• ‘DC Fast Overvoltage’ latch set ([BAT_MA_D> = 1) D88-26 (see above).
• ‘Emergency shutdown’ latch set – ([ESD_D> = 1) D88-24 (see above).
• 1 second Power-up reset pulse ([V_AUX> =1) D88-44 (see above).
• ‘Software trip’ – ([IBOPEN> = 1) D88-12. This is produced by the processor
system under software control and applied via data bus buffer D21-16 (See
paragraph [Link]).
Note: This signal trips the battery breaker on low DC voltage as follows:
– UPS on greater than 15% load = 330V
– UPS on less than 15% load = 360V
The low voltage trip level is programmable via the Operator Control Panel
SET-UP screen, and is adjustable between 1.6V/cell and 1.69V/cell; how-
ever the 30V window between the <>15% levels is not adjustable.

Inverter Start/Stop (On/Off)

The [ON-INV> output from D88-33 is connected to the Inverter Logic Board via
X3-36 (sheet 7) where it controls the inverter ‘Start/Stop’ status (see paragraph
2.3.8 on page 5-51). A logic low [ON-INV> signal commands the inverter to
‘STOP’ and can be effected by any one of the following D88 inputs (conversely,
all the following inputs must be in their ‘healthy’ low state in order for the inverter
to run):
• ‘DC Fast Overvoltage’ latch set ([BAT_MA_D> = 1) D88-26 (see above).
• ‘Emergency shutdown’ latch set – ([ESD_D> = 1) D88-24 (see above).
• 1 second Power-up reset pulse ([V_AUX> =1) D88-44 (see above).
• ‘Software control’ – ([INV-ON> = 0) D88-17. This is produced by the proc-
essor system under software control and applied via data bus buffer D21-6
(See paragraph [Link]). This signal is ‘low’ to inhibit the inverter and
‘high’ to enable it. When this signal is actively blocking the inverter (i.e.
low) it initiates alarm #30 [INV:SOFTWARE BLOCK.].
• ‘Manual inverter block’ – ([BLK_INV_M> = 1) D88-2 – logic high from the
manual inverter inhibit switch Q2.
If the [ON-INV> signal at D88 pin 33 is active (low), blocking the inverter,
alarm #32 [INV: HARDWARE BLOCK] will be active. Note that alarm #32
will be disabled if alarm #31 is active. Alarm #31 can be interpreted that
the inverter has been selected off, while alarm #32 suggests that the
inverter has been turned off for some other reason.
• Parallel Logic ‘Inverter OFF’ request – ([OFF_INV> = 1) D88-5. This input
allows the Parallel Logic Board to enable/inhibit the inverter in a ‘1+1’
configured system (see paragraph 2.3.1 on page 8-12). [OFF_INV> is high
to inhibit the inverter and vice-versa.

Rectifier Start/Stop (ON/OFF) [ON_REC>

The [ON_REC> output from D88-37 is connected to the Rectifier Logic Board via
X1-36 (sheet 7) where it controls the rectifier ‘Start/Stop’ status (see paragraph
2.3.6 on page 4-35). A logic low [ON_REC> signal turns OFF the rectifier and can
be effected by any one of the following D88 inputs:
• ‘DC Fast Overvoltage’ latch set ([BAT_MA_D> = 1) D88-26 (see above).

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• ‘Emergency shutdown’ latch set – ([ESD_D> = 1) D88-24 (see above).

• 1 second Power-up reset pulse ([V_AUX> =1) D88-44 (see above).
• ‘Software control’ – ([REC-ON> = 0) D88-40 – [REC-ON>. This is produced
by the processor system under software control and applied via the data
bus output buffer D21-15 (See paragraph [Link]). [REC-ON> is ‘low’ to
inhibit the rectifier and ‘high’ to enable it. When this signal is actively
blocking the rectifier (i.e. low) it initiates alarm #20 [RECT:SOFTWARE
BLOCK].
• ‘Manual rectifier block’ – ([BLK_REC_M> = 1) D88-4. This input is
obtained from the manual rectifier inhibit switch Q3.
If the [ON-REC> signal at D88 pin 37 is active (low), blocking the rectifier,
alarm #22 [RECT:HARDWARE BLOCK] will be active. Note that this will
be disabled if alarm #21 is active. Alarm #21 can be interpreted that the
rectifier has been selected off via the Operator Control Panel, while alarm
#22 suggests that the rectifier has been turned off for some other reason

[Link] Load transfer control

The transfer control logic within D88 is interlocked such that the ‘load on invert-
er’ [INV_L> and ‘load-on-bypass’ [MNS_L> commands are mutually exclusive.

‘Load on inverter’ command [INV_L>:

The Load on inverter’ command ([INV_L>) output from D88-36 goes high to trans-
fer the load to the inverter; and is connected to the Static Switch Driver Board via
X5-15 (sheet 7), where it turns OFF the static switch (disconnecting the load from
the bypass supply) and energises the ‘inverter-side’ contactor (K1) driver circuit.
It is also connected to the Inverter Logic Board, via X3-31, where it triggers the
latches within D11 which makes the inverter voltage track the bypass supply volt-
age for 100ms (See section 5 paragraph 2.3.3). This is done to provide a smooth
transfer from bypass to inverter and reduce the wear on the ‘inverter-side’ contac-
tor (K1).
In order for D88 pin 36 ([INV_L>) to go high, all of the following conditions must
be satisfied:
• ‘Inverter Logic Board OK’ – ([B-INV> = 0) D88-31. This input is driven by
the fault detection circuit on the Inverter Logic Board and applies a 1 sec-
ond logic high hold-off command to X3-33 ([BLKINV> diagram sheet 7)
when any of its internal faults are active (e.g. Vsat) (see paragraph 2.3.7
on page 5-50). This is connected to D88-31 in the form of [B-INV>, and
must therefore be logic low, indicating “no fault” in order to permit the
load to be connected to the inverter.
• ‘Software request’ – ([L_INV> = 1) D88-14. This is produced by the proces-
sor system and applied via the data bus output buffer D21-9 when all its
software-monitored parameters have been verified (e.g. Inverter voltage
OK, Sync OK etc.)(See paragraph [Link]).
• Parallel Logic ‘Inverter on inverter’ request – ([C_L_INV> =0) D88-6. This
input is generated by the Parallel Logic Board in a ‘1+1’ configured sys-
tem and goes low when the parallel system control conditions request con-
necting the load on inverter. In a single-module application this input,
which is applied via X7-40, is tied to logic low and has no affect.

‘Load on bypass’ command [MNS_L>:

The ‘load on bypass’ command output from D88-38 goes high to transfer the load
to the bypass; and is connected to the Static Switch Driver Board via X5-17 (sheet

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7), where it turns on the static switch driver circuit, connecting the load to the
bypass supply. It is also connected internally (within D88) to disable the ‘bypass
SCR open’ annunciation circuit when ‘load on bypass’ is not being commanded
– i.e. the ‘Open Circuit SCR’ fault is discounted while the load is ‘on-inverter’.
In order for D88 pin 38 ([MNS_L>) to go high, all of the following conditions must
be satisfied:
1. The static bypass must be ‘enabled’ – i.e. the [BLK_MNS> output on D88 pin
25 must be low (see above).
2. Parallel Logic ‘Inverter on bypass’ request – ([INV-DIS> =0) D88-6. This input
is generated by the Parallel Logic Board in a ‘1+1’ configured system and
goes low when the parallel system control conditions request connecting the
load on bypass. In a single-module application this input, which is applied via
X7-32, is tied to logic low and has no affect.
Note: on the Parallel Logic Board the signal at X1-32 is identified as
[I_BUS_INV_L>.

3. In addition to conditions (1) and (2) above, one of the following conditions
must also be valid:
a) ‘Software request’ – ([L_MNS> = 1) D88-41. This is produced by the proc-
essor system when all software-monitored parameters are correct (e.g.
Critical bus volts not OK, overload, bypass volts OK etc.) and applied via
the data bus output buffer D21-12 (See paragraph [Link]).
b) No ‘Load-on-inverter’ is being requested – i.e. D88-6 [C_L_INV> AND
D88-14 [L_INV> are both logic high (see above). This means that neither
the Parallel Logic Board nor the microprocessor system are calling for the
load to be connected to the inverter
c) Inverter is blocked, but still in-sync – i.e. D88-31 [BLK_INV> is high (see
above) AND the [SYN_KO> input to D88-18 is low. Note that [SYN_KO> is
derived via the processor system and D54, and is logic high when the
inverter and bypass are not in sync (see paragraph [Link] on page 7-52).

3.3.8 CAN bus communications drivers and control logic

(circuit diagram sheet 3).
The CAN bus communications system is described in paragraph 5.3.9. (Operator
Logic Board).

3.3.9 Real-time clock (RTC)

(circuit diagram sheet 3)
The MC68698 (D18) is a peripheral device which contains a real-time clock/cal-
endar, a 32 x 8 bit static RAM, and a synchronous, serial, three-wire interface for
communicating with the micro-controller. As it’s title suggests, the real time
clock accurately counts seconds, minutes, hours (AM/PM), Day-of-the week,
date, month and year (including auto-incrementing leap-year). In the UPS Logic
Board application it provides ‘date stamping’ for the Operator Control Panel mes-
sages and ‘service data’ entered via the Maintenance Menu Screen (see para-
graph [Link] on page 2-40). The device operates from the Ni-Cad back-up
battery to maintain its time-keeping function and prevent data loss when the gen-
eral +5V control power is turned off. It also contains many other circuit functions,

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such as an alarm facility, watchdog timer etc. which are not used in this applica-
tion but may be mentioned briefly in the following description.

Power supply details

D18 is powered from the +5 volt power supply, which is connected to pin 16
(Vcc) and available at all times provided the unit is powered up.
When jumper X33 is made 1-2 the battery-backed RAM supply [VRAM] (See par-
agraph 3.3.4) is connected to pin 13 [Vbatt> and also, via an R-C delay circuit
(R108/C54), to pin 10 [POR>.
The delayed input to pin 10 is seen as a ‘Power On Reset’ [POR> and resets the
device by briefly holding pin 10 low while the device is powered-up. However,
as the battery-backed supply is present at all times, this is effectively a ‘once-
only’ reset that takes place when X33 is initially made 1-2 (i.e. battery connected)
and is not affected by subsequent application/removal of the UPS Logic Board’s
+5V control power supply.
The board’s +5V supply rail is monitored at D18 pin 12; and when the voltage at
this pin is less than 0.7V above the Ni-Cad voltage (pin 13) the device switches
to a low-power stand-by mode whereby it maintains its time-keeping function but
internally inhibits serial communication facilities with the micro-controller. This
prevents the passage of invalid or spurious data while the micro-controller is pow-
ering-down and so prevents RTC data corruption.

Clock control
The RTC’s internal timer operation can be controlled from one of two sources;
either from an external crystal-controlled clock reference or a 50/60Hz mains-de-
rived sinusoidal signal. In this particular application an external crystal is used
and the 50/60Hz input to pin 11 (LINE) is grounded via R107.
For crystal operation pins 14 and 15 are connected to a 32.768kHz, 1.048576kHz,
2.097152kHz or 4.194304kHz crystal, as shown on the circuit diagram. A pro-
grammable internal divider circuit enables the particular external clock frequency
to be scaled down to that used by the internal logic. The internal clock signal is
made available at pin 1 (CLKO) but in this particular application is not used, and
remains unterminated.

Serial communications interface

Four lines, connected to pins 4 to 7, implement a bi-directional communications
interface with the micro-controller, and allow the micro to write configuration and
control data to the RTC and read the ‘time’ and register data. As described above,
such communication is inhibited if the UPS Logic Board’s +5V power rail is un-
available.
The [ORCS> input to pin 7 (SS) is seen as a ‘chip select’ input in this application
and must be held high while either a read or write event is taking place. Data is
input (written) to the RTC by [ORDI> to pin 5; and output (read) from the device
by [ORDO> from pin 7. In each case the data takes the form of a serial data stream
clocked in/out by the ‘serial clock’ signal [ORSK> applied to pin 4. Note that all
four of these signals are under direct control of the micro-controller and applied
to the data bus via the buffers shown on diagram sheet 4.

Other connections
The functions connected to pin 2, pin 3 and pin 9 are not used in this particular
application and these pins are tied to their default logic levels as shown.

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Section 7:

3.3.10 Data bus buffers ‘chip select’ decoding

The data bus communicates with the peripheral circuits and devices via 16 octal
buffers which are selected in ‘pairs’ to provide a 16 bit data bus transfer. The
micro-controller selects a particular buffer-pair by appropriately addressing the
‘chip select’ decoding circuit (D52) which then ‘enables’ the required buffers.
Details of the digital signals handled by each buffer are provided in the following
paragraphs.

Figure 7-8: Data bus buffer control (block diagram)

D8 D17
[CSIN1-> OE CP <CSOU1-]

D2 D25
OE CP

D1 D9
[CSIN2-> OE CP <CSOU2-]

D26 D21
OE CP

D51 D50
[CSIN3-> OE CP <CSOU3-]

D60 D55
OE CP

D7 D54
[CSDIS-> CP CP <CSOU4-]

D10 D56
CP CP
DATA
BUS
Control Bus
Microcontroller
Address Bus

AX11 1 12
[CSDIS->
AX12 2 13
[CSIN1->
AX13 3 14
[CSIN2->
AX14 4 15
[CSIN3->
5 16
AX15 D52 [CSOU1->
AX16 6 17
[CSOU2->
AX17 7 18
[CSOU3->
[RDX-> 8 19
[CSOU4->
[WRX-> 9

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3.3.11 Data bus input buffers

(diagram sheet 4).
Digital signals which are read by the microcontroller as part of its control function
are connected to the data bus via six type HCT 245 octal bus transceivers (See Ap-
pendix A.1) which are accessed in pairs to provide a 16-bit data transfer (See
Figure 7-8). The buffers ‘data direction’ pins are held permanently high, therefore
the data flow is fixed from ‘A-to-B’ in each device. ‘Chip select’ signals from
D52 are connected to the buffers ‘output enable’ pins which provides the means
for the micro to select each pair of devices as required.
The remainder of this sub-section lists the digital signals connected to the data bus
through the bus input buffers, and provides signal details where appropriate.
Note: The alarms shown are for version 4 software. These may vary from earlier
software versions, which will have different screen descriptions, the alarm
number and definition however remains the same.

[Link] Buffer D8 – activated by CSIN1

XRADT1
Source: Sheet 7 X1-31
Description: From the Power Rectifier overtemperature sensing device – this
input is not normally used and is held permanently low by jumper X10 (1-2) on
the Rectifier Logic Board. If used, in an overtemperature situation this input ini-
tiates alarm #24 [RECT: OVERTEMPERAT.] and the rectifier and inverter are
shut-down 1 minute later accompanied by alarm #62 [CUT-OFF: OVERTEM-
PER]. This alarm must be reset by pressing the manual reset push-button.

OVLREC
Source: Sheet 7 X1-32
Description: Rectifier Overload – this input goes high when the rectifier is op-
erating in input current limit mode (H6 illuminated on the Rectifier Logic Board)
– (See section 4 paragraph [Link]).
This initiates alarm #23 [RECTIFIER: I/P LIMIT].

BLKREC
Source: Sheet 7 X1-33
Description: Rectifier Blocked – this input goes high when the Rectifier Logic
board is in its ‘stop’ mode (See section 4 paragraph 2.3.6). This can be due to the
Rectifier Logic Board detecting an internal fault or a ‘stop’ (block) command
issued by the UPS Logic Board (See paragraph 3.3.7).
The internal fault channel is triggered by either: incorrect phase rotation; Rectifi-
er Logic Board power supply failure; or low input voltage (-20%). The external
fault channel initiated by the UPS Logic Board will be accompanied by alarm #21
[RECT: OFF VIA DISPL.] or alarm #22 [RECT: HARDWARE BLOCK] (See par-
agraph 3.3.7).

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SEQREC
Source: Sheet 7 X1-34
Description: Rectifier input phase sequence error – this input goes high when
the Rectifier Logic board phase sequence monitor detects an error on the incom-
ing 3 phase mains supply (H8 illuminated on the Rectifier Logic Board) (See sec-
tion 4 paragraph [Link]).

IN-LOW
Source: Sheet 7 X1-35
Description: Rectifier input undervoltage – this input goes high when the Rec-
tifier Logic board input voltage monitor detects a -20% undervoltage condition on
the incoming 3 phase mains supply (H9 illuminated on the Rectifier Logic Board)
(See section 4 paragraph [Link]).

XATI1 / XATI2 / XATI3

Source: Sheet 7 X2-40 / 41 / 42
Description: Not used – no connection on High Voltage Interface Board.

[Link] Buffer D2 – activated by CSIN1

SW-REC
Source: Sheet 7 X2-43
Description: Rectifier input switch monitor – this input goes low when the rec-
tifier input mains power switch is closed. This signal passes through the High
Voltage Interface Board (See section 7 paragraph 2.3.7). When the input switch
is open, this signal initiates alarm #04 [RECTIF. SWITCHOPEN].

SW-IN
Source: Sheet 7 X2-44
Description: Static Bypass switch monitor – this input goes low when the Static
Bypass mains power switch is closed. This signal passes through the High Volt-
age Interface Board (See section 7 paragraph 2.3.7). When the bypass switch is
open, this signal initiates alarm #02 [BYPASS SWITCH OPEN].

SW-BYP
Source: Sheet 7 X2-45
Description: Maintenance Bypass switch monitor – this input goes low when
the Maintenance Bypass switch is closed. This signal passes through the High
Voltage Interface Board (See section 7 paragraph 2.3.7). When the maintenance
bypass switch is closed, this signal initiates alarm #06 [MANUAL BYPASS
CLOSED].

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SW-OUT
Source: Sheet 7 X2-46
Description: Output switch monitor – this input goes low when the Output
switch is closed. This signal passes through the High Voltage Interface Board
(See section 7 paragraph 2.3.7). When the output switch is open, this signal ini-
tiates alarm #03 [OUTPUT SWITCH OPEN].

FUSINV
Source: Sheet 7 X2-48
Description: Not used - held permanently low due to link fitted to connector
X16 on the High Voltage Interface Board (see main equipment wiring diagrams).
If used, this input monitors the inverter fuse and on fuse failure initiates alarm #38
[INV: FUSE FAIL].

FUSREC
Source: Sheet 7 X2-49
Description: Not used - held permanently low due to link fitted to connector
X17 on the High Voltage Interface Board (see main equipment wiring diagrams).
If used, this input monitors the rectifier (input) fuses and on fuse failure initiates
alarm #25 [RECT: FUSE FAIL].

FUSBAT
Source: Sheet 7 X2-50
Description: Battery fuse monitor – this input goes high if the battery fuse rup-
tures (See section 7 paragraph 2.3.15).
The fuse is detected by a micro-switch located on the fuse which, when activated,
initiates alarm #57 [BATTERY: FUSE FAIL].

TH
Source: Sheet 7 X2-51
Description: Inverter thermostat monitor – this input goes high if an inverter
thermostat opens (overtemperature > 90°C) (See section 7 paragraph 2.3.13). In
the event of an overtemperature situation occurring, this input initiates alarm #34
[INV: OVERTEMPERATURE.] and the rectifier and inverter are shut-down 1
minute later accompanied by alarm #62 [CUT-OFF: OVERTEMPER.]. This alarm
must be reset by pressing the manual reset push-button (S1).

[Link] Buffer D1 – activated by CSIN2

SW-BAT
Source: Sheet 7 X2-53
Description: Battery circuit breaker monitor – this input goes low when the Bat-
tery switch (or contactor) is closed. This signal passes through the High Voltage
Interface Board (See section 7 paragraph 2.3.7). When the battery switch is open,
this signal initiates alarm #05 [BATTERY SWITCH OPEN].

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OVLINV
Source: Sheet 7 X3-32
Description: Inverter Overload – this input goes high when the inverter is oper-
ating in current limit mode (H14 illuminated on the Inverter Logic Board) – (See
section 5 paragraph 2.3.7). In an Overload condition, this signal initiates alarm
#33 [INV: CURRENT LIMIT].

BLKINV
Source: Sheet 7 X3-33
Description: Inverter Blocked – this input goes high when the Inverter Logic
Board is in its ‘stop’ mode (See section 5 paragraph 2.3.8). This can be due to the
Inverter Logic Board detecting an internal fault or a ‘stop’ (block) command
issued by the UPS Logic Board (See paragraph 3.3.7). The internal fault channel
is triggered by either: IGBT desaturation, ribbon cable disconnected, Inverter
Logic Board power failure. The external fault channel initiated by the UPS Logic
Board will be accompanied by alarm [#30], [#31] or [#32].

XINVI1
Source: Sheet 7 X3-40
Description: Not used – held permanently low due to X13 (2-3) on the Inverter
Logic Board which disables this alternative temperature sensor route. The active
thermostat route is via [TH> described earlier.

XSTAI1
Source: Sheet 7 X5-13
Description: Not used – held permanently low due to X11 (1-2) on the Static
Switch Driver Board. No thermostat is fitted on the heatsink.

XSTAT2
Source: Sheet 7 X5-14
Description: Inverter output contactor monitor – goes low when the inverter
output contactor is closed (load on inverter) and is used by the transfer control
logic software routine.

LINK X12
Source: On-board jumper X12
Description: The normal position is open – link is closed to disable Initialisa-
tion

[Link] Buffer D26 – activated by CSIN2

MRESET
Source: Sheet 3 – switch S1
Description: RESET switch – goes high when the on-board manual reset switch
(S1) is pressed and is used by the micro to unlatch “block commands” issued by
some of its software routines.

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BLK-MNS
Source: Sheet 3 – D88 pin 25
Description: ‘Static Switch blocked’ monitor – this input goes high to inform
the micro that the static switch control logic (on this Board) is inhibiting the static
switch (alarm #16 [BYP: HARDWARE BLOCK). This can be invoked by any of
the following signals applied to D88 (See paragraph [Link]).
– static switch manual inhibit switch (Q1) closed
– bypass phase sequence error detected
– emergency shutdown operated (latched)
– open circuit SCR (latched)
– UPS Logic Board power supply failure

M-SCR-OP
Source: Sheet 3 – D88 pin 32
Description: ‘Static Switch SCR open circuit’ monitor – this input goes high to
inform the micro that an open circuit static switch SCR has been detected (on this
Board) (alarm #15 BYP: SCR FAILURE]). This signal is latched within D88 and
must be reset using S1 to return to normal conditions.

M-ESD
Source: Sheet 3 – D88 pin 29
Description: ‘Emergency shutdown’ monitor – this input goes high to inform
the micro that an emergency shutdown (Emergency Stop) has been applied (See
paragraph [Link]) (alarm [#63] [CUT-OFF: EMERGENCY]). This signal is
latched within D88 and must be reset using S1 to return to normal conditions.

M-BAT-MA
Source: Sheet 3 – D88 pin 20
Description: DC Overvoltage – this input goes high to inform the micro that a
‘DC Overvoltage’ has been detected (See paragraph 3.3.7) (alarm [#58]
[DC BUS: FAST OVERVOL.]). This signal is latched within D88 and must be
reset by S1 to return to normal conditions.

SEQMNS
Source: Sheet 5 – D34 pin 10
Description: Bypass phase sequence error – this input goes high to inform the
micro that a ‘Bypass phase sequence error’ has been detected (See paragraph
[Link]). Note that the Rectifier Logic Board detects a phase sequence error on
the UPS (rectifier) input mains supply (See section 4 paragraph [Link]). A phase
sequence error initiates alarm [#14] [BYP: PHASE [Link]] and also ena-
bles alarm [#16] [BYP: HARDWARE BLOCK] via the micro.

EEDO
Source: Sheet 2 – D20 pin 4
Description: Output from the security EPROM to initiate the micro-controller.

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DRDO
Source: Sheet 3 – D18 pin 6
Description: Real Time Clock output (See paragraph 3.3.9).

[Link] Buffer D51 – activated by CSIN3

I-BST-BAT
Source: Sheet 7 – X7-35
Description: The signal to this input is generated on the Parallel Logic Board
when the modules in a 1+1-configured system are connected in ‘common battery’
mode; and is logic high when ‘battery boost’ is requested by either module (see
paragraph 2.6.2 on page 8-37). This informs the processor system to command
the Rectifier Logic Board to enter Boost Mode (see D17 [REC_A> [REC_B> out-
puts).

I-TST-BAT
Source: Sheet 7 – X7-36
Description: The signal to this input is generated on the Parallel Logic Board
when the modules in a 1+1-configured system are connected in ‘common battery’
mode; and is logic high when ‘battery test’ is selected in either module (see par-
agraph 2.6.3 on page 8-37). This informs the processor system to command the
Rectifier Logic Board to enter Battery Test Mode (see D17 [REC_A> [REC_B> out-
puts).

MNS-DIS
Source: Sheet 7 – X7-37
Description: The signal to this input is generated on the Parallel Logic Board,
and is applicable only in a 1+1-configured system. It is logic high if the
[D_MNS_DIS> output from D50-16 (via X1-49) is driven high in either module.

BLK-SEL
Source: Sheet 7 – X7-38
Description: The signal to this input is generated on the Parallel Logic Board
when the modules in a 1+1-configured system; and is logic high if the Parallel
Logic Board’s selective shutdown circuit is active (LED H1 illuminated on Par-
allel Logic Board) (see paragraph [Link] on page 8-13).

MNS-L
Source: Sheet 3 D88-38
Description: This input goes high when the control logic requests ‘load-on-by-
pass’. This signal is also fed to the Static Switch Driver Board (X5-17)

I-SW-BYP
Source: Sheet 7 – X7-59
Description: The signal to this input is generated on the Parallel Logic Board
and is logic low when the Maintenance Bypass Switch is closed is either module
connected to a 1+1-configured system.

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INV-L
Source: Sheet 3 – D88-36
Description: This input goes high when the control logic requests ‘load-on-in-
verter’. This signal is fed to the Static Switch Driver Board X5-15 where it initi-
ates the output contactor closure; and it is also connected to the Parallel Logic
Board where it enables the current sharing function in a 1+1-configured system
(see paragraph 2.5 on page 8-31).

INV-DIS
Source: Sheet 7 – X7-32
Description: This input signal is produced by the Parallel Logic Board in a 1+1-
configured system and is logic when the Parallel Logic Board requests ‘load-on-
bypass’ (see paragraph 2.3.2 on page 8-15). The signal is also applied to the
transfer control logic within D88 (See paragraph [Link]).

[Link] Buffer D60 – activated by CSIN3

BLK-EXT
Source: Sheet 7 – X8 pin 11
Description: From external alarms (AS400 interface board). This input pro-
vides a means of allowing the inverter to be turned OFF/ON from an external
signal via the Remote Alarms Board. The ‘Block’ (OFF) signal is applied as a
closed contact across the Remote Alarms Board terminal block X5 pins 1-2.
Note: Jumper X6 on the Remote Alarms Board must be selected 2-3 in order to
enable this function.

BLK-SYN
Source: Sheet 7 – X8 pin 12
Description: Sync disable – this is an input from the optional ‘remote alarm’s
board’ (AS400 interface board) which goes high (+5V) when the UPS is “ON-
GENERATOR” – and is normally used to prevent the inverter synchronising to a
frequency-wild standby generator. The On Generator status signal is applied as a
closed contact across the Remote Alarms Board terminal block X5 pins 3-4.
Note: The response to the “ON-GENERATOR” event is programmable via the Op-
erator Control Panel FUNCTION software screen which allows three separate
functions to enabled/disabled:
• Synchro Block – is concerned with the [BLK-SYN> signal mentioned here
and, when enabled, prevents the inverter from tracking the bypass fre-
quency when it is being provided by the standby generator.
• Charge Inhibit – is concerned with the battery recharge current limit
function which, when enabled, reduces the RECTIFIER current limit by
15%.
• Current Limit – is concerned with the rectifier input current limit
[XRADD1> function which, when enabled, reduces the input current limit
by 35%.
The reduced current limit functions are employed to lower the potential
maximum current demand if the standby generator is undersized.

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BLK-01
Source: Sheet 7 – X8 pin 9
Description: From external alarms (AS400 interface board) Not used.

BLK-CHG
Source: Sheet 7 – X8 pin 10
Description: Rectifier Disable – This input provides a means of allowing the
rectifier to be turned OFF/ON from an external signal via the Remote Alarms
Board. The ‘Block’ (OFF) signal is applied as a closed contact across the Remote
Alarms Board terminal block X5 pins 1-2.
Note: Jumper X6 on the Remote Alarms Board must be selected 1-2 in order to
enable this function.

Links X26
Source: Sheet 4 jumper X26
Description: The four sections of jumper X26 are detailed in a Table on the cir-
cuit diagram sheet 1 and summarized below:
Table 7-7: X26 Jumper details

Auto-transfer mode enabled (“on-line” operation).

Open Automatic load transfer from bypass to inverter when the
(Standard) inverter is available – i.e. the inverter is the preferred supply
source
LINK 1-2 Manual-transfer mode enabled (“off-line” operation).
Automatic load transfer from bypass to inverter only when
Closed the bypass is unavailable – i.e. the bypass is the preferred
supply source. Note: there will be a 3-cycle break on trans-
fer to inverter,

Open “Inverter voltage fail lockout monitor” disabled

LINK 3-4 “Inverter voltage fail lockout monitor” enabled. i.e. The
Closed
inverter is given 5 seconds to reach nominal voltage other-
(Standard)
wise it is latched OFF.

Open Enables the “Event History” monitor to store up to a maxi-

(Standard) mum of 10 alarms.

Resets the “Event History” monitor. Note: After the 10th

LINK 5-6 “event”, the monitor buffer is full an cannot store any further
Closed “events”. The buffer should be reset to 0 after each mainte-
nance or commissioning to enable new “events” to be cap-
tured.

Open
Password protection enabled.
LINK 7-8 (Standard)

Closed Password protection disabled

3.3.12 Data bus output buffers

(circuit diagram sheet 4).
Digital signals generated by the microcontroller as part of its control function are
fed to the peripheral circuits via 10 type-74C273 octal latches (See Appendix A.2)
which are accessed in pairs to provide a 16-bit data transfer (See Figure 7-8). The

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‘chip select’ signals from D52 provide the latch clock signals and data is therefore
transferred through the latches when the appropriate ‘chip select’ signal switches
from low to high. A logic low [RSTDX-> reset signal is connected to all the data
bus output buffers via jumper X25 (3-2) and drives all their outputs low when ap-
plied. [RSTDX-> is produced by the microcontroller (See paragraph 3.3.3) and
shown on the circuit diagram sheet 2.
The remainder of this sub-section lists the digital signals connected through the
latches, and provides signal details where appropriate.

[Link] Buffers D7 and D10– activated by CSDIS

These two devices connect the data bus output to the two on-board 7-segment di-
agnostic displays (H11 & H12). For a detailed description of the displayed param-
eters (see paragraph 3.3.17 on page 7-68).

[Link] Buffer D17 – activated by CSOUT1

XRADD1
Destination: Sheet 7 – X1 pin 37
Description: Reduced current limit – when this output goes high it reduces the
Rectifier Logic Board’s input current limit threshold by 35% (See section 4 par-
agraph [Link]).
Conditions: This software-selectable output is activated when the UPS is run-
ning on ‘standby generator’ as described on page 7-44 ([BLK_SYN>).

REC-B & REC-A

Destination: Sheet 7 – X1 pin 38 / 39
Description: Charge mode selection – these two outputs are connected to a de-
coder on the Rectifier Logic Board where they invoke one of four permissible
charge modes (see section 4 table 4-3).
Conditions: These outputs select Test, Boost, Float and Manual charge modes
in response to selections made on the Operator Control Panel. The automatic
Boost mode parameters, i.e. duration and threshold, are also operator-defined –
(see paragraph 2.5.6 on page 2-53). LEDs on the Rectifier Logic Board illumi-
nate to indicate the active charge mode.

XAT01 & XATO2

Destination: Sheet 7 – X2 pin 55 / 56
Description: Not used

INV-F
Destination: Sheet 7 – X3 pin 37
Description: Base frequency selection – informs the Inverter Logic Board’s
‘staircase pattern generator’ of the UPS system’s base frequency (i.e. 50/60Hz).
(See section 5 paragraph 2.3.2).
Conditions: This output is high for 50Hz and low for 60Hz as selected on the
Operator Control Panel – see ‘Selecting the UPS SETUP parameters’ in the com-
missioning procedure (see paragraph [Link] on page 2-35).

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INV-B & INV-A

Destination: Sheet 7 – X3 pin 38 / 39
Description: Inverter working voltage selection – these two outputs are con-
nected to a decoder on the Inverter Logic Board where they select one of four per-
missible charge modes (see section 5 table 5-3).
Conditions: The logic states of these outputs are determined by the working
voltage selected by the operator – see commissioning procedure (see paragraph
[Link] on page 2-34). LEDs on the Inverter Logic Board illuminate to indicate
the active selection.

[Link] Buffer D25 – activated by CSOUT1

XSTAO1 & XSTAO2

Destination: Sheet 7 – X5 pin 19 / 20
Description: Not used

RE485-
Destination: Sheet 7 – D58 pin 2
Description: This output selects the ‘Read Enable’ pin of D58, which is an
RS485 communications driver connected to the parallel interface connector X7
pins 59/60 – not used.

OE485
Destination: Sheet 7 – D58 pin 3
Description: This output selects the ‘Output Enable’ pin of D58, which is an
RS485 communications driver connected to the parallel interface connector X7
pins 59/60 – not used.

TP5
Destination: Sheet 7 – X18 pin 5
Description: Not used (test point for system software).

OUTBAT
Destination: Sheet 2 – V152
Description: This output, when high, ‘enables’ the on-board Ni-Cad battery
charger.
Conditions: This output enables the Ni Cad battery charger if its voltage falls
to 2.8Vdc and disables it again once the battery voltage rises to 3.6V.
Note: when the charger is enabled the [INTERNAL BATTERY LOW] warning is
annunciated (alarm [#76] active).

[Link] Buffer D9 – activated by CSOUT2

EECS / EESK / EEDI

Destination: Sheet 3 – D18 pin 7
Description: These outputs control the data acquisition of EEPROM D20

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ORCS
Destination: Sheet 3 – D18 pin 7
Description: Real Time Clock (RTC) ‘chip select’ (See paragraph 3.3.9).

ORSK
Destination: Sheet 3 – D18 pin 4
Description: Real Time Clock (RTC) ‘serial communications clock input’ (See
paragraph 3.3.9).

ORDI
Destination: Sheet 3 – D18 pin 5
Description: Real Time Clock (RTC) ‘serial data input’ (See paragraph 3.3.9).

SELANA / SELANB
Destination: Sheet 6
Description: These two outputs are connected to the address inputs of three 2-
pole multiplexers which select the analogue signals for the microcontroller’s A/D
inputs – e.g. selecting the analogue signals for display purposes (kVA values are
calculated in software using V x I).

[Link] Buffer D21 – activated by CSOUT2

ALMRES
Destination: Sheet 3 – D22 pin 1
Description: Software controlled RESET – This output, when high, resets the
Emergency Shutdown, DC Overvoltage and Open SCR fault latches within D22.
Conditions: This facility is not programmed into the current software and it is
therefore not used.

INV-ON
Destination: Sheet 3 – D88 pin 17
Description: ‘Inverter ON’ request – This output, when high, requests D88 to
issue an [ON_INV> command signal which is connected to the Inverter Logic
Board and turns ON the inverter – provided other D88 inputs are correct (See par-
agraph 3.3.7).
Conditions: (see paragraph 7.2.3 on page 7-160)

L-INV
Destination: Sheet 3 – D88 pin 14
Description: ‘Load-on-inverter’ request – This output is connected to the load
transfer control logic within D88 where it is interlocked with the [BLK_INV> and
[C_L_INV> signals within D88 (See paragraph [Link]). This signal is high when
the processor system requests ‘load-on-inverter’.
Conditions: (see paragraph 7.2.10 on page 7-180)

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L_MAINS
Destination: Sheet 3 – D88 pin 41
Description: ‘Load-on-bypass (mains)’ request – This output is connected to
the load transfer control logic within D88 where it is interlocked with several
other signals within D88 (See paragraph [Link]). This signal goes high when the
processor system requests ‘load-on-bypass’.
Conditions: (see paragraph 7.2.10 on page 7-180)

REC-ON
Destination: Sheet 3 – D88 pin 40
Description: ‘Rectifier ON’ request – This output, when high, requests D88 to
issue an [ON_REC> command signal, which is connected to the Rectifier Logic
Board and turns ON the rectifier (provided other D88 inputs are correct (See par-
agraph 3.3.7)).
Conditions: (see paragraph 7.2.2 on page 7-158).

IBOPEN
Destination: Sheet 3 – D88 pin 12
Description: Trip battery circuit breaker– This output, when high, requests D88
to issue a [BAT_TRP> command signal which is connected to the High Voltage In-
terface Board and turns OFF the battery circuit breaker driver transistor.
Conditions: This signal is software driven via a programmable parameter set-
ting entered from the Operator Control Panel to trip the battery circuit breaker
when the battery is fully discharged (see page 2-37). The Emergency Shutdown
and DC Overvoltage inputs to D88 pins 9 and 8 also trigger the battery trip signal
when active (See paragraph 3.3.7).

TP6
Destination: Sheet 7 – X18 pin 6
Description: Not used (test point for system software).

[Link] Buffer D50 – activated by CSOUT3

O_BLK_SW
Destination: Sheet 7 – X1-43
Description: This output is used in a multi-module system only and has no
affect in a single-module or 1+1 system. In a multi-module system the output is
connected to the Parallel Logic Board where, when high, it turns off the inverters
in all the modules connected to the system.

O_MNS_L_SS
Destination: Sheet 7 – X1-44
Description: This output is used in a multi-module system only and has no
affect in a single-module or 1+1 system. In a multi-module system the output is
connected to the Parallel Logic Board where, when high, it opens the output con-
tactor in every module when a transfer to bypass is commanded.

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O_MNS_D_SS
Destination: Sheet 7 – X1-45
Description: This output goes high when the bypass supply parameters are
deemed valid by the processor system. This is connected to the ‘bypass frequency
validation circuit on the Parallel Logic Board where it determines if the GVCO is
allowed to synchronise to the bypass (see paragraph [Link] on page 8-27).

TST_BAT
Destination: Sheet 7 – X1-46
Description: This output goes high when the processor system requests a ‘bat-
tery test’ function and is connected to the Parallel Logic Board. If the UPS is con-
figured as a 1+1 system with common battery, the Parallel Logic Board passes
this signal along the parallel control bus where it switches both modules to the
battery test mode – i.e. ensures both modules operate at the same charge voltage
(see paragraph 2.6.3 on page 8-37).

BST_BAT
Destination: Sheet 7 – X1-47
Description: This output goes high when the processor system requests a ‘bat-
tery boost’ function and is connected to the Parallel Logic Board. If the UPS is
configured as a 1+1 system with common battery, the Parallel Logic Board passes
this signal along the parallel control bus where it switches both modules to the
battery boost mode – i.e. ensures both modules operate at the same charge voltage
(see paragraph 2.6.2 on page 8-37).

MNS_SYN_KO
Destination: Sheet 7 – X1-48
Description: This output goes high when the processor system senses that the
Inverter Logic Board has achieved internal synchronism and is connected to the
Parallel Logic Board. If the UPS is configured as a 1+1 system this is used by the
GVCO synchronisation control system as part of its inter-module synchronisation
function (see paragraph 2.4 on page 8-19).

O_MNS_DIS
Destination: Sheet 7 – X1-49
Description: This high signal is connected to the Parallel Logic Board via X1-
49 which, via the parallel control bus, immediately returns a logic low [MNS_DIS>
signal back to X1-37 in both modules of a 1+1 configured system. This is input
to the processor system via D51-4.

[Link] Buffer D55 – activated by CSOUT3

PAR_REC
Destination: Sheet 7 – X7-51
Description: This signal is driven high by the processor system when it requests
‘parallel rectifier’ operation. It is connected to the Parallel Logic Board where it
energises relay K5, whose contacts complete the rectifier current sharing control
circuit.

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OUT-03
Destination: Sheet 7 – X8 pin 31
Description: Output to Parallel Logic Board
Conditions: Not used in a 1+1-configured system.

OUT-03
Destination: Sheet 7 – X8 pin 25
Description: Output to I/O interface (remote alarms, AS400 interface etc.).
Conditions: Not used

MNS-KO
Destination: Sheet 7 – X8 pin 26
Description: Output to I/O interface (remote alarms, AS400 interface etc.).
Conditions: Logic high if mains (bypass) supply error – i.e. overvoltage [#11],
undervoltage [#12], absent [#10] or bypass blocked [#17].

BATED
Destination: Sheet 7 – X8 pin 27
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Logic high if the battery voltage falls to its end-of-discharge level
[#56] – as set by operator through Operator Control Panel (see page 2-37). It is
also active if the battery breaker is open [#05] or the battery fuse is open [#57].

CHG-INH
Destination: Sheet 7 – X8 pin 28
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Logic high if the battery charger is inhibited (driven by the
[BLK-CHG> signal described on page 7-45). Jumper X4 pins 1-2 must be linked on
the Alarm Board.

SWBYP
Destination: Sheet 7 – X8 pin 29
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Logic high if maintenance bypass isolator is closed – accompanied
by alarm #06 [MANUAL BYPASS CLOSED].

OUT-01
Destination: Sheet 7 – X8 pin 23
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Not used in the present software implementation

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[Link] Buffer D54 – activated by CSOUT4

OUT-02
Destination: Sheet 7 – X8 pin 24
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Not used in the present software implementation

OVT-BAT
Destination: Sheet 7 – X8 pin 18
Description: Output to I/O interface (remote alarms, AS400 interface, Remote
Alarms Monitor etc).
Conditions: Logic high in the event of battery overtemperature – Not used in
the present software implementation.

SYN-KO
Destination: Sheet 7 – X8 pin 16
Description: Output to I/O interface (remote alarms, AS400 interface, Remote
Alarms Monitor etc).
Conditions: Logic high if the inverter is unsynchronised to the bypass supply
– i.e. if the phase displacement is more than ±9°. This condition will initiate alarm
#35 [INV: UNSYNCHRONISED].

ALL-GEN
Destination: Sheet 7 – X8 pin 17
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: This is the “Common Alarm” output to the Alarm Board and is
active if any of the following alarms are present: [#05], [#06], [#10], [#11], [#12],
[#16], [#17], [#24], [#33], [#34], [#52], [#56], [#57], [#66].

A400ON
Destination: Sheet 7 – X8 pin 31
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: This alarm is active when the load is on the UPS (inverter or by-
pass) and is interlocked with the Maintenance Bypass being closed.

A400UF
Destination: Sheet 7 – X8 pin 32
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Condition: Mains Failure alarm; enabled by alarm [#01] and active when [#22]
is energised.

A400BL
Destination: Sheet 7 – X8 pin 33
Description: Output to I/O interface (remote alarms, AS400 interface etc).

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Conditions: Low Battery warning; enabled by alarm [#01] and active when
[#56] is energised.

A400BY
Destination: Sheet 7 – X8 pin 34
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Load on Bypass; active when alarm [#18] is energised.

[Link] Buffer D56 – activated by CSOUT4

MNSREC
Destination: Sheet 7 – X8 pin 20
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Rectifier input voltage failure – active when H9 is illuminated on
the Rectifier Logic Board.

CS-KO
Destination: Sheet 7 – X8 pin 19
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Bypass-side Static Switch blocked – goes high if a fault is detected
on the static switch (alarm [#16] present).

BAT-DSC
Destination: Sheet 7 – X8 pin 13
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Battery discharging – active when alarm [#22] is present.

OVL
Destination: Sheet 7 – X8 pin 14
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Overload – active when alarm [#33] or [#66] is present.

OVT-DIS
Destination: Sheet 7 – X8 pin 15
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Overtemperature – active when alarm [#24] or [#34] is present.

OVT-AMB
Destination: Sheet 7 – X8 pin 30
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Output Air overtemperature – not used.

XINV01
Destination: Sheet 7 – X3 pin 24

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Description: Mains error inhibit to Inverter Logic Board transfer control.

Conditions: On the Inverter Logic Board a circuit within D11 provides a con-
trol signal [RIF> which briefly transfers the voltage reference signal to the bypass
supply just before the ‘inverter-side’ contactor is closed; (see paragraph 2.3.3 on
page 5-45). This signal, [XIN01>, goes high to inform the Inverter Logic Board of
a mains (bypass) voltage error and prevents the switch-over to the bypass supply
reference from taking place; and so prevents the inverter locking to an out-of-spec
voltage.

TP7
Destination: Sheet 7 – X18 pin 7
Description: Not used (test point for system software).

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Section 7:

3.3.13 Frequency sensing and control signals

Figure 7-9: Frequency synchronisation control

Parallel logic

54
X7
2
X2
X18-2 Bypass supply R-phase
D42 62 D53 5 8Vp-p
15 VI-A 15 voltage sensing
F-INM F-IN

X18-3 X3 X4
63 4 [O_BACK>
16
34 34
BACKM BACK

D17 INV-F 44
15 INV-F D1
50 /60 Hz 37 37
DATA selection
Clock Frequency 27
MICROCONTROLLER

BUS signals Divider

D54 SYNC-KO to tri-wave
6 generator
Sync error R247
detection phase
43
align

D60 2 BLK-SYN

288kHz
CLK

50/60Hz
Sync Inhibit
4
5V
(M:S variations ) 9
X34:2-3 = Single Phase VCO
1-2 = Parallel Locked
14 1 D1 Loop
64 5 D59 SYNC 13
SYNCM 20 Phase
35 35
2 21 14 Comparator
50/60Hz signal 15
synchronised to 3 SYNC D6 3
Master Freq
bypass (when present)
reference for
Inverter Osc
UPS Logic Board (correction) Inverter Logic Board

Important Note: This section describes the frequency control operation for a ‘single-module’ instal-
lation – i.e. where the module is operating as a single, stand-alone UPS system.

Where the module is part of a ‘1+1 System’, the control operation is very similar
except that the “bypass R_phase supply” signal to which the unit attempts to syn-
chronise is obtained from the Parallel Logic Board, and is subject to a complex
inter-module synchronisation regime.

To understand to synchronisation principles of a ‘1+1’ system, you are advised to

read section 8 paragraph 2.4 prior to this section.

[Link] Frequency control principles

The inverter frequency is determined by the VCO section of a phase locked loop
i.c. (D6) on the Inverter Logic Board which provides a 288kHz (nominal) clock
signal to a frequency-divider (within D1) which then clocks the multiplexers in
the ‘reference voltage generator’ circuit section 5 paragraph 2.3.2.

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Base frequency selection

The inverter base frequency is selected via the Operator Control Panel during
commissioning and is read by the microcontroller through the CAN bus. The
micro responds by appropriately setting the [INV-F> output from D17-15 – Low =
50Hz and High = 60Hz. This is connected to the ‘frequency divider’ on the Invert-
er Logic Board where it determines the division factor – i.e. when [INV-F> is low
the 288kHz VCO output is divided by 5760 to produce a 50Hz output at D1-27;
when [INV-F> is high the division is 4800 and produces a 60Hz output.

Frequency synchronisation
It is desirable that the inverter output is synchronised to the bypass supply under
normal operating conditions as this enables a ‘closed’ load transfer to be carried
out in the event of a UPS fault – where-by the static switch SCRs are turned on at
the same time as the inverter contactor is opened, and the load does not experience
a supply break.
If the inverter is not synchronised to the bypass supply there could be a large volt-
age difference across the static switch SCRs while the load is ‘on-inverter’ (i.e.
SCRs OFF) which might damage the UPS/load equipment during a subsequent
‘closed’ transfer: in such circumstances an ‘open’ transfer takes place if the UPS
develops a fault, where-by the inverter contactor is opened prior to turning ON
the static switch SCRs. This causes a load supply break of up to 1 second, which
is an inbuilt feature designed to avoid load damage.
The frequency synchronisation control mechanism is quite complex and effec-
tively based on two nested phase locked loops. The inner loop comprises D6 on
the Inverter Logic Board and the outer loop is functionally provided by the micro-
controller, under software control.

[Link] Frequency sync control and operation

Inverter Logic Board phase-locked-loop (assuming 50Hz operation.)

The ‘phase comparator’ section of D6 compares the 50Hz output from D1-27,
connected to D6-3, with a frequency reference signal annotated [SYNC> which is
produced by the microcontroller and connected to D6-14 (available at test point
X18-4). If the ‘phase comparator’ detects any phase difference between these two
signals its output at D6-13 will modify the VCO’s frequency in such a way as to
make the ‘frequency divider’ output at D1-27 match the [SYNC> signal frequency
– i.e. the VCO frequency will be modified until the ‘phase comparator’ within D6
sees no error between these signals, whereupon the circuit can be considered to
be phase-locked. Thus the inverter frequency tracks the [SYNC> signal ‘reference’
frequency.

[SYNC> signal generation (assuming 50Hz)

The microcomputer monitors the bypass supply R-phase waveform [VI-A> via a
comparator which extracts its frequency information, [F-INM>. This signal can be
seen at X18-2 as a squarewave coinciding with the bypass supply R-phase zero-
crossing points. The Inverter Logic Board frequency divider’s 50Hz output (D1-
27) is also monitored and is available at X18-3, annotated [BACKM>.
Under software control, the micro operates on these two signals in the same way
as described above for the Inverter Logic Board’s phase-locked-loop. That is, it
performs the ‘phase comparator’ and ‘VCO’ functions described above and pro-
duces a 50Hz output, [SYNC>, whose absolute frequency is controlled by the de-

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tected phase difference between [F-INM> and [BACKM> – i.e. the width of the pulse
is directly proportional to the amount of phase difference.

Example of sync control

The overall operation of the synchronisation control circuits can best be explained
by example. Consider the case where the bypass frequency suddenly jumps from
50Hz to 50.5Hz:
1. The micro will sense the jump in bypass frequency through a rise in [F-INM>
to 50.5Hz.
2. The micro will sense a phase error between [F-INM> and [BACKM> due to their
frequency difference and will ramp-up the [SYNC> signal frequency because it
senses that the bypass frequency is higher than that of the inverter.
Note: ramp-up speed is controlled under a slew rate software program factory
set at 0.1Hz /Second.
3. The ‘phase comparator’ in the Inverter Logic Board’s phase-locked-loop will
see the ramping [SYNC> frequency and detect that it is now higher than the
frequency divider’s ‘50Hz’ output.
4. The phase comparator error output (pin 13) will call for an increase in VCO
frequency, which will thus increase the ‘frequency divider’ clock rate and
thereby demand an increased inverter frequency.
5. The ‘50Hz’ outputs from the frequency divider also ramp-up in line with the
inverter frequency and have two affects:
a) The increasing output at D1-27 is fed back to the phase-locked-loop
(D6-3) where it maintains phase-lock – i.e. it ties the clock frequency to
the [SYNC> signal and maintains close tracking of this signal.
b) The same increasing output from D1-27 is fed back to the microcontroller
via R247 where it allows the phase error function to maintain a close
check on the ‘bypass/inverter’ frequency and phase relationship.
6. When the inverter frequency has risen to match the 50.5Hz bypass frequency,
and the [F-INM> and [BACKM> signals are in phase:
a) The [SYNC> frequency will stop ramping up and remain at 50.5Hz, syn-
chronised to the bypass supply due to the action of the micro.
b) The VCO clock frequency will remain constant – i.e. 290.88kHz
(5760 x 50.5 – as 5760 is the divider factor for 50Hz systems).
c) The output from D1 pin 27 will be steady at 50.5Hz and synchronised to
the [SYNC> signal.
7. If [SYNC> is synchronised to the bypass supply (6a) and the frequency divider
outputs/inverter are synchronised to the [SYNC> signal (6c) then this results in
the inverter being effectively synchronised to the bypass supply, are required.
Important notes: The above description requires qualification by the follow-
ing notes.
a) The internal mechanism of the frequency divider chip ties its ‘50Hz’ out-
puts to the zero-crossing points of the R-phase inverter voltage. Thus, as
the micro uses the bypass R-phase supply as its frequency sensing source,
this effectively ensures that the inverter and bypass supplies are synchro-
nised correctly from a phase alignment viewpoint.

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b) To aid description the above example assumed that the bypass frequency
underwent a stepped change; however, in practice any change in bypass
frequency is likely to occur gradually: in which case the circuit dynamics
are usually able to maintain a phase-locked condition during the period of
change, resulting in the inverter frequency tracking the bypass frequency
at all times without incurring a detectable phase error.
c) The synchronising ‘window’ and ‘slew-rate’ are adjustable and selected
from the Operator Control Panel setup menus. The ‘window’ defines the
limits to which the inverter is allowed to track the bypass frequency and
normally set to ±2%; while the ‘slew-rate’ defines the maximum permitted
rate-of-change of inverter frequency and is usually set to 0.1Hz/s.– i.e. this
determines the fastest rate of change of bypass frequency tolerated by the
synchronisation circuit whilst maintaining sync.
If the bypass frequency goes outside the permitted window for longer than
1 minute, the inverter frequency will return to its base frequency and await
the mains return within the sync window, where-upon it will re-synchro-
nise. An [INV:UNSYNCHRONIZED] (alarm #35) warning will be dis-
played while this situation is in effect.
d) In the event of a bypass supply failure the microcontroller will drive its
[SYNC> output to the ‘centre’ frequency – i.e. 50Hz.

Sync phase adjustment

R247 is connected to a ‘phase-shift’ circuit on the Inverter Logic Board and pro-
vides the means for trimming any error in the phase relationship between the in-
verter [BACKM> and bypass [F-INM> sense signals once the sync control circuit is
phase-locked – due mainly to component tolerances. Therefore, once the inverter
is synchronised this resistor can be adjusted to reduce the residual phase differ-
ence between the inverter R-phase output and the bypass R-phase supply.

[Link] Non-Sync detection and alarm

An alarm condition [SYN-KO> is flagged by the microcontroller when it detects
that the [BACKM> and [F-INM> signals are more than 11° out-of-phase. This is com-
municated to the Operator Logic Board via the CAN bus and also, via D54-6, to
the I/O interface connector X8-16 where it can be used to provide a remote alarms
indication (sheet 7). [SYN-KO> is ‘high’ when a non-sync condition is present.

[Link] External ‘sync inhibit’

In certain circumstances it may be necessary to inhibit the synchronisation loop –
for example when supplying the UPS from a stand-by generator whose frequency
regulation is poor. This can be achieved by an external input via the I/O connector
X8-11 [BLK-SYN> which is connected to the microcontroller via D60-2. This input
must be taken ‘high’ to inhibit the synchronisation function (See paragraph
[Link]).
Note: The control can be activated only after being ‘enabled’ in the ‘Function’ pa-
rameter software setup screen (see paragraph [Link] on page 2-43).

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3.3.14 Analogue signal processing

The UPS Logic Board monitors the UPS input voltage, output voltage, inverter
voltage, battery voltage, output current and battery current. These inputs are proc-
essed by analogue circuits (sheets 6 & 7) which provide appropriate signals for
the microcomputers A/D input port. In some cases the inputs are also converted
to digital alarm/status signals which are connected to the micro via the data bus.

[Link] Bypass voltage signal processing

Figure 7-10: Bypass voltage sensing block diagram

+5V
+2.5V
Line-Neut Line-Line
0V
3-Phase VIABM
Bypass N6 N29 To A/D
Volts Buffer Sum-Amp VIBCM
Multiplexers
Sense VICAM (Display uses)
REF-2 (2.5V)
8Vp-p [SVI> To SCR OPEN det.
N29d
Rectifier
[SVIM> To A/D Multiplexers
(Bypass volts monitor)

A-Ph
N14
Filter [F-IN> To Micro
(sync control - bypass R-ph)

B-Ph N14 D27 [SEQMNS>

Filter Ph-Seq
To Micro
(Phase Sequence
error detector)

Voltage sensing
The bypass voltage sense signals ([VI-A> - [VI-C>) are developed on the High Volt-
age Interface Board (See paragraph 2.3.6) and connected via X2 pins 15, 16, 17
to N6b/c/d which are unity-gain buffers (sheet 5). The signals at N6 outputs there-
fore equate to approximately 1% of the bypass supply line-neutral voltage (e.g.
2.4Vrms at 240V working) and are connected to several blocks as shown in
Figure 7-10.

Voltage monitoring
N29a-c take the line-to-neutral sense voltages produced by N6 and converts them
into line-to-line sense voltages suitable for connecting to the microcontroller A/D
inputs. Taking N29a as an example; this amplifier differentially sums the [VI-A>
and [VI-B> signals from N6 and produces the [VIABM> L-L signal. However the
amplifier attenuates the resultant signal to about 30% (e.g. 1.38V for 240V work-
ing) due to its feedback resistance ratios: also, the non-inverting input is connect-
ed to VREF-2 (2.5V reference voltage) rather than to the 0V rail, which therefore
applies a 2.5V offset to [VIABM>. Thus in a 240V system working at nominal volt-
age [VIABM> is approximately 3.9Vp-p centred on a 2.5V reference. This signal
sits well within the microcontroller’s A/D 0-5V input level, and is shown connect-
ed to the A/D multiplexer circuit (sheet 6).
Note: if the bypass voltage is missing [VIABM> will be 2.5Vdc due to the absence
of any ac signal.

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Bypass frequency and phase sequence monitors

The bypass R-phase signal [VI-A> from N6-14 is connected to a zero-crossing cir-
cuit comprising N14a/d which produces a squarewave output [F-IN> at D34-6
which coincides with the R-phase zero-crossing points. This signal is used by the
microcontroller in its frequency synchronisation control (See paragraph
[Link]).
A similar squarewave coinciding with the S-phase is obtained via N14b/c and
buffered by D34-8. These two squarewave signals are connected to a D-type flip-
flop (D27) which detects their phase relationship. Under normal circumstances
the R-phase signal should lead that of the S-phase; therefore when the rising-edge
R-phase signal clocks D27, its data (D) input should be ‘low’, producing a perma-
nent ‘high’ on its Q output which inverted to a ‘low’ [SEQMNS> signal at D34-10.
In the event of a phase sequence error, D27 will have a permanent ‘low’ clocked
through to its Q output and produce a ‘high’ [SEQMNS> signal.
[SEQMNS> is connected to the microcontroller via the data bus buffer D28-7
where it flags a phase rotation error – [BYP: PHASE [Link]] alarm #14
(See paragraph [Link]).

3-phase voltage monitor

A full-wave, three-phase diode bridge comprising V34-V36 & V40-V42, produc-
es a dc voltage proportional to the full three-phase supply which is fed to N29d.
This amplifier attenuates the signal by 55% due to the values of the feedback re-
sistors; therefore the output at N2-14 is approximately 2.5Vdc at nominal working
voltage. Note that this is a ripple voltage since there is very little capacitance
around the amplifier. Thus if any bypass phase voltage goes out of tolerance (e.g.
±10% window) the detector will sense the error. It does not require all three
phases to go outside the error window.
N2-14 provides signals to two other areas: [SVIM> is connected to the microcon-
troller A/D input via the multiplexer circuit shown on sheet 6 and used by the
micro to monitor the bypass voltage for a each individual phase (e.g. ±10% volt-
age error); and [SVI> is connected to the circuit (also on sheet 6) which detects an
open circuit static switch SCR.

[Link] Inverter voltage sensing

Figure 7-11: Inverter voltage sensing block diagram

error detected on individual phase
8Vp-p
2.2Vdc
Line-Neut
3-Phase
Inverter N3a-c N3d
Volts Buffer Rectifier [SVINVM>
Sense To A/D Multiplexers

Voltage sensing
The inverter voltage sense signals ([VINV-A> - [VINV-C>) are developed on the High
Voltage Interface Board (See paragraph 2.3.5) and connected via X2 pins 18, 19,
20 to N3a-c which are unity-gain buffers (sheet 5). The signals at N3 outputs
therefore equate to approximately 1% of the inverter line-neutral voltage. A full-
wave, three-phase diode bridge produces a dc voltage proportional to the full
three-phase output which is then fed to N3d. This amplifier attenuates the signal

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by 55% due to the values of the feedback resistors; therefore the output at N3-14
is approximately 2.5Vdc at nominal voltage, and connected to the microcontroller
A/D input via the multiplexer circuit shown on sheet 6. This is a ripple voltage as
described previously, and is monitored by the inverter voltage error software
function (i.e. ±10%).

[Link] Battery (bus) voltage sensing

Figure 7-12: Battery voltage sensing block diagram

[VBM>
3.25Vdc To A/D Multiplexers
@ 446V(bat)
N13a N13c
[V-B> Buffer Comparator [BAT-MA>
DC Overvoltage (Fast)
(set to 620V(bat))

Battery volts monitor

The DC busbar (battery) voltage sense signal [V-B> is developed on the High Volt-
age Interface Board (See paragraph 2.3.3) and connected via X2 pin 27 to N13a
which is a unity-gain buffer (sheet 5). The signal sensitivity is set on the High
Voltage Interface Board to approximately 7.3mV per Volt(bat) therefore [VBM> is
about 3.255V at nominal 446V float charge voltage. This signal is connected to
the microcontroller A/D input, via the multiplexer circuit shown on sheet 6, where
it is used by several software functions, such as: display metering; slow DC over-
voltage (max 2.4V/cell window); Low Battery warning (1.82V/cell window); End
of Discharge (1.67V/cell window); and % Charge/autonomy Time algorithms.

DC Overvolts detection (Fast)

[VBM> is also monitored by N13c, which is configured as a comparator and used
to detect a DC Bus overvoltage condition. N13c has a fixed threshold which op-
erates ([BAT-MA> goes high) when [VBM> reaches approximately 4.45V, which
equates to a DC Bus voltage of around 620Vdc.
[BAT-MA> is connected to the ‘Basic System Control Logic’ where it trips the bat-
tery circuit breaker, turns off the rectifier and inverter, and trips a latch (See par-
agraph [Link]). In an overvoltage situation – [DC BUS: FAST OVERVOL.] alarm
#58 – the ‘Basic System Control Logic’ responds by issuing a ‘high’ [MBATMA>
signal which flags the micro-controller via data bus buffer D26 (See paragraph
[Link]).

[Link] Battery current sensing

Figure 7-13: Battery current sensing block diagram

REF-2 (2.5V)

[I_B>
N13b
Buffer [IBM>
[I_B_P> To A/D Multiplexers

X36: 1-2 = Separate battery

2-3 = Common battery

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Battery current monitor

The battery current sense signal [I_B> is developed on the High Voltage Interface
Board (See paragraph 2.3.22) and connected via X2 pin 31 to N13b which has a
gain of approximately1.5 (sheet 5). The signal sensitivity is set on the High Volt-
age Interface Board by jumper X38 and the output [IBM> is connected to the
micro-controller A/D input via the multiplexer circuit shown on sheet 6 where it
is used for display purposes, and % Charge and Autonomy Time algorithms.
I_B_P is used in a 1+1 installation when the rectifier is paralleled in order to share
current in a common battery system (see paragraph 2.6.1 on page 8-36)

[Link] Output voltage sensing

Figure 7-14: Output voltage sensing block diagram

+5V
+2.5V
Line-Line
0V
3-Phase VOABM
Output N5 N31 To A/D
Volts Buffer Sum-Amp VOBCM
Multiplexers
Sense VOCAM (Monitoring &
display)
REF-2 (2.5V)
8Vp-p [SVOM> To A/D Multiplexers
N15a
(Critical bus monitor)
Rectifier
N15b-d [SCROPN>
Compar-
ator To Micro
[SVI>
(SCR open cct.)

Line-Neut
VOAM
N30 To A/D
Buffer VOBM
Multiplexers
VOCM (monitoring & display)
REF-2 (2.5V)

Voltage sensing
The bypass voltage sense signals ([VO-A> - [VO-C>) are developed on the High
Voltage Interface Board (See paragraph 2.3.6) and connected via X2 pins 21, 22,
23 to N5a-c which are unity-gain buffers (sheet 6). The signals at N5 outputs
therefore equate to approximately 1% of the output line-neutral voltage (e.g. 2.4V
(8Vp-p) at 240V) and connected to several blocks as shown in Figure 7-14.

Voltage monitoring
The signals from N5a-c are connected to two sets of buffers which provide line-
to-neutral and line-to-line monitoring voltages which are connected to the micro-
controller A/D inputs via the multiplexer circuit shown on sheet 6 and used for
metering & display purposes.
L-N voltage monitoring. is provided by N38a-c which attenuate the voltage
sense signals by approximately 55% and also applies a 2.5Vdc offset due to the
non-inverting connection being terminated at VREF-2 (2.5V reference voltage). At
240V nominal voltage the monitor output signals [VOAM>, [VOBM>, VOCM> are
therefore 1Vrms (2.8Vp-p) centred about a +2.5V reference which sits well within
the microcontroller’s A/D 0-5V input level.

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Note: if the output voltage is missing [VOAM> etc. will be 2.5Vdc due to the ab-
sence of any ac signal.
L-L voltage monitoring. is provided by N31a-c. Taking N31a as an example;
this amplifier differentially sums the A and B phase signals from N5 and produces
the [VOABM> L-L signal. However, the amplifier attenuates the resultant signal by
about 70% (e.g. 1.38V for 240V working) due to its feedback resistance ratios:
also, as with the L-N circuit described above, the non-inverting input is connected
to VREF-2 (2.5V reference voltage) rather than to the 0V rail, which applies a 2.5V
offset to [VOABM>. Thus in a 240V system working at nominal voltage [VOABM>
is approximately 3.9Vp-p centred on a 2.5V reference.

3-phase voltage monitor

A full-wave, three-phase diode bridge comprising V29-V31 etc, produces a dc
voltage proportional to the full output three-phase supply which is fed to N15a.
This amplifier attenuates the signal by 55% due to the values of the feedback re-
sistors; therefore the [SVOM> output at N15-1 will be approximately 2.5Vdc at
nominal working voltage. Note that this is a ripple voltage since there is very little
capacitance around the amplifier. [SVOM> is connected to the microcontroller A-
to-D inputs via the multiplexer circuit shown on sheet 6. This is used by the
micro-controller as a critical bus voltage error monitor (factory set to ±10%) for
transfer functions.

Open Circuit Static Switch SCR detection

As shown in Figure 7-14, the output voltage (3-phase) sense signal [SVOM> and
bypass voltage (3-phase) sense signal [SVI> are both connected to the Static
Switch ‘SCR open circuit’ detector.

[Link] Output current sensing

Figure 7-15: Output sensing block diagram

REF-2 (2.5V)

3-Phase
Output N4a-c N4d
Current Buffer Sum-amp [IONM>
Sense To A/D Multiplexers
(Overload & Timers)

[IOAM>
[IOBM> (Display Metering)
[IOCM>

Output current monitor

The UPS output current sense signals ([IO-A> - [IO-C>) are developed on the High
Voltage Interface Board (See paragraph 2.3.19) and connected via X2 pins 32,
33, 34 to N4a-c which attenuate the sense signals by approximately 75% and also
applies a 2.5Vdc offset due to the non-inverting connection being terminated at
VREF-2 (2.5V reference voltage). The output signals [IOAM> etc. are connected to
the microcontroller A/D inputs via the multiplexer circuit, and the 2.5V offset is
sufficient to make the a.c. current signal sit within the 0-5V A/D input voltage
range. These signals are by the micro’s ‘overload’ algorithm (i.e. 150% for 1

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minute, 125% for 10 minutes, 110% for 1 hour, 101% for 9 hours). They also rep-
resent the values shown on the Operator Control Panel ‘ Measurements’ display
screen.
N4d calculates the neutral current by differentially summing the three line cur-
rents – in a balanced three phase system the algebraic sum of the currents should
equal zero, thus if the system is unbalanced then the amount of imbalance repre-
sent the current flowing in the neutral path. The neutral current signal [IONM> is
also subject to the 2.5V offset and applied to the microcontroller A/D inputs via
the multiplexers in the same way as the line current signals.

[Link] Analogue signal monitoring multiplexers

The microcontroller has ten A/D inputs ([AN0> to [AN9>).
[AN6> to [AN9> are fed by fixed inputs signal sources; however, [AN0> to [AN5>
are fed via a series of multiplexers which allow the micro to select from various
signal sources. Three type 4052 multiplexers are used for this purpose, each ad-
dressed by two signals ([SELANA> and [SELANB>) produced by the microcontrol-
ler via data bus buffer D9 (See paragraph [Link]). Sheet 6 contains the
multiplexer circuit and illustrates the various monitored signals connected to their
data pins (See Appendix A.3). The multiplexers are inhibited if the -12V power
supply monitor detects an undervoltage by applying a logic high [FL-12-> to the
multiplexer inhibit inputs (pin 6) (See paragraph [Link]).
Note: the inputs annotated [T1> - [T4> are temperature sensing inputs – refer to the
High Voltage Interface Board description (See paragraph 2.3.12).
Note: the micro can access the A/D signals in parallel and where necessary can
calculate values for the display – e.g. kW = V x I.

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Section 7:

3.3.15 Power supplies

[Link] General description and voltage regulators

The UPS Logic Board ±12V power supply rails are provided from two parallel
sources and will be available if either source is live. The first source is from the
Rectifier Logic Board, which is itself powered from the AC-DC Power Supply
and available whenever the UPS input (rectifier) supply is live (see paragraph 2.1
on page 3-5); the second if from the Inverter Logic Board, which is powered from
the DC-DC Power Supply and is available whenever the rectifier is working or
the batteries are connected to the DC Busbar (see paragraph 3.1 on page 3-7).
From the UPS Logic Board the ±12V supplies are passed directly to all the re-
maining circuit boards and the communications port etc.

[Link] Reference voltage generators

Several devices require a stable +5V power supply which is provided by a simple
3-terminal +5V regulator (N1), shown on sheet 7.
In addition to the +5V power supply rail, there are also two reference voltage gen-
erators on the circuit board. One generates a regulated +5V, [VREF>, from the
+12V line and the other generates a regulated 2.5V output, [VREF-2>, from the
+5V supply rail. These reference voltages are used in conjunction with the micro-
controller’s A/D analogue inputs and are shown on sheet 5 of the circuit diagram.

+5V reference voltage [VREF>

This provides a stable power supply for the A/D converters within the micro
which is necessary for them to maintain their conversion accuracy.

2.5V reference voltage [VREF-2>

The micro-controller’s internal A/D converters operate on stable 0V and +5V
power rails, as described above. Therefore if an AC signal is to be monitored (e.g.
bypass voltage), or a positive-and-negative going DC signal (e.g. battery current),
then a 2.5V offset is required shift the 0V point of the monitored signal into the
centre of the A/D converters’ input working range. This enables the A/D circuit
to convert both halves of an AC waveform and both positive and negative transi-
tions of a dc signal voltage.

[Link] -12V undervoltage detector

Comparator N45a (sheet 5) serves as a -12V supply rail monitor and detects when
the -12V is less than approximately -9.8V. The operating threshold for this circuit
is set by V70 which applies a zener referenced voltage across R242/243 from the
+12V rail and under normal conditions sets N45-3 at about 1.86V. The -12V rail
is monitored via a resistor divider (R240/241) which is fixed at +3V at one end by
V70.
Due to the chosen resistor ratios, the voltage at N45-2 rises above 1.86V when the
-12V rail is less than -9.8V, at which point N45-1 switches low and produces a
logic high [FL-12-> signal and low [FL-12>.
When [FL-12> goes low it inhibits the back-up battery voltage sense signal to the
microcontroller via D44, as shown on diagram sheet 2 (See paragraph 3.3.4).
When [FL-12-> goes high is disables the microcontroller’s A/D input multiplexers,
as shown on sheet 6 (See paragraph [Link]).

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[Link] +12V undervoltage detector

Comparator N45b (sheet 5) serves as a +12V supply monitor. The operating
threshold for this circuit is set by [VREF-2> which applies a stabilised +2.5V to
N45-6, at about 1.86V. The +12V rail is monitored via a resistor divider (R246/
245/R244) which pulls the input to N45-5 below the 2.5V threshold when the
+12V rail fall below the 9.8V level. When this occurs the output at N45-7 switch-
es from high to low which is reflected at D57-8 and the resulting ‘low’ [PFO> flag
resets the microcontroller via its non-maskable interrupt (NMI) (See paragraph
3.3.2). The micro jumps to a ‘save data’ subroutine as the supply rails are crash-
ing.

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3.3.16 External communications

RS232 communications
In addition to the bi-directional communication facility with the Operator Logic
Board via the CAN Bus, the microcontroller can also be accessed externally via
a standard RS232 communications connection (X9). This is designed to be used
with a portable computer for diagnostic, calibration and configuration purposes.
Communication takes place through D16 which is a standard RS232 line driver/
receiver connected to the micro via [TXO0> and [RXO0>, as shown on sheet 7 (See
Appendix A.6).

RS-485 Parallel control communications

An RS485 communications facility is also shown on sheet 7, based around D58
(See Appendix A.5). The differential I/O bus of this device (pins 6 & 7) is connect-
ed to the Parallel Logic Board via X7 ([TXRX+>, [TXRX->).
Transmit mode. the transmit mode is enabled when [DE485> is high, whereup-
on the [TXDI> data from the microcontroller, applied to D58 pin 4, passes through
the device and drives its differential outputs as described in appendix A.5. Note
that X32 should be made in order to connect the bus termination resistor (R250)
across the transmission line to present the correct impedance to the differential
outputs.
Receive mode. the receive mode is enabled when [RE485-> is taken low, where-
upon the data on the differential I/O bus is converted into a data-stream and con-
nected to the microcontroller via [RXDI>.

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3.3.17 On board 7-segment indications summary

The following table provides a summary of the alarm codes indicated on the two
7-segment LEDs together with their alarm interpretations and associated Operator
Panel audible and visible alarm annunciations. Note that there is no on-screen
alarm history facility, but where two (or more) alarms are active simultaneously
the associated codes will be displayed in a cyclic fashion at 1 second intervals
Note: Where the fault LED state is annotated (*) this indicates that the alarm is
latched and must be reset using S1 on the UPS Logic Board
Note: The following table has been updated for version 4.0 software alarm de-
scriptions. Earlier software versions may differ slightly though the alarm function
remains the same.

Display Alarm Messages Audible Alarm FAULT LED (red)

CODE
(Correct Meaning) (Operator Panel) (Operator Panel)

01 [ NORMAL OPERATION ] OFF OFF

02 [ BYPASS SWITCH OPEN ] Continuous ON

03 [ OUTPUT SWITCH OPEN ] Continuous ON

04 [ RECTIF. SWITCH OPEN ] Continuous ON

05 [ BATTERY SWITCH OPEN ] Continuous ON

06 [ MANUAL BYPASS CLOSED] Pulsed Flashing

Manual bypass breaker closed

10 [BYP: ABSENT ] Intermittent Flashing

Bypass supply absent – i.e. <50V

11 [ BYP: OVERVOLTAGE ] Intermittent Flashing

Bypass supply over voltage –
upper limit set via mimic menu

12 [ BYP: UNDERVOLTAGE ] Intermittent Flashing

Bypass supply under voltage –
lower limit set via mimic menu

13 [ BYP: FREQUENCY ERROR] Intermittent Flashing

Bypass supply over/under freq –
window limit set via mimic menu

14 [ BYP: PHASE ROT. ERROR ] Continuous ON

Bypass phase rotation error

15 [ BYP: SCR FAILURE ] Continuous ON *

Bypass SCR open circuit

16 [ BYP:HARDWARE BLOCK ] Pulsed Flashing

Bypass supply blocked –
hardware block on UPS Logic Board

17 [ BYP: OFF VIA DISPLAY] Pulsed Flashing

Bypass blocked via operator menu

18 [ LOAD ON BYPASS ] Intermittent Flashing

19 [ BYP: OVERTEMPERATURE ] Continuous ON

Static bypass overtemperature
warning

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Display Alarm Messages Audible Alarm FAULT LED (red)

CODE
(Correct Meaning) (Operator Panel) (Operator Panel)

20 [ RECT:SOFTWARE BLOCK] Intermittent Flashing

Software block via micro

21 [ RECT: OFF VIA DISPL. ] Pulsed Flashing

Rectifier blocked via operator menu

22 [ RECT: HARDWARE BLOCK ] Continuous ON

Hardware block via UPS Logic Board

23 [ RECT: CURRENT LIMIT ] Intermittent Flashing

Rectifier input current limit

24 [ RECT: OVERTEMPERAT. ] Continuous ON

Rectifier overtemperature

25 [ RECT: FUSE FAIL ] Continuous ON

Input fuse failure (F10,F11,F12)

30 [ INV: SOFTWARE BLOCK ] Intermittent Flashing

Software block via micro

31 [ INV: OFF VIA DISPLAY ] Intermittent Flashing

Inverter blocked via operator menu

32 [ INV: HARDWARE BLOCK ] Continuous ON

Hardware block via UPS Logic Board

33 [ INV: CURRENT LIMIT ] Continuous ON

Inverter 150% current limit active

34 [ INV: OVERTEMPERATURE ] Continuous ON

Inverter overtemperature

35 [ INV: UNSYNCHRONIZED ] Intermittent Flashing

Inverter unsynchronised to bypass
warning

36 [ INV: OVERVOLTAGE ] Continuous ON

Inverter overvolts warning

37 [ INV: UNDERVOLTAGE ] Continuous ON

Inverter undervolts warning

38 [ INV: FUSE FAIL ] Continuous ON

Inverter fuse failure

39 [ OUTPUT: OVERVOLTAGE ] Continuous ON

Inverter overvoltage trip –
critical bus overvoltage trip to bypass

40 [ OUTPUT: UNDERVOLTAGE ] Continuous ON

Critical bus undervoltage trip to
bypass – level set via mimic menu

41 [ OUTPUT: NO VOLTAGE ] Continuous ON

UPS in off-line mode

42 [ OUTPUT: WAVEFORM ERR. ] Continuous ON

Critical bus peak voltage error

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Display Alarm Messages Audible Alarm FAULT LED (red)

CODE
(Correct Meaning) (Operator Panel) (Operator Panel)

43 [ INV: FREQUENCY ERROR ] Continuous ON

lnverter frequency error –
inverter frequency window is twice
the bypass window

44 [ INV: PARALLEL ERROR ] Continuous ON *

Paralleling current error

45 [ CONTACTOR FAILURE ]

50 [ BATTERY: UNDER TEST ] Pulsed OFF

Battery test in operation

51 [ BATTERY: TEST FAILED ] Intermittent Flashing *

Battery test has failed

52 [ BATTERY: DISCHARGING ] Intermittent Flashing

Battery is discharging

53 [ BATTERY: E.O.D. ] Continuous ON

Battery end_of_discharge trip –
level set via mimic menu

54 [ BOOST: TIME EXPIRED] Pulsed Flashing

Boost charge period expired

55 [ DC BUS: SLOW OVERVOL. ] Continuous ON *

DC slow overvolts warning –
level set via mimic menu

56 [ DC BUS: UNDERVOLTAGE ] Continuous ON

Low battery warning –
level set via mimic menu

57 [ BATTERY: FUSE FAIL ] Continuous ON

Battery fuse (F13) failure

58 [ DC BUS: FAST OVERVOL. ] Continuous ON *

Fast dc overvoltage –
fixed at 620V

60 [ BYP: XFER COUNT BLOCK ] Continuous ON *

Transfer counter exceeded
– i.e. >8 transfers in 1 minute

61 [ CUT-OFF: OVERLOAD ] Continuous ON *

Overload timer expired

62 [ CUT-OFF: OVERTEMPER. ] Continuous ON *

Overtemperature timer expired

63 [ CUT-OFF: EMERGENCY ] Continuous ON *

“Emergency power-off” activated

66 [ OVERLOAD PRESENT ] Continuous ON

Overload present (warning)

67 [ CUT-OFF: OVERLOAD ] Continuous ON *

Overload timer expired

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Display Alarm Messages Audible Alarm FAULT LED (red)

CODE
(Correct Meaning) (Operator Panel) (Operator Panel)

70 [ BAD EEPROM PROGRAM. ] Pulsed ON

Start-up error – use mimic reset

71 [ ERR. LRC PAR. PAG 1 ] Pulsed ON

Incorrect display variable

72 [ ERR. LRC PAR. PAG 2 ] Pulsed ON

Incorrect display variable

73 [ ERR. LRC PAR. PAG 3 ] Pulsed ON

Incorrect display variable

74 [ ERR LRC ALARM HIS. ] Pulsed ON

Alarm History buffer error

75 [ ERR LRC EVENT HIS. ] Pulsed ON

Alarm History buffer error

76 [ INTERNAL BATTERY LOW ] Pulsed ON

Internal PCB ni-cad battery Low

80 [ ERROR LRC TABLE ]

81 [ ERROR LRC PANEL ]

82 [ MODEM WRONG CONFIG. ]

83 [ ERROR LRC ALARM MEM. ]

84 [ MODEM NO RESPONSE ]
Modem incorrectly connected

85 [ MODEM FALSE COMMAND ]

Modem incorrectly configured

86 [ MODEM TIMEOUT TRASM. ]

Modem baud-rate error

87 [ CAN BUS NO RESPONSE ]

UPS-to-display not connected

88 [ AUTONOMY XXXX min ]

Battery autonomy time

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3.4 Summary information

Table 7-8: UPS Logic Board configuration jumpers

Link
Jumper Function
Position

OPEN (standard)

X12 1-2 Not Required

3-4 Not Required

1-2 EPROM Enable

X13
2-3 RAM Enable (standard)

1-2 Not Required

3-4 Not Required Testing only

X14 normally
5-6 Not Required open
7-8 Not Required

1-2 PLL option with CAP IN

X15
2-3 PLL option with FIN AUX (standard)

OPEN CAN Bus to display disabled

X16
1-2 CAN Bus to display enabled (standard)

1-2 ALE enable data save

X17
2-3 Power supply fail enable data save (standard)

1-2 EPROM II enable (not required)

X19
2-3 RAM II enable (not required)

+5V PCB enables microprocessor ref. For VA calculations

1-2
X20 (standard)

2-3 V ref. enables microprocessor ref. For VA calculations

1-2 Not Required

X21
2-3 RAM enable (standard)

1-2 EPROM enable (standard)

X22
2-3 Not Required

1-2 Not Required

2-3 EPROM enable (standard)

X23
3-4 Not Required

4-5 Not Required

1-2 RAM enable (standard)

2-3 EPROM enable (not required)

X24
3-4 RAM enable (standard)

4-5 EPROM enable (not required)

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CHAPTER 3 - UPS Logic Board (4550007 H)

Link
Jumper Function
Position

1-2 Manual reset of output buffers

X25
2-3 Microprocessor reset of output buffers (standard)

Open (Standard)
Auto-transfer mode enabled (“on-line” operation).
Automatic load transfer from bypass to inverter when the
inverter is available – i.e. the inverter is the preferred supply
source.
1-2 Closed
Manual-transfer mode enabled (“off-line” operation).
Automatic load transfer from bypass to inverter only when
the bypass is unavailable – i.e. the bypass is the preferred
supply source. Note: there will be a 3-cycle break on trans-
fer to inverter.

Open
“Inverter voltage fail lockout monitor” disabled.
Closed (Standard)
3-4
“Inverter voltage fail lockout monitor” enabled. i.e. The
X26 inverter is given 5 seconds to reach nominal voltage other-
wise it is latched OFF.

Open (Standard)
Enables the “Event History” monitor to store up to a maxi-
mum of 10 alarms.
Closed
5-6 Resets the “Event History” monitor. Note: After the 10th
“event”, the monitor buffer is full an cannot store any further
“events”. The buffer should be reset to 0 after each mainte-
nance or commissioning to enable new “events” to be cap-
tured.

Open (Standard)
Password protection enabled
7-8
Closed
Password protection disabled

OPEN Power up reset enabled (standard)

X28
CLOSED Power up reset disabled

OPEN 2.5V power supply monitor enabled (standard)

X29
1-2 2.5V power supply monitor disabled

OPEN Internal battery disabled

X31
1-2 Internal battery installed and charger enabled (standard)

OPEN RS485 port disabled

X32
1-2 RS485 port enabled (standard)

1-2 Calendar IC supply from VRAM (Standard)

X33
2-3 Calendar IC supply from internal battery

1-2 G.V.C.O. to inverter logic = parallel module

X34
2-3 Micro V.C.O. to inverter logic = single module

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CHAPTER 3 - UPS Logic Board (4550007 H)

Link
Jumper Function
Position

1-2 Separate battery per module (parallel system)

X35
2-3 Common battery (parallel system)
1-2 Separate battery per module (parallel system)
X36
2-3 Common battery (parallel system)

Table 7-9: UPS Logic Board potentiometer adjustment

Potentiometer Function
R209 5 volt reference adjustment. Check at X20 pin 1
R212 2.5 volt reference adjustment. Check at anode of V45

Table 7-10: UPS Logic Board LED indication

LED Colour Function

H1 Red Internal battery charger operating

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 Section 7: UPS System Control

Chapter 4 - UPS Logic Board (4550004 E)

4.1 Chapter overview

This chapter contains a circuit description of the UPS Logic Board used across the
whole 7200 Series UPS model range, and should be read in conjunction with cir-
cuit diagram SE-4550004-E (7 pages).
Signal annotations shown on the circuit diagrams are shown in italics in the fol-
lowing text – e.g. [CLKOUT>.

4.2 General description

4.2.1 Circuit board functions

Figure 7-16: UPS Logic Board connections

Rectifier Inverter Static Switch

Logic Board Logic Board Driver Board
X2 X4 X13

X1 X3 X5
Parallel
X7 Control
UPS Logic Board
Logic

X2 X8 X6 X4

X1 X1 X2 X9 Operator
High Voltage External Operator Control
I/face Board Alarm Options Logic Board Panel

The position of the UPS Logic Board with respect to the other control boards
places it at the heart of the UPS control operation and its functional responsibili-
ties can be broadly summarised as follows:
• Motherboard –
One of the most basic functions provided by the UPS Logic Board is to act
as a ‘motherboard’ for signals travelling directly between any of the other
circuit boards connected to it: e.g. the input voltage sense signals passes
directly from the High Voltage Interface Board to the Rectifier Logic
Board.
• System control –
The UPS Logic Board contains a microprocessor-based control system
which reads various status signals derived on the other circuit boards and

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CHAPTER 4 - UPS Logic Board (4550004 E)

produces several ‘system’ control logic signals: e.g. ‘stop/start’ signals to

the Rectifier/Inverter Logic Boards, and ‘transfer command’ signals to the
Static Switch Interface Board.
• Alarms control –
The UPS Logic Board acts as an assembly point for alarm signals gener-
ated on the various other boards, together with those generated on the UPS
Logic Board itself, and controls their distribution to the Operator Control
Panel and External Alarms Options under microprocessor supervision.
• Operator programming interface –
The UPS Logic Board microprocessor enforces the programmable system
operating parameters selected by the operator, via the Operator Logic
Board, onto the ‘system’ control logic
• Static Switch transfer control –
The UPS Logic Board contains decision-making logic which controls the
load transfer events between the inverter and static bypass supplies.

4.2.2 Input/Output connections

The UPS Logic Board has eight connectors (See Figure 7-16) whose connections
are summarised below.
• X1 – System control and monitoring signals to/from the Rectifier Board
4520074-A (See Table 7-11).
• X2 – System control and monitoring signals to/from the High Voltage
Interface Board 4590054-O (See Table 7-12).
• X3 – System control and monitoring signals to/from the Inverter Logic
Board 4530024-S (See Table 7-13).
• X4 – Power supply to Operator Logic Board 4550005-F (see circuit dia-
gram sheet 7).
• X5 – System control and monitoring signals to/from the Static Switch
Driver Board 4542041-X (See Table 7-14).
• X6 – Data/logic to/from Operator Logic Board 4550005-F (see circuit dia-
gram sheet 7).
• X7 – Used in multi-module parallel operating systems only.
• X8 – Alarm outputs to optional external (remote) alarm display boards
(see relevant external alarm interface board in the Options section of this
manual).

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CHAPTER 4 - UPS Logic Board (4550004 E)

Table 7-11: Connector X1 (To Rectifier Logic Board)

PIN I/O Function

1-4 I 0V – ground reference for digital electronics

5-8 I +12V power supply derived from AC-DC Power Supply Board

9-12 I -12V power supply derived from AC-DC Power Supply Board

13-14 I/O Common – ground reference for analogue sense signals

15 O VREC_AC: Input mains voltage sense signal (phases U-W) –

through connection from HVI Board – (15Vp-p)

16 O VREC_BA: Input mains voltage sense signal (phases V-U) –

through connection from HVI Board – (15Vp-p)

17 O VREC_CB:Input mains voltage sense signal (phases W-V) –

through connection from HVI Board – (15V p-p)

18 O IB: Battery current sense signal – through connection from HVI

Board – battery current limit control

19 – Not used in standard modules

20 O IREC: Rectifier input current sense signal – through connection

from HVI Board – input current limit control

21-23 – Not used in standard modules

24 I IREC_T: Used in parallel systems only (not available)

25 O VB: DC Bus (battery) voltage feedback – through connection from

HVI Board (-3.225Vdc @446V DC Bus)

26 O T_BAT: Battery cabinet temperature sensor – through connection

from HVI Board (2.98V @ 25°C)

27 O IDC_1: Not used in standard model (12 pulse rectifier only)

28 O IDC_2: Not used in standard model (12 pulse rectifier only)

29 O DB: Used in parallel systems only (input current sharing)

30 O DB_0: Used in parallel systems only (input current sharing)

31 – Not used in standard modules

32 I OVLREC: Rectifier overload error status (Overload = 1)

33 I BLKREC: Rectifier OFF/ON status (OFF = 1, ON = 0)

34 I SEQREC: Input mains phase sequence error status (Error = 1)

35 I IN_LOW: Low input volts 20% error status (Error = 1)

36 O ON_REC: Rectifier Run(1)/Stop(0) command from UPSLB micro

37 O XRADD_1: Reduced current limit from UPSLB micro (On Gen = 1)

38 O REC_A: Charge mode selection from UPSLB micro

39 O REC_B: Charge mode selection from UPSLB micro

40 – Not used in standard modules

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CHAPTER 4 - UPS Logic Board (4550004 E)

Table 7-12: Connector X2 (To High Voltage Interface Board)

PIN I/O Function

1-4 – 0V – ground reference for digital electronics

5-8 O +12V supply to HVI Board

9-12 O -12V supply to HVI Board

13-14 – Common – ground reference for analogue sense signals

15-17 I VI-A, VI-B, VI-C: Bypass sense voltages for U-V-W phases respec-
tively. Approximately 1% of bypass L-N voltage

18-20 I VINV-A, VINV-B, VINV-C: Inverter sense voltages for U-V-W

phases. Approximately 1% of inverter L-N voltage (8Vp-p)

21-23 I VO-A, VO-B, VO-C: UPS output sense voltages for U-V-W phases
respectively. Approximately 1% of UPS output L-N voltage (8Vp-p)

24-26 I VREC-AC, VREC-BA, VREC-CB: Input mains sense voltages.

Approximately 1.3% of input L-L voltage –
e.g. approx. range 5V - 5.5V (15Vp-p) for 380-415V nominal input

27 I V-B: DC Bus (Battery) volts sense signal. Approximately 0.7% of

the DC Bus voltage (+3.225Vdc @446V DC Bus)

28-30 I IINV-A, IINV-A, IINV-C: Inverter current sense (150% phaseback)

31 I I-B: Battery current sense signal (Batt I limit and current display)

32-34 I IO-A, IO-B, IO-C: Output current – O/load alarm/timer/display

35 I IREC-1: Input current sense signal (dc)

36-42 – Not used in standard modules

43 I SW-REC: Rectifier Input Switch auxiliary contact status

44 I SW-IN: Static Bypass Switch auxiliary contact status

45 I SW-BYP: Maintenance Bypass Switch auxiliary contact status

46 I SW-OUT: Output Switch auxiliary contact status

47 – Not used in standard modules

48 I FUSINV: Inverter fuse monitor (not used in standard module)

49 I FUSREC: Rectifier fuse monitor (not used in standard module)

50 I FUSBAT: Battery fuse monitor

51 I TH: Inverter thermostat contact status

52 I ESD: Emergency shutdown

53 I SW-BAT: Battery isolator auxiliary contact status

54 O BATTRP: Battery isolator trip signal

55-56 – Not used in standard modules

57-60 I T1, T2, T3, T4: Temperature sensing monitoring signals

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CHAPTER 4 - UPS Logic Board (4550004 E)

Table 7-13: Connector X3 (Inverter Logic Board)

PIN I/O Function

1-4 I 0V power supply rail

5-8 I +12V power supply derived from DC-DC Power Supply Board

9 - 12 I -12V power supply derived from DC-DC Power Supply Board

13 – Common

14 – Common

15-17 O [VI-A>, [VI-B>, [VI-C>: Bypass volts sense signals

– through connection from HVI Board

18-20 O [VIN-A>, [VIN-B>, [VIN-C>: Inverter volts sense signals

– through connection from HVI Board

21-23 O [IINV_A>, [IINV_B>, [IINV_C>: Inverter current sense signals

– through connection from HVI Board

24 O [XINVOI>: Mains error – load transfer to inverter (H)

25 O [DREF>: Output voltage adjustment - used in parallel modules

26 O [DREF0>: Output voltage adjustment - used in parallel modules

27-30 O [DV-A>, [DV-B>, [DV-C>, [DV-0>: Load sharing signals used for par-
allel modules only

31 O [INV-L>: Transfer load to inverter command from processor system

32 I [OVL-INV>: Inverter overload status to processor system (OVL = L)

33 I [BLK-INV>: Inverter On/Off status to processor system (Off = H)

34 I [BACK>: Sync signal back to processor system (Sync pulse train)

35 O [SYNC>: Produced by processor system (Sync pulse train)

36 O [ON-INV>: Inverter On/Off control from processor system (Off = L)

37 O [INV-F>: from processor system (Inv Freq)

38-39 O [INV_A>, [INV_B>: from processor system - used in output volts

selection

40 I Inverter thermostat status signals (optional)

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CHAPTER 4 - UPS Logic Board (4550004 E)

Table 7-14: Connector X5 (Static Switch Driver Board)

PIN I/O Function

1-4 O 0V power supply rail

5-8 O +12V power supply rail

9 - 12 O -12V power supply rail

13 I XSTAI1: Not used in standard module. Details required as to what

is connected to SSDB connector X7

14 I XSTAI2: Output contactor (inverter output) auxiliary contact status

– low = contactor closed

15-16 O INV-L: Transfer load to inverter command from processor system

17-18 O MNS-L: Transfer load to bypass command from processor system

19 – XSTAD1: Not used in standard module.

20 – XSTAD2: Not used in standard module.

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 4.2.3

ON
ON OFF
On Bypass
OFF
Bypass SCR control Inverter Run
ON
Block Diagram

On Inverter D23
OFF
Reset Inverter contactor
20MHz Rectifier Run
Power control ON
Clock
X28 OFF
7200 Series UPS Service Manual

S5
Reset
S1
Bypass On/Off
S2 D22
Inverter On/Off

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S3
Rectifier On/Off

Address X
X1 Rectifier
P0 Logic Bd

Output H.V.I Board

l
RAM EPROM CS X2
ro Buffer
nt
Output CAN Co
P3
Display Interface Da
ta X3 Inverter
P4 Input Logic Bd
Buffer
P2 SBS Board
X5
Data X

P1 Parallel
X7
MUX Logic
A/D D43
Figure 7-17: UPS Logic Board basic block diagram

Analogue Signal
Converters D48 Analogue X8 Alarm
P5 D49 Buffering Board
SECTION 7 - UPS System Control
CHAPTER 4 - UPS Logic Board (4550004 E)

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CHAPTER 4 - UPS Logic Board (4550004 E)

[Link] System overview

Processor system
The UPS Logic Board control system is based on a type 80C166 microcontroller,
as shown in Figure 7-17. This device contains six ports through which it commu-
nicates with peripheral circuits/devices, together with several ‘system control
lines’. It also contains an internal A/D converter, four programmable timers and
internal ROM & RAM.
The ports are configured by an initialisation routine performed by the system soft-
ware on power-up and can be summarised as follows.
• Port 0
This port is configured as a 16-bit bi-directional data bus <D0...D15>
• Port 1
This port is configured as the first 16-bits of an 18-bit address bus
<A0...A15> the other two address lines are provided by port 4.
• Port 2
The lower half of this port <P2-0...P2-7> carries various synchronising/tim-
ing signals and the upper half <P2-8...P2-15> comprises the CAN data bus,
which carries the data to/from the Operator Logic Board
• Port 3
This 16-bit port is configured as a mixture of inputs and outputs generally
concerned with controlling the CAN Bus data exchange.
• Port 4
The lower two lines only are utilised on port 4. These form the upper two
address lines <A16...A17> the lower address lines <A0...A15> are provided
by port 1.
• Port 5
The lower ten lines of this port <P5-0...P5-9> are configured to act as inputs
to the internal A/D converter.
• System control lines
In addition to the I/O ports the microcontroller also has the general control
I/O lines normally associated with a microprocessor-based system; such as
a system clock, reset, and Read/Write control.

Memory
The microcontroller uses both internal and external memory. 2 X 126k of battery-
backed RAM and 2 X 516k of EPROM are fitted to the board as standard which
holds the system operating software. Facilities are included on the board to allow
alternative memory configurations to be used as described later.

Data buffers
The 16-bit data bus is connected to various control circuit boards via input and
output data buffers, as shown in Figure 7-17, which are controlled by individual
‘chip select’ enable lines to direct the data flow to/from the appropriate source, as
required by the system control software.

Analogue signal processing

The microcontroller monitors various analogue signals which are connected to
the UPS Logic Board from the peripheral boards. These signals are processed by
suitable analogue circuitry, buffered where necessary, and applied to the micro-
controller’s A/D inputs via a series of multiplexer devices.

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Primary output control signals

Although the micro-controller produces numerous control logic signals, its pri-
mary outputs can be considered to be:
• Inverter Start/Stop
Signal to the Inverter Logic Board which determines whether or not the
inverter section is ‘enabled’ or ‘inhibited’.
• Rectifier Start/Stop
Signal to the Rectifier Logic Board which determines whether or not the
rectifier section is ‘enabled’ or ‘inhibited’.
• Load on inverter
Signal which controls the ‘inverter-side’ contactor (K1) and connects the
inverter output to the load.
• Load on bypass
Signal which controls the static switch and connects the load to the static
bypass supply.
Note: the ‘load on inverter’ and ‘load on bypass’ signals are interlocked
such that they cannot be activated simultaneously.

As shown on the block diagram, these signals are produced by a dedicated logic
block which is controlled by the data bus together with individual switches which
allow each of the above functions to be manually overridden.

Operator Interface
The microcontroller is connected to the Operator Logic Board via the CAN Bus,
which is a bi-directional serial communications link that enables the operator to
program several operational parameters into the micro-controller and also enables
various alarms and indications to be displayed on the Operator Control Panel.

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CHAPTER 4 - UPS Logic Board (4550004 E)

4.3 Detailed circuit description

4.3.1 Introduction
The UPS Logic Board circuit diagram (SE-4540004-E) comprises 7 sheets. With
reference to the block diagram description (See Figure 7-17), the drawings can
broadly be described as follows:
• Sheet 1 contains a ‘signal map’ identifying the functions covered on the
remaining pages. It also contains a summary chart detailing the various
configuration jumpers.
• Sheet 2 contains the
– basic microcontroller system
– data bus, address bus and control line buffers
– Ni-Cad battery back-up controller
– reset generator
• Sheet 3 contains the
– system RAM and ROM memory and its associated configuration links
– Inverter/Rectifier Start/Stop control logic
– load transfer control logic
– CAN bus communications drivers and control logic
– Real-time clock (RTC)
• Sheet 4 contains the
– data bus input buffers
– data bus output buffers
– on-board 7-segment indication circuit
• Sheet 5 contains analogue signal processing circuits for the
– input voltage sense signals
– inverter voltage sense signals
– DC (battery) bus voltage sense signal
– Battery current sense signal
it also contains reference voltage generators; power supply monitors; and
inverter overvoltage and input overvoltage fault detection circuits.
• Sheet 6 contains analogue signal processing circuits for the
– output voltage sense signals
– output current sense signals
it also contains the analogue signal multiplexers (for the A/D inputs), out-
put overvoltage and overcurrent fault detection circuits.
• Sheet 7 contains the
– input/output signal identifications details
– serial communications (RS485) driver and port
Note: On the diagrams, a ‘negative’ symbol at the end of a signal’s annotation in-
dicates that the signal is ‘active low’ – e.g. [RD> = [RD->.
As with all micro-based system, the microcontroller’s operation is determined by
the program held in the system’s memory: and as this is hidden to the service en-
gineer there is very little that can be done to ascertain that the board is working
correctly apart from checking the validity of its input and output signals, and other
signals generated on the board which are required by the central processor system.
The following description deals with the board on this basis, and should provide
sufficient information to determine whether or not the board is functioning cor-
rectly when it comes to troubleshooting. A full software description is beyond the
scope of this manual.

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4.3.2 Basic microcontroller system

(circuit diagram sheet 2)

Figure 7-18: Micro system control signals

Power Supply

20 READY 96 Ready
Clock XTAL1
CLKOUT 97 Clock out
Reset 27

Control Bus
RSTIN 25 Address latch enable
ALE
Power 29 BHE 92 Bus high enable
Fail NMI
RSTOUT 96 Reset out
Vref (+5V) 54
VAREF RD 26 Read

WR 95 Write
D42

Caution When monitoring the signals described in this section it is best done with control
power only – i.e. with the UPS power sections shut down and the circuit boards
live via the control power supply. The signals entering the left of the above dia-
gram are constant and can be monitored with a meter/oscilloscope; those shown
on the right of the diagram are not constant and best monitored with a logic probe.
The logic sequence/timing of these signals depend upon various circuit conditions
and cannot therefore be accurately defined; however, for field test purposes, the
presence of a ‘variable switching’ logic signal at these points would generally in-
dicate that the basic processor control bus is serviceable and the system software
is running.

Power supply
The microcontroller is powered from the general +5V rail which is provided by a
three-terminal 5V regulator (N1) shown on diagram sheet 7.

System clock (XTAL1)

A dedicated crystal-controlled clock generator (E2) provides a system clock
signal which is connected to the microcontroller (D12) pin 20. This signal is a
20MHz squarewave switching between +5V and 0V.

System reset (RSTIN)

On power-up, a 1 second logic low reset pulse, [RSTIN->, is applied to D42 pin 27
from the ‘reset generator’ circuit. This can also be manually applied for trouble-
shooting purposes by temporarily bridging jumper X28 (See paragraph 4.3.5).
The [RSTIN-> pulse forces the processor to restart its operation from the beginning
of its operating program which forces it to run through its initialisation routine.

Non-Maskable Interrupt (NMI)

When the input to D42 pin 29 (NMI) goes low it instructs the system software to
interrupt its present operation and execute a power-down routine to save critical
data.

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The source of this input is determined by X17 which is normally ‘made’ 2-3 and
selects the power failure detection circuit output [PFO> as the controlling signal –
this circuit is shown on diagram sheet 5 (See paragraph [Link]).

Reference voltage (VAREF)

The input to D42 pin 54 (VAREF) is a +5V reference voltage used by the internal
A/D converters to compute the digital values for all analogue signals – e.g volts/
current/VA etc. An adjustable reference voltage generator (N45 pin 8) (See par-
agraph [Link]), shown on diagram sheet 5, provides this input ([VREF>) via X20
which is normally ‘made’ 1-2.

Clock out (CLKOUT)

This output is a 20MHz squarewave synchronised to the processor clock input and
is used by the RAM/ROM memory address decoding logic D33 (See paragraph
4.3.6) shown on the diagram sheet 3. This is to ensure that when the processor
wishes to read from/write to memory the memory access is synchronised to the
internal microprocessor action – i.e. it ensures that the accessed memory address
is relevant to the current processor’s requirements.

Address latch enable (ALE)

This output goes high to enable the address bus to be latched into the RAM/ROM
memory address decoding logic D33 shown on the diagram sheet 3 – (See para-
graph 4.3.6).

Bus high enable (BHE)

The logic state of this output indicates whether the processor is internally enabling
its ‘high’ or ‘low’ byte data bus – i.e. it indicates if the micro wishes to read from
(or write to) the lower byte (D0....D7) or the higher byte (D8....D15). [BHE-> is
low when the high byte is being accessed, and vice versa, and is used by the RAM/
ROM memory address decoding logic shown on the diagram sheet 3 – (See par-
agraph 4.3.6).

Reset out (RSTOUT)

[RSTO-> is controlled by the reset input signal, [RSTIN->, and goes high while the
input rest signal is applied. This signal is synchronised to the system clock and
returns high an integral number of clock pulses after the input reset signal is re-
moved. The [RSTO-> signal is used by the RAM/ROM memory address decoding
logic shown on the diagram sheet 3 (See paragraph 4.3.6); and a buffered version,
[RSTOX->, is connected to the data bus output buffers as shown on diagram sheet
4 via jumper X25 (2-3) – (See paragraph 4.3.12).

Ready (Ready)
This input, when low, inserts wait states in the processor’s operation; thus slowing
it down. It is driven by the RAM/ROM memory address decoding logic shown on
the diagram sheet 3 – (See paragraph 4.3.6) – and holds off the processor’s oper-
ation until the appropriate address latching has taken place, thus effectively ex-
tending the read/write times when slower memory elements are being used.

Read (RD)
This output goes low when the processor wishes to read the data from the device
or memory location currently addressed by the address bus.

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Write (WR)
This output goes low when the processor wishes to write data to the device or
memory location currently addressed by the address bus.

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4.3.3 Data bus, address bus and control bus buffers

(circuit diagram sheet 2).

Data bus buffer

Two type ACT245 octal bus transceivers (D32 & D36) are employed as bi-direc-
tional protection buffers between the microcontroller (D0....D15) and the data bus
(DX0....DX15). D32 buffers the ‘low’ byte (D0....D7) and D36 the ‘high’ byte;
however both are controlled by a common data direction signal – i.e. the micro-
controller’s [RD-> output – therefore the data direction of all 16 data bus lines are
controlled by a single signal.
These devices are described in appendix A (See paragraph A.1).
When the microcontroller drives its [RD-> output low it sets the data direction
through the buffers from B-to-A, which allows the data bus contents through to
the microcontroller’s data inputs. At other times, when [RD-> is high, data flows
through the buffers from A-to-B, allowing the micro to place data onto the data
bus, which can then be written to a peripheral circuit as required.

Address bus buffer

The address bus is also buffered by two ACT245 devices (D38 & D41) but, unlike
the data bus described above, in this case the data direction is fixed by connecting
pin 1 of each device to a permanent +5V supply. Thus the address bus data always
flows through the devices in the A-to-B direction and used to select a memory lo-
cation – the buffered address bus is annotated (AX0....AX17).
Note: AX16 & AX17 are buffered by the control bus buffer described below.

Control bus buffer

The control bus signals [RD->, [WR->, [BHE->, [RSTO-> are all buffered by D47.
This device is configured with fixed data direction A-to-B, in the same manner as
the address bus buffer described above, by the application of a fixed +5V supply
at D47 pin 1. The buffered control signals [RDX->, [WRX->, [BHEX->, [RSTOX-> are
used by various circuits distributed throughout the circuit diagrams.
In all cases the above mentioned buffers have pull-up resistors connected to their
input and output pins – e.g. resistor packs R307, R309 etc.

4.3.4 Ni-Cad Battery back-up controller

(circuit diagram sheet 2).
A 3.6V 280mAh Ni-Cad battery is fitted to the UPS Logic Board to back-up the
RAM contents and maintain the RTC time-keeping operation when the UPS is
turned OFF; when fully charged the battery offers a back-up period of up to 4 to
5 months.
The charger circuit is activated by the [OUTBAT> signal which is produced by the
processor via D25 pin 19 (diagram sheet 4). When [OUTBAT> goes high it turns
on V152 which then turns on V151 to supply the battery charge current via led
H8, R32 and V73. The charge voltage is limited to 4.7V by zener V14.
Note: the battery can be disabled for shipping/storage by opening jumper X31.
The battery is connected to the RAM memory devices and Real Time Clock
device – shown on diagram sheet 3 – via V32 and the battery supply annotated
[VRAM>. Thus, if the board’s power supply is turned off (i.e. UPS fully powered
down) the programmable parameters held in RAM (e.g. kVA, working voltage

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and frequency, battery charging parameters and display language) are main-
tained; and the real-time clock keeps running. It is not therefore necessary to re-
program these parameters following every start-up.
Note: Jumper X31 must be made in order to enable this function.
The [VBATT> output is not connected to other parts of the circuit, but it is moni-
tored by the microcontroller’s analogue input [AN9> via D44, which is a quad an-
alogue switch. [VBATT> is switched through D44 pin 2, by [FL-12> when it goes
high; this is controlled by a ±12V supply rail monitor circuit (diagram sheet 5)
which inhibits the [VBATT> sense signal if the ±12V power rails are invalid, thus
preventing an erroneous battery voltage fault being detected by the micro under
these conditions.
Note: the other three gates within D44 are not used and their inputs are tied to 0V.

[OUTBAT> signal details

The micro-controller monitors the NiCad battery voltage (3.6V nom) via AN9
and its internal A/D converter (as described above) and turns on the Ni-Cad
charger, by driving the [OUTBAT> signal high, if the Ni-Cad voltage falls below
2.8V. When the charger is active, the [BACK-UP BATTERY LOW] message is dis-
played on the Operator Control Panel (alarm #76) and led H8 illuminates. Once
the battery is recharged to 3.6V the charger is turned off by the [OUTBAT> signal
returning low and the alarm message is cancelled. Thus the Ni-Cad battery is
charged only when necessary and is not permanently trickle-charged.
Note: the NiCad charger may be active for several hours when the UPS is first
commissioned (depending on the initial battery charge state) – jumper X31 must
be fitted to ‘enable’ the battery back-up facility.

4.3.5 Reset generator

(circuit diagram sheet 2).
A purpose-designed Supply Voltage Supervisor (N24) provides the micro with a
1 second sec logic low [RSTIN-> reset signal on power-up. This signal, which is
applied to the micro pin 27, can also be initiated manually by temporarily making
jumper X28 (1-2). The [RSTIN> signal also resets the RAM chip select signals pro-
duced by D19a/d (shown on circuit diagram sheet 3) and points the micro to its
initialisation routines.

Caution Using X28 to activate the reset circuit during normal UPS operation will crash the
unit, because the ‘run’ signals to the rectifier, inverter and static switch will be dis-
abled for the 1 second reset period.

On power-up (reset) the micro-controller receives initialisation data from D20

which is an EEPROM used to store the Emerson/Liebert/SICE software passport
identification. Amongst other things this configures the micro’s programmable
ports P0-P5 to the parameters required to operate in this application. Without this
security interlock the micro-controller will be inactive. An inverse output, [V-
AUX>, goes high on reset and is connected to D22 and D23 in the ‘Inverter/Recti-
fier Start/Stop control logic’ and ‘Load transfer control logic’ (circuit diagram
sheet 3). This resets the logic latches (Emergency Stop, DC Overvolts, etc.) and
re-applies the ‘run’ signals to the rectifier, inverter and static switch.
Note: the reset time is determined by R157/C97, and begins when the +5V supply
rail reaches 3.6V on initial power-up.

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4.3.6 System RAM and ROM memory addressing

(circuit diagram sheet 3).
The system memory comprises 2 x 512k EPROMs (D35 & D46) and 2 x 128k
RAM chips (D28 & D40). All these devices have an 8-bit data bus output; how-
ever, the EPROMs have a 16-bit address input while the RAM chips have a 17-
bit address facility.

Random Access memory (RAM)

This is the read/write memory store; sometimes referred to as the temporary
store. Any data fed in from the peripheral devices or produced during the execu-
tion of the main program will be temporarily held in RAM – e.g. UPS setup pa-
rameters such as kVA, nominal voltages/frequency, serial number, passwords,
etc. This is a ‘volatile’ location, meaning that when power is lost to the component
all data is also lost; thus the need for the on-board back-up Ni-Cad battery.

Read Only Memory (ROM)

This memory contains the ‘operating system program’, or firmware, which is ba-
sically a sequence of instructions to be carried out by the micro-controller in order
to make it perform the actions required of it. Upon power-up the micro is pointed
to the first instruction as part of its reset initialisation, and from then on it steps
through the programmed instructions in a sequence dictated by various events and
monitored conditions.
ROM is ‘non-volatile’, which means that it does not lose its memory contents in
the event of a loss of power.

Address decoding – D33 / D19

The ‘output enable’ pins of all four memory devices are controlled by the control
bus [RD-> line, therefore when this line goes low the processor can read the data
held at the current address from any of the devices. The purpose of the ‘address
decoding’ circuit is to enable the microcontroller to select which of the EPROM
or RAM devices it wishes to communicate with at any given time. The memory
devices’ ‘chip select’ inputs are controlled by a circuit comprising an ASIC i.c.
(D33) and two gates of D19.
D33’s inputs are connected to A0, A14....A17, and several control bus signals –
as described in paragraph 4.3.2. – which are all controlled by the microcontroller.
The output signals, [CSEP1L->, [CSEP1H->, [CSRA1L->, and [CSRA1H->, adopt logic
states determined directly by these processor-controlled inputs and are synchro-
nised to the processor operation by the 20MHz [CLKOUT> signal.
When low, [CSEP1L-> and [CSEP1H-> enable the EPROM devices via their ‘chip
enable’ inputs (pin 20), while [CSRA1L-> and [CSRA1H-> perform a similar func-
tion on the RAM chips.
The [READY> output from D33 is fed back to the micro to inform it that the appro-
priate addresses have been loaded into D33’s internal latches (See paragraph
4.3.2).
As D19 provides the ‘chip select’ inputs to the RAM devices it is powered from
the battery-backed RAM supply to prevent RAM data corruption on UPS power
down.
Note: jumper X14 provides a test facility for bench testing only and all links
should be open during normal operation.

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AX15 & AX16 configuration links

The UPS Logic Board has been designed to facilitate future software upgrades by
including configuration links to permit the addressing of alternative memory de-
vices. These links affect the routing of the AX15 and AX16 address lines, and the
standard configuration is shown below in Figure 7-19.
In the standard configuration the signals annotated [PIN29EP> and [PIN3EP> are
connected to the EPROMs’ A14 and A15 inputs and are therefore driven by the
AX15 and AX16 address lines respectively. The [PIN31RAM> signal (AX16) is
connected to the A15 input of both RAM devices and the [PIN3RAM> signal
(AX15) is connected to the RAM ‘write enable’ inputs.

Figure 7-19: AX15 & AX16 decoding configuration links

X19 X13
1 1
2 2
[PIN31RAM>
3 3

[AX16>
X22 X21
1 1
2 2
[PIN3EP> [PIN3RAM>
3 3

X23 X24
5 5
4 4
3 3
[AX15>
2 2
[PIN29EP> [PIN29RAM>
1 1
[WRX–>

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4.3.7 Basic system control logic

The term ‘Basic System Control Logic’ is used here to described the signals gen-
erated by the UPS Logic Board which control the ‘start/stop’ commands to the
rectifier and inverter, the battery circuit breaker ‘trip’ control, and the ‘load trans-
fer’ control between inverter and static bypass.
These functions are controlled by two ASICs annotated D22 and D23 which are
shown on sheet 3 of the diagram and also in greater detail in Figure 7-20 below.

Figure 7-20: Basic system control logic (internal detail)

ALARMS_RES 1
D21-2
V-AUX 2
D22
N24-6
M_RESET 3
ESD 4
R97 17 M_ESD
N15-8 D26-5
M-ESD 5
R86 SCR_OPN 6
N15-14
MNS_L 7
Z39 16 MSCROP
D26-4
0V MSCROP 8
BAT_MA 9
D34-12
15 M_BAT_MA
D26-6
M_BAT_MA 11

12 BLK_MAINS
SEQ_MAINS 13 D26-3
D26-7
BLK_BYP 14

R112

R111

R113
C64
C63

C62
0V

M_BAT_MA 1 D23
IB_OPEN 2
D21-16 12 BAT_TRP X2-54
V-AUX 3
M_ESD 4

BLK_INV_M 5 15 ON_INV X3-36

INV_ON 6
D21-5

RST_OUT 8
D21-6
16 INV_L X5-16
L_INV 9 X5-31
D21-9
BLK_MAINS 7
+5V 17 MNS_L X5-17

L_MAINS 11
D21-12
Q1 S1 Q2 Q3
R109

R154

R106

R110

19 ON_REC X1-36
BLK_REC_M 13
14
0V REC_ON
D21-15
Block Manual Block Block
Bypass RESET Inverter Rectifier

[Link] D22 Functional description

D22 provides four status signals which are used by D23 and are also monitored
by the microcontroller via the data bus input buffers.

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Emergency shutdown [ESD>

The ‘emergency shutdown’ signal [ESD> to D22-4 is driven by external circuitry
and connected via X2-52 (sheet 7) as a logic high when the emergency shutdown
is applied. When D22 pin 4 goes high it drives pin 17 high which then provides a
latching input back to D22 pin 5 which holds pin 17 high until the reset circuit is
activated – the latching signal is debounced by R112/C63. D22 pin 5 also turns
off the bypass enable signal via D22 pin 12 – i.e. turns off the bypass SCRs.
In addition to providing the latching function, the ‘high’ output from D22-17,
[M_ESD>, is fed to the microcontroller via data bus buffer D26-5 to initiate alarm
#63 [CUT-OFF: EMERGENCY] (See paragraph [Link]) and it is also connected
to D23-4 where it:
• Trips the battery circuit breaker ([BAT_TRP> = 0)
• Turns Off (stops) the rectifier ([ON_INV> = 0)
• Turns Off (stops) the inverter ([REC> = 0)

Static switch SCR open

The ‘static switch SCR open’ signal [SCROPN> to D22-6 is produced by N15-8 or
N5-14 (sheet 6) as a logic high when the detection circuits ‘sees’ a voltage drop
across one of the static bypass SCRs. When D22 pin 6 goes high it drives pin 16
high (provided the ‘load on mains’ input to D22-7 is also high) which then pro-
vides a latching input back to D22 pin 8. This inhibits the output on pin 12 and
holds pin 16 high until the reset circuit is activated – the latching signal is de-
bounced by R111/C62. Thus [SCROPN> will block the bypass only when the load
is ‘on-bypass’.
In addition to providing the latching function, the ‘high’ output from D22-16,
[MSCROP>, is fed to the microcontroller via the data bus buffer D26-4 (See para-
graph [Link]) where it annunciates alarm #15 [I/P: SCR CUT OFF].

DC Overvoltage – fast
The ‘DC Fast Overvoltage’ signal [BAT_MA> to D22-9 is driven by N13-8 (sheet
5) and is logic high when a DC busbar (battery) overvoltage condition (>620V) is
present. When D22 pin 9 goes high it drives pin 15 high which then provides a
latching input back to D22 pin 11 which holds pin 15 high until the reset circuit
is activated – the latching signal is debounced by R113/C64.
In addition to providing the latching function the ‘high’ output from D22-15,
[MBATMA>, is fed to the microcontroller via the data bus buffer U26-6 to initiate
alarm #58 [DC BUS: FAST OVERV.] (See paragraph [Link]) and it is also con-
nected to D23-1 where it:
• Trips the battery circuit breaker ([BAT_TRP> = 0)
• Turns Off (stops) the rectifier ([ON_INV> = 0)
• Turns Off (stops) the inverter ([REC> = 0)

Static bypass inhibit

The [BLKMNS> output from D22 pin 12 goes high when D22 detects any condition
which requires the load to be prevented from being connected to the static bypass
supply. This output is fed to the microcontroller via the data bus buffer U26-3 to
initiate alarm #17 [BYPASS INHIBIT REM.] (See paragraph [Link]) and is also
connected to D23-7 where, when ‘high’, it inhibits the ‘load-on-bypass’ com-
mand [MNS_L> output from D23 pin 17.
The [BLKMNS> signal can be driven high by any of the following conditions:

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• ‘Emergency shutdown’ latch set (D22-5 = high)

• ‘Bypass SCR open’ latch set (D22-8 = high)
• 1 second Power-up reset pulse (D22-5 = positive-going pulse)
• Static bypass mains phase sequence error (D22-13 = high) from D27 on
diagram sheet 5
• ‘Manual block’ applied from switch Q1 (D22-14 = high)

RESET
There are three reset signal sources applied to D22:
• D22-1 receives a logic high reset signal from the microcontroller via the
data bus output buffer D21-2 (See paragraph [Link]). This is a software
reset programmable via the Operator Control Board
• D22-2 receives a logic high reset pulse when the board is powered up (See
paragraph 4.3.5)
• D22-3 is driven high when the manual reset button (S1) is pressed

The ‘Emergency shutdown’, ‘Bypass SCR open’ and ‘DC overvoltage’ latches
described above are all reset when any one of the three reset inputs are active.
Note: the ‘power-up’ reset signal to D22-2 also resets the [BLKMNS> output from
D22-12, described immediately above.

[Link] D23 Functional description

D23 provides five major control signals, as detailed below:

Battery circuit breaker trip

A logic low [BATTRP> output from D23-12 trips the battery circuit breaker via
X2-54 (sheet 7), which is connected to the High Voltage Interface Board (See sec-
tion 7 paragraph 2.3.8). This signal can be driven low by any of the following
D23 inputs:
• ‘DC Fast Overvoltage’ to D23-1 ([MBATMA> = 1) from D22-15 (see above)
• ‘Emergency shutdown’ to D23-4 ([MSDD> = 1) from D22-17 (see above)
• ‘Power-up reset’ to D23-3 (see above)
• ‘Software trip’ to D23-2 – [IBOPEN> generated by the microcontroller and
connected via the data bus output buffer D21-16 (See paragraph [Link]).
Note: This signal trips the battery breaker on low DC voltage as follows:
– UPS on less than 15% load = 330V
– UPS on greater than 15% load = 360V
The low voltage trip is programmable via the Operator Control Panel Set-
Up parameters, and is adjustable between 1.6V/cell and 1.69V/cell. The
30Volt window at the 15% level is not adjustable.

Inverter Start/Stop (On/Off)

The [ON-INV> output from D23-15 is connected to the Inverter Logic Board via
X3-36 (sheet 7) where it controls the inverter ‘Start/Stop’ status. A logic low
[ON-INV> signal commands the inverter to ‘Stop’ and can be effected by any one
of the following D23 inputs (conversely, all the following inputs must be in their
‘healthy’ low state in order for the inverter to run):
• ‘DC fast overvoltage’ (>620V) to D23-1 – ([MBATMA> = 1) from D22-15
(see above)
• ‘Emergency shutdown’ to D23-4 – ([MSDD> = 1) from D22-17 (see above)
• ‘Power-up reset’ to D23-3 (see above)

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• ‘Software control’ to D23-6 – [INV-ON> generated by the microcontroller

and connected via the data bus output buffer D21-6 (See paragraph
[Link]). This signal is ‘low’ to inhibit the inverter and ‘high’ to enable it.
When this signal is actively blocking the inverter (i.e. low) it initiates
alarm #31 [INVERTER: OFF REM.].
• ‘Manual inverter block’ to D23-5 – logic high from the manual inverter
inhibit switch Q2. If the [ON-INV> signal at D23 pin 5 is active (low),
blocking the inverter, alarm #30 [INVERTER: OFF] will be active. Note
that alarm #31 will be disabled if alarm #30 is active. Alarm #31 can be
interpreted that the inverter has been selected off, while alarm #30 sug-
gests that the inverter has been turned off for some other reason.

Rectifier Start/Stop (On/Off)

The [ON-REC> output from D23-19 is connected to the Rectifier Logic Board via
X1-36 (sheet 7) where it controls the rectifier ‘Start/Stop’ status. A logic low
[ON-REC> signal turns OFF the rectifier and can be effected by any one of the fol-
lowing D23 inputs (conversely, all the following inputs must be in their “healthy”
state in order for the rectifier to run):
• ‘DC Fast Overvoltage’ (>620V) to D23-1 – ([MBATMA> = 1) from D22-15
(see above)
• ‘Emergency shutdown’ to D23-4 – ([MSDD> = 1) from D22-17 (see above)
• ‘Power-up reset’ to D23-3 (see above)
• ‘Software control’ to D23-14 – [REC-ON> generated by the microcontrol-
ler and connected via the data bus output buffer D21-12 (See paragraph
[Link]) this signal is ‘low’ to inhibit the rectifier and ‘high’ to enable it.
When this signal is actively blocking the rectifier (i.e. low) it initiates
alarm #20 [RECTIFIER: OFF].
• ‘Manual rectifier block’ to D23-13 – logic high from the manual rectifier
inhibit switch S2. If the [ON-REC> signal at D23 pin 19 is active (low),
blocking the rectifier, alarm #22 [RECTIFIER: BLOCK] will be active.
Note that this will be disabled if alarm #21 is active. Alarm #21 can be
interpreted that the rectifier has been selected off via the Operator Control
Panel, while alarm #22 suggests that the rectifier has been turned off for
some other reason

Load transfer control

The transfer control logic within D23 is interlocked such that the ‘load on invert-
er’ [INV_L> and ‘load-on-bypass’ [MNS_L> commands are mutually exclusive.
[INV-L>: This output, from D23-16, goes high to transfer the load to the inverter
and is connected to the Static Switch Driver Board via X5-15 (sheet 7), where it
turns off the static switch (disconnecting the load from the bypass supply) and en-
ergises the ‘inverter-side’ contactor (K1) driver circuit.
It is also connected to the Inverter Logic Board, via X3-31 where it triggers the
latches within D11 which makes the inverter voltage track the bypass supply volt-
age for 100ms (See section 5 paragraph 3.3.3). This is done to provide a smooth
transfer from bypass to inverter and reduce the wear on the ‘inverter-side’ contac-
tor (K1).
In order for D23 pin 16 to go high, D23 requires pin 8 ([RSTOUT>) to be low and
pin 9 ([L-INV>) high. Both these signals are produced by the microcontroller and
connected to D23 via the data bus output buffer D21 (See paragraph [Link]).

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[RSTOUT> is a 1 second hold-off command issued by the microcontroller when it

is performing its initialisation checks during power-up; and [L-INV> is the ‘trans-
fer-load-to-inverter’ command issued when all its software-controlled parameters
have been verified (e.g. Inverter voltage OK, Sync OK etc.).
[MNS-L>: This output, from D23-17, goes high to transfer the load to the
bypass and is connected to the Static Switch Driver Board via X5-17 (sheet 7),
where it turns on the static switch driver circuit, connecting the load to the bypass
supply. It is also connected to D22-7 where (when low) it disables the ‘bypass
SCR open’ input to D22-6 when the load is not connected to the bypass supply.
In order for D23 pin 17 to go high D23 requires:
• pin 7 to be low (i.e. no [BLKMNS> from D22)

AND
• either pin 8 [RSTOUT> to be high – not requesting ‘load-on-inverter’
OR
pin 11 ([L-MNS>) high – requesting ‘load-on-bypass’.

The signals to pins 8 and 11 are produced by the microcontroller and connected
to D23 via the data bus output buffer D21 (See paragraph [Link]). [RSTOUT> is
a 1 second hold-off command issued by the microcontroller when it is performing
its initialisation checks during power-up; and [L-MAINS> is the “transfer-load-to-
bypass” command issued when all its software-controlled parameters have been
verified for appropriate action (e.g. Critical bus volts not OK, overload, bypass
volts OK etc.).

4.3.8 CAN bus communications drivers and control logic

(circuit diagram sheet 3).
The CAN bus communications system is described in paragraph 5.3.9. (Operator
Logic Board).

4.3.9 Real-time clock (RTC)

(circuit diagram sheet 3)
The MC68698 (D18) is a peripheral device which contains a real-time clock/cal-
endar, a 32 x 8 bit static RAM, and a synchronous, serial, three-wire interface for
communicating with the micro-controller. As it’s title suggests, the real time
clock accurately counts seconds, minutes, hours (AM/PM), Day-of-the week,
date, month and year (including auto-incrementing leap-year). In the UPS Logic
Board application it provides ‘date stamping’ to the Operator Control Panel mes-
sages and ‘service data’ as entered via the Maintenance Menu Screen (see para-
graph [Link] on page 2-40). The device operates from the Ni-Cad back-up
battery to maintain its time-keeping function and prevent data loss when the gen-
eral +5V control power is turned off. It also contains many other circuit functions,
such as an alarm facility, watchdog timer etc. which are not used in this applica-
tion but may be mentioned briefly in the following description.

Power supply details

D18 is powered from the Ni-Cad-backed [VRAM> supply which is available at all
times provided jumper X31 is made 1-2 (See paragraph 4.3.4). This supply is
connected to pin 16 (Vcc), pin 13 (Vbatt) and also, via an R-C delay circuit
(R1087/C54), to pin 10 (POR). The general +5V control power rail is also moni-
tored by the device at pin 12 (VSYS).

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The delayed input to pin 10 is seen as a Power On Reset (POR) and resets the
device by briefly holding pin 10 low while the device is powered-up. Note that as
the battery-backed supply is present at all times, this is effectively a ‘once-only’
reset that takes place when X13 is initially made (i.e. battery connected) and is not
affected by subsequent application/removal of the UPS Logic Board’s +5V con-
trol power supply.
The board’s +5V supply rail is monitored at D18 pin 12; and when the voltage at
this pin is less than 0.7V above the Ni-Cad voltage (pin 16) the device switches
to a low-power standby mode whereby it maintains its time-keeping function but
internally inhibits the serial communication facilities with the micro-controller.
This prevents the passage of invalid or spurious data while the micro-controller is
powering-down and so prevents RTC data corruption.

Clock control
The RTC’s internal timer operation can be controlled from one of two sources;
i.e. either from an external crystal-controlled clock reference or a 50/60Hz mains-
derived sinusoidal signal. In this particular application an external crystal is used
and the 50/60Hz input to pin 11 (LINE) is grounded via R107.
For crystal operation pins 14 and 15 are connected to a 32.768kHz, 1.048576kHz,
2.097152kHz or 4.194304kHz crystal, as shown on the circuit diagram. A pro-
grammable internal divider circuit enables the particular external clock frequency
to be scaled down to that used by the internal logic. The internal clock signal is
made available at pin 1 (CLKO) but in this particular application is not used, and
remains unterminated.

Serial communications interface

Four lines, connected to pins 4 to 7, implement a bi-directional communications
interface with the micro-controller, and allow the micro to write configuration and
control data to the RTC and read the ‘time’ and register data. As described above,
such communication is inhibited if the UPS Logic Board’s +5V power rail is un-
available.
The [ORCS> input to pin 7 (SS) is seen as a ‘chip select’ input in this application
and must be held high while either a read or write event is taking place. Data is
input (written) to the RTC by [ORDI> to pin 5; and output (read) from the device
by [ORDO> from pin 7. In each case the data takes the form of a serial data stream
clocked in/out by the ‘serial clock’ signal [ORSK> applied to pin 4. Note that all
four of these signals are under direct control of the micro-controller and applied
to the data bus via the buffers shown on diagram sheet 4.

Other connections
The functions connected to pin 2, pin 3 and pin 9 are not used in this particular
application and these pins are tied to their default logic levels as shown.

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Section 7:

4.3.10 Data bus buffers ‘chip select’ decoding

The data bus communicates with the peripheral circuits and devices via 16 octal
buffers which are selected in ‘pairs’ to provide a 16 bit data bus transfer. The mi-
crocontroller selects a particular buffer-pair by appropriately addressing the ‘chip
select’ decoding circuit (D52) which then ‘enables’ the required buffers. Details
of the digital signals handled by each buffer are provided in the following para-
graphs.

Figure 7-21: Data bus buffer control (block diagram)

D8 D17
[CSIN1-> OE CP <CSOU1-]

D2 D25
OE CP

D1 D9
[CSIN2-> OE CP <CSOU2-]

D26 D21
OE CP

D51 D50
[CSIN3-> OE CP <CSOU3-]

D60 D55
OE CP

D7 D54
[CSDIS-> CP CP <CSOU4-]

D10 D56
CP CP
DATA
BUS
Control Bus
Microcontroller
Address Bus

AX11 1 12
[CSDIS->
AX12 2 13
[CSIN1->
AX13 3 14
[CSIN2->
AX14 4 15
[CSIN3->
5 16
AX15 D52 [CSOU1->
AX16 6 17
[CSOU2->
AX17 7 18
[CSOU3->
[RDX-> 8 19
[CSOU4->
[WRX-> 9

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4.3.11 Data bus input buffers

(diagram sheet 4).
Digital signals which are read by the microcontroller as part of its control function
are connected to the data bus via six type HCT 245 octal bus transceivers (See Ap-
pendix A.1) which are accessed in pairs to provide a 16-bit data transfer (See
Figure 7-21). The buffers ‘data direction’ pins are held permanently high, there-
fore the data flow is fixed from ‘A-to-B’ in each device. ‘Chip select’ signals from
D52 are connected to the buffers ‘output enable’ pins which provides the means
for the micro to select each pair of devices as required.
The remainder of this sub-section lists the digital signals connected to the data bus
through the bus input buffers, and provides signal details where appropriate.

[Link] Buffer D8 – activated by CSIN1

XRADT1
Source: Sheet 7 X1-31
Description: From the Power Rectifier overtemperature sensing device – this
input is not normally used and is held permanently low by jumper X10 (1-2) on
the Rectifier Logic Board. If used, in an overtemperature situation this input ini-
tiates alarm #24 [RECTIFIER: OVERTEMP.] and the rectifier and inverter are
shut-down 1 minute later accompanied by alarm #62 [CUT-OFF: OVERTEMP].
This alarm must be reset by pressing the manual reset push-button.

OVLREC
Source: Sheet 7 X1-32
Description: Rectifier Overload – this input goes high when the rectifier is op-
erating in input current limit mode (H6 illuminated on the Rectifier Logic Board)
– (See section 4 paragraph [Link]).
This initiates alarm #23 [RECTIFIER: I/P LIMIT].

BLKREC
Source: Sheet 7 X1-33
Description: Rectifier Blocked – this input goes high when the Rectifier Logic
board is in its ‘stop’ mode (See section 4 paragraph 2.3.6). This can be due to the
Rectifier Logic Board detecting an internal fault or a ‘stop’ (block) command
issued by the UPS Logic Board (See paragraph [Link]).
The internal fault channel is triggered by either: incorrect phase rotation; Rectifi-
er Logic Board power supply failure; or low input voltage (-20%). The external
fault channel initiated by the UPS Logic Board will be accompanied by alarm #21
[RECTIFIER: OFF REM.] or alarm #22 [RECTIFIER: BLOCK] (See paragraph
[Link]).

SEQREC
Source: Sheet 7 X1-34
Description: Rectifier input phase sequence error – this input goes high when
the Rectifier Logic board phase sequence monitor detects an error on the incom-
ing 3 phase mains supply (H8 illuminated on the Rectifier Logic Board) (See sec-
tion 4 paragraph [Link]).

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IN-LOW
Source: Sheet 7 X1-35
Description: Rectifier input undervoltage – this input goes high when the Rec-
tifier Logic board input voltage monitor detects a -20% undervoltage condition on
the incoming 3 phase mains supply (H9 illuminated on the Rectifier Logic Board)
(See section 4 paragraph [Link]).

XATI1 / XATI2 / XATI3

Source: Sheet 7 X2-40 / 41 / 42
Description: Not used – no connection on High Voltage Interface Board.

[Link] Buffer D2 – activated by CSIN1

SW-REC
Source: Sheet 7 X2-43
Description: Rectifier input switch monitor – this input goes low when the rec-
tifier input mains power switch is closed. This signal passes through the High
Voltage Interface Board (See section 7 paragraph 2.3.7). When the input switch
is open, this signal initiates alarm #04 [RECTIF. BREAKER OPEN].

SW-IN
Source: Sheet 7 X2-44
Description: Static Bypass switch monitor – this input goes low when the Static
Bypass mains power switch is closed. This signal passes through the High Volt-
age Interface Board (See section 7 paragraph 2.3.7). When the bypass switch is
open, this signal initiates alarm #02 [BYPASS BREAKER OPEN].

SW-BYP
Source: Sheet 7 X2-45
Description: Maintenance Bypass switch monitor – this input goes low when
the Maintenance Bypass switch is closed. This signal passes through the High
Voltage Interface Board (See section 7 paragraph 2.3.7). When the maintenance
bypass switch is closed, this signal initiates alarm #06 [ON MANUAL BYPASS].

SW-OUT
Source: Sheet 7 X2-46
Description: Output switch monitor – this input goes low when the Output
switch is closed. This signal passes through the High Voltage Interface Board
(See section 7 paragraph 2.3.7). When the output switch is open, this signal ini-
tiates alarm #03 [OUTPUT BREAKER OPEN].

FUSINV
Source: Sheet 7 X2-48
Description: Not used - held permanently low due to link fitted to connector
X16 on the High Voltage Interface Board (see main equipment wiring diagrams).
If used, this input monitors the inverter fuse and on fuse failure initiates alarm #38
[INVERTER: FUSE FAIL].

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FUSREC
Source: Sheet 7 X2-49
Description: Not used - held permanently low due to link fitted to connector
X17 on the High Voltage Interface Board (see main equipment wiring diagrams).
If used, this input monitors the rectifier (input) fuses and on fuse failure initiates
alarm #25 [RECTIFIER: FUSE FAIL].

FUSBAT
Source: Sheet 7 X2-50
Description: Battery fuse monitor – this input goes high if the battery fuse rup-
tures (See section 7 paragraph 2.3.15).
The fuse is detected by a micro-switch located on the fuse which, when activated,
initiates alarm #57 [BATTERY: FUSE FAIL].

TH
Source: Sheet 7 X2-51
Description: Inverter thermostat monitor – this input goes high if an inverter
thermostat opens (overtemperature > 90°C) (See section 7 paragraph 2.3.13). In
the event of an overtemperature situation occurring, this input initiates alarm #34
[INVERTER: OVERTEMP.] and the rectifier and inverter are shut-down 1 minute
later accompanied by alarm #62 [CUT-OFF: OVERTEMPER]. This alarm must be
reset by pressing the manual reset push-button (S1).

[Link] Buffer D1 – activated by CSIN2

SW-BAT
Source: Sheet 7 X2-53
Description: Battery circuit breaker monitor – this input goes low when the Bat-
tery switch (or contactor) is closed. This signal passes through the High Voltage
Interface Board (See section 7 paragraph 2.3.7). When the battery switch is open,
this signal initiates alarm #05 [BATTERY BREAKER OPEN].

OVLINV
Source: Sheet 7 X3-32
Description: Inverter Overload – this input goes high when the inverter is oper-
ating in current limit mode (H14 illuminated on the Inverter Logic Board) – (See
section 5 paragraph 3.3.7). In an Overload condition, this signal initiates alarm
#33 [INVERTER: [Link]].

BLKINV
Source: Sheet 7 X3-33
Description: Inverter Blocked – this input goes high when the Inverter Logic
Board is in its ‘stop’ mode (See section 5 paragraph 3.3.8). This can be due to the
Inverter Logic Board detecting an internal fault or a ‘stop’ (block) command
issued by the UPS Logic Board (See paragraph [Link]). The internal fault chan-
nel is triggered by either: IGBT desaturation, ribbon cable disconnected, Inverter
Logic Board power failure. The external fault channel initiated by the UPS Logic
Board will be accompanied by alarm [#30], [#31] or [#32].

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XINVI1
Source: Sheet 7 X3-40
Description: Not used – held permanently low due to X13 (2-3) on the Inverter
Logic Board which disables this alternative temperature sensor route. The active
thermostat route is via [TH> described earlier.

XSTAI1
Source: Sheet 7 X5-13
Description: Not used – held permanently low due to X11 (1-2) on the Static
Switch Driver Board. No thermostat is fitted on the heatsink.

XSTAT2
Source: Sheet 7 X5-14
Description: Inverter output contactor monitor – goes low when the inverter
output contactor is closed (load on inverter) and is used by the transfer control
logic software routine.

LINK X12
Source: On-board jumper X12
Description: Not used.

[Link] Buffer D26 – activated by CSIN2

MRESET
Source: Sheet 3 – switch S1
Description: RESET switch – goes high when the on-board manual reset switch
(S1) is pressed and is used by the micro to unlatch “block commands” issued by
some of its software routines.

BLKMNS
Source: Sheet 3 – D22 pin 12
Description: ‘Static Switch blocked’ monitor – this input goes high to inform
the micro that the static switch control logic (on this Board) is inhibiting the static
switch (alarm #16 [BYPASS INHIBIT]). This can be invoked by any of the follow-
ing signals applied to D22 (See paragraph [Link]).
– static switch manual inhibit switch (Q1) closed
– bypass phase sequence error detected
– emergency shutdown operated (latched)
– open circuit SCR (latched)
– UPS Logic Board power supply failure

MSCROP
Source: Sheet 3 – D22 pin 16
Description: ‘Static Switch SCR open circuit’ monitor – this input goes high to
inform the micro that an open circuit static switch SCR has been detected (on this
Board) (alarm #15 [I/P: SCR CUT-OFF]). This signal is latched within D22 and
must be reset using S1 to return to normal conditions.

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M-ESD
Source: Sheet 3 – D22 pin 17
Description: ‘Emergency shutdown’ monitor – this input goes high to inform
the micro that an emergency shutdown (Emergency Stop) has been applied (See
paragraph [Link]) (alarm [#63] [CUT-OFF: EMERGENCY]). This signal is
latched within D22 and must be reset using S1 to return to normal conditions.

MBATMA
Source: Sheet 3 – D22 pin 15
Description: DC Overvoltage – this input goes high to inform the micro that a
‘DC Overvoltage’ has been detected (See paragraph [Link]) (alarm [#58]
[DC BUS: FAST OVERV.]). This signal is latched within D22 and must be reset
by S1 to return to normal conditions.

SEQMNS
Source: Sheet 5 – D34 pin 10
Description: Bypass phase sequence error – this input goes high to inform the
micro that a ‘Bypass phase sequence error’ has been detected (See paragraph
[Link]). Note that the Rectifier Logic Board detects a phase sequence error on
the UPS (rectifier) input mains supply (See section 4 paragraph [Link]). A phase
sequence error initiates alarm [#14] [I/P: PHASE [Link]] and also enables
alarm [#16] [BYPASS INHIBIT] via the micro.

EEDO
Source: Sheet 2 – D20 pin 4
Description: Output from the security EPROM to initiate the micro-controller.

DRDO
Source: Sheet 3 – D18 pin 6
Description: Real Time Clock output (See paragraph 4.3.9).

[Link] Buffer D51 – activated by CSIN3

PAIN1 to PAIN8
Source: Sheet 7 – X7
Description: Data from parallel control bus – not used in a ‘single-module’ in-
stallation. The Parallel Logic board interfaces with the micro via this buffer and
is active only in the “1+1” and “multi-module” system configurations

[Link] Buffer D60 – activated by CSIN3

BLK-SYN
Source: Sheet 7 – X8 pin 11
Description: Sync disable – this is an input from the optional ‘remote alarm’s
board’ (AS400 interface board) which goes high (+5V) when the UPS is “ON-
GENERATOR” – and is normally used to prevent the inverter synchronising to a
frequency-wild standby generator. The On Generator status signal is applied as a
closed contact across the Remote Alarms Board terminal block X5 pins 3-4.

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Note: The response to the “ON-GENERATOR” event is programmable via the Op-
erator Control Panel FUNCTION software screen which allows three separate
functions to enabled/disabled:
• Synchro Block – is concerned with the [BLK-SYN> signal mentioned here
and, when enabled, prevents the inverter from tracking the bypass fre-
quency when it is being provided by the standby generator.
• Charge Inhibit – is concerned with the battery recharge current limit
function which, when enabled, reduces the RECTIFIER current limit by
15%.
• Current Limit – is concerned with the rectifier input current limit
[XRADD1> function which, when enabled, reduces the input current limit
by 35%.
The reduced current limit functions are employed to lower the potential
maximum current demand if the standby generator is undersized.

BLK-EXT
Source: Sheet 7 – X8 pin 12
Description: From external alarms (AS400 interface board). This input pro-
vides a means of allowing the inverter to be turned OFF/ON from an external
signal via the Remote Alarms Board. The ‘Block’ (OFF) signal is applied as a
closed contact across the Remote Alarms Board terminal block X5 pins 1-2.
Note: Jumper X6 on the Remote Alarms Board must be selected 2-3 in order to
enable this function.

BLK-01
Source: Sheet 7 – X8 pin 9
Description: From external alarms (AS400 interface board) Not used.

BLK-CHG
Source: Sheet 7 – X8 pin 10
Description: Rectifier Disable – This input provides a means of allowing the
rectifier to be turned OFF/ON from an external signal via the Remote Alarms
Board. The ‘Block’ (OFF) signal is applied as a closed contact across the Remote
Alarms Board terminal block X5 pins 1-2.
Note: Jumper X6 on the Remote Alarms Board must be selected 1-2 in order to
enable this function.

Links X26
Source: Sheet 4 jumper X26
Description: The four sections of jumper X26 are detailed in a Table on the cir-
cuit diagram sheet 1 and summarized below:

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Table 7-15: X26 Jumper details

LINK 1-2 Open Auto-transfer mode enabled (“on-line” operation).

(Standard) Automatic load transfer from bypass to inverter when
the inverter is available – i.e. the inverter is the pre-
ferred supply source

Closed Manual-transfer mode enabled (“off-line” operation).

Automatic load transfer from bypass to inverter only
when the bypass is unavailable – i.e. the bypass is the
preferred supply source. Note: there will be a 3-cycle
break on transfer to inverter,

LINK 3-4 Open “Inverter voltage fail lockout monitor” disabled

Closed “Inverter voltage fail lockout monitor” enabled. i.e. The

(Standard) inverter is given 5 seconds to reach nominal voltage
otherwise it is latched OFF.

LINK 5-6 Open Enables the “Event History” monitor to store up to a

(Standard) maximum of 10 alarms.

Closed Resets the “Event History” monitor. Note: After the 10th
“event”, the monitor buffer is full an cannot store any fur-
ther “events”. The buffer should be reset to 0 after each
maintenance or commissioning to enable new “events”
to be captured.

LINK 7-8 Open Password protection enabled.

(Standard)

Closed Password protection disabled

4.3.12 Data bus output buffers

(circuit diagram sheet 4).
Digital signals generated by the microcontroller as part of its control function are
fed to the peripheral circuits via 10 type-74C273 octal latches (See Appendix A.2)
which are accessed in pairs to provide a 16-bit data transfer (See Figure 7-21).
The ‘chip select’ signals from D52 provide the latch clock signals and data is
therefore transferred through the latches when the appropriate ‘chip select’ signal
switches from low to high. A logic low [RSTDX-> reset signal is connected to all
the data bus output buffers via jumper X25 (3-2) and drives all their outputs low
when applied. [RSTDX-> is produced by the microcontroller (See paragraph 4.3.3)
and shown on the circuit diagram sheet 2.
The remainder of this sub-section lists the digital signals connected through the
latches, and provides signal details where appropriate.

[Link] Buffers D7 and D10– activated by CSDIS

These two devices connect the data bus output to the two on-board 7-segment di-
agnostic displays (H11 & H12). For a detailed description of the displayed param-
eters (see paragraph 4.3.17 on page 7-126).

[Link] Buffer D17 – activated by CSOUT1

XRADD1
Destination: Sheet 7 – X1 pin 37

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Description: Reduced current limit – when this output goes high it reduces the
Rectifier Logic Board’s input current limit threshold by 35% (See section 4 par-
agraph [Link]).
Conditions: This software-selectable output is activated when the UPS is run-
ning on ‘standby generator’ as described on page 7-103 ([BLK-SIN>).

REC-B & REC-A

Destination: Sheet 7 – X1 pin 38 / 39
Description: Charge mode selection – these two outputs are connected to a de-
coder on the Rectifier Logic Board where they invoke one of four permissible
charge modes (see section 4 table 4-3).
Conditions: These outputs select Test, Boost, Float and Manual charge modes
in response to selections made on the Operator Control Panel. The automatic
Boost mode parameters, i.e. duration and threshold, are also operator-defined –
(see paragraph 2.5.6 on page 2-53). LEDs on the Rectifier Logic Board illumi-
nate to indicate the active charge mode.

XAT01 & XATO2

Destination: Sheet 7 – X2 pin 55 / 56
Description: Not used

INV-F
Destination: Sheet 7 – X3 pin 37
Description: Base frequency selection – informs the Inverter Logic Board’s
‘staircase pattern generator’ of the UPS system’s base frequency (i.e. 50/60Hz).
(See section 5 paragraph 3.3.2).
Conditions: This output is high for 50Hz and low for 60Hz as selected on the
Operator Control Panel – see ‘Selecting the UPS SETUP parameters’ in the com-
missioning procedure (see paragraph [Link] on page 2-35).

INV-B & INV-A

Destination: Sheet 7 – X3 pin 38 / 39
Description: Inverter working voltage selection – these two outputs are con-
nected to a decoder on the Inverter Logic Board where they select one of four per-
missible charge modes (see section 5 table 5-10).
Conditions: The logic states of these outputs are determined by the working
voltage selected by the operator – see commissioning procedure (see paragraph
[Link] on page 2-34). LEDs on the Inverter Logic Board illuminate to indicate
the active selection.

[Link] Buffer D25 – activated by CSOUT1

XSTAO1 & XSTAO2

Destination: Sheet 7 – X5 pin 19 / 20
Description: Not used

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RE485-
Destination: Sheet 7 – D58 pin 2
Description: This output selects the ‘Read Enable’ pin of D58, which is an
RS485 communications driver connected to the parallel interface connector X7
pins 59/60 – not used.

OE485
Destination: Sheet 7 – D58 pin 3
Description: This output selects the ‘Output Enable’ pin of D58, which is an
RS485 communications driver connected to the parallel interface connector X7
pins 59/60 – not used.

TP5
Destination: Sheet 7 – X18 pin 5
Description: Not used (test point for system software).

OUTBAT
Destination: Sheet 2 – V152
Description: This output, when high, ‘enables’ the on-board Ni-Cad battery
charger.
Conditions: This output enables the Ni Cad battery charger if its voltage falls
to 2.8Vdc and disables it again once the battery voltage rises to 3.6V.
Note: when the charger is enabled the [BACK-UP BATTERY LOW] warning is an-
nunciated (alarm [#76] active).

[Link] Buffer D9 – activated by CSOUT2

EECS / EESK / EEDI

Destination: Sheet 3 – D18 pin 7
Description: These outputs control the data acquisition of EEPROM D20

ORCS
Destination: Sheet 3 – D18 pin 7
Description: Real Time Clock (RTC) ‘chip select’ (See paragraph 4.3.9).

ORSK
Destination: Sheet 3 – D18 pin 4
Description: Real Time Clock (RTC) ‘serial communications clock input’ (See
paragraph 4.3.9).

ORDI
Destination: Sheet 3 – D18 pin 5
Description: Real Time Clock (RTC) ‘serial data input’ (See paragraph 4.3.9).

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SELANA / SELANB
Destination: Sheet 6
Description: These two outputs are connected to the address inputs of three 2-
pole multiplexers which select the analogue signals for the microcontroller’s A/D
inputs – e.g. selecting the analogue signals for display purposes (kVA values are
calculated in software using V x I).

[Link] Buffer D21 – activated by CSOUT2

ALMRES
Destination: Sheet 3 – D22 pin 1
Description: Software controlled RESET – This output, when high, resets the
Emergency Shutdown, DC Overvoltage and Open SCR fault latches within D22.
Conditions: This facility is not programmed into the current software and it is
therefore not used.

INV-ON
Destination: Sheet 3 – D23 pin 6
Description: ‘Inverter ON’ request – This output, when high, requests D23 to
issue an [ON_INV> command signal which is connected to the Inverter Logic
Board and turns ON the inverter – provided other D23 inputs are correct (See par-
agraph [Link]).
Conditions: (see paragraph 7.2.3 on page 7-160)

RSTOUT
Destination: Sheet 3 – D23 pin 8
Description: Software controlled “reset” – When low, this output resets the
“load-on-inverter” signal the [L_INV> and “load-on-mains” signal [L_MAINS>.
Conditions: The signal deactivates the above signals while the micro is reload-
ing the default parameters, which can be activated using the RELOAD UPS DATA
selection on the Operator Control Panel menu screens. Note: the load should
always be on the “Maintenance Bypass” before performing a “system reload”.

L-INV
Destination: Sheet 3 – D23 pin 9
Description: ‘Load-on-inverter’ request – This output is interlocked with the
[RSTOUT> signal within D23 (See paragraph [Link]). In order to command the
‘load-on-inverter’ this signal must be high and the [RSTOUT> signal low.
Conditions: (see paragraph 7.2.10 on page 7-180)

LMAINS
Destination: Sheet 3 – D23 pin 11
Description: ‘Load-on-bypass (mains)’ request – In order to command the
‘load-on-bypass’ this signal and the [RSTOUT> signal must be high– see also
[RSTOUT>, above.

Conditions: (see paragraph 7.2.10 on page 7-180)

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REC-ON
Destination: Sheet 3 – D23 pin 14
Description: ‘Rectifier ON’ request – This output, when high, requests D23 to
issue an [ON_REC> command signal which is connected to the Rectifier Logic
Board and turns ON the rectifier (provided other D23 inputs are correct (See par-
agraph [Link])).
Conditions: (see paragraph 7.2.2 on page 7-158).

IBOPEN
Destination: Sheet 3 – D23 pin 2
Description: Trip battery circuit breaker– This output, when high, requests D23
to issue a [BAT_TRP> command signal which is connected to the High Voltage In-
terface Board and turns OFF the battery circuit breaker driver transistor.
Conditions: This signal is software driven via a programmable parameter set-
ting entered from the Operator Control Panel to trip the battery circuit breaker
when the battery is fully discharged (see page 2-37). The Emergency Shutdown
and DC Overvoltage inputs to D23 pins 4 and 1 also trigger the battery trip signal
when active (See paragraph [Link]).

TP6
Destination: Sheet 7 – X18 pin 6
Description: Not used (test point for system software).

[Link] Buffer D50 – activated by CSOUT3

PAOUT1....PAOUT8
Destination: Sheet 7 – X7
Description: Data to parallel control bus – used in ‘parallel’ installations only.

[Link] Buffer D55 – activated by CSOUT3

PAOUT9 / PAOUT10
Destination: Sheet 7 – X7
Description: Data to parallel control bus – not used in a ‘single-module’ instal-
lation.

OUT-03
Destination: Sheet 7 – X8 pin 25
Description: Output to I/O interface (remote alarms, AS400 interface etc.).
Conditions: Not used

MNS-KO
Destination: Sheet 7 – X8 pin 26
Description: Output to I/O interface (remote alarms, AS400 interface etc.).

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Conditions: Logic high if mains (bypass) supply error – i.e. overvoltage [#11],
undervoltage [#12], absent [#10] or bypass blocked [#17].

BATED
Destination: Sheet 7 – X8 pin 27
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Logic high if the battery voltage falls to its end-of-discharge level
[#56] – as set by operator through Operator Control Panel (see page 2-37). It is
also active if the battery breaker is open [#05] or the battery fuse is open [#57].

CHG-INH
Destination: Sheet 7 – X8 pin 28
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Logic high if the battery charger is inhibited (driven by the
[BLK-CHG> signal described on page 7-104). Jumper X4 pins 1-2 must be linked
on the Alarm Board.

SWBYP
Destination: Sheet 7 – X8 pin 29
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Logic high if maintenance bypass isolator is closed – accompanied
by alarm #06 [ON MANUAL BYPASS].

OUT-01
Destination: Sheet 7 – X8 pin 23
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Not used in the present software implementation

[Link] Buffer D54 – activated by CSOUT4

OUT-02
Destination: Sheet 7 – X8 pin 24
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Not used in the present software implementation

OVT-BAT
Destination: Sheet 7 – X8 pin 18
Description: Output to I/O interface (remote alarms, AS400 interface, Remote
Alarms Monitor etc).
Conditions: Logic high in the event of battery overtemperature – Not used in
the present software implementation.

SYN-KO
Destination: Sheet 7 – X8 pin 16

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Description: Output to I/O interface (remote alarms, AS400 interface, Remote

Alarms Monitor etc).
Conditions: Logic high if the inverter is unsynchronised to the bypass supply
– i.e. if the phase displacement is more than ±9°. This condition will initiate alarm
#35 [INVERTER: OUT OF SYNC].

ALL-GEN
Destination: Sheet 7 – X8 pin 17
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: This is the “Common Alarm” output to the Alarm Board and is
active if any of the following alarms are present: [#05], [#06], [#10], [#11], [#12],
[#16], [#17], [#24], [#33], [#34], [#52], [#56], [#57], [#66].

A400ON
Destination: Sheet 7 – X8 pin 31
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: This alarm is active when the load is on the UPS (inverter or by-
pass) and is interlocked with the Maintenance Bypass being closed.

A400UF
Destination: Sheet 7 – X8 pin 32
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Condition: Mains Failure alarm; enabled by alarm [#01] and active when [#22]
is energised.

A400BL
Destination: Sheet 7 – X8 pin 33
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Low Battery warning; enabled by alarm [#01] and active when
[#56] is energised.

A400BY
Destination: Sheet 7 – X8 pin 34
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Load on Bypass; active when alarm [#18] is energised.

[Link] Buffer D56 – activated by CSOUT4

MNSREC
Destination: Sheet 7 – X8 pin 20
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Rectifier input voltage failure – active when H9 is illuminated on
the Rectifier Logic Board.

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CS-KO
Destination: Sheet 7 – X8 pin 19
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Bypass-side Static Switch blocked – goes high if a fault is detected
on the static switch (alarm [#16] present).

BAT-DSC
Destination: Sheet 7 – X8 pin 13
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Battery discharging – active when alarm [#22] is present.

OVL
Destination: Sheet 7 – X8 pin 14
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Overload – active when alarm [#33] or [#66] is present.

OVT-DIS
Destination: Sheet 7 – X8 pin 15
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Overtemperature – active when alarm [#24] or [#34] is present.

OVT-AMB
Destination: Sheet 7 – X8 pin 30
Description: Output to I/O interface (remote alarms, AS400 interface etc).
Conditions: Output Air overtemperature – not used.

XINV01
Destination: Sheet 7 – X3 pin 24
Description: Mains error inhibit to Inverter Logic Board transfer control.
Conditions: On the Inverter Logic Board a circuit within D11 provides a con-
trol signal [RIF> which briefly transfers the voltage reference signal to the bypass
supply just before the ‘inverter-side’ contactor is closed; (see paragraph 3.3.3 on
page 5-65). This signal, [XIN01>, goes high to inform the Inverter Logic Board of
a mains (bypass) voltage error and prevents the switch-over to the bypass supply
reference from taking place; and so prevents the inverter locking to an out-of-spec
voltage.

TP7
Destination: Sheet 7 – X18 pin 7
Description: Not used (test point for system software).

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Section 7:

4.3.13 Frequency sensing and control signals

Figure 7-22: Frequency synchronisation control

X2
X18-2 Bypass supply R-phase
D42 62 D53 5 8Vp-p
15 VI-A 15 voltage sensing
F-INM F-IN

X18-3 X3 X4 phase
63 4 align
16 FRFB
34 34
BACKM BACK R247

D17 INV-F 44
15 INV-F D1
37 37
50 /60 Hz
DATA selection 27
Clock Frequency
MICROCONTROLLER

BUS signals 26
Divider
D54 SYNC-KO to tri-wave
6 generator
Sync error
detection
43

50/60Hz
288kHz
CLK
D60 2 BLK-SYN
4
Sync Inhibit Phase
9
Locked
VCO
Loop
X18-4
64 D59 15 14 13
SYNCM 5 SYNC SYNC Phase
35 35
Master Freq Comparator
50/60Hz signal
synchronised to reference for D6 3
bypass (when present) Inverter Osc
(correction)
UPS Logic Board Inverter Logic Board

[Link] Frequency control principles

The inverter frequency is determined by the VCO section of a phase locked loop
i.c. (D6) on the Inverter Logic Board which provides a 288kHz (nominal) clock
signal to a frequency-divider (within D1) which then clocks the multiplexers in
the ‘reference voltage generator’ circuit (See section 5 paragraph 3.3.2).

Base frequency selection

The inverter base frequency is selected via the Operator Control Panel during
commissioning and is read by the microcontroller through the CAN bus. The
micro responds by appropriately setting the [INV-F> output from D17-15 – Low =
50Hz and High = 60Hz. This is connected to the ‘frequency divider’ on the Invert-
er Logic Board where it determines the division factor – i.e. when [INV-F> is low
the 288kHz VCO output is divided by 5760 to produce a 50Hz output at D1-26/
27; when [INV-F> is high the division is 4800 and produces a 60Hz output.

Frequency synchronisation
It is desirable that the inverter output is synchronised to the bypass supply under
normal operating conditions as this enables a ‘closed’ load transfer to be carried

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out in the event of a UPS fault – where-by the static switch SCRs are turned on at
the same time as the inverter contactor is opened, and the load does not experience
a supply break.
If the inverter is not synchronised to the bypass supply there could be a large volt-
age difference across the static switch SCRs while the load is ‘on-inverter’ (i.e.
SCRs OFF) which might damage the UPS/load equipment during a subsequent
‘closed’ transfer: in such circumstances an ‘open’ transfer takes place if the UPS
develops a fault, where-by the inverter contactor is opened prior to turning ON
the static switch SCRs. This causes a load supply break of up to 1 second, which
is an inbuilt feature designed to avoid load damage.
The frequency synchronisation control mechanism is quite complex and effec-
tively based on two nested phase locked loops. The inner loop comprises D6 on
the Inverter Logic Board and the outer loop is functionally provided by the micro-
controller, under software control.

[Link] Frequency sync control and operation

Inverter Logic Board phase-locked-loop (assuming 50Hz operation.)

The ‘phase comparator’ section of D6 compares the 50Hz output from D1-26,
connected to D6-3, with a frequency reference signal annotated [SYNC> which is
produced by the microcontroller and connected to D6-14 (available at test point
X18-4). If the ‘phase comparator’ detects any phase difference between these two
signals its output at D6-13 will modify the VCO’s frequency in such a way as to
make the ‘frequency divider’ output at D1-26 match the [SYNC> signal frequency
– i.e. the VCO frequency will be modified until the ‘phase comparator’ within D6
sees no error between these signals, whereupon the circuit can be considered to
be phase-locked. Thus the inverter frequency tracks the [SYNC> signal ‘reference’
frequency.

[SYNC> signal generation (assuming 50Hz)

The microcomputer monitors the bypass supply R-phase waveform [VI-A> via a
comparator which extracts its frequency information, [F-INM>. This signal can be
seen at X18-2 as a squarewave coinciding with the bypass supply R-phase zero-
crossing points. The Inverter Logic Board frequency divider’s 50Hz output (D1-
27) is also monitored and is available at X18-3, annotated [BACKM>.
Under software control, the micro operates on these two signals in the same way
as described above for the Inverter Logic Board’s phase-locked-loop. That is, it
performs the ‘phase comparator’ and ‘VCO’ functions described above and pro-
duces a 50Hz output, [SYNC>, whose absolute frequency is controlled by the de-
tected phase difference between [F-INM> and [BACKM> – i.e. the width of the pulse
is directly proportional to the amount of phase difference.

Example of sync control

The overall operation of the synchronisation control circuits can best be explained
by example. Consider the case where the bypass frequency suddenly jumps from
50Hz to 50.5Hz:
1. The micro will sense the jump in bypass frequency through a rise in [F-INM>
to 50.5Hz.
2. The micro will sense a phase error between [F-INM> and [BACKM> due to their
frequency difference and will ramp-up the [SYNC> signal frequency because it
senses that the bypass frequency is higher than that of the inverter.

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3. The ‘phase comparator’ in the Inverter Logic Board’s phase-locked-loop will

see the ramping [SYNC> frequency and detect that it is now higher than the
frequency divider’s ‘50Hz’ output.
4. The phase comparator error output (pin 13) will call for an increase in VCO
frequency, which will thus increase the ‘frequency divider’ clock rate and
thereby demand an increased inverter frequency.
5. The two ‘50Hz’ outputs from the frequency divider also ramp-up in line with
the inverter frequency and have two affects:
a) The increasing output at D1-26 is fed back to the phase-locked-loop
(D6-3) where it maintains phase-lock – i.e. it ties the clock frequency to
the [SYNC> signal and maintains close tracking of this signal.
b) The increasing output from D1-27 is fed back to the microcontroller via
R247 where it allows the phase error function to maintain a close check on
the ‘bypass/inverter’ frequency and phase relationship.
6. When the inverter frequency has risen to match the 50.5Hz bypass frequency,
and the [F-INM> and [BACKM> signals are in phase:
a) The [SYNC> frequency will stop ramping up and remain at 50.5Hz, syn-
chronised to the bypass supply due to the action of the micro.
b) The VCO clock frequency will remain constant – i.e. 290.88kHz
(5760 x 50.5 – as 5760 is the divider factor for 50Hz systems).
c) The outputs from D1 pins 26 and 27 will be steady at 50.5Hz and synchro-
nised to the [SYNC> signal.
7. If [SYNC> is synchronised to the bypass supply (6a) and the frequency divider
outputs/inverter are synchronised to the [SYNC> signal (6c) then this results in
the inverter being effectively synchronised to the bypass supply, are required.
Important notes: The above description requires qualification by the follow-
ing notes.
a) The internal mechanism of the frequency divider chip ties its ‘50Hz’ out-
puts to the zero-crossing points of the R-phase inverter voltage. Thus, as
the micro uses the bypass R-phase supply as its frequency sensing source,
this effectively ensures that the inverter and bypass supplies are synchro-
nised correctly from a phase alignment viewpoint.
b) To aid description the above example assumed that the bypass frequency
underwent a stepped change; however, in practice any change in bypass
frequency is likely to occur gradually: in which case the circuit dynamics
are usually able to maintain a phase-locked condition during the period of
change, resulting in the inverter frequency tracking the bypass frequency
at all times without incurring a detectable phase error.
c) The synchronising ‘window’ and ‘slew-rate’ are adjustable and selected
from the Operator Control Panel setup menus. The ‘window’ defines the
limits to which the inverter is allowed to track the bypass frequency and
normally set to ±2%; while the ‘slew-rate’ defines the maximum permitted
rate-of-change of inverter frequency and is usually set to 0.1Hz/s.– i.e. this
determines the fastest rate of change of bypass frequency tolerated by the
synchronisation circuit whilst maintaining sync.
If the bypass frequency goes outside the permitted window the inverter
frequency will return to its base frequency and await the mains return

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CHAPTER 4 - UPS Logic Board (4550004 E)

within the sync window, where-upon it will re-synchronise. An

[INVERTER: OUT OF SYNC] (alarm #35) warning will be displayed
while this situation is in effect.
d) In the event of a bypass supply failure the microcontroller will drive its
[SYNC> output to the ‘centre’ frequency – i.e. 50Hz.

Sync phase adjustment

R247 is connected to a ‘phase-shift’ circuit on the Inverter Logic Board and pro-
vides the means for trimming any error in the phase relationship between the in-
verter [BACKM> and bypass [F-INM> sense signals once the sync control circuit is
phase-locked – due mainly to component tolerances. Therefore, once the inverter
is synchronised this resistor can be adjusted to reduce the residual phase differ-
ence between the inverter R-phase output and the bypass R-phase supply.

[Link] Non-Sync detection and alarm

An alarm condition [SYN-KO> is flagged by the microcontroller when it detects
that the [BACKM> and [F-INM> signals are more than 11° out-of-phase. This is com-
municated to the Operator Logic Board via the CAN bus and also, via D54-6, to
the I/O interface connector X8-16 where it can be used to provide a remote alarms
indication (sheet 7). [SYN-KO> is ‘high’ when a non-sync condition is present.

[Link] External ‘sync inhibit’

In certain circumstances it may be necessary to inhibit the synchronisation loop –
for example when supplying the UPS from a stand-by generator whose frequency
regulation is poor. This can be achieved by an external input via the I/O connector
X8-11 [BLK-SYN> which is connected to the microcontroller via D60-2. This input
must be taken ‘high’ to inhibit the synchronisation function (See paragraph
[Link]).
Note: The control can be activated only after being ‘enabled’ in the Function pa-
rameter software setup screen (see paragraph [Link] on page 2-43).

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4.3.14 Analogue signal processing

The UPS Logic Board monitors the UPS input voltage, output voltage, inverter
voltage, battery voltage, output current and battery current. These inputs are proc-
essed by analogue circuits (sheets 6 & 7) which provide appropriate signals for
the microcomputers A/D input port. In some cases the inputs are also converted
to digital alarm/status signals which are connected to the micro via the data bus.

[Link] Bypass voltage signal processing

Figure 7-23: Bypass voltage sensing block diagram

+5V
+2.5V
Line-Neut Line-Line
0V
3-Phase VIABM
Bypass N6 N29 To A/D
Volts Buffer Sum-Amp VIBCM
Multiplexers
Sense VICAM (Display uses)
REF-2 (2.5V)
8Vp-p [SVI> To SCR OPEN det.
N29d
Rectifier
[SVIM> To A/D Multiplexers
(Bypass volts monitor)

A-Ph
N14
Filter [F-IN> To Micro
(sync control - bypass R-ph)

B-Ph N14 D27 [SEQMNS>

Filter Ph-Seq
To Micro
(Phase Sequence
error detector)

Voltage sensing
The bypass voltage sense signals ([VI-A> - [VI-C>) are developed on the High Volt-
age Interface Board (See paragraph 2.3.6) and connected via X2 pins 15, 16, 17
to N6b/c/d which are unity-gain buffers (sheet 5). The signals at N6 outputs there-
fore equate to approximately 1% of the bypass supply line-neutral voltage (e.g.
2.4Vrms at 240V working) and are connected to several blocks as shown in
Figure 7-23.

Voltage monitoring
N29a-c take the line-to-neutral sense voltages produced by N6 and converts them
into line-to-line sense voltages suitable for connecting to the microcontroller A/D
inputs. Taking N29a as an example; this amplifier differentially sums the [VI-A>
and [VI-B> signals from N6 and produces the [VIABM> L-L signal. However the
amplifier attenuates the resultant signal to about 30% (e.g. 1.38V for 240V work-
ing) due to its feedback resistance ratios: also, the non-inverting input is connect-
ed to VREF-2 (2.5V reference voltage) rather than to the 0V rail, which therefore
applies a 2.5V offset to [VIABM>. Thus in a 240V system working at nominal volt-
age [VIABM> is approximately 3.9Vp-p centred on a 2.5V reference. This signal
sits well within the microcontroller’s A/D 0-5V input level, and is shown connect-
ed to the A/D multiplexer circuit (sheet 6).
Note: if the bypass voltage is missing [VIABM> will be 2.5Vdc due to the absence
of any ac signal.

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Bypass frequency and phase sequence monitors

The bypass R-phase signal [VI-A> from N6-14 is connected to a zero-crossing cir-
cuit comprising N14a/d which produces a squarewave output [F-IN> at D34-6
which coincides with the R-phase zero-crossing points. This signal is used by the
microcontroller in its frequency synchronisation control (See paragraph
[Link]).
A similar squarewave coinciding with the S-phase is obtained via N14b/c and
buffered by D34-8. These two squarewave signals are connected to a D-type flip-
flop (D27) which detects their phase relationship. Under normal circumstances
the R-phase signal should lead that of the S-phase; therefore when the rising-edge
R-phase signal clocks D27, its data (D) input should be ‘low’, producing a perma-
nent ‘high’ on its Q output which inverted to a ‘low’ [SEQMNS> signal at D34-10.
In the event of a phase sequence error, D27 will have a permanent ‘low’ clocked
through to its Q output and produce a ‘high’ [SEQMNS> signal.
[SEQMNS> is connected to the microcontroller via the data bus buffer D28-7
where it flags a phase rotation error – [I/P: PHASE [Link]] alarm #14 (See
paragraph [Link]).

3-phase voltage monitor

A full-wave, three-phase diode bridge comprising V34-V36 & V40-V42, produc-
es a dc voltage proportional to the full three-phase supply which is fed to N29d.
This amplifier attenuates the signal by 55% due to the values of the feedback re-
sistors; therefore the output at N2-14 is approximately 2.5Vdc at nominal working
voltage. Note that this is a ripple voltage since there is very little capacitance
around the amplifier. Thus if any bypass phase voltage goes out of tolerance (e.g.
±10% window) the detector will sense the error. It does not require all three
phases to go outside the error window.
N2-14 provides signals to two other areas: [SVIM> is connected to the microcon-
troller A/D input via the multiplexer circuit shown on sheet 6 and used by the
micro to monitor the bypass voltage for a each individual phase (e.g. ±10% volt-
age error); and [SVI> is connected to the circuit (also on sheet 6) which detects an
open circuit static switch SCR.

[Link] Inverter voltage sensing

Figure 7-24: Inverter voltage sensing block diagram

error detected on individual phase
8Vp-p
2.2Vdc
Line-Neut
3-Phase
Inverter N3a-c N3d
Volts Buffer Rectifier [SVINVM>
Sense To A/D Multiplexers

Voltage sensing
The inverter voltage sense signals ([VINV-A> - [VINV-C>) are developed on the High
Voltage Interface Board (See paragraph 2.3.5) and connected via X2 pins 18, 19,
20 to N3a-c which are unity-gain buffers (sheet 5). The signals at N3 outputs
therefore equate to approximately 1% of the inverter line-neutral voltage. A full-
wave, three-phase diode bridge produces a dc voltage proportional to the full
three-phase output which is then fed to N3d. This amplifier attenuates the signal

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by 55% due to the values of the feedback resistors; therefore the output at N3-14
is approximately 2.5Vdc at nominal voltage, and connected to the microcontroller
A/D input via the multiplexer circuit shown on sheet 6. This is a ripple voltage as
described previously, and is monitored by the inverter voltage error software
function (i.e. ±10%).

[Link] Battery (bus) voltage sensing

Figure 7-25: Battery voltage sensing block diagram

[VBM>
3.25Vdc To A/D Multiplexers
@ 446V(bat)
N13a N13c
[V-B> Buffer Comparator [BAT-MA>
DC Overvoltage (Fast)
(set to 620V(bat))

Battery volts monitor

The DC busbar (battery) voltage sense signal [V-B> is developed on the High Volt-
age Interface Board (See paragraph 2.3.3) and connected via X2 pin 27 to N13a
which is a unity-gain buffer (sheet 5). The signal sensitivity is set on the High
Voltage Interface Board to approximately 7.3mV per Volt(bat) therefore [VBM> is
about 3.255V at nominal 446V float charge voltage. This signal is connected to
the microcontroller A/D input, via the multiplexer circuit shown on sheet 6, where
it is used by several software functions, such as: display metering; slow DC over-
voltage (max 2.4V/cell window); Low Battery warning (1.82V/cell window); End
of Discharge (1.67V/cell window); and % charge/autonomy time algorithms.

DC Overvolts detection (Fast)

[VBM> is also monitored by N13c, which is configured as a comparator and used
to detect a DC Bus overvoltage condition. N13c has a fixed threshold which op-
erates ([BAT-MA> goes high) when [VBM> reaches approximately 4.45V, which
equates to a DC Bus voltage of around 620Vdc.
[BAT-MA> is connected to the ‘Basic System Control Logic’ where it trips the bat-
tery circuit breaker, turns off the rectifier and inverter, and trips a latch (See par-
agraph [Link]). In an overvoltage situation – [DC BUS: FAST OVERV.] alarm
#58 – the ‘Basic System Control Logic’ responds by issuing a ‘high’ [MBATMA>
signal which flags the micro-controller via data bus buffer D26 (See paragraph
[Link]).

[Link] Battery current sensing

Figure 7-26: Battery current sensing block diagram

REF-2 (2.5V)

N13b
[I-B> Buffer [IBM>
To A/D Multiplexers

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Battery current monitor

The battery current sense signal [I-B> is developed on the High Voltage Interface
Board (See paragraph 2.3.22) and connected via X2 pin 31 to N13b which has a
gain of approximately1.5 (sheet 5). The signal sensitivity is set on the High Volt-
age Interface Board by jumper X38 and the output [IBM> is connected to the
micro-controller A/D input via the multiplexer circuit shown on sheet 6 where it
is used for display purposes, and % charge and Autonomy Time algorithms.

[Link] Output voltage sensing

Figure 7-27: Output voltage sensing block diagram

+5V
+2.5V
Line-Line
0V
3-Phase VOABM
Output N5 N31 To A/D
Volts Buffer Sum-Amp VOBCM
Multiplexers
Sense VOCAM (Monitoring &
display)
REF-2 (2.5V)
8Vp-p [SVOM> To A/D Multiplexers
N15a
(Critical bus monitor)
Rectifier
N15b-d [SCROPN>
Compar-
ator To Micro
[SVI>
(SCR open cct.)

Line-Neut
VOAM
N30 To A/D
Buffer VOBM
Multiplexers
VOCM (monitoring & display)
REF-2 (2.5V)

Voltage sensing
The bypass voltage sense signals ([VO-A> - [VO-C>) are developed on the High
Voltage Interface Board (See paragraph 2.3.6) and connected via X2 pins 21, 22,
23 to N5a-c which are unity-gain buffers (sheet 6). The signals at N5 outputs
therefore equate to approximately 1% of the output line-neutral voltage (e.g. 2.4V
(8Vp-p) at 240V) and connected to several blocks as shown in Figure 7-27.

Voltage monitoring
The signals from N5a-c are connected to two sets of buffers which provide line-
to-neutral and line-to-line monitoring voltages which are connected to the micro-
controller A/D inputs via the multiplexer circuit shown on sheet 6 and used for
metering & display purposes.
L-N voltage monitoring. is provided by N38a-c which attenuate the voltage
sense signals by approximately 55% and also applies a 2.5Vdc offset due to the
non-inverting connection being terminated at VREF-2 (2.5V reference voltage). At
240V nominal voltage the monitor output signals [VOAM>, [VOBM>, VOCM> are
therefore 1Vrms (2.8Vp-p) centred about a +2.5V reference which sits well within
the microcontroller’s A/D 0-5V input level.
Note: if the output voltage is missing [VOAM> etc. will be 2.5Vdc due to the ab-
sence of any ac signal.

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L-L voltage monitoring. is provided by N31a-c. Taking N31a as an example;

this amplifier differentially sums the A and B phase signals from N5 and produces
the [VOABM> L-L signal. However, the amplifier attenuates the resultant signal by
about 70% (e.g. 1.38V for 240V working) due to its feedback resistance ratios:
also, as with the L-N circuit described above, the non-inverting input is connected
to VREF-2 (2.5V reference voltage) rather than to the 0V rail, which applies a 2.5V
offset to [VOABM>. Thus in a 240V system working at nominal voltage [VOABM>
is approximately 3.9Vp-p centred on a 2.5V reference.

3-phase voltage monitor

A full-wave, three-phase diode bridge comprising V29-V31 etc, produces a dc
voltage proportional to the full output three-phase supply which is fed to N15a.
This amplifier attenuates the signal by 55% due to the values of the feedback re-
sistors; therefore the [SVOM> output at N15-1 will be approximately 2.5Vdc at
nominal working voltage. Note that this is a ripple voltage since there is very little
capacitance around the amplifier. [SVOM> is connected to the microcontroller A-
to-D inputs via the multiplexer circuit shown on sheet 6. This is used by the
micro-controller as a critical bus voltage error monitor (factory set to ±10%) for
transfer functions.

Open Circuit Static Switch SCR detection

As shown in Figure 7-27, the output voltage (3-phase) sense signal [SVOM> and
bypass voltage (3-phase) sense signal [SVI> are both connected to the Static
Switch ‘SCR open circuit’ detector.

[Link] Output current sensing

Figure 7-28: Output sensing block diagram

REF-2 (2.5V)

3-Phase
Output N4a-c N4d
Current Buffer Sum-amp [IONM>
Sense To A/D Multiplexers
(Overload & Timers)

[IOAM>
[IOBM> (Display Metering)
[IOCM>

Output current monitor

The UPS output current sense signals ([IO-A> - [IO-C>) are developed on the High
Voltage Interface Board (See paragraph 2.3.19) and connected via X2 pins 32,
33, 34 to N4a-c which attenuate the sense signals by approximately 75% and also
applies a 2.5Vdc offset due to the non-inverting connection being terminated at
VREF-2 (2.5V reference voltage). The output signals [IOAM> etc. are connected to
the microcontroller A/D inputs via the multiplexer circuit, and the 2.5V offset is
sufficient to make the a.c. current signal sit within the 0-5V A/D input voltage
range. These signals are by the micro’s ‘overload’ algorithm (i.e. 150% for 1
minute, 125% for 10 minutes, 110% for 1 hour, 101% for 9 hours. They also rep-
resent the values shown on the Operator Control Panel ‘Measurements’ display
screen.

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N4d calculates the neutral current by differentially summing the three line cur-
rents – in a balanced three phase system the algebraic sum of the currents should
equal zero, thus if the system is unbalanced then the amount of imbalance repre-
sent the current flowing in the neutral path. The neutral current signal [IONM> is
also subject to the 2.5V offset and applied to the microcontroller A/D inputs via
the multiplexers in the same way as the line current signals.

[Link] Analogue signal monitoring multiplexers

The microcontroller has ten A/D inputs ([AN0> to [AN9>).
[AN6> to [AN9> are fed by fixed inputs signal sources; however, [AN0> to [AN5>
are fed via a series of multiplexers which allow the micro to select from various
signal sources. Three type 4052 multiplexers are used for this purpose, each ad-
dressed by two signals ([SELANA> and [SELANB>) produced by the microcontrol-
ler via data bus buffer D9 (See paragraph [Link]). Sheet 6 contains the
multiplexer circuit and illustrates the various monitored signals connected to their
data pins (See Appendix A.3). The multiplexers are inhibited if the -12V power
supply monitor detects an undervoltage by applying a logic high [FL-12-> to the
multiplexer inhibit inputs (pin 6) (See paragraph [Link]).
Note: the inputs annotated [T1> - [T4> are temperature sensing inputs – refer to the
High Voltage Interface Board description (See paragraph 2.3.12).
Note: the micro can access the A/D signals in parallel and where necessary can
calculate values for the display – e.g. kW = V x I.

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Section 7:

4.3.15 Power supplies

[Link] General description and voltage regulators

The UPS Logic Board ±12V power supply rails are provided from two parallel
sources and will be available if either source is live. The first source is from the
Rectifier Logic Board, which is itself powered from the AC-DC Power Supply
and available whenever the UPS input (rectifier) supply is live (see paragraph 2.1
on page 3-5); the second if from the Inverter Logic Board, which is powered from
the DC-DC Power Supply and is available whenever the rectifier is working or
the batteries are connected to the DC Busbar (see paragraph 3.1 on page 3-7).
From the UPS Logic Board the ±12V supplies are passed directly to all the re-
maining circuit boards and the communications port etc.

[Link] Reference voltage generators

Several devices require a stable +5V power supply which is provided by a simple
3-terminal +5V regulator (N1), shown on sheet 7.
In addition to the +5V power supply rail, there are also two reference voltage gen-
erators on the circuit board. One generates a regulated +5V, [VREF>, from the
+12V line and the other generates a regulated 2.5V output, [VREF-2>, from the
+5V supply rail. These reference voltages are used in conjunction with the micro-
controller’s A/D analogue inputs and are shown on sheet 5 of the circuit diagram.

+5V reference voltage [VREF>

This provides a stable power supply for the A/D converters within the micro
which is necessary for them to maintain their conversion accuracy.

2.5V reference voltage [VREF-2>

The micro-controller’s internal A/D converters operate on stable 0V and +5V
power rails, as described above. Therefore if an AC signal is to be monitored (e.g.
bypass voltage), or a positive-and-negative going DC signal (e.g. battery current),
then a 2.5V offset is required shift the 0V point of the monitored signal into the
centre of the A/D converters’ input working range. This enables the A/D circuit
to convert both halves of an AC waveform and both positive and negative transi-
tions of a dc signal voltage.

[Link] -12V undervoltage detector

Comparator N45a (sheet 5) serves as a -12V supply rail monitor and detects when
the -12V is less than approximately -9.8V. The operating threshold for this circuit
is set by V70 which applies a zener referenced voltage across R242/243 from the
+12V rail and under normal conditions sets N45-3 at about 1.86V. The -12V rail
is monitored via a resistor divider (R240/241) which is fixed at +3V at one end by
V70.
Due to the chosen resistor ratios, the voltage at N45-2 rises above 1.86V when the
-12V rail is less than -9.8V, at which point N45-1 switches low and produces a
logic high [FL-12-> signal and low [FL-12>.
When [FL-12> goes low it inhibits the back-up battery voltage sense signal to the
microcontroller via D44, as shown on diagram sheet 2 (See paragraph 4.3.4).
When [FL-12-> goes high is disables the microcontroller’s A/D input multiplexers,
as shown on sheet 6 (See paragraph [Link]).

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CHAPTER 4 - UPS Logic Board (4550004 E)

[Link] +12V undervoltage detector

Comparator N45b (sheet 5) serves as a +12V supply monitor. The operating
threshold for this circuit is set by [VREF-2> which applies a stabilised +2.5V to
N45-6, at about 1.86V. The +12V rail is monitored via a resistor divider (R246/
245/R244) which pulls the input to N45-5 below the 2.5V threshold when the
+12V rail fall below the 9.8V level. When this occurs the output at N45-7 switch-
es from high to low which is reflected at D57-8 and the resulting ‘low’ [PFO> flag
resets the microcontroller via its non-maskable interrupt (NMI) (See paragraph
4.3.2). The micro jumps to a ‘save data’ subroutine as the supply rails are crash-
ing.

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4.3.16 External communications

RS232 communications
In addition to the bi-directional communication facility with the Operator Logic
Board via the CAN Bus, the microcontroller can also be accessed externally via
a standard RS232 communications connection (X9). This is designed to be used
with a portable computer for diagnostic, calibration and configuration purposes.
Communication takes place through D16 which is a standard RS232 line driver/
receiver connected to the micro via [TXO0> and [RXO0>, as shown on sheet 7 (See
Appendix A.6).

RS-485 Parallel control communications

An RS485 communications facility is also shown on sheet 7, based around D58
(See Appendix A.5). The differential I/O bus of this device (pins 6 & 7) is connect-
ed to the Parallel Logic Board via X7 ([TXRX+>, [TXRX->).
Transmit mode. the transmit mode is enabled when [DE485> is high, whereup-
on the [TXDI> data from the microcontroller, applied to D58 pin 4, passes through
the device and drives its differential outputs as described in appendix A.5. Note
that X32 should be made in order to connect the bus termination resistor (R250)
across the transmission line to present the correct impedance to the differential
outputs.
Receive mode. the receive mode is enabled when [RE485-> is taken low, where-
upon the data on the differential I/O bus is converted into a data-stream and con-
nected to the microcontroller via [RXDI>.

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4.3.17 On board 7-segment indications summary

The following table provides a summary of the alarm codes indicated on the two
7-segment LEDs together with their alarm interpretations and associated Operator
Panel audible and visible alarm annunciations. Note that there is no on-screen
alarm history facility, but where two (or more) alarms are active simultaneously
the associated codes will be displayed in a cyclic fashion at 1 second intervals
Note: Where the fault LED state is annotated (*) this indicates that the alarm is
latched and must be reset using S1 on the UPS Logic Board

Display Alarm Messages Audible Alarm FAULT LED (red)

CODE
(Correct Meaning) (Operator Panel) (Operator Panel)

01 [ NORMAL OPERATION ] OFF OFF

02 [ BYPASS BREAKER OPEN ] Continuous ON

03 [ OUTPUT BREAKER OPEN ] Continuous ON

04 [ RECTIF. BREAKER OPEN ] Continuous ON

05 [ BATTERY BREAKER OPEN ] Continuous ON

06 [ ON MANUAL BYPASS ] Pulsed Flashing

Manual bypass breaker closed

10 [ I/P: ABSENT ] Intermittent Flashing

Bypass supply absent – i.e. <50V

11 [ I/P: OVER LIMITS ] Intermittent Flashing

Bypass supply over voltage –
upper limit set via mimic menu

12 [ I/P: UNDER LIMITS ] Intermittent Flashing

Bypass supply under voltage –
lower limit set via mimic menu

13 [ I/P: FREQUENCY ERROR] Intermittent Flashing

Bypass supply over/under freq –
window limit set via mimic menu

14 [ I/P: PHASE ROT. ERROR ] Continuous ON

Bypass phase rotation error

15 [ I/P: SCR CUTOFF ] Continuous ON *

Bypass SCR open circuit

16 [ BYPASS INHIBIT ] Pulsed Flashing

Bypass supply blocked –
hardware block on UPS Logic Board

17 [ BYPASS INHIBIT REM. ] Pulsed Flashing

Bypass blocked via operator menu

18 [ LOAD ON BYPASS ] Intermittent Flashing

19 [ BYPASS OVERTEMPERAT. ] Continuous ON

Static bypass overtemperature
warning

20 [ RECTIFIER: OFF ] Intermittent Flashing

Software block via micro

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Display Alarm Messages Audible Alarm FAULT LED (red)

CODE
(Correct Meaning) (Operator Panel) (Operator Panel)

21 [ RECTIFIER: OFF REM. ] Pulsed Flashing

Rectifier blocked via operator menu

22 [ RECTIFIER: BLOCK ] Continuous ON

Hardware block via UPS Logic Board

23 [ RECTIFIER: I/P LIMIT ] Intermittent Flashing

Rectifier input current limit

24 [ RECTIFIER: OVERTEMP. ] Continuous ON

Rectifier overtemperature

25 [ RECTIFIER: FUSE FAIL ] Continuous ON

Input fuse failure (F10,F11,F12)

30 [ INVERTER: OFF ] Intermittent Flashing

Software block via micro

31 [ INVERTER: OFF REM. ] Intermittent Flashing

Inverter blocked via operator menu

32 [ INVERTER: BLOCK ] Continuous ON

Hardware block via UPS Logic Board

33 [ INVERTER: CURR. LIMIT ] Continuous ON

Inverter 150% current limit active

34 [ INVERTER: OVERTEMP. ] Continuous ON

Inverter overtemperature

35 [ INVERTER:OUT OF SYNC ] Intermittent Flashing

Inverter unsynchronised to bypass
warning

36 [ INVERTER: OVERVOLTA. ] Continuous ON

Inverter overvolts warning

37 [ INVERTER: UNDERVOLTA. ] Continuous ON

Inverter undervolts warning

38 [ INVERTER: FUSE FAIL ] Continuous ON

Inverter fuse failure

39 [ OUTPUT: OVERVOLTAGE ] Continuous ON

Inverter overvoltage trip –
critical bus overvoltage trip to bypass

40 [ OUTPUT: UNDERVOLTAGE ] Continuous ON

Critical bus undervoltage trip to
bypass – level set via mimic menu

41 [ OUTPUT: NO VOLTAGE ] Continuous ON

UPS in off-line mode

42 [ OUTPUT: WRONG [Link] ] Continuous ON

Critical bus peak voltage error

43 [ INVERTER: WRONG FREQ ] Continuous ON

lnverter frequency error –
inverter frequency window is twice
the bypass window

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CHAPTER 4 - UPS Logic Board (4550004 E)

Display Alarm Messages Audible Alarm FAULT LED (red)

CODE
(Correct Meaning) (Operator Panel) (Operator Panel)

44 [ INVERTER: SEL. BLOCK ] Continuous ON *

Paralleling current error

50 [ BATTERY: UNDER TEST ] Pulsed OFF

Battery test in operation

51 [ BATTERY: TEST FAILED ] Intermittent Flashing *

Battery test has failed

52 [ BATTERY: DISCHARGING ] Intermittent Flashing

Battery is discharging

53 [ BATTERY: E.O.D. ] Continuous ON

Battery end_of_discharge trip –
level set via mimic menu

54 [ [Link] CHARGE ] Pulsed Flashing

Boost charge period expired

55 [ DC BUS: OVERVOLTAGE ] Continuous ON *

DC slow overvolts warning –
level set via mimic menu

56 [ DC BUS: UNDERVOLTAGE ] Continuous ON

Low battery warning –
level set via mimic menu

57 [ BATTERY: FUSE FAIL ] Continuous ON

Battery fuse (F13) failure

58 [ DC BUS: FAST OVERVOLT. ] Continuous ON *

Fast dc overvoltage –
fixed at 620V

60 [ BYPASS OVERUSE ] Continuous ON *

Transfer counter exceeded
– i.e. >8 transfers in 1 minute

61 [ CUT-OFF: OVERLOAD ] Continuous ON *

Overload timer expired

62 [ CUT-OFF: OVERTEMPER. ] Continuous ON *

Overtemperature timer expired

63 [ CUT-OFF: EMERGENCY ] Continuous ON *

“Emergency power-off” activated

66 [ OVERLOAD ] Continuous ON
Overload present (warning)

67 [ CUT-OFF: OVERLOAD ] Continuous ON *

Overload timer expired

70 [ BAD EEPROM PROGRAM. ] Pulsed ON

Start-up error – use mimic reset

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Display Alarm Messages Audible Alarm FAULT LED (red)

CODE
(Correct Meaning) (Operator Panel) (Operator Panel)

71 [ ERR. LRC PARAM.PAG1 ] Pulsed ON

Incorrect display variable

72 [ ERR. LRC PARAM.PAG2 ] Pulsed ON

Incorrect display variable

73 [ ERR. LRC PARAM.PAG3 ] Pulsed ON

Incorrect display variable

74 [ ERR LRC ALARM HIST. ] Pulsed ON

Alarm History buffer error

75 [ ERR LRC EVENT HIST. ] Pulsed ON

Alarm History buffer error

76 [ BACK-UP BATTERY LOW ] Pulsed ON

Internal PCB ni-cad battery Low

80 [ ERROR LRC TABLE ]

81 [ ERROR LRC PANEL ]

82 [ MODEM WRONG CONFIG. ]

83 [ ERROR LRC ALARM MEM. ]

84 [ MODEM NO RESPONSE ]
Modem incorrectly connected

85 [ MODEM FALSE COMMAND ]

Modem incorrectly configured

86 [ MODEM TIMEOUT TRASM. ]

Modem baud-rate error

87 [ CAN BUS NO RESPONSE ]

UPS-to-display not connected

88 [ AUTONOMY XXXX min ]

Battery autonomy time

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CHAPTER 4 - UPS Logic Board (4550004 E)

4.4 Summary information

Table 7-16: UPS Logic Board configuration jumpers

Link
Jumper Function
Position

X11 NO LINK Disable RS232 port (standard)

1-2 Enable RS232 port

X12 OPEN (standard)

1-2 Not Required

3-4 Not Required

X13 1-2 EPROM Enable

2-3 RAM Enable (standard)

X14 1-2 Not Required

3-4 Not Required Testing only

normally
5-6 Not Required open
7-8 Not Required

X15 1-2 PLL option with CAP IN

2-3 PLL option with FIN AUX (standard)

X16 OPEN CAN Bus to display disabled

1-2 CAN Bus to display enabled (standard)

X17 1-2 ALE enable data save

2-3 Power supply fail enable data save (standard)

X19 1-2 EPROM II enable (not required)

2-3 RAM II enable (not required)

X20 1-2 +5V PCB enables microprocessor ref. For VA calculations

(standard)

2-3 V ref. enables microprocessor ref. For VA calculations

X21 1-2 Not Required

2-3 RAM enable (standard)

X22 1-2 EPROM enable (standard)

2-3 Not Required

X23 1-2 Not Required

2-3 EPROM enable (standard)

3-4 Not Required

4-5 Not Required

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Link
Jumper Function
Position

X24 1-2 RAM enable (standard)

2-3 EPROM enable (not required)

3-4 RAM enable (standard)

4-5 EPROM enable (not required)

X25 1-2 Manual reset of output buffers

2-3 Microprocessor reset of output buffers (standard)

X26 1-2 Open (Standard)

Auto-transfer mode enabled (“on-line” operation).
Automatic load transfer from bypass to inverter when the
inverter is available – i.e. the inverter is the preferred supply
source.
Closed
Manual-transfer mode enabled (“off-line” operation).
Automatic load transfer from bypass to inverter only when
the bypass is unavailable – i.e. the bypass is the preferred
supply source. Note: there will be a 3-cycle break on trans-
fer to inverter.

3-4 Open
“Inverter voltage fail lockout monitor” disabled.
Closed (Standard)
“Inverter voltage fail lockout monitor” enabled. i.e. The
inverter is given 5 seconds to reach nominal voltage other-
wise it is latched OFF.

5-6 Open (Standard)

Enables the “Event History” monitor to store up to a maxi-
mum of 10 alarms.
Closed
Resets the “Event History” monitor. Note: After the 10th
“event”, the monitor buffer is full an cannot store any further
“events”. The buffer should be reset to 0 after each mainte-
nance or commissioning to enable new “events” to be cap-
tured.

7-8 Open (Standard)

Password protection enabled
Closed
Password protection disabled

X28 OPEN Power up reset enabled (standard)

CLOSED Power up reset disabled

X29 OPEN 2.5V power supply monitor enabled (standard)

1-2 2.5V power supply monitor disabled

X31 OPEN Internal battery disabled

1-2 Internal battery installed and charger enabled (standard)

X32 OPEN RS485 port disabled

1-2 RS485 port enabled (standard)

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Table 7-17: UPS Logic Board potentiometer adjustment

Potentiometer Function
R209 5 volt reference adjustment. Check at X20 pin 1
R212 2.5 volt reference adjustment. Check at anode of V45

Table 7-18: UPS Logic Board LED indication

LED Colour Function

H1 Red Internal battery charger operating

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 Section 7:

Chapter 5 - Operator Logic Board

5.1 Chapter overview

This chapter contains a circuit description of the Operator Logic Board used
across the entire 7200 Series UPS model range, and should be read in conjunction
with circuit diagram SE-4550005-F (4 pages).
Signal annotations shown on the circuit diagrams are shown in italics in the fol-
lowing text – e.g. [CLKOUT>. Where a signal is ‘active low’ it is followed by a ne-
gating symbol – e.g. [RSTD->

5.2 General description

5.2.1 Circuit board functions

The Operator Logic Board provides a microprocessor-controlled interface be-
tween the Operator Control Panel and the microcontroller-based UPS control
system on the UPS Logic Board. Its primary functions can be summarised as fol-
lows:
• Display indication–
The UPS Logic Board provides the Operator Logic Board with data per-
taining to various system operating parameters which are converted to a
format suitable for driving the Operator Control Panel LCD display.
• Operator input–
The Operator Control Panel switches are monitored by the Operator Logic
Board which converts any switch operation into a format understood by
the UPS Logic Board.
• External communications options –
The Operator Logic Board provides several external communications
facilities for use with remote alarm/control stations.
Connector X8 – provides a two-way RS232 read/write control port.
Connector X5 – provides a one-way RS232 read only control port.
Connector X5 – provides a one-way RS485 read only control port.
The board also contains an RS232/modem interface which can be used for
diagnostic purposes.
• Isolated power supply –
An isolated power supply is contained on the Operator Logic Board which
is used by the circuits associated with the communications facilities. Inter-
nal communications between the Operator Logic Board and the UPS
Logic Board is by means of a CAN bus (Controller Area Networking).
Power supply isolation increases noise immunity and helps avoid spurious
data transfer between the micro-computer systems contained on each
board.

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CHAPTER 5 - Operator Logic Board

5.2.2 Input/Output connections

Figure 7-29: Operator Logic Board connections

RS232 RS232 RS485

Modem Comms Comms
Facility (Reserved) Facility
(read/write) (read only) (read only)

X8 X5 X4

Operator Logic Board

X1 X9 X2

Isolated
CAN Bus
power supply
feed

X4 X6
Operator UPS Logic Board
Panel

The Operator Logic Board has six connectors (See Figure 7-29) whose connec-
tions are summarised below.
• X1 – Connection to the Operator Control Panel
• X2 – System control and monitoring signals to/from the UPS Logic
Board. This connection takes the form of a serial data link (CAN Bus).
• X4 – Standard RS485 comms port (read only)
• X5 – Standard RS232 comms port (read only)
• X8 – Standard RS232 comms port/modem interface available for external
control/monitoring/diagnostics facilities (read/write)
• X9 – Control power supplies (±12V) from the system control power rails
via the UPS Logic Board.

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 5.2.3

Reset
20MHz
Block Diagram

Power
Clock
X26
7200 Series UPS Service Manual

ROM RAM

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Address Bus or Data Bus
Horn

Latch
P0
X23
AX
DX
CAN D12 CAN Bus
Decode

Data
RS232 D19 P4 RS232
Read Serial Port X8
Only P3 Decode Read/
D11 Write

RS485 D20
Read LEDS
LE LEDs
Only Ds

P1 Bar Gr
Display
Switch
Latch
s Charac
he
itc
Sw X1
Switches

P5 R21
D2 = 80C166
Figure 7-30: Operator Logic Board basic block diagram

Contrast
Adjustment
SECTION 7 - UPS System Control
CHAPTER 5 - Operator Logic Board

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CHAPTER 5 - Operator Logic Board

[Link] System overview

Processor system
The Operator Logic Board control system is based on a type 80C166 microcon-
troller, as shown in Figure 7-30. This device, which is identical to that used on the
UPS Logic Board, contains six configureable ports through which it communi-
cates with peripheral circuits/devices, together with several ‘system control
lines’. It also contains several internal A/D converters, four programmable timers
and internal ROM (32k) and RAM (1k).
The ports are configured by an initialisation routine performed by the system soft-
ware on power-up and can be summarised as follows.
• Port 0
Port 0 is configured as a multiplexed Data/Address bus and is connected to
both the Address and Data bus ports of the peripheral devices through a
series of controlled latches, providing an 8-bit data bus <DX0...DX7> or 16-
bit address bus <AX0...AX15>.
• Port 1
This is configured as a 16-bit output port. Its primary outputs, [LD1> to
[LD9> drive the Operator Control Panel LEDs. Other outputs provide the
LCD display ‘read’ and ‘write’ control signals and ‘chip select’ signals for
the RS485 communications port device.
• Port 2
Three lines of this port are used in conjunction with the CAN serial data
controller. For reasons of clarity this port is not shown in Figure 7-30.
• Port 3
This port is configured to work with the internal timers and is used to con-
trol the RS232 and RS485 access, and also the audible warning sounder
associated with the UPS Alarms annunciation.
• Port 4
The lower two lines only are utilised on port 4. These provide the upper
two address lines <A16...A17> – the lower address lines <A0...A15> are pro-
vided by port 0. These lines, which do not pass through the selectable
buffers used by the lower 16 address lines, are always available and used
as inputs by the ‘address decoding’ which produce the ‘chip select’ signals
used by the various peripheral devices.
• Port 5
The lower five lines of this port <P5-0...P5-4> monitor the Operator Control
Panel switches and detects their operation.
• System control lines
In addition to the I/O ports, the microcontroller also has a control bus with
I/O lines generally associated with a microprocessor-based system; such
as a system clock, reset, address latch enable, power reset and Read/Write
control. These are connected to the peripheral devices where required.

Memory
The microcontroller uses both internal and external memory; 256k of RAM and
256k of EPROM are fitted to the board as standard and holds the system operating
software. Facilities are included on the board to allow alternative memory config-
urations to be used as described later.

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Data/Address latch & buffers

The 16-bit data/address bus is connected to the various peripheral devices and
boards via input and output data latches/buffers, as shown in Figure 7-30. These
buffers are controlled by individual ‘chip select’ select lines to direct the data flow
to/from the appropriate source, as required by the system control software.

5.3 Detailed circuit description

5.3.1 Introduction
The Operator Logic Board circuit diagram (SE-4550005-F) comprises 4 sheets.
With reference to the block diagram description, the drawings can broadly be de-
scribed as follows:
• Sheet 1 contains a ‘signal map’ identifying the functions covered on the
remaining pages. It also contains a summary chart detailing the various
configuration jumpers (X11 – X25).
• Sheet 2 contains the switched-mode isolated power supply circuit.
• Sheet 3 contains the
– basic microcontroller system.
– data bus, address bus and control bus buffers.
– address decoding.
– system RAM and ROM memory and its associated configuration links.
– power-up reset generator.
• Sheet 4 contains the
– CAN bus communications drivers and control logic.
– RS232 (modem) communications interface.
– RS485 communications interface.
– Operator Control Panel interface.

As with all micro-based system, the microcontroller’s operation is determined by

the program held in the system’s memory and, as this is hidden to the service en-
gineer, there is very little that can be done to ascertain that the board is working
correctly apart from checking the validity of its input and output signals, and other
signals generated on the board which are required by the central processor system.
The following description deals with the board on this basis, and should provide
sufficient information to allow a troubleshooting engineer to determine whether
or not the board is functioning correctly. A detailed software description is
beyond the scope of this manual.

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5.3.2 Basic microcontroller system

(circuit diagram sheet 2)

Figure 7-31: Micro system control signals

Power Supply

Clock 20 25
XTAL1 ALE Address latch enable

Control Bus
Reset 27 28
RSTIN RSTOUT Reset Out

+5V Vref 54 26
VAREF RD Read

95 Write
D2 WR

Caution When monitoring the signals described in this section it is best done with control
power only – i.e. with the UPS power sections shut down and the circuit boards
live via the control power supply. Some signals are irregular, or have very large
mark:space ratios, and are best monitored with a logic probe. The logic se-
quence/timing of these signals depend upon various circuit conditions and cannot
therefore be accurately defined; however, for field test purposes, the presence of
a ‘variable switching’ logic signal at these points would generally indicate that the
basic processor control bus is serviceable and the system software is running.

Power supply
The microcontroller is powered from the isolated +5V rail which is provided by
a switched-mode power supply circuit shown on diagram sheet 2 (See paragraph
5.3.12).

System clock (XTAL1)

A dedicated crystal-controlled clock generator (E2) provides a system clock
signal which is connected to the microcontroller pin 20. This signal is a 20MHz
squarewave switching between +5V and 0V.

System reset (RSTIN)

A one second logic low reset pulse, [RSTIN->, is applied to D42 pin 27 on power-
up from the ‘reset generator’ circuit. This can also be manually applied for trou-
bleshooting purposes by bridging and un-bridging jumper X26.

Reset out (RSTOUT)

[RSTO-> is controlled by the reset input signal, [RSTIN->, and goes high while the
input rest signal is applied. This signal is synchronised to the system clock and
returns high an integral number of clock pulses after the input reset signal is re-
moved. The [RSTO-> signal is connected to the ‘address decoder’ circuit from
where it resets the peripheral devices.
That is, upon receipt of the “wake-up” request ([RSTIN->) the microprocessor
issues a “wake-up” call ([RSTO->) to all the other relevant devices.

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Reference voltage (VAREF)

The input to D2 pin 54 (VAREF) is a reference voltage used by the internal A/D
converters; however, in this application the A/D circuits are not used and this
input is connected directly to the general +5V supply rail.

Address latch enable (ALE)

When the multiplexed Address/Data bus (port 0) carries Address information this
output goes ‘high’. This is used to control the address bus buffers as described
below.

Read (RD)
This output goes low when the processor wishes to read the data from the device
or memory location currently addressed by the address bus.

Write (WR)
This output goes low when the processor wishes to write data to the device or
memory location currently addressed by the address bus

5.3.3 Data bus, address bus and control bus buffers

(circuit diagram sheet 3.)

Overview
As described above, the microcontroller’s Port 0 acts as a multiplexed 16-bit Ad-
dress/Data bus. When this bus carries Address information the [ALE> output goes
‘high’ to enable the address bus latches (D5 and D6) whose buffered outputs are
then treated as a 16-bit address bus [AX0...AX15>. Conversely, when [ALE> is ‘low’
the bus information is interpreted as Data and connected to the peripheral devices
via an 8-bit data bus latch (D7) in conjunction with the ‘read’ [RD-> control line.

Address bus buffer

Two 74HCT573 devices serve as the address buffers (D5 & D6) – these are de-
scribed in Appendix A (See appendix A.4).
In this application the Output Enable pins are connected to a permanent logic low
(0V) and the devices are therefore permanently enabled. The Address/Data bus
contents are thus transferred to the buffers’ output when the Address Latch Enable
[ALE> signal, connected to D5/D6 pin 11, goes high.

The buffered address bus is annotated (AX0....AX15) and is shown connected to

the ROM (D8) and RAM (D9) memory. It is also connected to the peripheral de-
vices shown on the circuit diagram sheet 4.

Data bus buffer

A type 74HCT245 octal bus transceiver (D7) is employed as bi-directional buffer
between the microcontroller (D0....D7) and the data bus (DX0....DX7).
The data direction through D7 is controlled by the microcontroller’s [RD-> output.
Thus, when the microcontroller drives its [RD-> output low it sets the data direc-
tion from B to A through the buffers (See appendix A.1), which allows the data
bus contents through to the microcontroller’s data inputs. At other times, when
[RD-> is high, data flows through the buffers from A to B, allowing the micro to
place data onto the data bus which can then be written to a peripheral circuit as
required.

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Control bus buffer (diagram sheet 4)

Two 74HCT245 devices serve as the control bus buffers (D18 & D17). These are
identical to the data bus buffer but have a fixed data direction (A-to-B) as pin 1 is
permanently connected to +5V in each case. D17 interfaces the tactile switches
(ENTER, UP, DOWN) and the three mimic LEDs on the Operator Control Panel.
D18 deals with the 6-segment bargraphs (%load & autonomy time) and the con-
trol bus [RD> and [WR-> signals. The buffered control signals [RDX-> and [WRX->,
are used by various devices distributed throughout the circuit diagrams.
In all cases the above mentioned buffers have pull-up resistors connected to their
input and output pins to protect their internal logic – e.g. resistor packs R52 - R54.

5.3.4 Reset generator

(circuit diagram sheet 3.)
A purpose-designed Supply Voltage Supervisor (N4) provides the micro with a
one second logic low [RSTIN-> reset signal on power-up. This logic low pulse,
which is applied to the micro pin 27, can also be initiated manually by ‘making’
jumper X26 (1-2). It also sends a logic high reset signal [RSTO-> to the ‘address
decoding’ circuit (D10) from where it resets the peripheral devices via their ap-
propriate ‘chip select’ or ‘chip enable’ inputs (See paragraph 5.3.6).
Note: the reset time is determined by R4/C1, and begins when the +5V supply rail
reaches 3.6V on initial power-up.

5.3.5 Alarm buzzer

(circuit diagram sheet 3.)
The alarm buzzer is driven by the processor’s port 3.0 output via driver transistor
V11. Various alarm sound sequences are used to annunciate different types of
alarm warning and responses. These are obtained by the processor producing var-
ious mark:space drive waveforms and are therefore strictly processor dependant.
During troubleshooting the alarm sounder can be inhibited by fitting a jumper to
X23 (1-2) which clamps the base of V11 to 0V and prevents it from turning on.

5.3.6 Address decoding – D10

(circuit diagram sheet 3.)
The microcontroller communicates with
• the system memory – RAM and ROM (D8 and D9).
• the Operator Control Panel – via connector X1.
• the UPS Logic Board – via D12 and the CAN Bus.
• the Serial Line Controller (D11) – which interfaces with the RS232 and
RS485 communications facilities.
Under the control of the micro, the ‘address decoding’ circuit (D10) produces in-
dividual ‘enable’ signals for each of the above mentioned devices which allows
the micro to select a particular device with which it wishes to communicate at any
point in time.
D10 is a purpose-designed ASIC chip which decodes address lines AX11...AX17
together with the control bus [RD->, [WR-> and [RSTO-> lines, and from these
inputs it provides the following controlled signals:
• [CSEPR-> – logic low selects the EPROM memory chip (D8).
• [CSRAM-> – logic low selects the RAM memory chip (D9).

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• [CSCAN-> – logic low selects the CAN bus interface (D12 on sheet 4).
• [CSER-> – logic low selects the Serial Line Controller (D11 on sheet 4).
• [CSDISP-> – logic low selects the Operator Control Panel (X1 on sheet 4).
• Buffered AX16 and AX17 address bus lines.

5.3.7 System RAM and ROM memory addressing

(Refer to diagram sheet 3.)

Figure 7-32: AX14 & AX15 decoding configuration links

X14 X19
1 1
[WRX->
2 2
[PIN31EP> [PIN31RAM>
3 3

[AX15>
X15 X18
1 1
2 2
[PIN3EP> [PIN3RAM>
3 3

X16 X17
1 1
[RDX->
2 2
[PIN29EP> [PIN29RAM>
3 3
[AX14>
4 4
5 5
+5V

X12 X13
3 3
2 2
[PIN3EP> D9 pin 28
1 1
[AX17>

The system memory comprises a 256k EPROM (D8) and 256k of RAM (D9).

AX14 & AX15 configuration links

The Operator Logic Board has been designed to ease future software upgrades by
including configuration links to permit the addressing of alternative memory de-
vices. These links affect the routing of the AX15 and AX16 address lines, and the
standard configuration is shown in Figure 7-32.
EPROM (D8) Configuration. In the standard configuration the signals anno-
tated [PIN29EP> and [PIN3EP> are connected to EPROM D8’s A14 and A15 inputs
and are therefore driven by the AX14 and AX15 address lines respectively. The
[PIN31EP> input to D8 is concerned with selecting the “program” mode, and is left
open circuit due to the lack of jumper on X14. [PIN30EP> is held at a permanent
+5V (due to the jumper 2-3) on X12.

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Two conditions must be satisfied to connect the device’s D0....D7 outputs to the
data bus. First, the EPROM’s ‘output enable’ pin (pin 24), which is controlled by
the control bus [RDX->, must be low. Second, the ‘chip select’ (CS) input to pin
22, which is connected to the buffered [AX16> address line obtained from D10,
must also be low. Note that [AX16> is not subject to the [ALE> signal switching
through D5/D6 and is therefore permanently accessible by the processor.
RAM (D9) Configuration. In the standard configuration the signals annotated
[PIN29RAM> and [PIN3RAM> are connected to the RAM’s A14 and A15 inputs.

[PIN29RAM> is not used and is open-circuit due to the lack of jumper fitted to X17
pin 2. [PIN3RAM> is connected to the buffered Address line [AX14> due to the
jumpers on X18 and X17
Once again, two conditions must be satisfied to connect the device’s D0....D7 out-
puts to the data bus. First, the RAM’s ‘output enable’ pin (pin 22), which is con-
trolled by the control bus [RDX->, must be low. Second, the ‘chip select’ (CS)
input to pin 20, which is connected to the [CSRAM-> output from D10, must also
be low.

5.3.8 Interface to the Operator Control Panel

(circuit diagram sheet 4 – see also drawing SM-0360803-B sheets 2/3.)
The Operator Control Panel is connected to X1 and its interface signals can be
segregated into three areas; namely LED Driver; LCD Driver; and Push-button
Detection – each of which is described below.

LED Driver
Multiplexed power supplies. The operator control panel contains 17 leds ar-
ranged in three ‘banks’ – two banks of 6 led and one bank of 5 leds. The anodes
of all the leds forming a particular bank are connected, via current limiting resis-
tors, to a common +5V power supply; therefore three supplies are required in
total. Referring to the diagram sheet 4, these supplies are obtained by three mul-
tiplexed signals ([LD7>, [LD8>, [LD9>) which are produced by the microcontroller
and then buffered by D17 and transistors V12-V14 to provide [LC0>, [LC1>, [LC2>.
These transistors are thus switched sequentially (i.e. “strobed”) to provide the
positive power feed to each ‘bank’ of leds in turn.
LED Control. Each ‘bank’ of leds are controlled by a common control bus pro-
duced by the microcontroller annotated [LD1> to [LD6>. These signals are buffered
by D18 and connected X1 as [LD0> to [LD5>. As the micro strobes the positive
supply to each ‘bank’ of leds it drives its control bus lines ‘low’ to illuminate a
particular led within the ‘bank’. By driving the leds in this manner the micro has
full control over which leds are illuminated.
Note: the positive supply is strobed at a rate of 83.3Hz and therefore the leds do
not appear to flicker when illuminated.

LCD Driver
The LCD Display device on the Operator Control Panel displays 4 lines of twenty
characters and is used to indicate status information, alarm warning messages and
also provides the messaging system used by the operator to select various opera-
tional parameters.
The textual message information is stored in the Operator Logic Board’s ROM
and output to the Operator Control Panel by the microcontroller, via the data bus

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[DX0> to [DX7>, at convenient intervals in a suitable form which can be interpreted

by LCD display device.
As the microcontroller “sees” the LCD device as just another device on the data
bus it must also provide a means of addressing it when required. This is achieved
through a combination of the [CSDISP> ‘chip select’ signal from the address de-
coding circuit of D10 (See paragraph 5.3.6) and a ‘Write’ signal [RWDISP> pro-
duced directly by the processor port 1. To access the LCD display [CSDISP> must
be taken ‘high’ and [RWDISP> ‘low’.
Note: A reset signal [RSDISP> is also produced by the micro port 1 which can to-
tally reset the LCD display device.
Other lines connected to the LCD device are concerned with its power supply re-
quirements. The device requires +5V at X1-32; 0V at X1-30 and X1-2; and a var-
iable “contrast” supply in the range 0V to +5V at X1-4.

Push-button Detection
The five push-button on the Operator Control Panel are connected to a common
0V supply presented to X1 pin 31 and, when pressed, they route this 0V back to:
• X1 pin 21 (UP)
• X1 pin 23 (DOWN)
• X1 pin 25 (ENTER)
• X1 pin 27 (ESCAPE)
• X1 pin 29 (ALARM CANCEL)
These signals, annotated [P-0> to [P-4>, are buffered by D17 and the resulting
[TST1> to [TST5> signals are polled by the microcontroller at regular intervals to
enable it to detect when a particular push-button is pressed.

5.3.9 Interface to the CAN Bus

(circuit diagram sheet 4.)
The Operator Logic Board uses the CAN bus to communicate with the UPS Logic
Board. This bus carries bi-directional data between these two boards; e.g. opera-
tional status and alarm parameters are passed from the UPS Logic Board to the
Operator Logic Board for processing and display on the Operator Control Panel.
Selections made by the operator at the Operator Control Panel are passed via the
Operator Logic Board to the UPS Logic Board to set the system operating param-
eters.
The CAN bus (see appendix B) utilises an 82C200 controller and 82C250 inter-
face chip, both of which are described in appendix A.
82C200 control signals. The CAN bus controller is connected to the micro-
controller’s 8-bit data bus (DX0....DX7) in the same way as the other peripheral
devices. The microcontroller must therefore provide a means of addressing it
when required. This is achieved through a combination of the [CSCAN> ‘chip se-
lect’ signal from the address decoding circuit of D10 (See paragraph 5.3.6) and
buffered read/write signals ([RDX-> and [WRX->).
Note: an initialising reset signal [RSCAN> is also produced by the micro port 3
which starts communications.
82C250 control signals. This device is described in detail in appendix A (See
appendix A.10). Jumper X24 should be made 1-2 to connect the 120 Ohm line ter-
mination resistor across its I/O line terminals. “High speed” mode is permanently
selected due to pin 8 being grounded.

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5.3.10 Serial (modem) Interface

(circuit diagram sheet 4.)
Serial (modem) communications is afforded by D11, which is a type 8521A Uni-
versal Synchronous/Asynchronous Receiver/Transmitter (USART) working in
conjunction with D13, which is a bi-directional line driver device type LT1133.
8521A operation. This device (D11) converts the parallel data into a serial data
format for transmission, and vice-versa for data reception. This device is de-
scribed in detail in appendix A (See appendix A.8).
D11 is connected to the 8-bit data bus (DX0....DX7) and selected by a logic low
[CSSER-> signal produced by the address decoding circuit. Read/Write control is
afforded by the buffered [RDX-> and [WRX->, both of which are active ‘low’.
The microcontroller port 3 provides the 8521 with its general clock signal, [CLK-
SER> at approximately 1.25MHz, and also a reset signal [RESSER> which is
active ‘high’.
The Data/Control input (D11 pin 12) is controlled by the buffered address line
[AX0>, which is ‘high’ for data transfer and ‘low’ for control word transfer.

The serial I/O data and control lines are interfaced to the modem port (X8) via the
LT1133 driver circuit which converts the 8521A outputs to RS232C levels.

5.3.11 RS232 & RS485 Interface

(Refer to diagram sheet 4.)
Two of the controlled timers within the microcontroller (D2) are configured to op-
erate as further communication interfaces. Data I/O transfer is processed via port
3 with one port annotated [TXD0> & [RXD0>, and the other [TXD1> & [RXD1>. These
I/O data lines are raised to RS232 levels by D19 (MAX232) and RS485 levels by
D20 (75176) – D20 is controlled by the [RE485-> & [OE485> outputs from port 1.

RS232 communications via D19 and X5

The RS232 interface (D19) is provided by a standard MAX232 device (See ap-
pendix A.7).
This is a dual channel device: channel 1 interfaces [TXD0> & [RXD0> which is per-
manently connected to the RS232 I/O port at X5. Channel 2 interfaces [TXD1> &
[RXD1> and is connected to X4 via jumpers X20 (1-2), X21 (2-3), X22 (2-3). This
is the “standard” configuration for these jumpers.

RS485 communications via D20 and X4

The RS485 interface (D20) is provided by a SN75176A differential bus transceiv-
er (See appendix A.5).
This is a single channel device which interfaces [TXD1> & [RXD1> only, via jump-
ers X20 (2-3), and is connected to X4 via jumpers X21 (1-2), X22 (1-2). When
the jumpers are configured in the above positions they effectively route the RS485
communications through to X4 whilst still enabling RS232 communications at
X5.
The transmit data and receive data flow is controlled through D20 by means of
the [RE485-> & [OE485> inputs to pins 2 and 3. A truth table showing the full af-
fects of these inputs is provided in appendix A (See appendix A.5).

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5.3.12 Power Supply

(circuit diagram sheet 1.)
As many of the circuits on the Operator Logic Board are connected to external
(possibly remote) devices, such as a modem, they are all powered from an isolated
+5V power rail which is derived from an on-board dc-dc power converter based
on a purpose-designed current-mode PWM controller (UC3845). This controller
is fully described in appendix A (See appendix A.9).

Power circuit operation

The dc-dc converter’s input power is obtained from the UPS Logic Board’s ±12V
which is connected to X9 pins 1 and 3. This is filtered by C41 and L1/L2 to pro-
vide an unregulated power rail of approximately 24V; although the -12V rail is
taken as the 0V reference by the control electronics.
The converter operation is based on FET V10. When this device is turned ON it
draws current through the transformer primary (1-10) which induces opposing
currents into the secondary windings – note the winding polarities.
In practice, V10 is driven by a variable PWM output from N1 (at a basic rate of
40kHz) and the net result is an alternating current induced in winding 5-6 which
is full-wave rectified by V9 to provide a d.c. voltage smoothed by L3/C52/C53.
This “smoothed” voltage is regulated at +5V by appropriately controlling V10’s
PWM gate drive signal.

PWM control operation

The PWM controller (N1) is powered from a 16V zener-regulated supply ob-
tained from the unregulated 24V rail – note that N1 requires a minimum of
8.4Vdc to function correctly (See appendix A.9). The base PWM frequency is set
to approximately 40kHz by R35/C44 (i.e. the PWM pulse repetition rate is ap-
proximately 25µs.).
Current feedback signal. A current feedback signal is obtained from R40
(0.33R) which is connected in series with the transformer primary current
switched by V10. The voltage across this resistor will thus be proportional to the
current drawn through the primary winding when V10 is turned on. This current
feedback signal is fed to N1 pin 1 which internally regulates the mark-to-space
ratio of the PWM output at pin 6 for load stepping and overloads.
Voltage feedback signal. A voltage feedback signal is obtained via an opto-
coupled circuit which monitors the voltage across the isolated +5V rail. N3 is a
reference voltage generator which aims at maintaining 2.5V at its reference input
(N3 pin 1 – i.e. at the junction of R47/R48). This means that it therefore attempts
to maintain +5V at the top of R47 – which is connected directly to the output +5V
rail.
If the +5V rail therefore rises above or falls below its nominal +5V level then N3
will reduce/increase (respectively) the conduction through the opto-isolator,
which is thus sensed by N1.
The feedback voltage is source via the +5V reference voltage produced by N1 at
pin 8 and superimposed on the junction of R33 and R34 according to the amount
of conduction of V21, as shown in Figure 7-33.
Indications. An led (H1 is connected across the isolated +5V rail and illumi-
nates when this supply is correct.

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Figure 7-33: Voltage feedback signal

N1

7
2 VCC
VFB
5V(ref) 8
VREF
R32
1 6
COMP O/P
Output V21
22k 3
voltage R33
ISENSE
sensing 10k 4
RT/CT
VCC
UC3842

5
R34
4k7

5.4 Summary information

Table 7-19: Operator Logic Board configuration jumpers

Link
Jumper Function
Position

X11 OPEN +5v enable main CPU (Standard)

CLOSED ALE enable main CPU

X12 1-2 Main CPU enable EPROM

2-3 +5v enable EPROM (Standard)

X13 1-2 Main CPU enable RAM

2-3 +5v enable RAM (Standard)

X14 1-2 Not Required Testing Only

2-3 Not Required Open = Standard

X15 1-2 Main CPU enable EPROM (Standard)

2-3 Not Required

X16 1-2 Not Required

2-3 Main CPU enable EPROM (Standard)

3-4 Not Required

4-5 Not Required

X17 1-2 Write to RAM enable

2-3 Not Required

3-4 Main CPU enable RAM (Standard)

4-5 Not Required

X18 1-2 Not Required

2-3 Main CPU enable RAM (Standard)

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Link
Jumper Function
Position

X19 1-2 Not Required RAM extension

2-3 Not Required Normally open

X20 1-2 Read/Write RS232 enable (Standard)

2-3 Read/Write RS485enable

X21 1-2 Enable port x4 for RS485

2-3 Enable port x4 for RS232 (Standard)

X22 1-2 Enable port x4 for RS485

2-3 Enable port x4 for RS232 (Standard)

X23 1-2 Inhibit buzzer

2-3 Enable buzzer (Standard)

X24 1-2 Enable CAN bus to UPS logic (Standard)

2-3 Disable CAN bus to UPS logic

X25 1-2 Enable RS485 bus to port x4 (Standard)

2-3 Disable RS485 bus to port x4

X26 OPEN +5v power supply reset enabled (Standard)

CLOSED +5v power supply reset disabled

Table 7-20: Operator Logic Board potentiometer adjustment

Potentiometer Function
R21 Display contrast adjustment

Table 7-21: Operator Logic Board LED indication

LED Colour Function

H1 Green Internal power supply operating

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 Section 7:

Chapter 6 - Operator Control Panel

6.1 Section overview

This section contains a circuit description of the Operator Control Panel used
across the entire 7200 Series UPS model range, and should be read in
conjunction with circuit diagram SE-0360803-B.
Signal annotations shown on the circuit diagrams are shown in italics in the
following text – e.g. [CLC2>.

6.2 General description

6.2.1 Circuit board functions

The Operator Control Panel functions can be summarised as follows:
• LED Display indication–
This board contains LED which provides the operator with various status
indications – i.e. UPS module mimic; load bargraph; battery charge/auton-
omy time bargraph; alarm warning indication.
• Operator input switches–
The Operator Control Panel switches provide the means for the operator to
effect system control through a menu/messaging system.
• LCD Display Panel–
The LCD display panel provides status and alarm messages for the opera-
tor together with the menus used by the operator in setting up and interro-
gating the UPS control system.

6.2.2 Input/Output connections

All input/output signals are connected to the Operator Logic Board via a single
34-way ribbon connector.

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6.3 Detailed circuit description

6.3.1 LED Display indication

Figure 7-34: LED Display indication

LC0 X7-5

LC1 X7-3

LC2 R3 R2 R1
X7-1

R1
R2
R3
R4
R5
R6
R7
R8

R1
R2
R3
R4
R5
R6
R7
R8

R1
R2
R3
R4
R5
R6
R7
R8
C

C
1
2
3
4
5
6
7
8
9

1
2
3
4
5
6
7
8
9

1
2
3
4
5
6
7
8
9
D17 D15 D13 D11 D9 D7 D5 D3 D1

D16 D14 D10 D8 D4 D2

D12 D6

LD5 X7-7
LD4 X7-9
LD3 X7-11
LD2 X7-13
LD1 X7-15
LD0 X7-17

The operator control panel contains 17 leds arranged in three ‘banks’ as shown in
Figure 7-34 – two banks of 6 led and one bank of 5 leds.
• LEDs 1-5 provide module mimic indication, alarm active and battery CB
• LEDs 6-11 provide the load bargraph indication and overload
• LEDs 12-17 provide the battery charge bargraph indication and autonomy

The anodes of all the leds forming each of the above ‘banks’ are connected, via
current limiting resistors, to a +5V power supply. These +5V supplies are provid-
ed by three multiplexed signals ( [LC0>, [LC1>, [LC2>) which are provided by the
Operator Logic Board – i.e. these supplies are “strobed” to provide the positive
power feed to each ‘bank’ of leds in turn (See paragraph 5.3.8) .
Each ‘bank’ of leds are controlled by a common control bus produced by the
Operator Logic Board annotated [LD1> to [LD6>. As the positive supply is strobed
to each ‘bank’ of leds, the leds illuminate according to which of the control bus
lines are ‘low’. By driving the leds in this manner the microcontroller on the
Operator Logic Board has full control over which individual leds are illuminated
at any particular time.
Note: the positive supply is strobed at a high frequency and therefore the leds do
not appear to flicker when illuminated

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6.3.2 Operator input switches

Figure 7-35: Operator switches

0V X7-31

S1

P4 X7-21
UP

S2

P3 X7-23
DOWN

S3
P2 X7-25
ENTER

S4
P1 X7-27
ESCAPE

S5
P0 X7-29
ALARM CANCEL

The five push-button on the Operator Control Panel are connected to a common
0V supply presented to X7 pin 31 from the Operator Logic Board; when pressed,
they route a 0V signal (annotated [P-0> to [P-4>) back to the microcontroller on
the Operator Logic Board via the connections shown in Figure 7-35.

6.3.3 LCD Display Panel

Figure 7-36: LCD Display module

7
X7-14 D0
8
X7-16 D1
9
X7-18 D2
10
X7-20 D3
11
X7-22 D4
12
X7-24 D5
13
X7-26 D6
14
X7-28 D7
2
X7-4 VDD
3
X7-6 VL
1
X7-2 VSS
5
X7-10 R/WR
4
X7-8 RS
6
X7-12 E
K
X7-32 +5V
A
X7-30 0V
4 x 20
LCD_MODULE

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 Section 7: UPS System Control

Chapter 7 - System software

7.1 Introduction
The general UPS control operation is based on the microcontroller system con-
tained on the UPS Logic Board, as described in chapter 3 of this section (see par-
agraph 3.3.2 on page 7-24). The following description explains in basic terms
how the microcontroller system is programmed to operate and provides details of
the conditional flowcharts applicable to the major UPS control signals (e.g. recti-
fier OFF/ON, inverter OFF/ON, load transfer control).
Despite the fact that the software is not generally accessible to the service engi-
neer, an understanding of some of the sub-routines described later can be an in-
valuable troubleshooting aid to differentiate between the ‘cause and effects’ of
certain conditions.
The “C” programming language used to write the system software is closely re-
lated to the actual digital processing, and comprises a sequence of instructions
which determines the microcontroller operation. The program is held in two 512k
Read-Only Memory chips (EEPROM) D35 & D46 which are accessed by the mi-
crocontroller via the system address and data busses. D20 is also a ROM device,
and contains initialisation data.
Although it does not contain the “system software” itself, the Random Access
Memory (RAM) holds important data concerning the system’s operation, such as
that programmed by the operator from the Operator Control Panel, which is re-
quired by the main program. Battery back-up is provided to maintain such data
when the UPS is powered down. RAM also provides a temporary store for data
produced by the main program during its routine execution.

7.2 Program structure and execution

Initialisation
When the UPS is first powered up the microcontroller receives a 1 second reset
pulse from the reset generator (see paragraph 3.3.5 on page 7-27) which forces
the micro to read the instruction contained in a particular memory location (usu-
ally 0000). This is the start point of an initialisation routine which sets up the com-
plete microcontroller system in readiness for entry into the main program. The
initialisation routine performs functions such as configuring the microcontroller
I/O ports, peripheral communication ports and protocols, internal timers and A/D
converters; and reading system data (such as UPS module rating and configura-
tion) from the non-volatile RAM. Some of these functions are performed once
only during the initial set-up whilst others are also revisited during the main pro-
gram execution – e.g. if the module kVA rating or single/parallel configuration
data is changed whilst the module is running it will not affect the main program
until the microcontroller is reset.
Note: the reset generator can also be triggered manually through the selection of
jumper X28; however, if a reset is applied whilst the UPS is running it will crash
due to the rectifier, inverter and static switch all being turned off during the reset
period. USE WITH CAUTION!

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Main program
The system software will enter its main program once the initialisation routines
have been completed. The main program comprises a series of instructions which
are executed sequentially in a continuous loop (See Figure 7-37).
Figure 7-37 shows that the main program operates on two levels; identified in the
illustration as the ‘foreground’ and ‘background’ routines. Notice that both the
‘foreground’ and ‘background’ routines call various ‘sub-routines’ whilst work-
ing through the main program loop. A sub-routine is a self-contained “mini-pro-
gram” that can be called from various points in the main program loop.
The ‘foreground’ routine services vital functions which are required to be per-
formed at regular intervals, or at a particular time, in order to secure proper system
control: while the ‘background’ routine is of secondary importance and executed
on an opportunity basis when the ‘foreground’ routine is idle. For example, the
sub-routine that checks that the inverter output voltage is within limits is consid-
ered ‘critical’ and is called every 250µs; while the sub-routine that checks the
state of the inverter ON/OFF menu selection is less-critical and perhaps executed
once per second. All program timing functions are tied to the microcontroller
system clock (20MHz), which also synchronises the address/data bus transfer op-
erations, and the microcontroller’s internal programmable timers.
A successful ‘real-time’ program requires that the main program loop is complet-
ed as fast as possible and it is therefore good practice to return to the main pro-
gram from a sub-routine as quickly as possible.

‘Background routine’
The background routine is responsible for managing the calculation of the voltage
and current signals produced by the A/D converters and storing the results in the
appropriate RAM memory locations from where they are read at regular intervals
by the foreground routine. It also reads the condition of the Operator Control
Panel buttons and sets status flags in the RAM memory.

‘Foreground routine’
The foreground routine calls a series of sub-routines to carry out a check of the
many variables and status flags held in memory and perform various functions de-
pending on the results – i.e. the sub-routines make decisions based on the state of
the memory contents that they read.
For example: a sub-routine that controls the state of the [REC_ON> signal is called
every 500msecs. This signal determines whether or not the rectifier is requested
to turn ON (see page 7-33) and in making the decision, the sub-routine looks at
the following status flags stored in memory:
• the manual ‘rectifier inhibit’ switch status (UPS Logic Board).
• the rectifier fuse fail status.
• the selected rectifier ON/OFF status (from Operator Control Panel menu
screen).
If all three of the above conditions are conducive to starting the rectifier, the soft-
ware will drive the [REC_ON> signal high which turns on the rectifier, and also
sends a status signal via the CAN bus to inform the display system of the new rec-
tifier status. Several other sub-routines which control similar signals to
[REC_ON>, and are therefore of prime interest to the service engineer, are illustrat-
ed in detail later in this chapter.

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Figure 7-37: Main program “Foreground” and “Background” routines

SUB: Look-up A/D

START START
CPU
input (Vb)
Clock
Calculate Vb Set Initial flags

Calculate Vinv If clock=0001 Exec SUB: INV-ON

SUB: INV-ON See Flow-chart 1
Calculate Ib

Background Routine
If clock=0010 Exec SUB: REC-ON
: SUB: R E C _ O N See Flow-chart 2
:
: If clock=0150 Exec SUB: SYNC_OK

Foreground Routine
SUB: S Y N C _ O K See Flow-chart 3
Running in
Set Flags
background If clock=0200 Exec SUB: IB_OPEN
Check Display SUB: IB_OPEN See Flow-chart 4
Buttons
:
: :
: :
:
If clock=nnnn
Return to START Execute SUB: nnnn

Return to START
Page 1
Inv. Volts flag_1
Vb=432 Ib : Page 2
Window REC_ON
Low Batt flag_2 :
Vout : :
Warning INV_ON
DC Over :
Vinv : : flag_3
voltage RAM
In. Volts : MEMORY
Vin : : flag_4
Window
: : : : :

Start
Sub-Routine 1
Start Execute Chk1 if t=0.5µs

CHK Vb Execute Chk2 if t=100µs

CHK Vin .......... Sub-Routine 2

Begin SUB:

.......... ..........

.......... ..........
Main Programme
Background Routines

Question 1? No Process A
.......... ..........

.......... ..........

Yes Question 2
.......... ..........

.......... Process B No
..........

Process C
.......... .......... Process D

End
(Return to start) ..........

End End SUB:

(Return to start)

Question a condition
(e.g. Is Vb < undervoltage trip level)

Perform a function
(e.g. Set BatU/V Flag - Trip battery etc.)

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CHAPTER 7 - System software

7.2.1 Initialisation/Reset
The system reset routine is activated when the UPS is first powered up or follow-
ing the application of the hardware reset (see paragraph 3.3.5 on page 7-27).
Note: the reset pulse is applied for approximately 10/20ms in order to allow the
+5V power rail to stabilise.
The Initialise/Reset routine:
• resets the micro’s peripheral devices by forcing the output digital signals
to logic low (with the exception of the [SYNC>, [PWM1>, [PWM2>,
[PLLOU1> signals, whose states remain undefined).

• verifies no-reversal of the output digital connectors.

• initialises the software application into the working RAM
• starts the ‘watch-dog’ timer
• verifies that the EEPROM holds valid system parameters (See Chart 7-1).
• checks the nominal sync frequency
• checks the visual display and 7-segment led (for 5 seconds)
• returns a Pass/Fail status.

Checking the system parameter data

The initialisation/reset routine checks that the programmed system parameters are
acceptable for the correct operation of the UPS equipment. The parameters are
held in three pages of the EEPROM. Page 1 holds the parameters set by the Op-
erator Control Panel and pages 2 & 3 contain the internal parameters. A Longitu-
dinal Redundancy Counter (LRC) is associated with each page to allow error
checking.
Default values for the system parameters are held in fixed memory addresses in
the system EPROMS. The EEPROMs’ data can thus be reinitialised with the
EPROM default values by following the “RELOAD DATA” procedure on the
Operator Control Panel (see paragraph [Link] on page 2-46). This should be car-
ried out if an LRC error is found with the page associated with the Operator Panel
entered data.

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Flow Chart 7-1: Initialisation/Reset

Begin SUB: [RESET>

Does memory Failed LRC P2

page 2 initialse No set error 72
correctly? [ERROR LRC PAR PAG 2]

Yes

Does memory Failed LRC P3

page 3 initialse No set error 73
correctly? [ERROR LRC PAR PAG 3]

Yes

Does memory Failed LRC P1

page 1 initialse No set error 71
correctly? [ERROR LRC PAR PAG 1]

Yes

Does UPS
set error 70
Power rating No
[BAD EEPROM PROGRAMM]
parameter exist?

Yes

Is link X12 made 1-2? Yes

No

Initialisation passed Initialisation failed

End SUB
Return to main program

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CHAPTER 7 - System software

7.2.2 Rectifier ON/OFF subroutine

This subroutine enables the software to control the rectifier ON/OFF function.

The sub-routine is affected by the following inputs:

• Rectifier fuse-fail monitor ([FUSREC>) –
connected to X2 pin 49 from the fuse’s fault detection micro-switch. A
fuse failure event activates alarm #25.
• ‘Rectifier Block’ (BLK_RAD>) –
derived from the fault detection logic on the Rectifier Logic Board which
shuts down the rectifier if that board detects an internal fault (applied to
X3 pin 33).
• Operator Control Panel ON/OFF selection ([TLC_REC>) –
Applied via the CAN Bus from the Operator Logic Board. An OFF status
event activates alarm #21.

The sub-routine produces the following output:

• Rectifier ON/OFF command signal [REC_ON>–
connected as an input to D88 where it affects the logic state of the ultimate
rectifier control signal [ON_REC> (see paragraph 3.3.7 on page 7-29).
This signal is applied via the CAN Bus from the Operator Logic Board
and activates alarm #20 [RECT: SOFTWARE BLOCK] when in its OFF
status.

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Flow Chart 7-2: Rectifier RUN control [REC_ON>

Begin SUB: [REC_ON>

(every 500ms)

Is the
Rectifier Block signal
Yes
active on the Rectifier
Logic Board?

No

Is the Rectifier
Fuse Fail Yes
active?

No

Is the
Rectifier selected ON
No
at the Operator Control
Panel?

Yes

Set [REC_ON> Set [REC_ON>

output to ON output to OFF
(Logic high) (Logic Low)
[Turn OFF Alarm #20] [Turn ON alarm #20]

End SUB
(return to main prog.)

REC_ON
EPO
To Rectifier
PS FAIL D88 [ON_REC>
Logic Board
Man Inhibit (Q3)
DC O/volts

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CHAPTER 7 - System software

7.2.3 Inverter OFF/ON Sub-routine

This subroutine enables the software to control the inverter ON/OFF function

The sub-routine is affected by the following inputs:

• Battery voltage validation ([ST_BAT>) –
as determined by the battery voltage monitor sub-routine (See Chart 7-7).
• Inverter block (BLK_INV>) –
derived from the fault detection logic on the Inverter Logic Board which
shuts down the inverter if that board detects an internal fault (applied to
X3 pin 33).
• Output Isolator status ([SW_OUT>) –
connected to X2 pin 46 from Isolator’s auxiliary contact. When open, it
initiates alarm #03.
• Maintenance Bypass Isolator status ([SW_BYP>) –
connected to X2 pin 45 from Isolator’s auxiliary contact. When Closed, it
initiates alarm #06.
• External ‘Inverter Block’ command ( [BLK_EXT>) –
connected to X8 pin 11 and applied via the optional Alarms Interface
Board.
• Operator Control Panel ON/OFF selection ([TLC_INV>) –
applied from the Operator Logic Board via the CAN bus. When OFF, it
initiates alarm #31.
• Load status ([ST_CA>) –
signifies load on inverter/bypass/open as determined by the load transfer
control sub-routine (See Figure 7-39).

The sub-routine produces the following output:

• Inverter ON/OFF command signal [INV_ON>–
connected as an input to D88 where it affects the logic state of the ultimate
inverter control signal [ON_INV> (see paragraph 3.3.7 on page 7-29).
This signal is applied via the CAN Bus from the Operator Logic Board
and activates alarm #30 [INV: SOFTWARE BLOCK] when in its OFF sta-
tus.

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Flow Chart 7-3: Inverter RUN control [INV_ON>

Begin SUB: [INV_ON>
(every 500ms)

Is the battery
Yes voltage within permissible No
range?

Is the
Inverter Block signal
Yes
active on the Inverter
Logic Board?

No Is an
External Block Yes
being applied?

No

Are the Output

Isolator and Maint. Isolator Yes
closed together?

No

Is the
Inverter selected ON
No
at the Operator Control
Panel?

Yes

Set [INV_ON> Set [INV_ON>

output to ON output to OFF
(Logic high) (Logic low)
[Remove alarm #30] [Activate alarm #30]

End SUB
(return to main prog.)

INV_ON
EPO
PS FAIL D88 [ON_INV> To Inverter
Logic Board
Man Inhibit (Q2)
DC O/volts

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CHAPTER 7 - System software

7.2.4 Frequency synchronisation control

The Inverter synchronisation control is complex and, for the purpose of this de-
scription, is divided into three flow charts.

Figure 7-38: Frequency synchronisation software block diagram

[FOK>
(alarm #13)
[PLL>

Window Limits PLL PLL

Sync
Mains OK Sync Calculate Slew
[F_IN> Source Error [SYNC>
Routine Source Phase Rate
Selector
[SVI> Displacement Control

[BLK_SYN> [BACK>
External Sync Inhibit
Inverter Freq F/Back
[SYNC_OK>
(alarm #35)

“Mains OK” routine. This routine is responsible for verifying that the bypass
supply is fully available and the bypass frequency is within the selected voltage
and frequency window limits. The major output from this routine is monitored by
the Sync Source Selector routine which determines whether the inverter is to:
1. Synchronise to the bypass supply (if the bypass is valid).
2. Synchronise to the last available valid frequency – i.e. if the frequency goes
outside the sync-window the selected frequency will remain at the window
edge frequency for 1 minute (debounce) then revert to the internally gener-
ated base frequency reference clock (50/60Hz).
Note: when the bypass frequency returns to within the window the PLL will
revert to synchronising to the bypass after 1 second.
3. Synchronise to the internal reference clock if the bypass supply disappears.

The sub-routine is affected by the following inputs:

• Bypass R-phase frequency ([F-IN>) –
Manufactured from X2 pin 15 via the High Voltage Interface Board.
• Nominal frequency (50/60Hz) –
Selected via the Operator Control Panel and applied via the CAN bus.
• Acceptable sync window (±1Hz) –
Programmed via the Operator Control Panel through the “set-up” menu,
and applied via the CAN bus.
• Bypass voltage status (SVI) –
This flag is set by another subroutine depending on the bypass voltage sta-
tus – i.e:
0 = OK (bypass voltage within the mimic-programmed limits [±10%])
1 = LOW (bypass undervoltage [below -10%]) alarm #12 active.
2 = HIGH (bypass voltage high [above +10%]) alarm #11 active.
3 = ABSENT (bypass voltage less than 50V) alarm #10 active.

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The sub-routine affects the following outputs:

• Frequency status flag ([FOK>) –
OFF = FAULT
ON = OK.
Disables/enables alarm #13
• PLL enable flag –
Enables/disabled frequency slew-rate control (See Chart 7-5)
• Reference frequency status ([Sync Source>) –
Selects the frequency value to which the PLL will lock – i.e. to the “Last
frequency” or “internal clock.”
. Flow Chart 7-4: “Mains OK” Routine

Begin SUB: F r e q u e n c y
Calculation

Is the bypass
Is the bypass Has the 1Sec
frequency within the
voltage present? Yes Yes stability timer
selected window?
(SVI = Not 3) expired?
(±1Hz)

No No
Yes No

Has the 1Sec Sync Source = P R E V I O U S ( 2 )

stability timer Yes frequency (Use last available Set FOK = ON
expired? frequency as reference) (bypass frequency is OK)

Set FOK = OFF Set PLL> flag = ON

(bypass frequency is not OK) Enable the PLL slew rate
Annunciate alarm #13 control
[BYP: FREQUENCY ERROR]
Reset delay counter = 0 Sync Source = MAINS (1)

Start the "re-enable" timer

(1minute)

Set [PLL> flag = OFF

Disable the PLL slew-ratre control

Increment the 1 sec "PLL

re-enable" counter

No

Has the
Yes "1 min re-enable" counter
timed-out?

Sync Source = BASE FREQ (3)

No

End SUB:
Return to main program

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CHAPTER 7 - System software

Sync Source Selector. This subroutine enables the software to control the PLL
frequency selection (see paragraph 3.3.13 on page 7-55).

The sub-routine is affected by the following inputs:

• External sync inhibit ([BLK-SYN>) –
connected to X8 pin 12 from External Alarms Interface option.
• External sync inhibit ([ON_GEN>) –
One of the functions of the “On-Generator” input is to disable the inverter
synchronisation (selected via the Operator control Panel SET-UP menu).
• Permission to enable sync inhibit operation ([GREL_BLK_SINC>) –
this is a programmable parameter (see paragraph [Link] on page 2-43).
• PLL Phase Locked ([PLL_ON>) –
A software routine which determines if the inverter and bypass are within
±9° of each other.
PLL_ON = within ±9° of each other
PLL_OFF = not within ±9° of each other
• Timeout value for bypass frequency monitor ([FOK>) –
this is a programmable parameter associated with the timeout of the
“Bypass Frequency Not OK” status.

The sub-routine produces the following outputs:

• Sync Source –
master frequency reference to the phase displacement calculation routine.
• PLL locked ([SYNC_OK>)
Enables/Disables alarm #35

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Flow Chart 7-5: Sync Source Selector Routine

Begin SUB: PLL Sync

Is the Is an Is the mains

external block facility external Block synch inhibit frequency within the
No No Yes
enabled (ON_GEN) & signal being applied selected window?
(GREL_BLK_SINC ) (BLK_SYN)? (FOK=ON)?

From Mains
Yes frequency
validation chart

No

Sync Source = Present

PLL held to present frequency

Has the mains Is the PLL

Yes been out of limits for No phase locked within ±9°?
> 10Secs? (PPL Flag=ON)

No
No

Sync Source = BASE FREQ Has the PLL

PLL locked to internal clock been locked for at least No
50/60Hz frequency 1 Sec?

Sync Source = PREVIOUS SYNC_OK = OFF

PLL held to previous
frequency
Active alarm 35
Yes [INV: UNSYNCHRONIZED]

SYNC_OK = OFF
Active alarm 35
[INV: UNSYNCHRONIZED]
SYNC_OK = ON

De-active alarm 35
[INV: UNSYNCHRONIZED]

End SUB:
Return to main program

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CHAPTER 7 - System software

Phase displacement calculation. This routine controls the rate of change of

the inverter frequency in order to track the bypass supply frequency. The “target”
slew rate is programmable via the Operator Control Panel – i.e. the amount of dis-
placement error is multiplied the gain factor entered under the “Speed” menu on
the Operator Control Panel.

The sub-routine is affected by the following inputs:

• Sync Source –
The is the master frequency reference as selected by the Sync Source
Selector and Mains OK routines. This reference may be:
a) Present frequency –
Holds the inverter frequency constant at the present value when an exter-
nal inhibit is applied (e.g. via the optional Alarm Board).
b) Previous frequency –
If the mains frequency goes outside its window limits, this holds the
inverter frequency constant at the last valid mains frequency (e.g. at the
window edge frequency).
c) Base frequency–
Reverts the inverter back to the Base Frequency if no mains reference fre-
quency is available.
d) Mains frequency –
Forces the inverter to track the bypass frequency as long as it remains
available and within the window limits.
• Inverter Frequency [BACK> –
Actual inverter frequency as presented to the Inverter Logic Board.

The sub-routine produces the following outputs:

• Inverter Sync ([SYNC>) –
Master frequency reference to the Inverter Logic Board.
• Error –
A phase displacement is calculated depending on the relationship between
the two inputs (Sync Source & [BACK>). The detected error is then multi-
plied by a programmed “gain” parameter, which is entered via the “Speed”
display menu. This either speeds-up or slows-down the inverter clock
(nominal 288kHz) on the Inverter Logic Board in order to make the
inverter track the “Sync source” reference frequency.
The “Gain” figure obviously affects the rate at which the inverter fre-
quency is allowed to change while undertaking its tracking function, and
is put into effect in the PLL Slew Rate Control Routine.

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Flow Chart 7-6: PLL Slew rate control (phase displacement calculation).

Begin SUB: PLL Phase

Detector

Calculate phase displacement Calculate phase displacement

Is the "Out-of-phase"
between inverter [BACK> and No Yes between inverter [BACK> and
flag ON?
[Sync Source] [Sync Source]

Is the error greater Is the error greater

Yes No
than ±9°? than ±8°?

Set "Out-of-phase" flag Set "Out-of-phase" flag

No = ON = OFF Yes

Calculate phase error direction Calculate phase error direction

(lead/lag) (lead/lag)

Calculated error w.r.t. slew Calculated error w.r.t. slew

rate gain (set via "Speed") rate gain (set via "Speed")

Add calculated "error" to Add calculated "error" to

inverter clock. inverter clock.
(Slew-rate control routine) (Slew-rate control routine)

Set "Out-of-phase" flag Set "Out-of-phase" flag

= OFF = ON

End SUB:
Return to main program

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CHAPTER 7 - System software

7.2.5 Battery circuit breaker control

This subroutine enables software control of the battery circuit breaker via the
[IB_OPEN> signal applied to U23 (see paragraph 3.3.7 on page 7-29).

This subroutine reacts to changes in the battery status flag (ST_BAT) which indi-
cates whether the battery voltage is above the ‘slow overvoltage’ level, below the
‘undervoltage trip’ level, or positioned satisfactorily between the two. Changes in
status affect the state of [IB_OPEN> after a suitable debounce period, which is ap-
plied to prevent spurious operation. The debounce period of all three status chang-
es are factory programmed independently.

The sub-routine is affected by the following inputs:

• Battery voltage ([VB>) –
connected to X2 pin 27 via High Voltage Interface board
• Battery maximum threshold ([Vs_sup_bat>) –
programmed via the Display menu system.
• Battery undervoltage trip threshold ([Vs_inf_bat>) –
software calculated depending on discharge current (Ib) and programmed
via the Display menu system.
• Rectifier in Manual Mode status –
command input from Operator Control Panel.
• Battery Test Mode status –
enabled & programmed from Operator Control Panel.
• Battery Boost Charge Mode status –
enabled & programmed via the Display menu system
• On-Generator status –
when enabled (from Operator Panel) reduces the battery charge when the
UPS is running On-Generator (see paragraph [Link] on page 2-43) –
requires Alarm Interface Board input.

The sub-routine affects the following outputs:

• Battery status flag ([ST_BAT>) –
depending on the measured battery voltage, [ST_BAT> can have one of
three possible values;
– [ST_BAT> = BAT_BAS (battery undervoltage alarm [53])
– [ST_BAT> = BAT_ALT (battery overvoltage alarm [55])
– [ST_BAT> = BAT_OK (battery voltage within acceptable range) .

• Battery circuit breaker control ([IB_OPEN>) –

connected as an input to D88 where it affects the logic state of the ultimate
Battery Trip signal [BAT_TRP> (see paragraph 3.3.7 on page 7-29) – logic
high trips the battery breaker and low ‘enables’ it.

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Flow Chart 7-7: Battery Control

Begin SUB: Battery circuit

breaker control (Executed every 500ms)

Is the battery
voltage (VB) below the To Next Page
No
set low volts level?
(Vs_inf_bat)
(See Chart 7-9)

Yes

Is ST_BAT
already flagging an
Yes No
undervolts trip status?
(BAT_BAS)

Has the Low

DC condition been
No
present for longer than
1Sec?

Yes

Set ST_BAT to BAT_BAS

to flag Low Voltage Trip
-activate alarm [53]

Set IB_OPEN high to open the

battery circuit breaker

HIGH

End SUB:
Return to main program
[IB_OPEN>
M_BAT_MA
RESET D88 BAT_TRIP
M_ESD

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CHAPTER 7 - System software

Flow Chart 7-7: Continued......

From Previous Page

Is the battery
voltage above the set
No To Next Page
slow overvolts level?
(Vs_sup_bat)

Yes

Is ST_BAT
already flagging a
Yes No
slow overvoltage status?
(BAT_ALT)

Is the battery in
Yes TEST; MANUAL or
BOOST mode?

No

Is the
Yes ON GENERATOR block
applied?

No

Has the Low

DC condition been
No
present for longer than
1Sec?

Yes

Set ST_BAT to BAT_ALT

to flag High Voltage Trip
-activate alarm [55]

Set IB_OPEN high to open the

battery circuit breaker

HIGH

End SUB:
Return to main program

[IB_OPEN>
M_BAT_MA
RESET D88 BAT_TRIP
M_ESD

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Flow Chart 7-7: Continued......

From Previous Page No

Is ST_BAT
already flagging an
Yes
OK status?
(BAT_OK)

No

Has the DC Bus

No been stable for longer
than 5 secs?

Yes

Set ST_BAT to BAT_OK

to flag Battery OK
- for Alarm Interface board
Set IB_OPEN low to enable
the battery circuit breaker

[IB_OPEN>
LOW
M_BAT_MA
RESET D88 BAT_TRIP
M_ESD

End SUB:
Return to main program

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CHAPTER 7 - System software

7.2.6 Low Battery Pre-alarm

This sub-routine controls the annunciation of the [DC BUS: UNDERVOLTAGE]
warning (alarm # 56) when the battery voltage falls to a value just above the un-
dervoltage trip voltage.
A delay counter provides a 1 second delay between a change in alarm status and
the alarm indication to prevent spurious operation.

The sub-routine is affected by the following inputs:

• Battery voltage ([VB>) –
connected to X2 pin 27 via the High Voltage Interface board.
• Battery Pre-alarm operating threshold ([Vs_pre_al_bat>) –
programmed via the Operator Logic board and applied via the CAN bus.

The sub-routine affects the following outputs:

• Battery Pre-alarm status flag ([sta_pre_bat>) –
enables/disables [ DC BUS UNDERVOLTAGE ] alarm [#56].

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Flow Chart 7-8: Low battery pre-alarm

Begin SUB: Battery Low

Voltage Pre-Alarm (Executed every 500ms)

Is the battery
voltage (VB) below the
No Yes
pre-alarm volts
level?

Is alarm #56 Is alarm #56

[DC BUS: UNDER- [DC BUS: UNDER-
No Yes
VOLTAGE] active VOLTAGE] active
at present? at present?

Yes No

Has VB been Has VB been

above pre-alarm level for No No below pre-alarm level for
longer than 1Sec? longer than 1Sec?

Yes Yes

Remove alarm #56 Display alarm #56

[DC BUS: UNDERVOLTAGE] [DC BUS: UNDERVOLTAGE]

End SUB:
Return to main program

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CHAPTER 7 - System software

7.2.7 Battery undervoltage trip threshold

This sub-routine calculates the battery undervoltage trip (End-of Discharge) ref-
erence level ([Vs_inf_bat>) used in the battery circuit breaker control sub-routine
(See Chart 7-7).
The operating threshold value depends on the percentage battery current being
drawn; basically, the undervoltage trip voltage is raised by 10% if the battery dis-
charge current is less than 10% of its fully-rated current. This is to prevent the bat-
tery from undergoing a prolonged low-level discharge and thus enhances the
overall battery performance and working life.

The sub-routine is affected by the following inputs:

• Battery current ([IB>) –
from X2 pin 31 via the High Voltage Interface board.
• Battery circuit breaker status ([SW_BAT>) –
from X2 pin 53 via the High Voltage Interface board.
• Number of battery elements –
entered via Operator Control Panel and applied via the CAN bus.
• Nominal ‘End-of-discharge’ voltage (V/Cell) –
entered via Operator Control Panel and applied via the CAN bus.
• Background task results –
2 flags are set in RAM by a background sub-routine, calculated as follows:
NOMINAL = N. BATT. EL x END DIS.
110% NOMINAL = NOMINAL + 10%

N. BATT. EL. = Number of battery cells connected in the string, as entered

via the “SET UP” Display menu.
END DIS. = Minimum discharge voltage per battery cell, also entered via
the “SET UP” Display menu.

Example: if 198 cells & end of discharge = 1.67V/Cell then:

NOMINAL = 330.6V and 110 NOMINAL = 363.76V

The sub-routine affects the following outputs:

• Battery undervoltage trip reference ([Vs_inf_bat>) –
(See Chart 7-7)

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Flow Chart 7-9: Battery undervoltage trip threshold

Begin SUB: Battery undervoltage

threshold selection (Executed every 500ms)

Is the battery circuit

breaker open?

No

Yes Is the battery current

No
less than 10% ?

Yes

Use the upper level Use the lower level

Vs_inf_bat = 110% NOMINAL Vs_inf_bat = NOMINAL

End SUB:
Return to main program

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CHAPTER 7 - System software

7.2.8 Battery Boost charge

This sub-routine determines when the Rectifier Logic Board is requested to oper-
ate in the Boost Charge mode (see paragraph 2.3.2 on page 4-26).
Boost charge is enabled from the Operator Control Panel and can be invoked
Manually or Automatically.
• Manual selection puts the charger in an immediate Boost mode.
• Automatic Boost mode is invoked if the charge current is greater than a
programmed threshold level for 1 minute following the return of the mains
supply after an outage. The system remains in the boost mode until either
the battery current falls below the threshold for 5 seconds, or the boost
charge timer (up to ten hours) expires (in which case an error is flagged –
alarm #54 – and further Boost charge operation is locked out.

The sub-routine is affected by the following inputs:

• Battery current ([IB>) –
from X2 pin 31 via the High Voltage Interface board.
• Automatic Boost charge enable/inhibit –
selected from Operator Control Panel and applied via the CAN bus.
• Manual Boost charge requested–
selected from Operator Control Panel and applied via the CAN bus.
• Battery in Test mode –
flag set by another sub-routine (See Chart 7-11).
• Rectifier in Manual mode –
flag set by another sub-routine.
• On-Generator mode –
flag set by another sub-routine.
• Automatic changeover threshold –
programmable from Operator Control Panel (default = 10% of battery cur-
rent limit threshold) and applied via the CAN bus.
• 1 minute timer –
to determine when to enter Auto Boost Mode – factory default setting.
• 5 second timer –
to determine when to exit Auto Boost under normal conditions (i.e. battery
regains its charge) – factory default setting.
• Boost Mode timer (to 10 hours) –
to determine when to exit Boost Mode under fault conditions (i.e. battery
fails to regain its charge and charge current remains high). Programmable
from Operator Control Panel and applied via the CAN bus.

The sub-routine affects the following outputs:

• Charge Mode selection signals ([REC_A> and [REC_B>) –
selects charge mode on Rectifier Logic Board.
• Boost charge status flag –
signalling boost active/inactive/timeout
• Alarm #54 driver [BOOST: TIME EXPIRED]
signalling boost charger timer expired.

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Flow Chart 7-10: Battery Boost

Begin SUB: Boost charge

(Executed every 500ms)

Is an
Is BATTERY TEST Is rectifier in
No No ON GENERATOR No
request active? MANUAL mode?
condition active?

Yes Yes Yes

Is the Automatic Has BOOST

No BOOST function No mode been manually
enabled? selected?
Reset "Batt-in-BOOST" flag to OFF
(i.e. Stop Boost charge even if it is
already in progress) Yes
Yes

Is the battery
current > 10% of the
No Is alarm #54
rated Batt. current
already active (latched)
limit?
[BOOST: TIMER
EXPIRED]?

Yes

Increment 1 minute delay

timer

No

Has delay
timer reached its
No
terminal count
(1min)? Request "BOOST Charge
Mode" to Rectifier Logic Bd
(REC_A=0 / REC_B=1)
Yes Set the "Battery In Boost
Charge" flag = ON.

Start BOOST charge timer

Is the battery
Increment 5 second timer No current > 10% of the rated
current limit?

Has timer Yes

reached its
No Increment BOOST Charge
terminal count
(5 sec)? timer

Request "FLOAT Charge Mode" to

Rectifier Logic Bd (REC_A=1 / Has
Yes REC_B=0) Yes BOOST charge
Activate alarm #54 (latched) timer reached its terminal
Request "FLOAT Charge Mode" [BOOST: TIME EXPIRED] count (10Hrs
to Rectifier Logic Bd (REC_A=1 max)?
/ REC_B=0) Reset 5 second timer

Reset 5 second timer

No

End SUB:
Return to main program

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CHAPTER 7 - System software

7.2.9 Battery Test

A “Battery Test” routine is enabled from the Operator Control Panel and can be
invoked Manually or Automatically at a set date and time (see paragraph [Link]
on page 2-42). When the TEST is invoked the rectifier is turned off and the bat-
teries are discharged for a predefined period (nominally 5 minutes). A check is
made during the TEST period to ensure that the battery voltage does not fall
below a predefined minimum value (nominally 1.9V/Cell). If the battery fails this
check an alarm is annunciated and the rectifier is turned back on to take over the
supply to the inverter.
The battery test subroutine handles the management of the Test process.

The sub-routine is affected by the following inputs:

• Battery voltage ([VB>) –
connected to X2 pin 27 via High Voltage Interface BOard
• Automatic Test date/time start details –
programmed via the Operator Control Panel and applied via the CAN bus.
• Final test voltage threshold (1.9V/cell) –
programmed via the Operator Control Panel and applied via the CAN bus.
• End-of-test (FAIL) debounce delay(1.5s) –
factory-fixed delay time to prevent spurious detections
• Automatic Test duration period –
programmed via the Operator Control Panel and applied via the CAN bus.
• Battery Test request (manual) –
programmed via the Operator Control Panel and applied via the CAN bus.
• Battery Test request (auto) –
programmed via the Operator Control Panel and applied via the CAN bus.
• ‘Rectifier in Manual’ status flag ([st_rad_man>) –
flag set by another sub-routine.
• ‘On Generator’ status flag ([st_grel_blk_car>) –
flag set by another sub-routine.

The sub-routine affects the following outputs:

• Charge Mode selection signals ([REC_A> and [REC_B>) –
selects charge mode on the Rectifier Logic Board (see paragraph 2.3.2 on
page 4-26).
• State of test result on exit ([TST_BAT>) –
OFF = OK and ON = FAIL.
enables alarm #51 driver [BATTERY: TEST FAILED]
• ‘Battery in test’ mode status flag ([abil_tst_bat>) –
ON = Test in progress
enables alarm #50 driver [BATTERY: UNDER TEST ]
•

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Flow Chart 7-11: Battery Test

Begin SUB: Battery TEST (Executed every 500ms)

(Initialisation request)

Is an Is a Manual
Is rectifier in
No ON GENERATOR No OR Automatic Test
MANUAL mode?
condition active? request active?

Yes

Yes
Yes No
Set TST_BAT to OFF (Stop
the Battery Test even if it is
already in progress)

Is the
Increment test duration counter Yes programmed test No
duration >0mins?
Set [abil_tst_bat> flag=ON.
Annunciate alarm #50
[BATTERY: UNDER TEST]
Request "TEST Mode" to
Rectifier Logic Bd
(REC_A=1 / REC_B=1)
set [TST_BAT> = ON Is [tst_bat> = ON
No
(enable the TEST flag) (test enabled)?

Yes

Is the battery Has the TEST

voltage below the duration counter
No No
test threshold? reached its final count?
(1.9V/cell) (5 mins)

Reset delay
No
counter to 0
Yes

Yes

Increment delay counter

Set [TST_BAT> = OFF

Has the delay (Stop the battery test))
counter reached its
No Yes
terminal count? Remove alarm #50
(1.5s) [BATTERY: UNDER TEST]

Request "FLOAT Mode" to

Reset delay Rectifier Logic Bd
counter to 0 (REC_A=1 / REC_B=0)

Activate alarm #51 Reset the test duration

[BATTERY: TEST FAILED] counter to 0

End SUB:
Return to main program

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CHAPTER 7 - System software

7.2.10 Load transfer control logic

[Link] Transfer control system overview

The Transfer Control Logic consists of four sub-routines, each of which is asso-
ciated with a particular transfer control logic state. During each cycle of the main
program (100µs), only one of these four routines is executed, as determined by the
state of the “Load Status Flag” (ST_CA): namely –
• “initialisation” mode (ST_CA = 0).
• “load-on-bypass” mode (ST_CA = 1).
• “load-on-inverter” mode (ST_CA = 2).
• “out-of-sync transfer” mode (ST_CA = 3).

That is, the four routines comprising the Load Transfer Control Logic themselves
form a closed loop which is accessed every 100µs, whereby the selected routine
to be executed is determined by the condition of the “Load Status Flag” (ST_CA)
set on the previous pass. This is illustrated in Figure 7-39.

Example
Assuming that ST_CA is currently set to “1” (load-on-bypass mode).
The load-on-bypass sub-routine’s preferred action is to transfer the load to the in-
verter, after first examining the inverter output voltage status and confirming that
it’s OK.
If the inverter voltage status is found acceptable, this sub-routine grants the output
contactor (K1) “permission to close” and sets ST_CA =2 – which means that on the
next entry to the Transfer Control Logic (100µs later) the load-on-inverter sub-
routine will be selected for execution.
On the other hand, if the inverter voltage status indicates an error condition then
the subroutine will not grant permission to close K1 and ST_CA will remain set to
“1” – which means that the load-on-bypass routine will be executed again the next
time the Transfer Control Logic is called (in 100µs).

Due to its complexity, the four Transfer Control Logic subroutines are described
individually on the following pages.

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Figure 7-39: Transfer Control Logic sub-routines

Power-up

ST_CA=0

ST_CA=0
Initialisation Mode
ST_CA=0 ST_CA=0

ST_CA=1

ST_CA=3
ST_CA=1
Out-Of-Sync Transfer ST_CA=1
Load-On-Bypass Mode
Mode

ST_CA=1

ST_CA=3 ST_CA=2
ST_CA=2
Load-On-Inverter Mode

ST_CA=2

[Link] ST_CA=0 (Load status = Initialisation mode)(See Chart 7-12)

This is the Load Transfer Control Logic subroutine entered during initial power-
up, or when commanded by one of the other sub-routines (See Figure 7-39).
When in this routine, the software examines various flags in order to undertake
any actions appropriate to the “initialisation” mode of operation. For example; if
the bypass voltage status is OK it will lead to closing the bypass SCRs, and if the
inverter output voltage is OK it will lead to closing the output contactor (K1).
Once the appropriate action is determined, the load status flag (ST_CA) is reas-
signed (ST_CA=1 or ST_CA=2) which calls the appropriate sub-routine the next
time the Transfer Control Logic subroutine is executed (in 100µs).
If no appropriate flags are set, the program returns to the main program without
changing ST_CA, –i.e. leaving the load disconnected and ST_CA=0. Thus the next
time the Load Transfer Control Logic subroutine is called (in 100µs) this same in-
itialisation routine will be repeated.

Monitored flags
The initialisation mode sub-routine monitors the following flags:
1. Bypass voltage monitor status – ST_SVI
The bypass voltage is monitored by the UPS Logic Board micro via the High
Voltage Interface Board. The ripple voltage to the A/D allows the individual
monitoring of each phase, and a software routine compares the actual values
against the programmed limit values to set the flag status:

0 = OK (bypass voltage within the mimic-programmed limits [±10%])

1 = LOW (bypass undervoltage [below -10%])
2 = HIGH (bypass voltage high [above +10%])
3 = ABSENT (bypass voltage less than 50V)

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2. Bypass Blocked Status – BL_RETE

This flag is generated by a software routine which monitors the condition of:
• [BLK_MNS> signal (alarm #16) –
which is activated by emergency power off; open bypass SCRs; phase
rotation error; open bypass breaker; PCB power supply failure.
• [TLC_RETE> signal (alarm #17) –
bypass inhibit selection made by operator.

BL_RETE = ON – if either alarm #16 or #17 is active.

BL_RETE = OFF – if alarm #16 or #17 are both inactive.

3. Inverter Voltage Monitor Status – ST_SVINV

The inverter voltage is monitored by the UPS Logic Board micro via the High
Voltage Interface Board. The ripple voltage to the A/D allows the individual
monitoring of each phase, and a software routine compares the actual values
against the programmed limit values to set the flag status:

0 = OK (inverter voltage within the mimic-programmed limits [±10%])

1 = LOW (inverter undervoltage [below -10%]) Activates alarm #37.
2 = HIGH (inverter voltage high [above +10%]) Activates alarm #36.
3 = ABSENT (inverter voltage less than 50V)
4. Operator-selected Inverter ON/OFF – TLC_INV
The Inverter ON/OFF selection from the Operator Control Panel is monitored
by the UPS Logic Board micro via the CAN Bus.

TLC_INV = ON (Start inverter)

TLC_INV = OFF (Stop inverter) Activates alarm #31.

5. Inverter Logic Board Run Status – BL_INV

The Inverter Logic Board’s Stop/Run status is monitored by the UPS Logic
Board micro. When in the inverter Stop mode, alarm #32 will be active.

BL_INV = ON – if Inverter Logic Board Run/Stop control is in its Stop mode.

BL_INV = OFF – if Inverter Logic Board Run/Stop control is in its Run mode.

6. Overload Latch Status – BLK_INV_OVL

Presented to the UPS Logic Board micro from the 150% inverter current limit
detection circuit on the Inverter Logic Board. A software delay allows 5 sec-
onds of inverter operation before alarm #61 is latched.

BLK_INV_OVL = ON – if overcurrent latch is activated –contactor K1 tripped.

BLK_INV_OVL = OFF – if the overcurrent latch is not activated.

7. 10 second stability timer status – BLK_INV_DP

The inverter is given 10 seconds to reach nominal voltage (i.e. within the
mimic-programmed limits).

BLK_INV_DP = ON – block closure of the output contactor (K1).

BLK_INV_DP = OFF – permit closure of the output contactor (K1).

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Flow Chart 7-12: Transfer Control - (ST_CA=0)

Begin SUB: Load transfer
control

Is the load
Is the Is the "bypass
status flag in its
No Yes Bypass Voltage OK? Yes block" status active? No
initialisation state?
(ST_SVI = OK) (BL_RETE = OFF)
(ST_CA=0)
1

No

Yes
To Next Chart
Is the
Yes Inverter Voltage OK?
(ST_SVINV = OK) LOAD ON BYPASS
Set ST_CA = 1
annunciate alarm #18
[LOAD ON BYPASS]
Is the inverter
selected ON from the Set [L_MAINS> = 1
No
Operator Panel? Turn ON bypass SCRs
TLC_INV = ON
Set [L_INV> = 0
No Open inverter contactor (K1)

Yes

Is the "Inverter
No Run" status OK?
[INV_BLK>=OFF

Yes

Is the "Inverter
Yes Overload Block" active?
[BLK_INV_OVL>
=ON

No

Is
the "10s Stability
Timer" latch active? No LOAD ON INVERTER
[BLK_INV_DP> Set ST_CA=2
= ON remove alarm #18
[LOAD ON BYPASS]
Set [L_MAINS> = 0
Turn OFF bypass SCRs

Set [L_INV> = 1
Yes
Close inverter contactor (K1)

End SUB:
Return to Main Program

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[Link] ST_CA=1 (Load status = Load-on-bypass mode) (See Chart 7-13)

This is the Load Transfer Control Logic subroutine entered when the load is con-
nected to the bypass supply; as commanded by ST_CA=0 during the initialisation
routine, or ST_CA=2 while the load is “on-inverter” (See Figure 7-39).
When in this routine, the software examines various flags in order to undertake
any actions appropriate to the “load-on-bypass” mode of operation. For example;
if the inverter voltage status is OK it will lead to the closure of the output contac-
tor (K1), if the bypass voltage fails it will lead to the opening of the bypass SCRs.
Once the appropriate action is determined the load status flag (ST_CA) is reas-
signed (i.e. ST_CA=2 or ST_CA=0) which calls the appropriate sub-routine the next
time the Transfer Control Logic subroutine is executed (in 100µs).
If no appropriate flags are set, the program returns to the main program without
changing ST_CA, – i.e. leaving the load “on-bypass” and ST_CA=1. Thus the next
time the Load Transfer Control Logic subroutine is called (in 100µs) this same
“load-on-bypass” routine will be repeated.

Monitored flags
The “load-on-bypass” mode sub-routine monitors the following flags:
1. Bypass Blocked Status – BL_RETE
This flag is generated by a software routine which monitors the condition of:
• [BLK_MNS> signal (alarm #16) –
which is activated by emergency power off; open bypass SCRs; phase
rotation error; open bypass breaker; PCB power supply failure.
• [TLC_RETE> signal (alarm #17) –
bypass inhibit selection made by operator.

BL_RETE = ON – if either alarm #16 or #17 is active.

BL_RETE = OFF – if alarm #16 or #17 are both inactive.

2. Auto-retransfer Mode Selection – X26:1-2

If jumper X26 pins 1-2 are “made” it allows the examination of the “once-
only” transfer flag (BLK_COM_DP) which is set (ON) if the load has previ-
ously been transferred to the inverter. If X2 pins 1-2 are open this flag is
ignored.
3. Inverter block Latch Status – TMP
Before the load is transferred to the inverter, a temporary flag is enabled
which monitors the status of:
• Overload timeout flag (alarm #61)
• Inverter run flag (alarm #32) – see BL_INV below
• “One-transfer” flag (enabled by X26:1-2 see above)
• 10 second “Stability” flag (enabled by X26:3-4)
• Transfer counter flag (>8 transfers)

If any of the above flags are active, the TMP flag is set to ON and prevents the
inverter output contactor (K1) being closed. Note that if the TMP flag is ON it
can be reset only by selecting the inverter OFF/ON at the Operator Control
Panel.

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4. Inverter Voltage Monitor Status – ST_SVINV

The inverter voltage is monitored by the UPS Logic Board micro via the High
Voltage Interface Board. The ripple voltage to the A/D allows the individual
monitoring of each phase, and a software routine compares the actual values
against the programmed limit values to set the flag status:

0 = OK (inverter voltage within the mimic-programmed limits [±10%])

1 = LOW (inverter undervoltage [below -10%]) Activates alarm #37.
2 = HIGH (inverter voltage high [above +10%]) Activates alarm #36.
3 = ABSENT (inverter voltage less than 50V)

5. Operator-selected Inverter ON/OFF – TLC_INV

The Inverter ON/OFF selection from the Operator Control Panel is monitored
by the UPS Logic Board micro via the CAN Bus.

TLC_INV = ON (Start inverter)

TLC_INV = OFF (Stop inverter) Activates alarm #31.

6. Synchronisation Status – SYNK_OK

A software routine within the PLL sub-routine verifies that the inverter and
bypass voltages are within ±9° of each other. The inverter output contactor
(K1) is inhibited for 5 seconds after this condition is satisfied in order to vali-
date the circuit’s stability and allow time for the PLL to bring the phase dis-
placement error to zero.

SYNK_OK = ON (OK to transfer)

SYNK_OK = OFF (not OK to transfer)

7. Transfer Counter Status – CTR_ATT_RETE

The transfer counter is incremented each time the load is transferred from the
inverter to bypass, and flags an error if more than eight transfers take place
over a one minute period. In such an occurrence the counter locks out the out-
put contactor to prevent further transfers from taking place.
a) Before the load is transferred to the inverter (ST_CA=2), the transfer
counter is checked to see if this is the first transfer-to-inverter event. If it
is, a one minute timer started; if it is not, then the timer is already running.
b) Next, the transfer counter is examined. If the counter contents is less than
eight, the output contactor (K1) is permitted to close. If the counter equals
8 (or more) the one minute timer is examined to see if it has timed-out;
and if so, the temporary flag TMP is enabled (see above) which prevents
the output contactor (K1) closing.
c) The transfer counter is reset to zero if the inverter voltage falls below its
nominal range, thus it is active only as long as the inverter voltage is OK.
8. Inverter Logic Board Run Status – BL_INV
The Inverter Logic Board’s Stop/Run status is monitored by the UPS Logic
Board micro. When in the inverter Stop mode, alarm #32 will be active.

BL_INV = ON – if Inverter Logic Board Run/Stop control is in its Stop mode.

BL_INV = OFF – if Inverter Logic Board Run/Stop control is in its Run mode.

9. 10s stability counter enable status – X26:3-4

The inverter is allowed 10 seconds to reach its nominal voltage (i.e. within its
selected working voltage range [±10% default]). If the inverter fails to satisfy

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CHAPTER 7 - System software

this condition it is turned OFF and alarm #32 annunciated. This feature can be
enabled/disabled via jumper X26 pins 3-4 (closed = enabled); the status of
which is read by this subroutine.
[Link] voltage monitor status – ST_SVI
The bypass voltage is monitored by the UPS Logic Board micro via the High
Voltage Interface Board. The ripple voltage to the A/D allows the individual
monitoring of each phase, and a software routine compares the actual values
against the programmed limit values to set the flag status:

0 = OK (bypass voltage within the mimic-programmed limits [±10%])

1 = LOW (bypass undervoltage [below -10%]) Activates alarm #12.
2 = HIGH (bypass voltage high [above +10%]) Activates alarm #11.
3 = ABSENT (bypass voltage less than 50V) Activates alarm #10.

11.150% Current Limit Status – OVL_INV

The 150% overload condition is detected on the Inverter Logic Board and
passed to the UPS Logic Board micro. Alarm #33 annunciates the overload
fault condition.
The ST_CA=1 sub-routine monitors this signal to enable it to hold the load
“on-bypass”, even if the bypass voltage is outside its programmed voltage
limits, once the inverter is feeding a short-circuit present between the inverter
power blocks and the output contactor (K1).

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Flow Chart 7-13: Transfer Control - (ST_CA=1)

From Previous Chart

Is the load
Is the "bypass
status flag in its Set ST_CA = 0
Yes block" status active? Yes
Load-on-bypass mode? (return to intialise mode)
(BL_RETE = ON)
(ST_CA=1)
Set [L_MAINS> = 0
Turn OFF bypass SCRs

No Set [L_INV> = 0
No Open inverter contactor (K1)

Is X26:1-2 Closed?
To Chart 7-14 (only one transfer to Yes
inverter allowed)

No
Reset "Once Only Transfer " Is the "once only
flag to OFF transfer" flag activated?
(i.e. load on inverter
once before)

Enable Inverter OFF latch No

(TMP=ON) Yes
To monitor:

1. Overload timeout flag Set Transfer counter = 0

2. Inverter block flag
3. Transfer counter >8
4. Once only transfer flag
5. 10s Stability flag

(If any of the above is activated

then TMP=ON, else TMP=OFF)

Is the inverter Is
Is the inverter
selected ON at the the "inverter Off
Yes voltage OK? Yes Yes
mimic panel? Latch" active?
(ST_SVINV=OK)
(TLC_INV=ON) (TMP=ON)

No

Disable Inverter OFF latch

(TMP=ON) No No
End SUB:
(Use the mimic display to rest the Return to Main Program
latch trigger source from 1 -5 in
above dialog box)

A B C

To Next Chart To Next Chart To Next Chart

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CHAPTER 7 - System software

Flow Chart 7-13: Continued

From Previous Chart From Previous Chart

A B C

Is the inverter Is the inverter in

voltage not OK? No No sync with bypass?
(ST_SVINV=KO) SNYK_OK=ON

Yes Yes

Is "Inverter Run"
Is the transfer
signal present? No Yes
counter at zero?
(BL_INV=OFF)

Start the 1 minute timer

Yes
No

Is
X26:3-4 Closed? Is the transfer
No Yes
(10s inverter stability counter >8?
check enabled)

Yes Has 1 minute

No
timer expired?

Has 10s delay

No
expired? Yes No

Set Counter >8 flag ON

(CTR_ATT_RETE = ON)
Yes (trigger Alarm #60)
This will also set (TMP=ON)
Turn Inverter OFF Reset 1 minute counter = 0
Set BLK_INV = ON
(trigger Alarm #32)
Activate 10Sec Stability flag
(i.e. TMP = ON) Is the 5 seconds
No "wait in bypass"
delay expired?
Are the bypass
volts OK? Yes
(ST_SVI = 0)
Yes
Set ST_CA = 2
(Load on inverter mode)
No
Is the inverter
Set [L_MAINS> = 0
current limit active? Yes
Turn OFF bypass SCRs
OVL_INV=ON
Set [L_INV> = 1
Close inverter contactor (K1)

No Set "Once only transfer" flag

Set ST_CA = 0 (i.e. TMP = ON)
(return to initialise mode)
Set [L_MAINS> = 0
Turn OFF bypass SCRs
Set [L_INV> = 0
Open inverter contactor (K1)

End SUB:
Return to Main Program

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7200 Series UPS Service Manual SECTION 7 - UPS System Control
CHAPTER 7 - System software

[Link] ST_CA=2 (Load status = Load-on-inverter mode)

This is the Load Transfer Control Logic subroutine entered when the load is con-
nected to the inverter supply; as commanded by ST_CA=0 during the initialisa-
tion routine, or ST_CA=1 while the load is “on-bypass” (See Figure 7-39).
When in this routine, the software examines various flags in order to undertake
any actions appropriate to the “load-on-inverter” mode of operation. For example;
if the inverter voltage status is not OK (KO) it will lead to the closure of the bypass
SCRs and the opening of the output contactor (K1). Once the appropriate action
is determined the load status flag (ST_CA) is reassigned (i.e. ST_CA=1 or ST_CA=3)
and the next time the Load Transfer Control Logic subroutine is called (in 100µs)
then the appropriate sub-routine will be executed.
If no appropriate flags are set, the program returns to the main program without
changing ST_CA, – i.e. leaving the load “on-inverter” and ST_CA=2. Thus the
next time the Load Transfer Control Logic subroutine is executed (in 100µs) this
same “load-on-inverter” routine will be called.

Monitored flags
The “load-on-inverter” mode sub-routine monitors the following flags:
1. Output Voltage Monitor Status – ST_SVO
The output voltage is monitored by the UPS Logic Board micro via the High
Voltage Interface Board. The ripple voltage to the A/D allows the individual
monitoring of each phase, and a software routine compares the actual values
against the programmed limit values to set the flag status:

0 = OK (output voltage within the mimic-programmed limits [±10%])

1 = LOW (output undervoltage [below -10%]) Activates alarm #40.
2 = HIGH (output voltage high [above +10%]) Activates alarm #39.
3 = ABSENT (output voltage less than 50V) Activates alarm #41.

2. Inverter Logic Board Run Status – BL_INV

The Inverter Logic Board’s Stop/Run status is monitored by the UPS Logic
Board micro. When in the inverter Stop mode, alarm #32 will be active.

BL_INV = ON – if Inverter Logic Board Run/Stop control is in its Stop mode.

BL_INV = OFF – if Inverter Logic Board Run/Stop control is in its Run mode.

3. Operator-selected Inverter ON/OFF – TLC_INV

The Inverter ON/OFF selection from the Operator Control Panel is monitored
by the UPS Logic Board micro via the CAN Bus.

TLC_INV = ON (Start inverter)

TLC_INV = OFF (Stop inverter) Activates alarm #31.

4. Bypass voltage monitor status – ST_SVI

The bypass voltage is monitored by the UPS Logic Board micro via the High
Voltage Interface Board. The ripple voltage to the A/D allows the individual
monitoring of each phase, and a software routine compares the actual values
against the programmed limit values to set the flag status:

0 = OK (bypass voltage within the mimic-programmed limits [±10%])

1 = LOW (bypass undervoltage [below -10%]) Activates alarm #12.
2 = HIGH (bypass voltage high [above +10%]) Activates alarm #11.
3 = ABSENT (bypass voltage less than 50V) Activates alarm #10.

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SECTION 7 - UPS System Control 7200 Series UPS Service Manual
CHAPTER 7 - System software

5. Bypass Blocked Status – BL_RETE

This flag is generated by a software routine which monitors the condition of:
• [BLK_MNS> signal (alarm #16) –
which is activated by emergency power off; open bypass SCRs; phase
rotation error; open bypass breaker; PCB power supply failure.
• [TLC_RETE> signal (alarm #17) –
bypass inhibit selection made by operator.

BL_RETE = ON – if either alarm #16 or #17 is active.

BL_RETE = OFF – if alarm #16 or #17 are both inactive.

6. Synchronisation Status – SYNK_OK

A software routine within the PLL sub-routine verifies that the inverter and
bypass voltages are within ±9° of each other. The inverter output contactor
(K1) is inhibited for 5 seconds after this condition is satisfied in order to vali-
date the circuit’s stability and allow time for the PLL to bring the phase dis-
placement error to zero.

SYNK_OK = ON (OK to transfer)

SYNK_OK = OFF (not OK to transfer)

7. Transfer Counter Status – CTR_ATT_RETE

The transfer counter is incremented each time the load is transferred from the
inverter to bypass, and flags an error if more than eight transfers take place
over a one minute period. In such an occurrence the counter locks out the out-
put contactor to prevent further transfers from taking place.
a) Before the load is transferred to the inverter (ST_CA=2), the transfer
counter is checked to see if this is the first transfer-to-inverter event. If it
is, a one minute timer started; if it is not, then the timer is already running.
b) Next, the transfer counter is examined. If the counter contents is less than
eight, the output contactor (K1) is permitted to close. If the counter equals
8 (or more) the one minute timer is examined to see if it has timed-out;
and if so, the temporary flag TMP is enabled (see above) which prevents
the output contactor (K1) closing.
c) The transfer counter is reset to zero if the inverter voltage falls below its
nominal range, thus it is active only as long as the inverter voltage is OK.
8. 150% Current Limit Status – OVL_INV
The 150% overload condition is detected on the Inverter Logic Board and
passed to the UPS Logic Board micro. Alarm #33 annunciates the overload
fault condition. The purpose of monitoring the flag in this instance is to force
the inverter to feed a short circuit for 5 seconds if the bypass is absent.
9. 10s stability counter enable status – X26:3-4
If this function is enabled, and the bypass voltage is unavailable, the inverter
is allowed 10 seconds to reach its nominal voltage (i.e. within its selected
working voltage range [±10% default]). If the inverter fails to satisfy this con-
dition it is turned OFF and alarm #32 annunciated. This feature can be ena-
bled/disabled via jumper X26 pins 3-4 (closed = enabled); the status of which
is read by this subroutine. If this function is disabled, the critical bus status
has no influence on the inverter run signal.

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7200 Series UPS Service Manual SECTION 7 - UPS System Control
CHAPTER 7 - System software

Flow Chart 7-14: Transfer Control - (ST_CA=2)

From Chart 7-13

Is the
Is the load
"critical bus volts
status flag in its
Yes monitor" status OK? No
Load-on-inverter mode?
(ST_SVO = 0)
(ST_CA=2)

No Yes

3 Is the "inverter
No Run" status OFF? Yes
BL-INV=OFF
To Chart 7-15

Is the
Inverter selected Is the
OFF at the Mimic Panel? Yes bypass voltage OK? Yes
(TLC_INV=OFF) (ST_SVI=0)

No

Is the "inverter Is the

Yes Run" status OFF? Yes bypass block active?
BL-INV=OFF (BL_RETE=ON)

No

No No
Is the
Inverter selected
Yes OFF at the Mimic Panel?
(TLC_INV=OFF)

Set ST_CA = 0
Is the inverter in
Set [L_MAINS> = 0
No sync with the bypass?
Turn OFF bypass SCRs
(SNYK_OK=ON)
Set [L_INV> = 0
Open inverter contactor (K1) No

Reset Transfer Counter

Yes

D E F
End SUB:
Return to Main Program
To next chart To next chart To next chart

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SECTION 7 - UPS System Control 7200 Series UPS Service Manual
CHAPTER 7 - System software

Flow Chart 7-14: Continued

From previous chart From previous chart From previous chart

D E F

Is the 150%
current limit flag active? Yes Set ST_CA = 1
Set ST_CA = 3
(OVL_INV=ON) Set [L_MAINS> = 1
Set [L_MAINS> = 0 Turn ON bypass SCRs
Turn OFF bypass SCRs Set [L_INV> = 0
Open inverter contactor (K1)
Set [L_INV> = 0
Increment transfer counter
Open inverter contactor (K1)
Start 5 second "wait in
bypass" delay timer

Has 5 second
No
timer expired?
Is the
Inverter selected
No OFF at the Mimic Panel?
(TLC_INV=OFF)
Yes
No
Set ST_CA = 0
Set [L_MAINS> = 0 Yes
Turn OFFbypass SCRs
Set [L_INV> = 0
Open inverter contactor (K1) Turn Inverter OFF for 1 sec.
Reset transfer counter
Set Blk_INV=ON
Alarm #32

Activiate Overload Alarm #61

End SUB:
Is X26:3-4 Return to Main Program
Yes
closed?

Has the 10s

Yes
delay expired?

Set ST_CA = 0
Set [L_MAINS> = 0
Turn OFFbypass SCRs
Set [L_INV> = 0
Open inverter contactor (K1)
Reset transfer counter

No Set Blk_INV=ON
Alarm #32
Set 10s Stability flag=ON
(i.e. TMP=ON)

No

End SUB:
Return to Main Program

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7200 Series UPS Service Manual SECTION 7 - UPS System Control
CHAPTER 7 - System software

[Link] ST_CA=3 (Load status = Out-of-Sync transfer mode)

This is the Load Transfer Control Logic subroutine entered when commanded by
ST_CA=2 while the load is “on-inverter” (See Figure 7-39).
When in this routine, the software examines various flags in order to undertake
any actions appropriate to the “out-of-sync” mode of operation. For example;
once an out-of-sync transfer has occurred, a three second break is introduced
before the bypass SCRs are closed.
Once the appropriate actions are taken, the load status flag is re-assigned to either
ST_CA = 1 or ST_CA = 0, which calls for one of the routines described earlier to
be executed on the next pass of the main program.
If no appropriate flags are set, the program returns to the main program without
changing the load status flag (ST_CA still = 3). Thus the next time the Load
Transfer Control Logic subroutine is executed (in 100µs) this same “out-of-sync”
subroutine will be called.

Monitored flags
The “out-of-sync” transfer mode sub-routine monitors the following flags:
1. Output contactor (K1) status flag – XSTAI2
This flag is initially set (OFF) as K1 is closed while the load is “on-inverter”
(ST_CA=2). When undertaking an “out-of-sync” transfer, contactor K1
should open, then after a delay of 3 seconds the bypass SCRs should be
turned ON. The 3 second delay is controlled by the system software and is
initiated when XSTAI2 indicates that K1 is open. Note that XSTAI2 is con-
nected to K1 auxiliary contacts and sensed via the High Voltage Interface
Board.

XSTAI2 = ON (K1 contactor is closed)

XSTAI2 = OFF (K1 contactor is open)

2. Bypass Blocked Status – BL_RETE

This flag is generated by a software routine which monitors the condition of:
• [BLK_MNS> signal (alarm #16) –
which activated by emergency power off; open bypass SCRs; phase rota-
tion error; open bypass breaker; PCB power supply failure.
• [TLC_RETE> signal (alarm #17) –
bypass inhibit selection made by operator.

BL_RETE = ON – if either alarm #16 or #17 is active.

BL_RETE = OFF – if alarm #16 or #17 are both inactive.

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SECTION 7 - UPS System Control 7200 Series UPS Service Manual
CHAPTER 7 - System software

Flow Chart 7-15: Transfer Control - Initialisation mode (ST_CA=3)

From chart 7-14

Is
the load
Is K1 Status
status flag in its "Out-
Yes Monitor Disabled? No
of-sync transfer" mode?
(XSTAI=ON)
(ST_CA=3)

Yes

No Is K1 Open yet
(XSTAI2=ON)

Has the 3 sec time

No
delay expired?

No
Yes

Yes

Start 3 second time delay

disable K1 Status Monitor

Is the Bypass Set XSTAI2 = ON)
No Block status active? Yes
(BL_RETE=ON)

Set ST_CA = 1
Set ST_CA = 0
(annunciate Alarm #16)
Set [L_MAINS> = 1 Set [L_MAINS> = 0
Turn ON bypass SCRs Turn OFF bypass SCRs

Set [L_INV> = 0 Set [L_INV> = 0

Open inverter contactor (K1) Open inverter contactor (K1)

Increment Transfer Counter Reset Transfer Counter

End SUB:
Return to Main Program

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 Section 8: ‘1+1’ UPS System Control

Chapter 1 - "1+1" Configured Systems

1.1 Introduction .............................................................................................. 8-1
1.1.1 “1+1” Power circuit considerations ............................................. 8-1
1.1.2 “1+1” Control circuit considerations ........................................... 8-1
Chapter 2 - Parallel Logic Board – 4520075B
2.1 Chapter Overview. .................................................................................... 8-5
2.2 General Description .................................................................................. 8-5
2.2.1 Input/Output connections ............................................................. 8-5
2.2.2 Circuit board functions .............................................................. 8-10
2.3 General module output control ............................................................... 8-12
2.3.1 Inverter ON/OFF request – [OFF_INV> ........................................ 8-12
Selective shutdown .......................................................... 8-13
2.3.2 Load transfer control .................................................................. 8-15
Load-on-inverter request – [C_L_INV> .......................... 8-16
Load-on-bypass request – [O_BUS_INV_L> ................. 8-17
2.4 Frequency synchronisation principles .................................................... 8-19
2.4.1 Introduction ................................................................................ 8-19
Inverter frequency control – overview ............................. 8-19
Basic GVCO sync principles on module start-up ............ 8-20
2.4.2 GVCO Detailed description of operation .................................. 8-23
2.4.3 PLL Phase Comparator (D29) ................................................... 8-26
2.4.4 D30 Parallel Control Functions ................................................. 8-26
Bypass validation ............................................................. 8-27
Sync source selector ......................................................... 8-27
Sync bus comparator ........................................................ 8-28
VCO-in-loop relay control ............................................... 8-28
Internal Sync Logic .......................................................... 8-29
2.5 Output current sharing ............................................................................ 8-31
2.5.1 Introduction ................................................................................ 8-31
2.5.2 Current sharing error detection principles ................................. 8-31
2.5.3 Current-sharing relay control (K3/K4) ...................................... 8-33
2.5.4 Selective shutdown .................................................................... 8-34
Current-sharing error ....................................................... 8-34
Reverse Power detector .................................................... 8-35
Forward Power detector ................................................... 8-35
2.5.5 On-line module counter ............................................................. 8-35
2.6 Parallel rectifier operation ...................................................................... 8-36
2.6.1 Rectifier current-sharing control ................................................ 8-36
2.6.2 Boost charge control .................................................................. 8-37
2.6.3 Battery test control ..................................................................... 8-37

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SECTION 8 - ‘1+1’ UPS System Control 7200 Series UPS Service Manual

2.7 Other Features and functions .................................................................. 8-38

2.7.1 Ribbon cable connection monitor .............................................. 8-38
2.8 Parallel Logic Board circuit operation during start-up ........................... 8-39
2.8.1 Initialisation/reset ....................................................................... 8-39
2.8.2 Inverter run-up and synchronisation .......................................... 8-39
2.8.3 Connecting to the parallel control bus ....................................... 8-40
2.8.4 Load transfer to inverter ............................................................. 8-40
2.8.5 Load retransfer back to bypass .................................................. 8-42
2.9 Test mode of operation: .......................................................................... 8-42

ii 11pm.fm5 - Issue 2 Dated 21/08/97

 Section 8: "1+1" Configured Systems

Chapter 1 - "1+1" Configured Systems

1.1 Introduction
A basic description of the principles of a “1+1” configured system is provided in
section 1 (see paragraph 1.4 on page 1-7) – the basic block diagram is repeated
in Figure 8-1, below.

Figure 8-1: “1+1” System configuration block diagram

RECTIFIER INVERTER INV (SS)

Inverter Static
Rectifier BYP (SS)
Control Logic Bypass
Control Logic

Static Switch
Inter-Module Parallel Control Logic
Control Logic
Maint. Bypass
Output
(LOAD)
Power-
Supply
Maint. Bypass
Static Switch
Inter-Module Parallel Control Logic
Control Logic

Rectifier Inverter
Static BYP (SS)
Control Logic Control Logic
Bypass

RECTIFIER INVERTER INV (SS)

1.1.1 “1+1” Power circuit considerations

As the above diagram shows, in a ‘1+1’ system the power outputs from the two
modules are connected to an external common output busbar from where it is
routed to the critical load equipment using normal distribution methods. There-
fore, from a ‘power’ point of view there are no modifications required to the
standard ‘single-module’ UPS.

1.1.2 “1+1” Control circuit considerations

The extra ‘control’ requirements of a ‘1+1’ system over that of a ‘single-module’
are quite extensive due to the fact that the UPS output power terminals are con-
nected to a common bus. The additional features require an exchange of various
control and status signals, both analogue and digital, to pass between the two
modules. Such signals are connected via the Parallel Logic Boards which are con-
nected together by cross-connected ribbon cables which form a ‘Parallel Control
Bus’ – (See Figure 8-2).

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SECTION 8 - "1+1" Configured Systems 7200 Series UPS Service Manual
CHAPTER 1 - "1+1" Configured Systems

Figure 8-2: ‘1+1’ Control Logic

Parallel
MODULE 1 MODULE 2
X3 Bus X3
Parallel Parallel
Logic Logic
Board Board
X1 X2 X2 X1

X7 X7
Rect. Logic Bd X1 X1 Rect. Logic Bd
X3 X3
Inv. Logic Bd Inv. Logic Bd
UPS UPS
Logic Logic
Static Sw. Drv. Bd Board Board Static Sw. Drv. Bd
X5 X5
High Voltage I/F Bd High Voltage I/F Bd
X2 X2

These inter-module control functions fall into the following broad categories:

Balanced output requirements

It is crucial that the modules’ outputs are balanced in order to prevent a circulating
current flowing from one module to the other, as such an event could cause sig-
nificant module damage and invalidate the critical load supply. Balanced condi-
tions are achieved by ensuring that the inverters are always fully synchronised to
each other and their output voltages are equal. As with the case of the ‘single-
module’ it is also necessary to synchronise the inverters to the bypass supply in
order facilitate a no-break load transfer when required.

Transfer control requirements

Once again due to the paralleled nature of the modules’ outputs, it is crucial that
the load transfer control mechanisms in each module are controlled from a
common point. That is, to prevent equipment damage due to one module transfer-
ring its output to bypass whilst the other is ‘on inverter’. A common control
system is therefore used which manages the load transfer according whether the
system is configured as redundant or non-redundant.

Redundant vs Non-Redundant configuration

Redundant system. In a ‘redundant’ system, if one module fails the remaining
module will remain on-line to maintain the critical load; therefore if a module
goes faulty its output contactor is tripped to take it off-line but its static bypass is
not activated. The static bypass circuit is only triggered if a fault develops in the
second module which requires it also to be taken off-line.
In a redundant system the modules are thus sized such that the potential maxi-
mum load can be powered by just one of the two modules. Under normal circum-
stances both modules are operational and share the load current equally – i.e.
under full load conditions both modules operate at 50% of their nominal rating.

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7200 Series UPS Service Manual SECTION 8 - "1+1" Configured Systems
CHAPTER 1 - "1+1" Configured Systems

Non-redundant system. In a ‘non-redundant’ configuration, if one module

fails then both modules are taken off-line (by opening their output contactors) and
the load transferred to the static bypass. The load will not re-transfer to the invert-
ers until both inverters are fully operational and fully synchronised etc.
In a non-redundant system each module’s nominal rating must be at least 50% of
the potential maximum load.

Inter-module power rectifier control

The power rectifier is only affected by the parallel control bus in a “1+1” system
if a ‘common battery’ is used – i.e. if both UPS modules are connected to a single
battery bank (via separate battery isolators of course). In this type of installation
the power rectifiers in each module are effectively connected in parallel and must
be controlled such that the battery charge current is shared equally between them.
A ‘common battery’ option kit is available. This contains DCCTs (DC Current
Transformers) which are fitted to the battery power lines and connected via the
parallel control bus to a sharing circuit in the rectifier control block.
See the Options section in the relevant system IOM user manual for full details.

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SECTION 8 - "1+1" Configured Systems 7200 Series UPS Service Manual
CHAPTER 1 - "1+1" Configured Systems

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 Section 8:

Chapter 2 - Parallel Logic Board – 4520075B

2.1 Chapter Overview.

This chapter contains a circuit description of the Parallel Logic Board used across
the whole 7200 Series UPS model range when configured to operate as a ‘1+1’
system, and should be read in conjunction with circuit diagram SE-4520075-B (4
pages). Signal annotations shown on the circuit diagrams are shown in italics in
the following text – e.g. [SYN_INT>.

2.2 General Description

2.2.1 Input/Output connections

Connectors X2 & X3
As mentioned above, connectors X2 & X3 are cross-connected from one module
to the other – i.e. X2 on one module is connected to X3 on the other, and vice-
versa. The signals passing between these connectors are therefore bi-directional.
Table 8-1:

Pin Signal Signal Function

1 A_CON / 0V Used to detect that the ribbon cable is connected –

2 B_CON / 0V (See paragraph 2.7.1)

If a module applies an [O_BLK_SW> signal to X1-43 it

is passed to both modules via this line, and thereby
3 B_BLK_SW
turns off the inverters in both modules by driving the
[OFF_INV> output at D31-19 high. (see page 8-12)

If a module applies an [O_MNS_L_SS> signal to X1-

44 it is passed to both modules via this line. This is
used by the load transfer control logic when the board
4 B_MNS_L_SS
is fitted in a multi-module MSS cabinet only, and is
overridden in a 1+1 system by jumper X6-4(see page
8-16).

If a module applies an [O_MNS_D_SS> signal to X1

pin 45 it inhibits the passage of the mains frequency
5 B_MNS_D_SS signal [F-IN> through D31 (See paragraph [Link]).
This signal is coupled to the second module via the
parallel bus X2/X3 pin 5 (inhibit = low).

This is taken high when the VCO-in-loop relay (K1) is

closed in either module, and is used to inform the
6 B_PAR_SYN
GVCO whether to start in the “master” or “slave” mode
during turn-on (See paragraph [Link]).

The [O_MNS_SYN_OK> signal to X1-48 informs the

Parallel Logic Board when the Inverter Logic Board’s
7 B_MNS_SYN_OK master oscillator is “internally synchronised”. This is
applied to the ‘bypass validation’ circuit in both mod-
ules (See paragraph [Link])

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SECTION 8 - "1+1" Configured UPS System Control 7200 Series UPS Service Manual
CHAPTER 2 - Parallel Logic Board

Pin Signal Signal Function

Used when common battery system is used to force

8 B_BST_BAT both modules into boost mode if selected in either
module (See paragraph 2.6.2).

This line couples together the [O_MNS_DIS> input to

X1-49. When [O_MNS_DIS> is low in both modules
9 B_MNS_DIS
the bus line goes high and feeds back a logic high to
the UPSLB via X1-37 [MNS_DIS>

This line couples the load-on-bypass request and is

logic high (requesting load on inverter) only when nei-
10 B_INV_LOD
ther module is calling for “load on inverter”. This line
affects the output on X1-32 (See paragraph [Link])

This line is connected to the GVCO [FRQ_OSC> out-

put if relay K1 is closed (in either module,) and thereby
11 B_FREQ_PAR
forms the parallel GVCO sync bus (See paragraph
[Link]).

This line, goes low only when the VCO in loop relay
(K1) is closed in both modules, and is used to signal
12 B_INV_IND
the availability of both modules in a non-redundant
system.

Used when common battery system is used to force

13 B_TST_BAT both modules into TEST mode if selected in either
module (See paragraph 2.6.3).

High when Maintenance Bypass Switch is closed in

14 B_SW_BYP
either module (see X1 - 34).

This line carries the bypass (mains) frequency signal

15 B_FREQ_MNS between the modules when it has been accepted by
the bypass validation circuit (See paragraph [Link]).

16-
- NIU
18

19
- 0V
20

21 COMM_P These two lines are used to parallel the battery current
sense signals when required. Not used for a particular
22 I_B_P purpose on this board. input via X1 18/19.

This line connects the ‘available module counter’ cir-

24 O_N_INV cuits together to allow the number of available mod-
ules to be detected (See paragraph 2.5.5).

23 B_IM_0
25 B_IM_C
26 B_IM_R These lines carry the current sharing sense signals
27 B_IM_A (See paragraph 2.5)
28 B_IM_B
29 B_C_0
30 B_C_P

31
0V
32

33 - NIU

34 B_GND Parallel bus ground connection

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7200 Series UPS Service Manual SECTION 8 - "1+1" Configured UPS System Control
CHAPTER 2 - Parallel Logic Board

Connector X1
Table 8-2:

Pin Signal Signal Function

1-4 0V

5-8 +12V

9 - 10 -12V

11 VO_A
Output voltage sense signals derived on the High
12 VO_B Voltage Interface Board. Used by the ‘selective shut-
down’ circuit (See paragraph 2.5.4).
13 VO_C

14 COM Analogue sense signal common

15 IO_A
Output current sense signals derived on the High
16 IO_B Voltage Interface Board. Used by the current sharing
and selective shutdown circuits (See paragraph 2.5).
17 IO_C

18 I_B_P These two inputs are used to parallel the battery cur-
rent sense signals when required. Not used for a par-
19 COMM_P ticular purpose on this board but connected directly to
second module via parallel bus X2/X3 pins 21/22.

20 DV_A These outputs are generated by the current sharing

circuit and go to the Inverter Logic Board (via UPSLB)
21 DV_B where they perform individual fine adjustment of each
22 DV_C output line voltage to balance the line currents
between the two paralleled machines. DV-0 is a neu-
23 DV_0 tral point for these signals (See paragraph 2.5.2).

Input from rectifier current sense amp on Rectifier

Logic Board. This represents the rectifier current
24 IREC_T taken by this module and is used by the current shar-
ing circuit if a common battery system is used (See
paragraph 2.6.1).

This output is the result of the rectifier current sharing

circuit and passes to the Rectifier Logic Board in the
25 DB form of a correction signal to ensure balanced input
currents to both modules when a common battery
system is used (See paragraph 2.6.1).

26 - NIU

27-28 0V

29-30 - +5V

31 - NIU

This is a logic low load-on-bypass request to the con-

trol logic on UPSLB. Due to the parallel bus connec-
32 I_BUS_INV_L tion (X2/3 - 10) the output is low only when load-on-
bypass is requested by both modules (See paragraph
[Link]).

This is an input via HVIB which is low when the Out-

33 SW_OUT
put Switch is closed (see page 8-13).

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Pin Signal Signal Function

This is an input via HVIB which is low when the Main-

34 SW_BYP tenance Bypass Switch is closed in either module
(see page 8-13).

Output to UPSLB which, when high, initiates Battery

35 I_BST_BAT Boost. Used in common battery system only and is
enabled by jumper X6-2.(See paragraph 2.6.2)

Output to UPSLB which, when high, initiates Battery

36 I_TST_BAT Test. Used in common battery system only and is
enabled by jumper X6-2. (See paragraph 2.6.3)

The input to X1-49 from the UPSLB goes high.

This input is coupled together via the parallel control
37 MNS_DIS bus (X2/3 - 9), and when [O_MNS_DIS> is low in
both modules a logic high is fed back to the UPSLB
via X1-37 [MNS_DIS>

Output to the UPSLB which is high when the ‘selec-

38 BLK_SEL tive shutdown’ circuit is active (led H1 illuminated)
(See paragraph [Link]).

Output to inverter ON/OFF control logic on UPSLB.

39 OFF_INV
Turns OFF inverter if high. (See paragraph 2.3.1)

Output to load-on-inverter control logic on UPSLB.

40 C_L_INV Requests load on inverter selection if high (See para-
graph [Link]).

Input from the reset circuit on the UPSLB which,

41 RES_EXT when high, resets several functions within the Parallel
Logic Board ASIC devices.

Input from the UPSLB reset generator chip which

42 V_AUX resets various latches within D39 and D31on power-
up. The signal is a 1 second logic high pulse.

Input from the UPSLB software-controlled inverter off

signal [O_BLK_SW>. The signal is also coupled to
the second module via X2/X3 pin 3 which enables the
43 O_BLK_SW
inverters in both modules to be turned off if a
[O_BLK_SW> signal is generated in either module
(See paragraph 2.3.1)

This input is used by the load transfer control logic

when the board is fitted in a multi-module MSS cabi-
44 O_MNS_L_SS
net, it is not functional in a 1+1 system due to config-
uration jumper X6-4. (see page 8-16).

Input from the UPSLB processor system. When high,

it inhibits the passage of the mains frequency signal
45 O_MNS_D_SS [F-IN> through the bypass validation circuit. This sig-
nal is coupled to the second module via the parallel
bus X2/X3 pin 5 (See paragraph [Link]).

Input from the UPSLB processor system which goes

46 O_TST_BAT high when it calls for a battery test sequence (See
paragraph 2.6.3).

Input from UPSLB which, when high, requests Bat-

47 O_BST_BAT
tery Boost (See paragraph 2.6.2).

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CHAPTER 2 - Parallel Logic Board

Pin Signal Signal Function

Input from UPSLB which is low when the Inverter

48 O_MNS_SYN_OK Logic Board’s master oscillator has achieved internal
synchronisation (See paragraph [Link]).

The input to X1-49 from the UPSLB goes high.

This input is coupled together via the parallel control
49 O_MNS_DIS bus (X2/3 - 9), and when [O_MNS_DIS> is low in
both modules a logic high is fed back to the UPSLB
via X1-37 [MNS_DIS>.

This input is driven by the fault output on the Inverter

50 BLK_INV Logic Board and provides an input to the ‘sync source
selector’ circuit (See paragraph [Link])

Input from the UPS Logic Board Processor system

51 PAR_REC which is high when it is programmed with parallel rec-
tifier operation (See paragraph 2.6).

This input from the UPS Logic Board goes high when
52 INV_L the load is “on-inverter” and is used to validate the
‘selective shutdown’ circuit (See paragraph [Link]).

This is connected to the GVCO output [FRQ_OSC>

and thereby represents the reference frequency to
53 FRQ_SYN
which the UPS inverter synchronises (See Figure 8-
5).

This output passes the parallel sync bus frequency to

54 FRQ_PAR
the UPS Logic Board (See Figure 8-5).

This input is a squarewave at the incoming mains R-

phase frequency, used as the bypass reference fre-
55 F_IN
quency is accepted by the ‘bypass validation’ circuit
(See paragraph [Link]).

56 - NIU

This input is high when the UPS Logic Board deter-

mines that the inverter is operating normally and is
57 INV_OK
used by the synchronisation control logic within D30
during start-up (See paragraph 2.4.4).

This input is generated on the UPS Logic Board and

is logic high when the battery is low or the bus voltage
58 CON_SEL is 150% of nominal charge voltage. This is used by
the ‘selective shutdown’ circuit (See paragraph
[Link])

This output goes low when the [SWBYP> input to X1-

34 is low in either module (i.e. when Maintenance
59 I_SW_BYP
Bypass Switch is closed in either module) (see page
8-13).

This input is generated by the UPS Logic Board and

is low, to disable the “load on bypass” request, if the
60 N_AUX_CONT
inverter output contactor is closed (See paragraph
[Link]).

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CHAPTER 2 - Parallel Logic Board

2.2.2 Circuit board functions

Figure 8-2 illustrates the position of the Parallel Logic Board in a ‘1+1 config-
ured’ module. The inter-module control signals pass from one module to the other
by means of the ribbon-cables fitted to the boards’ X2 and X3 connectors, which
are cross-coupled – i.e. X2 on one Parallel Logic Board is connected to X3 on the
other. Due to their function, the ribbon cables connecting the two boards together
are referred to in this manual as the “parallel control bus”. The parallel control
functions will be maintained if one of the two cables is disconnected but for safety
reasons both cables should normally be connected – led H2 illuminates if one
cable becomes disconnected, but the system is not otherwise affected.
The third connector (X1) on the Parallel Logic Board is connected to the UPS
Logic Board from where it has access to the remaining module control boards.
This topology allows any control board in one module to communicate with any
control board in the second module, as required by the control regime.
In addition to its role in providing a parallel control bus, the Parallel Logic Board
contains a number of active circuits whose functions are summarised below.
Note: each of the following categories are assigned major section headings in the
remainder of this chapter:

General module output control

The Parallel Logic Board generates control logic signals which:
• provides an Inverter Start/Stop command signal which is connected as an
input to the Inverter Start/Stop control logic on the UPS Logic Board.
• provides the ‘static switch control section’ of the UPS Logic Board with
load transfer control signals which determine whether the load is con-
nected to the inverter (output contactor closed) or static bypass supply.
• monitors the number of available modules and shuts-down the inverter
(via the UPS Logic Board) if the system redundancy is exceeded.

Module frequency control and synchronisation control

Although each UPS module ultimately operates at a frequency determined by its
Inverter Logic Board’s master oscillator, in a 1+1 system the Parallel Logic Board
provides a complex synchronisation function which operates between the two
modules and also between the modules and the bypass supply. This ensures that
the two modules are frequency-locked together at all times when the inverters are
operating in parallel, and also locked to the bypass supply provided it remains
healthy.

Output current control

When both modules are on-line and feeding a common load, their power inverter
sections are effectively operating in parallel and should share the load current
equally. It is especially important that circulating currents are not allowed to
appear in the UPS output stages, whereby one module attempts to reverse-feed the
other.
The Parallel Logic Board contains analogue circuits which:
• provide an output current-sharing function by using fine control of the
Inverter Logic Board voltage regulation circuit in such a manner as to
ensure that both UPS modules produce an equal output current.
• provide protection against current sharing failure and trip the module off-

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CHAPTER 2 - Parallel Logic Board

line if it detects that one module is feeding reverse current into the other.
This function is called “Selective Shutdown” in this manual.

Common battery control

In installations where a common battery is used by both modules, the Parallel
Logic Board provides a rectifier current-sharing function whereby is finely ad-
justs the rectifier voltage to obtain balanced rectifier input currents. If both mod-
ules produce the same output current and take the same input current this implies
that they are also (within limits) providing the same amount of battery charge cur-
rent.
When a common battery is used, the Parallel Logic Board also controls the recti-
fier float/boost charge mode selection in both modules to ensure they operate in
the same mode at all times.

Miscellaneous functions
In addition to the ‘easily categorised’ functions mentioned above, the Parallel
Logic Board also provides other minor functions which are mainly associated
with its role of providing the parallel control bus.

The digital control element of the above functions are carried out by two ASIC
circuits shown on page 1 of the circuit diagram – D30 and D31. The internal logic
of these devices is not described in detail in this chapter; however an appreciation
of their input/output conditional relationships is essential to understand the wider
functionality of the circuits which they control, therefore internal block diagrams
of these devices are used to aid explanation where necessary.

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SECTION 8 - "1+1" Configured UPS System Control 7200 Series UPS Service Manual
CHAPTER 2 - Parallel Logic Board

Section 8:

2.3 General module output control

The signals described in this sub-section are concerned with turning ON/OFF the
inverter in the local module and controlling the load transfer between the inverter
and bypass supplies – these signals are developed by D31, as described below.

2.3.1 Inverter ON/OFF request – [OFF_INV>

Figure 8-3: Inverter ON/OFF & Selective Shutdown

X1 X7 X3 X4

19 5 33 13 7
D31 [OFF_INV> 39 39 D88 [ON_INV> 36 39 D11 [BLK>
1=OFF 1=ON 1=OFF

Parallel Logic Board UPS Logic Board Inverter Logic Board

D31 Internal Block Diagram

31
[RIT_INV_L>
27 Selective 37
[C_N_INV> Shutdoown [BLK_SEL>
11 Logic
[CON_SEL>

43
[TEST>
[BLK_SW> (mm only) 26

6
[I_SW_BYP> Inverter
14 ON/OFF 19
[SW_OUT> Logic [OFF_INV>
17
[CONN_A>
18
[CONN_B>

An ‘inverter ON/OFF’ control signal [OFF_INV> is produced by D31 pin 19 and

applied to the ‘inverter inhibit logic’ on the Inverter Logic Board (D11) via the
path shown above in Figure 8-3. The [OFF_INV> signal at D31-19 goes high to ‘in-
hibit’ the inverter and low to ‘enable’ it. Note that the signal does not pass straight
through D88 on the UPS Logic Board, but is combined with several other inverter
inhibit logic signals at that point. It is therefore quite possible for the signal at
D31-19 to call for the inverter to be enabled ([OFF_INV> = low) but for some other
input to D88 to override this request on the UPS Logic Board ([ON_INV> = stays
low). Similarly, there are other inputs to D11 on the Inverter Logic Board which
can override an [ON_INV> request.
The [OFF_INV> signal logic state at D31-19 depends upon a complex combination
of the inputs to D31, as described below, and it is driven high (turning off the in-
verter) if any of the following conditions are true:

Selective shutdown. (D31 pin 37 high)

The ‘selective shutdown’ function is concerned with a current sharing prob-
lem. The error detection circuit, which is explained in paragraph 2.5.4, is part
of the current sharing control description; however the effects of the ‘selective
shutdown’ error signal within D31 is described below in paragraph [Link]. In
summary, if the selective shutdown logic within D31 becomes active D31-37
([BLK_SEL>) will switch high (illuminating H1) in addition to driving D31-19
([OFF_INV>) high.

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Software block. (D31 pin 26 high)

Note: in a 1+1 configured system this input is overridden internally due to
jumper X6-4 being made (pulling D31-1 permanently low). Therefore, the
described affects of this signal on the Inverter ON/OFF control signal apply
only when the board is fitted in a multi-module inverter system.

A logic high signal applied to X1-43 from the UPS Logic Board
([O_BLK_SW>) is inverted by a section of D23 from where it is connected to
the parallel control bus (X2/3 pin 3). The signal at this point ([B_BLK_SW>) is
also reinverted at D26 pin 6 to provide the high [BLK_SW> signal to D31-26
which turns off the inverter. This means that in a multi-module system all the
modules are affected by the software block signal if it is generated in any
module.

Maintenance bypass interlock. (D31 pin 6 high and pin 14 low)

If the Maintenance Bypass Switch is closed (D31-6 is high) at the same time
as the module’s Output Switch (D31-14 is low) it will drive D31-19 high,
turning off the inverter to prevent damage occurring due to reverse power
flow from the mains into the inverter.
Note: the Maintenance Bypass switch contacts are sensed by both modules
via the parallel control bus X2/3 pin 14. Thus, the inverter is shut down in
both modules if the maintenance bypass switch is closed in either module.

Output switch interlock. (D31 pin 43 high)

When operating in a 1+1 configuration, it is required that the inverter is
allowed to operate only if the UPS output switch is closed. This ensures that
the parallel current-sharing and frequency control systems are enabled. There
is however a TEST facility which is invoked by jumper X6-8 on the Parallel
Logic Board which, when closed, overrides this interlock to allow the inverter
to be run-up for test purposes with the output switch open.
When the module is not operating in the TEST mode – i.e jumper X6-8 is
open (D31-43 high) – the inverter will be turned off by the input to D31 pin
14 which is driven high when the output switch is open.

Test mode interlock. (D31 pin 43 low)

When the UPS is running in the TEST mode, jumper X6-8 is fitted (D31-43 is
low), the inverter will be turned OFF if the module’s Output Switch is closed
(D31-14 is low).

Open circuit parallel control bus. (D31 pins 17 and 18 high)

If both ribbon cables that form the parallel control bus (to connectors X2 and
X3) are improperly connected (D31-17 & D31-18 both high) the inverter will
be shut down for safety reasons due to the loss of the parallel control bus.

Note: led H2 will illuminate when either one of these cables are disconnected,
driven by a logic high output on D31-32.

[Link] Selective shutdown

This paragraph considers the actions of the ‘selective shutdown’ circuit within
D31 (See Figure 8-3), and its effects on the [OFF_INV> inverter ON/OFF com-
mand at D31-19.

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The ‘Selective Shutdown’ circuit detects various forms of current sharing faults
and is shown on page 3 of the circuit diagram (see paragraph 2.5.4 on page 8-34).
The detector’s output signal [IN_SEL> goes high in a current-related fault event
and is inverted to a low at D31 pin 4 which:
• Turns off the inverter (drives D31-19 [OFF_INV> high).
• Sends a [BLK_SEL> status signal to the UPS Logic Board (from D31-37
and X1-38) to inform that board of the current conditions.
• Illuminates H1.
• Drives the output on D31-13 high.
This output is debounced and inverted, and fed back to D31-9 as a logic
low signal which latches the above signals in their fault state. Once acti-
vated, the latch must be reset by pressing the RESET push-button on the
UPS Logic Board, which applies a logic high [RES_EXT> input to D31-8
via X1-41. Note that when the module is first started the power-supply
monitor on the UPS Logic Board applies a 1 second logic high [V_AUX>
reset pulse to D31-5 which initially holds off the ‘selective shutdown’
latch (connected via X1-42).
In order for the [IN_SEL> ‘selective shutdown’ signal to produce the above outputs
from D31, the following conditions have to be satisfied on other D31 inputs.
If any of these conditions are not satisfied the ‘selective shutdown’ signal
[IN_SEL> is ignored by D31 internally.

Load on inverter (D31 pin 31 low).

The UPS Logic Board must be commanding ‘load on-inverter’. This is vali-
dated as a logic low on D31 pin 31.

UPS Not in ‘Test’ mode (D31 in 43 high).

The UPS must not be operating in the ‘Test’ mode. Jumper X6-8 must there-
fore be open, providing a logic high at D31 pin 43.

Two modules on line (D31 in 27 high).

In a ‘non-redundant’ system the [C_N_INV> input to D31 pin 27, generated by
the module counter circuit (see paragraph 2.5.5 on page 8-35), is logic high
when both modules are on line, which is a requirement for the selective shut-
down circuit output to be valid.
In a ‘redundant module’ system it is permissible for one module to operate
alone, and where this is the case the ‘selective shutdown’ circuit is irrelevant.
The [C_N_INV> input to D31 pin 27 is overridden in this case by making
jumper X6-3.

DC Bus above Vmin & Load below 150% nominal (D31 pin 11 high).
These two conditions are detected by the UPS Logic Board and a single sig-
nal ([CON_SEL>) is connected to D31 pin 11 which is high when both condi-
tions are satisfactory.

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2.3.2 Load transfer control

Figure 8-4: Load Transfer control logic

X1 X7 X5 X3

1 8 [O_BUS_INV_L> 7 38
32 32 [INV_DIS> [MNS_L> 17 17 [MNS_L>
[I_BUS_INV_L>
1=load on bypass 1=turn on
0=enable load on byp
static bypass
D31 D88
1=turn close inv
output contactor
12 6 36
[C_L_INV> 40 40 [C_L_INV> [INV_L> 15 15 [INV_L>
0=enable load on inv 1=load on inv
Static Switch
Parallel Logic Board UPS Logic Board Driver Board

D31 Internal Block Diagram

24 21 [RIP>
VCO-in-loop
[O_PAR_SYN> To Relay
Control
K1/K2
43
[TEST>

7 18
[PAR_INV> [O_BUS_INV_L>
28
[MNS_L_SS> (mm only)
27
[C_N_INV>
34
[N_AUX_CON>
25 Load 12
[INV_L> Transfer [C_L_INV>
1 logic
Jumper X6-4 (made)
Jumper X6-1 44
(made = non-redundant)
44 20
[INV_IND> [O_INV_IND>

Load transfer control is based on several complex circuits which are interlocked
in such a way as to avoid the bypass static switch being activated while the invert-
er output contactor is closed, and vice versa, to prevent back-feeding the UPS in-
verter from the mains supply.
In a ‘single-module’ installation this function is performed by the UPS Logic
Board’s micro-controller system in conjunction with other status signals applied
to D88. However, when the module is connected in a 1+1 configuration it requires
additional circuitry to cater for the parallel control elements of the load transfer
operation – i.e. to ensure that both modules transfer the load between inverter and
bypass simultaneously, and also to manage the transfer-to-bypass requirements in
a redundant-module situation. These ‘additional’ parallel control functions are
provided by the Parallel Logic Board, based on the logic operation within D31.
As illustrated in Figure 8-4, D31 on the Parallel Logic Board produces two signals
associated with load transfer control. The [C_L_INV> output from D31-12 informs
the UPS Logic Board that it is safe (from a paralleling point of view) to transfer
the load to the inverter; and the [O_BUS_INV_L> output from D31-18, which is in-
terlocked with [C_L_INV> within D31, informs the UPS Logic Board whether or
not it is safe to transfer the load to the bypass supply. Both these signals are de-
scribed in more detail below.
Note: A detailed description of the load transfer control operation during module
start-up is provided in paragraph 2.8.

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[Link] Load-on-inverter request – [C_L_INV>

The [C_L_INV> output from D31 pin 12 goes low when the logic within D31
deems it safe to transfer the load to the inverter, and can be viewed as a ‘load on
inverter’ request. This is applied to D88 on the UPS Logic Board and, provided
other inputs to D88 are valid, produces a logic high [INV_L> output at D88 pin 36.
This is connected to the Static Switch Driver Board where it activates the inverter
‘output contactor close’ circuit; thereby connecting the load to the inverter. To
drive [C_L_INV> low (to request ‘load-on-inverter’) all the conditions described
immediately below must be valid.

Module synchronisation validation (D31 pin 7 low)

D30-14 applies a logic high [O_PAR_SYN> signal to D31 pin 24 when it
detects that the module synchronisation conditions are valid. This drives D31-
21 low ([RIP>) which is debounced and inverted at D28-4 to appear as a logic
high [PAR_INV> input to D31-7.

Note 1: the [RIP> signal also energises the ‘VCO-in-loop’ relays (K1/K2)
which connect the module’s synchronisation control circuits to the parallel
frequency control bus (See paragraph 2.4).
Note 2: the [PAR_INV> signal is also used by the ‘available module counter’
circuit (See paragraph 2.5.5) and ‘current-sharing’ relay control circuit (K3/
K4) (See paragraph 2.5.3).

When the TEST mode jumper X6-8 is made (D31-43=low) the [O_PAR_SYN>
signal has no affect on D31, and D31-21 [RIP> is held permanently high.

Valid ‘Available module counter’ output (D31 pin 27 high)

In a ‘non-redundant’ system the ‘available module’ counter is configured to
produce a logic high [C_N_INV> signal only when both modules are available.
In a ‘redundant’ module system [C_N_INV> goes high when the local module
is available irrespective of the state of the second module.

No “load-on-bypass” request from system (D31 pin 28 low)

This input is overridden in a 1+1 module due to jumper X6-4 being fitted; the
following description thus applies only when the board is fitted to a module
forming part of a multi-module system.

In a multi-module system, the decision whether to connect the load to the

inverter or bypass supply rests with the UPS Logic Board’s micro-controller
system. When it decides to connect the load to the bypass supply, the UPS
Logic Board sends a logic high [O_MNS_L_SS> signal to the Parallel Logic
Board X1 pin 44. This is inverted to a logic low at D23 pin 11
([B_MNS_L_SS>) and connected to the parallel control bus via X2/3 pin 4, and
also reinverted at D26 pin 8 to provide a logic high [MNS_L_SS> input to D31
pin 28 – i.e. when the UPS Logic Board is calling for ‘load-on-bypass’, the
logic high [MNS_L_SS> input to D31 pin 28 forces D31-12 high to prevent it
from signalling a ‘load-on-inverter’ request.

Note: due to the fact that the ‘load-on-bypass’ request from the UPS Logic
Board is connected to the parallel control bus X2/3 pin 4 ([B_MNS_L_SS>), it
affects all modules when either of them is calling for load-on-bypass.

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‘Non-redundant’ module conditional logic (D31 pin 29 low)

In a ‘non-redundant’ system the load must not be transferred to the inverters
unless both inverters are fully operational and connected to the parallel con-
trol ‘sync’ and ‘current-sharing’ busses. Therefore a circuit is required which
prevents [C_L_INV> requesting ‘load-on-inverter’ until these conditions are
satisfied.

The circuit which performs this task is again within D31, and acts in response
to the [PAR_INV> signal applied to D31-7 (which is high when the module is
connected to the parallel control bus), and the [C_N_INV> signal from the
‘available module counter’ circuit applied to D31-28 (which is high when
both modules are running.
When both these conditions are satisfied, the [O_INV_IND> output from D31-
20 is driven low. This is inverted to a high at D24 pin 17 and connected to the
parallel control bus (X2/X3-12), and then reinverted to a low at D26 pin 12
([INV_IND>) and applied to D31 pin 29. D31-29 must be low to enable the
[C_L_INV> output from D31 pin 12 to go low and request load-on-inverter.

Note that the parallel control bus action means that these conditions must be
valid in both modules before either module is allowed to request ‘load-on-
inverter’.

In a ‘redundant-module’ system the [INV_IND> input to D31-29 is overridden

by the removal of the configuration jumper X6-1 and the input to D31-29 has
no effect. (X6-1 must be fitted to obtain non-redundant operation.)

TEST mode of operation

When the TEST mode is selected (jumper X6-8 made) the [C_L_INV> output
at D31-12 is forced low irrespective of the state of the other conditions
described above. This allows the inverter output contactor operation to be
tested while the load is isolated from the inverter through opening the output
power switch.

[Link] Load-on-bypass request – [O_BUS_INV_L>

The [O_BUS_INV_L> output from D31 pin 18 goes low when the logic within D31
deems it unsafe to power the load from the inverter. It can therefore be viewed as
a ‘load on bypass’ request as, under normal conditions, the UPS system should
always attempt to transfer the load to the bypass supply whenever the inverter
supply becomes invalid (See Figure 8-4).
When requesting ‘load-on-bypass’, the low [O_BUS_INV_L> output is inverted to
a high [B_INV_LOAD> at D24-18 from where it is connected to the second module
via the parallel control bus X2/X3 pin 10. It is then re-inverted to a low
[I_BUS_INV_L> at D26-10 from where it is connected to D88 on the UPS Logic
Board. The parallel control bus thus couples together this signal between the two
modules in such a way that both modules will detect the ‘load on bypass’ request
when it is generated by either module. This is crucial to avoid a potentially cata-
strophic situation if one module only were to transfer to bypass while the other
remained ‘on inverter’.
On the UPS Logic Board, D88 produces a logic high [MNS_L> output at pin 38
provided other inputs to D88 are valid. This is then connected to the Static Switch
Driver Board where it activates the static bypass SCR driver circuit.

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CHAPTER 2 - Parallel Logic Board

D31 pin 18 [O_BUS_INV_L> is driven low (to request ‘load-on-bypass’) if any of

the four conditions described immediately below are valid:

“Load-on-bypass” request from system (D31 pin 28 high.)

As described above, this input is overridden in a 1+1 module due to jumper
X6-4 being fitted; the following description thus applies only when the board
is fitted to a module forming part of a multi-module system.

The decision whether to connect the load to the inverter or bypass supplies
rests with the UPS Logic Board’s micro-controller system. When it decides to
connect the load to the bypass supply, the UPS Logic Board sends a logic
high [O_MNS_L_SS> signal to the Parallel Logic Board X1 pin 44. This is
inverted to a logic low at D23 pin 11 ([B_MNS_L_SS>) from where it is con-
nected to the parallel control bus via X2/X3 pin 4, and also reinverted at D26
pin 8 to provide a logic high [MNS_L_SS> input to D31 pin 28.

Note 1: the [O_MNS_L_SS> signal also inhibits the ‘load on inverter’ request
from within D31 as described earlier.

Note 2: due to the fact that the ‘load-on-bypass’ command from the UPS
Logic Board is connected to the parallel control bus ([B_MNS_L_SS>), it
affects both modules when either one of them is calling for load-on-bypass.

UPS Logic Board not commanding ‘load on inverter’ (D31 pin 25 low.)
D31 pin 25 input is connected to the [INV_L> signal applied to X1 pin 52 and
is logic low when the UPS Logic Board is not commanding the Static Switch
Driver Board to close the output contactor – i.e. not commanding ‘load-on-
inverter’.

Module synchronisation invalid (D31 pin 7 low.)

This input is driven low when the [RIP> output from D31 pin 21 is high, which
occurs when there is a sync error between the modules or bypass supply. Also
used by the ‘load on inverter’ request signal [C_L_INV> described above (See
paragraph [Link]).
In practice this input is normally effective only while the module is being
started, and is unlikely to appear once the modules have achieved initial syn-
chronisation.
When the TEST mode jumper X6-8 is made (D31-43=low) D31-21 is held
permanently high, which allows the load transfer circuit to be tested while the
module is isolated from the load by means of opening the output switch.

Output contactor auxiliary (D31 pin 34 high).

The [N_AUX_CONT> input to D31-34 is controlled by the UPS Logic Board
processor system and is driven high when the output contactor auxiliary con-
tacts are open.

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CHAPTER 2 - "1+1" Configuration Control Principles

Section 8:

2.4 Frequency synchronisation principles

2.4.1 Introduction
When two UPS modules are operating with their outputs connected in parallel,
such as in the case of a ‘1+1’ system, it is of paramount importance that their out-
puts are synchronised in both phase and frequency to prevent large, damaging,
circulating currents appearing.
Not only must the two modules be synchronised to each other, but they must also
be synchronised to the bypass supply in order to allow a no-break transfer to take
place between the UPS and bypass supplies when called for. The system synchro-
nisation control circuitry is therefore necessarily complex.
This section begins by providing a fairly detailed overview of the frequency con-
trol and synchronisation principles and continues with a full description of the
major signals and components employed by this function

[Link] Inverter frequency control – overview

Figure 8-5: Frequency control block diagram

X2/
Parallel Logic Board
X3

Parallel Sync Bus

X7 X1
K1/K2
11
54 54 [FRQ_PAR>

53 53 [FRQ_SYN> -

6 33 FRQ_PAR>
3

14 D29

-
[O_MNS 25 (PLL)
45 45
_D_SS> [FRQ_REF>
D30
ASIC [FRQ_OSC>
[O_MNS 8 31 13
48 48
_SYN_OK>
[PH_COM_2>
Micro Controller System

5
55 55 [F_IN> GVCO

[SYN_INT>
[FRQ_
MNS>
X2

(Bypass Frequency
- [F_IN> 15
Single module)

X1 X7

[BACK> 34 34 [BACK>

44 27 Reference
32 32 D1
[INV_F> [INV_F> Osc O/P Sinewave
(Divider)
Select 50/60Hz Generator
Base Frequency Master
Clk
Oscillator

40 40 14 D6 3
[SYNC> [SYNC>
(PLL)

UPS Logic Board Inverter Logic Board

In each module the inverter frequency is controlled directly by the ‘master oscil-
lator’ section of the Inverter Logic Board. As shown in Figure 8-5, the ‘master os-
cillator’ comprises a phase-locked-loop (PLL) integrated circuit (D6) and a
frequency divider (D1), both of which are controlled by the UPS Logic Board
micro-control system. The nominal 50/60 Hz oscillator output from D1 pin 27
controls the reference sinewave generator circuits and thus controls the inverter
operating frequency.

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In practice, the VCO section of D6 clocks D1 which divides the clock pulses by
a factor determined by the [INV_F> signal to D1 pin 44. This input thus determines
whether the master oscillator operates at a base frequency of 50Hz or 60 Hz, as
programmed into the UPS Logic Board micro controller system.
The phase comparator section of the PLL (D6) compares the oscillator output (pin
3) with a frequency reference signal ([SYNC> pin 14) which is again supplied by
the UPS Logic Board micro controller system. Any detected phase error between
these two signals will amend the VCO output to the frequency divider which has
the effect of correcting the oscillator output frequency and make it track the
[SYNC> reference frequency. Thus the [SYNC> signal indirectly determines the in-
verter frequency through its effect on the ‘master oscillator’. Note that the UPS
Logic Board also monitors the ‘master oscillator’ frequency via the [BACK> signal
connected via X1 in 34.

Sync operation in a ‘single-module’ system’

As explained in the Inverter Logic Board detailed description, in the case of a
single-module system the [SYNC> reference signal is made to track a bypass fre-
quency signal [F_IN> which is derived from the bypass R-phase supply via X2 pin
15. Such tracking is performed in software by comparing [F_IN> with [BACK> and
adjusting the [SYNC> reference frequency accordingly. Thus in the simple ‘single-
module’ the ‘master oscillator’ effectively functions within two nested phase-
locked loops; the outer one being software controlled and the other being part of
the ‘master oscillator’ itself.

Sync operation in a ‘1+1’ system’

In a ‘1+1’ system, the Inverter Logic Board’s ‘master oscillator’ functions in the
same manner as for a ‘single-module’ system; however, due to the complex par-
allel-operating requirements, the [SYNC> reference signal is made to track the
[FRQ_SYN> output of the ‘Governing Voltage Controlled Oscillator’ (GVCO) on
the Parallel Logic Board, rather than the bypass frequency directly.
The reason for adding this extra layer of complexity to the synchronisation regime
is that it allows the GVCO outputs from both modules to be directly coupled to-
gether via the parallel control bus and thereby ensure that the [SYNC> reference
signals are locked together in both modules.

[Link] Basic GVCO sync principles on module start-up

As shown in Figure 8-5, the GVCO is synchronised to the [FRQ_REF> signal pro-
duced at D30 pin 31 via a phase-locked-loop (PLL) circuit (D29). The phase de-
tector section of the PLL detects any phase difference between the [FRQ_REF>
signal (D29-14) and the GVCO [FRQ_SYN> output (D29-3), and produces a fre-
quency correction signal ([PH_COM_2>) which makes the GVCO track the
[FRQ_REF> signal frequency.

The [FRQ_REF> signal itself can be derived from one of two sources – i.e. to the
‘bypass frequency’ [F_IN> or the ‘parallel sync bus frequency’ [FRQ_PAR>, as de-
termined by the ‘sync-source selector’ circuit within D30. Alternatively, if neither
of these signals are present, the PLL can be disabled and the GVCO made to op-
erate at its base frequency (i.e. 50/60Hz).
The ‘selected’ sync source depends on whether or not the bypass supply is avail-
able and the sequence in which the modules are started. A brief description of the
various options is given below:

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Bypass supply present & first module to be started

When the first module is started, the ‘sync source selector’ circuit within D30
connects the bypass frequency signal [F_IN> present at D30 pin 5 through to D30
pin 31 ([FRQ_REF>). Thus, due to the action of the PLL described above, in this
situation the GVCO synchronises the bypass mains frequency.
When the UPS Logic Board micro controller system detects that the Inverter
Logic Board has gained internal synchronism (i.e. the Inverter Logic Board’s
‘master oscillator’ PLL is phase-locked) its sends a logic high [O_MNS_SYN_OK>
signal to D30 pin 18 which energises the VCO-in-loop relay (K1/K2).
Note; for reasons of clarity the relay energising circuit is not shown in Figure 8-5.
This relay has several contacts, which are described in detail later: however, the
primary contact, shown in the block diagram, connects the GVCO [FRQ_PAR>
output to the parallel ‘sync bus’. This in effect connects the GVCO output of the
first module to be started to the corresponding point (X2/X3 pin 11) in the second
module (which is not yet running).
To summarize the circuit action; at the end of the start-up sequence of the first
module:
• its GVCO is synchronised to the bypass supply.
• its Inverter Logic Board master oscillator is synchronised to the GVCO
output (therefore the inverter is also indirectly synchronised to the bypass
supply).
• the VCO-in-loop relay is energised and the GVCO output is placed onto
the parallel sync bus.

Bypass supply present & second module to be started

When the second module is started, its ‘sync source selector’ within D30 initially
connects its [FRQ_REF> output (D30-31) to the ‘parallel sync bus’ frequency ref-
erence signal [FRQ_PAR> (D30-6). Thus the action of the PLL phase comparator
effectively synchronises the GVCO of the second module to track the parallel
sync bus frequency (which is in fact derived from the GVCO output from the first
module). This condition can be looked upon at as being a ‘master/slave’ situation;
whereby the GVCO of the on-coming module is slaved to that of the module al-
ready running.
A ‘sync bus comparator’ circuit within D30 compares the local GVCO’s
[FRQ_SYN> output with the ‘parallel sync bus’ signal ([FRQ_PAR> from the first
module), and detects when the local (slave) GVCO is fully synchronised to the
‘parallel sync bus’ (master). Notice that this comparator actually monitors the fre-
quency at either side of the ‘VCO-in-loop’ relay contact – which is still open in
the second module at this time.
When the ‘sync bus comparator’ detects that the local GVCO is properly synchro-
nised and UPS Logic Board micro controller system detects that the Inverter
Logic Board has achieved ‘internal sync’ (i.e. a logic high [O_MNS_SYN_OK>
signal to D30 pin 8), D30 will energise the ‘VCO-in-loop relay’ (K1/K2) in the
second module.
This has two major affects:
1. It connects the second module’s GVCO output to the sync bus in parallel with
the existing GVCO signal from the first module; thus ensuring that both
GVCOs remain fully synchronised from this point onwards.

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2. It makes the ‘sync source selector logic’ within D30 now select the bypass
frequency [F_IN> as the sync reference source ([FRQ_REF>) instead of the
‘parallel sync bus’ [FRQ_PAR> signal. This means that the local GVCO now
tracks the bypass supply frequency directly and is no longer seen as being
‘slaved’ to the first module but is in fact acting as a ‘master GCVO’ in its own
right.

To summarize the circuit action; at the end of the start-up sequence of the second
module:
• the GVCO of the first module is synchronised to the bypass frequency.
• the GVCO of the second module is also synchronised to the bypass fre-
quency.
• the VCO-in-loop relay is energised in both modules, connecting the out-
puts from both GVCOs together via the parallel sync bus.

Starting a module while the bypass supply is missing

On start-up, if the bypass supply is missing, D30 produces an ‘internal sync’ com-
mand signal ([SYN_INT>) which inhibits the GVCO synchronisation circuit, and
forces it to operate at its ‘base frequency’ (i.e. 50/60Hz).
In the first module to be started, the ‘VCO-in-loop’ relay (K1/K2) will be ener-
gised when the UPS Logic Board micro controller system detects that the Inverter
Logic Board has achieved ‘internal sync’ (i.e. a logic high [O_MNS_SYN_OK>
signal to D30 pin 8). This then places the GVCO output (still operating at its base
frequency) onto the ‘parallel sync bus’ in the same way as described on the pre-
vious pages.
When the second module is started it operates in its ‘slave’ mode, as before, and
initially synchronises to the ‘parallel sync bus’ (which is at the base frequency of
the first module’s GVCO). However, once the ‘sync bus comparator’ within D30
detects synchronism between the local GVCO and the parallel sync bus, it will en-
ergise the ‘VCO-in-loop’ relay whereupon the module changes over from ‘slave’
to ‘master’ mode.
This situation now presents a problem which must be overcome. That is, both
modules are now operating independently at their base frequency yet connected
together via the parallel sync bus; and no matter how closely the two GVCOs are
matched, their base frequencies are certain to drift apart and thus cause a non-syn-
chronous condition. This potential problem is overcome by a second parallel sync
bus line, (not shown in Figure 8-5), which connects together the integrator sec-
tions of both GVCOs via a second contact of the ‘VCO-in-loop’ relay. This abso-
lutely locks together the GVCOs and ensures they both operate at exactly the
same frequency – i.e. act as one. This is explained in more detail in the GVCO
functional description below.
Note: in practice they will adopt the frequency of the fastest running oscillator.
If either module detects that the bypass supply becomes available, the ‘sync
source selector’ within D30 will remove the GVCO inhibit and connect the
bypass [F_IN> signal through to both modules. Under these circumstances both
GVCOs, acting as one, remain fully synchronised together while they seek and
then track the bypass frequency.

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CHAPTER 2 - "1+1" Configuration Control Principles

2.4.2 GVCO Detailed description of operation

Figure 8-6:
Governing VCO Block Diagram
[FRQ_SYN> -
Sync Inhibit [SYN_INT>
from D30 [FRQ_PAR>

X2/
K1 X3

Parallel Sync Bus

Angle Comparator -
[PH_COM_2> Integrator [FRQ_OSC> 11
Regulator (Schmitt)
From PLL

K2
[C_P> 30

Reference VCO-in-loop
Voltage relays
Frequency
correction
signal
R18/
R20

Figure 8-6 illustrates a detailed block diagram of the GVCO block shown in
Figure 8-5 complete with its major input/output signal annotations. The complete
circuit is shown on page 2 of the circuit diagram.
The above diagram shows that the GCVO comprises four functional sub-blocks;
namely, the ‘angle regulator’, ‘reference voltage’, ‘integrator’ and ‘comparator’.

Overview description
Basically, the oscillator function is satisfied by the integrator and comparator
blocks – i.e. the integrator provides the comparator with an ramp signal which
causes the comparator output ([FRQ_OSC>) to switch logic states when the ramp
reaches the comparator threshold. This is then fed back to the integrator
([FRQ_SYN>) making the integrator ramp in the opposite direction. Once again
when the ramp reaches the comparator’s threshold the comparator output
([FRQ_OSC>) switches back to its original state and the integrator ramp is made
to reverse once more. This sequence of events is regenerative and leads to a
square waveform at [FRQ_OSC> and a triangular waveform at the integrator out-
put.
The oscillator frequency is determined by the integrator’s ramp-rate – i.e. if the
ramp rate is increased, it takes less time for the comparator to reach its switching
threshold which results in an increased frequency. The ramp rate is voltage-con-
trolled by the output of the ‘reference voltage’ block which, in the absence of any
synchronising signal, is set by R18/R20 to produce an oscillator output of 50/
60Hz – this is described as the GVCO “base frequency”. When the GVCO is syn-
chronised to a reference frequency (e.g. bypass supply) an additional ‘correction’
voltage is superimposed upon the reference voltage which modifies the GVCO
frequency and makes it track the desired frequency reference.
The ‘angle regulator’ circuit provides signal conditioning to the correction volt-
age ([PH_COMP_2>), which is produced by the phase comparator section of PLL
D29 (See Figure 8-5), to control its slew-rate etc.
Each of the sub-blocks mentioned are described in more detail below.

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Reference voltage
The ‘reference voltage’ circuit comprises a three-terminal regulator (N12) and
four sections of N8.
N12 provides a stable +2.5V at its cathode. This is connected to N8a/b via varia-
ble resistor R18, and to N8c/d via R20. Considering N8c/d; N8c inverts the +2.5V
stabilised voltage such that a negative reference voltage appears at D22 pin 3, and
this is again inverted by N8d (unity gain) which provides a positive voltage at D22
pin 5. R20 should be adjusted for -4V at D22-3 and +4V at D22-5. N8a/b operate
in a similar manner to provide positive and negative reference voltages to D22
pins 1 and 2 respectively – calibration of R18 is described later.

Integrator & Comparator

These two sub-blocks are so inter-dependant that their operation is best described
together. The integrator comprises N7a-c and the comparator N7d
The circuits’ operation is best understood by considering one cycle of its operat-
ing sequence, beginning with the analogue switches in their states shown in the
diagram – as follows:
1. The negative reference voltage on IC22 pin 2 passes through IC29 and is
inverted to a positive voltage at N7a pin 1, which charges C76 via R119. The
output from N7b follows the capacitor voltage and therefore ramps in a posi-
tive direction.
2. N7d compares the positive-ramping signal from N7b pin 7 with the positive
threshold present on IC22 pin 4 (set by R20).
3. When the positive-going ramp on N7d pin 12 rises above the positive thresh-
old on pin 13 (which is set by R20 and applied through D22 pins 5-4), its out-
put pin 14 ([FRQ_OSC>) switches from logic low to high, with the following
effects:
a) It drives D23-14 low (sheet 4) which is connected to the parallel sync bus
via X2/X3 pin 11 ([B_FRQ_PAR>) provided the VCO-in-loop relay K1 is
closed. If K1 is closed the [B_FRQ_PAR> signal is also inverted to a high at
D26-2 ([F_PAR>) and fed to D30 pin 6 (sheet 1) from where it is connected
to the internal ‘sync bus comparator’.
Note: [F_PAR> is also fed to the UPS Logic Board micro controller system
via X1-54 (sheet 4).
b) The low from D23-14 is inverted to a high at D25-12 ([FRQ_SYN>) which
is fed back to the UPS Logic Board micro controller system (X7-53) as the
frequency reference pulse to which the Inverter Logic Board’s master
oscillator is ultimately synchronised.
c) The high [FRQ_SYN> at D25-12 is also fed to D30 pin 33 from where it is
connected to the internal ‘sync bus comparator’.
d) Finally, the high [FRQ_SYN> at D25-12 is connected to the control gate of
solid-state switches D22 pins 9 & 10, which makes the switches change-
over from their state shown on the diagram.
4. With solid state switches D22 in their new positions, N7a pin 1 now switches
low and discharges C76 through R119.
5. The output from N7b pin 7 follows the capacitor discharge and thus now
ramps in a negative direction.

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6. When the negative-going ramp on IC16 pin 12 falls below the negative
threshold now applied to pin 13 (which is once again set by R20 but now
applied through D22 pins 3-4) the [FRQ_OSC> output at N7d pin 14 switches
from a logic high to logic low.
7. This reverses the signals described in 3a to 3d above, which now revert to
their original logic state. This includes the control gate signals to D22 pins 9
& 10, which now open and cause the above sequence to be repeated.
Frequency calibration. The above sequence shows that the circuit is self os-
cillating at a rate determined by the voltages set by R18 and R20 as these affect
the ramp rate of the integrator and the comparator’s switching threshold.
Calibrate R18 and R20 should be calibrated to obtain the GVCO base frequency
as follows:
1. Ensure there are no external sync sources (turn off bypass supply).
2. Adjust R20 to obtain 4.0Vdc at test point X8 pin 3.
3. If necessary adjust R18 to obtain 50Hz (60Hz) at test point X8 pin 2.
Note: jumper X7 shunts R108, which is in R18’s resistor chin, and should be
positioned 2-3 (open) when operating at 50Hz and 1-2 (closed) at 60Hz.
Integrator phase locking. In the overview description of the frequency syn-
chronisation principles it was stated that the GVCO will operate at its ‘base fre-
quency’ if the bypass supply is unavailable. It also explained that under these
circumstances the GVCO integrator sections were locked together between the
two modules to ensure that both GVCOs adopt a common frequency and phase.
In practice, this is achieved by a set of the VCO-in-loop relay contacts (K2) which
directly connect the integrator outputs together on both modules when the relays
are energised. With reference to the circuit diagram, the points in question are an-
notated <C_P> and <C_0> on page 2, which are connected to the parallel control
bus X2/X3 pins 29 & 30 when K2 is closed (see sheet 4). The effectively connects
together the top of the integrator capacitors (C76) in both modules which ensures
that the integrators in both modules change direction simultaneously – thereby
locking the oscillators together absolutely once the VCO-in-loop relay has closed.

Angle Regulator
The ‘angle regulator’ circuit integrates the [PH_COM_2> frequency error signal
produced by the PLL D29, to provide the GVCO with a suitable frequency cor-
rection signal to keep it synchronised to the selected sync source.
The frequency correction signal is applied to N8a, via R104, where it is added to
the reference voltage set by R18. In this way the correction signal is able to
modify the integrator ramp-rate, and thereby modify the GVCO output frequency
in order to synchronise the GVCO to the bypass (or parallel sync bus) frequency.
The correction signal takes the form of an analogue voltage which goes positive
to increase the GVCO frequency and vice-versa.
Relating this to the diagram (sheet 1), the [PH_COM_2> error signal produced at
D29 pin 13 takes the form of a series of positive or negative going pulses of var-
ying width – depending on the polarity and magnitude of the detected phase error.
These pulses are converted to an analogue voltage by a complex 4-pole filter
(sheet 2) comprising N9a, D22 (normally made 12 to 14), N10a, IN10b, N10c,
and N10d. N8a ultimately sums the correction signal (via R104) with the refer-
ence voltage set by R18.

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The correction signal is inhibited when the bypass supply is unavailable. This is
achieved by the [SYN_INT> output from D30 pin 29 which goes high if the bypass
is missing (or out of limits). This energises D22 control gate (pin 11) which dis-
connects the [PH_COM_2> from the filter input and replaces it with a 0V level ref-
erenced through R84. Under these conditions the correction signal emerging from
N10d pin 14 ramps back to 0V which therefore applies zero frequency correction
to the GVCO which allows it to operate at its ‘base frequency’ – as set by R18.

2.4.3 PLL Phase Comparator (D29)

This circuit is based on the phase-comparator section of a type 4046 phase locked
loop integrated circuit which monitors the GVCO output waveform [FRQ_SYN>
at pin 3 and the selected sync source waveform [FRQ_REF> at pin 14. If these
waveforms are unsynchronised the [PH_COM_2> output at pin 13 exhibits either a
positive or negative going pulse of a width proportional to the detected phase dif-
ference. A positive pulse is produced if [FRQ_SYN> leads [FRQ_REF> (i.e. the
GVCO frequency is the greater) and vice versa.
The [PH_COM_2> output pulses are integrated by the ‘angle regulator’ circuit and
then applied to the GVCO as an analogue error correction signal which modifies
the GVCO operating frequency. Thus if the PLL phase comparator detects an
error it ultimately modifies the GVCO frequency to make it track the [FRQ_REF>
reference frequency.

2.4.4 D30 Parallel Control Functions

Figure 8-7:
D30 Internal Block Diagram

18 Internal 29
[MNS_SYN_OK> Sync [SYN_INT>
Logic

41 14
[38] [T> [O_PAR_SYN>
40 VCO-in-loop
[37] [SYN_PAR_KO>
Relay Control 38
20 [CON_PAR> [41]
[PAR_SYN>
4
(Reset) [V-AUX>
34
[BLK_INV>
39
[INV_OK>
27
[SYN_PAR>
33
[FRQ_SYN>
Sync Bus 37
[PH_COM> [40]
6 Comparator
[FRQ_PAR>

31
[FRQ_REF>
Sync Source
28 Selector 27
[11] [I_FRQ_MNS> [SYN_PAR>

8
[O_MNS_SYN_OK>
5 Bypass 11
[F_IN> [O_FRQ_MNS> [28]
25 Validation
[MNS_D_SS>

D30 is an ASIC device containing numerous static logic gates which serve several
functions associated with the frequency synchronisation control; most of which
have been mentioned earlier. For reasons of clarity these are shown in block dia-
gram form in Figure 8-7, although in reality many of these blocks are to some
extent interactive, and share some of the input signals shown.

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[Link] Bypass validation

This block validates the bypass frequency signal [F_IN> to determine if it is suita-
ble for use by the sync source selector circuit.
The bypass frequency sense signal [F_IN> is connected to D30-5 and is allowed
through D30, to appear at D30-11 as [O_FRQ_MNS> provided both the following
conditions are satisfied:
1. The Inverter Logic Board’s master oscillator is phase-locked. Sensed by a
logic low [O_MNS_SYN_OK> input to D30-8.
2. The UPS Logic Board micro controller system has determined that the bypass
supply is within the programmed voltage and frequency limitation. Sensed by
a logic high [MNS_D_SS> input to D30-25.

Note: in each case, these input signals are coupled to both modules via the parallel
control bus via X2/3 pins 7 & 5 respectively; therefore the frequency validation
function of D30 will be affected in both modules if an invalid condition is present
in either module.
Provided the above conditions are satisfactory, the [O_FRQ_MNS> bypass fre-
quency signal output at D30-11 is inverted by D23-13 and reinverted by D26-4
and then reapplied to D30-28 as [I_FRQ_MNS> from where it is internally connect-
ed to the sync source selector circuit. The reason for this double-inversion is to
allow the signal at D23-13 to be coupled to the second module via the parallel
control bus via X2/X3 in 15. Thus, once again the [I_FRQ_MNS> input to D30-28
is applied to both modules even if the bypass frequency is being sensed by one
module only.

[Link] Sync source selector

This circuit determines whether the bypass frequency signal [I_FRQ_MNS> (pin
28) or parallel sync bus signal [FRQ_PAR> (pin 6) is allowed through D30 to
appear at pin 31 as the frequency reference signal [FRQ_REF>. Whichever is the
case, the [FRQ_REF> signal produced at D30-31 provides the main frequency ref-
erence signal to the PLL phase comparator and therefore dictates the GVCO op-
erating frequency.
Under normal circumstances the circuit selects the bypass frequency reference
signal [I_FRQ_MNS> except for the case where the module is the second to be start-
ed, whereupon it momentarily selects the parallel sync bus signal [FRQ_PAR> until
it becomes fully synchronised – i.e. during the period of “slave” operation (See
paragraph [Link]).
A second output from the sync source selector, at D30-27, goes high when the
‘parallel sync bus’ is the selected frequency reference and illuminates led H3.
Under normal circumstances, LED H3 should therefore illuminate briefly when
the second module is started and then remain extinguished while the module is
synchronised to the bypass supply.
The external conditions necessary to select the parallel sync bus as the reference
signal, and illuminate H3, are as follows (all conditions must be valid):
1. External reset signal is not applied (D30-4 = low).
2. VCO-in-loop relay K1 is closed in the first module (D30-4 = low).
3. VCO-in-loop relay K1 is open in the local module (D30-14 = low).
4. [BLK_INV> signal to D30-34 = high (no inverter problem).

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5. [INV_OK> signal to D30-39 = high (no inverter problem).

Note: once the VCO in loop relay becomes energised in the local module, the
[PAR_INV> signal from D28-4 to D30-26 goes high and overrides the effects
of the [INV_OK> signal within D30.

[Link] Sync bus comparator

The sync bus comparator circuit monitors the frequency of the local GVCO
output ([FRQ_SYN> applied to D30-33) and the parallel sync bus ([FRQ_PAR> ap-
plied to D30-6) and drives the [PH_COMP> output at D30 pin 37 low when the two
monitored signals are in-phase. This output is inverted and debounced by D27 and
its associated R-C components, and then fed back to D30 pin 40 as a logic high
[SYN_PAR_KO> signal – which is then internally connected to the VCO-in-loop
relay control circuit.
In practice the two monitored signals are taken from either side of the VCO-in-
loop relay contacts and therefore indicate when it is safe to close the relay (K1/
K2) from a parallelling viewpoint.

[Link] VCO-in-loop relay control

This circuit determines when it is safe to close the VCO-in-loop relay (K1/K2),
by driving [O_PAR_SYN> (D30-14) high, and thus connect the GVCO output to
the parallel sync bus.
The circuit’s internal logic is affected by the following signals:
• External reset [V_AUX> at D30-4.
• [PAR_SYN> at D30-20.
• [BLK_INV> at D30-34
• [INV_OK> at D30-39
Note: once the VCO in loop relay becomes energised in the local module,
the [PAR_INV> signal from D28-4 to D30-26 goes high and overrides the
effects of the [INV_OK> signal within D30.
• [SYN_PAR_KO> at D30-40

The logic state (and sequence) of these signals required to energise K1 depends
on whether the module in question is the first or second module to be started, as
described below:

First module to be started

1. As there is no module yet connected to the parallel sync bus, the [PAR_SYN>
input to pin 20 is high.
2. Provided there is no problem with the inverter control, the [INV_OK> and
[SYN_PAR_KO> status signals to pins 34 and 39 are both high once the
inverter has run-up.
3. The above conditions drives the [CON_PAR> output on pin 38 high, which is
then inverted, debounced and delayed by R151/C107/D27, and applied to pin
41 as a logic low ([T1>).
4. Provided there is no reset applied to pin 4 (low) and the inverter status signals
to pins 34 and 39 are still both valid (high), the logic low [T1> input to pin 41
will drive pin 14 high and energise the VCO-in-loop relay (K1/K2) via
[O_PAR_SYN> and one section of D24 (test point X12-1 = low).

5. When the VCO-in-loop relay energises:

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a) It connects the GVCO (and integrator) output to the parallel sync bus.
b) A further contact closes and places a logic low signal to D30 pin 20 in
both modules (via the parallel control bus). This has no effect on the cur-
rent module, but will inform the second module (when it is started) that
the first module is already running.
6. In addition to energising the VCO-in-loop relays (K1/K2), the [O_PAR_SYN>
output from D30-14 also signals the “parallel” status to D31-24 which drives
D31-21 low (provide not in test mode). (See paragraph [Link]). One effect of
this is that D31 applies a logic high [PAR_INV> signal to D30 pin 26 which
overrides the [INV_OK> signal.
7. The [O_PAR_SYN> output at pin 14 will remain high, holding-on relay K1/K2
unless one of the following conditions occur:
a) The reset signal is applied to D30 pin 4 (high).
b) The [BLK_INV> signal to pin 39 goes to an invalid state (low).
c) Both the [INV_OK> signal to pin 34 and the [PAR_INV> signal to pin 26 go
simultaneously low
d) The sync bus comparator detects a problem – [SYN_BUS_KO> to pin 40
goes low. This is unlikely to occur in the first module unless K1 is faulty,
or the is a printed circuit board fault.

Second module to be started

1. As the first module is already running and its VCO-in-loop relay is closed,
connecting its GVCO output to the parallel sync bus, the [PAR_SYN> input to
pin 20 is low.
2. Provided there is no problem with the inverter control, the [INV_OK> and
[SYN_PAR_KO> status signals to pins 34 and 39 are both high.

3. When the sync bus comparator detects that the local GVCO and the parallel
synch bus are in-phase, the [SYN_PAR_KO> input to pin 40 will go high.
4. The above conditions drives the [CON_PAR> output on pin 38 high, which is
then inverted, debounced and delayed by R151/C107/D27, and applied to pin
41 as a logic low ([T1>).
5. Provided there is no reset applied to pin 4 (low) and the inverter status signals
to pins 34 and 39 are still both valid (high), the logic low [T1> input to pin 41
will drive pin 14 high and energise the VCO-in-loop relay (K1/K2) via
[O_PAR_SYN> and one section of D24 (test point X12-1 = low).

6. When the VCO-in-loop relay energises, the GVCO output is connected to the
parallel sync bus via one contact of K1. A second K1 contact closes which
reinforces the logic low signal to D30 pin 20 in both modules (via the parallel
control bus).
7. The [O_PAR_SYN> output at pin 14 will remain high to hold on relay K1/K2
unless the conditions described above with respect to the first module occur.

[Link] Internal Sync Logic

This logic block is responsible for detecting when it is unsafe to synchronise the
GCVO to the [FRQ_REF> signal, but instead make it operate at its ‘base’ frequen-
cy (See paragraph 2.4.2).

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The [SYN_INT> output at pin 29 goes high to invoke the GVCO base-frequency
operation (also described as “internal sync”), and can be brought about by any one
of the following four logic combinations:

Reset
1. If an external reset [V_AUX> signal (high) is applied to pin 4. Note that this is
sourced from the software reset circuit on the UPS Logic Board.

Inverter problem
2. If either of the inverter status signals to D30 pins 34 and 39 are invalid (low),
while the local module is not connected to the parallel sync bus (pin 14 low)
but the second module is connected to the parallel sync bus (pin 20 low).
Note: if such an inverter problem occurs at D30-34 it will trip the local mod-
ule’s VCO-in-loop relay, as described above, therefore driving pin 14 low
automatically.

Inverter Logic Board loses internal sync

3. If the Inverter Logic Board master oscillator loses sync ([MNS_SYN_OK> pin
18 high) when either module is connected to the parallel sync bus
([PAR_SYN> pin 20 low OR [O_PAR_SYN> pin 14 high). Note that if such a
situation occurs it should affect both modules in an identical manner as both
are connected via the parallel control bus via X2/X3 pin 7 (low).

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Section 8:

2.5 Output current sharing

2.5.1 Introduction

Figure 8-8: Simplified current-sharing circuit (R-phase)

R1
X1 R42
R1 2 N1a X1 Current
CT Neutral 14
1 R30 R36 9 N1c sharing error
LOCAL 15 R1 8 R48
3 DV-A 20 signal
R-ph current 10 [ DV-A >
R21 To Inverter
Logic Board
X2/3
N4a D21 R11 (via UPS Logic
Current 3 To Selective
R11 N1b 12 Board)
sharing 27 1 5 14 shutdown
bus RL-K3/4 2 7 circuit
6
R31 13 11
R1
“0”
ABIL_RIP

The current sharing circuit is shown on sheet 3 of the circuit diagram.

In a ‘1+1’system the inverters should share the load current equally when both
modules are connected to the critical bus.
The current sharing circuit shown above controls this function by comparing the
two modules’ currents via a current sharing line of the parallel control bus and
generating an error signal if a difference is detected. The error signal is passed to
the Inverter Logic Board where it modifies the local inverter’s output voltage, by
up to ±5%, in order to restore a balanced current sharing condition. This action is
undertaken on an individual phase basis and an error signal is thus produced for
each of the three inverter phases.
The following text describes the operation of the R phase current sharing circuit
in detail – the other two phases work in an identical manner. Figure 8-8 shows a
simplified diagram of the R-phase circuit used in the description.

2.5.2 Current sharing error detection principles

The local module’s R phase output current sense signal ( [IO_A>) enters X1 pins 15
(signal) and 14 (neutral) and is buffered by N1a. The ac signal at N1 pin 1 is thus
proportional to the current being drawn from the local module, and connected to
N1c pin 9, via R30/R36, and also to N4a pin 3, via R21/R24.
RL-K3 energises when the [PAR_INV> signal from IC31 pin 7 goes high, which
occurs just after the VCO-in-loop relay is energised. RL-K3 contacts connect the
local current sense signal passing through R21 onto the parallel control bus at X2/
3 pin 27. Notice that due to the parallel bus connection, X2/3 pin 27 is connected
directly to the corresponding point on the Parallel Logic Board in the second mod-
ule.

Circuit operation when one module only is running

When a module is shut-down (off-line) its RL-K3 is de-energised and solid state
switch D21 is open (contacts as shown) – because [ABIL_RIP> is low due to the fact
that the inverter output contactor is open. These conditions force the current shar-
ing error signal [Dv-R> to zero volts, as the current sense signal from N1a is fed to

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N1c pins 9 and 10 in anti-phase and are self cancelling.

Note: R10 and R11 are of equal value (3k9).
In a ‘redundant-module’ configured ‘1+1’ system it is permissible to operate on
one module only (i.e. with the second module shut down). Under these conditions
D21’s contacts change over when the inverter output contactor is closed
([ABIL_RIP> = 1) and the current sense signal at N1a pin 1 is now buffered by N4a
and N1b and connected to N1c pin 10 via R31, D21 and R37.
However, R31 is of equal value to R30 (6K8), and once again the anti-phase sig-
nals applied to IC1c pins 9 and 10 will be of equal magnitude and keep the error
signal at 0V. Put simply, under these conditions the lone module attempts to cur-
rent-share ‘with itself’ and is therefore never in error.
Note: In this scenario RL-K3 energises, and connects the current sense signal to
the current sharing bus line once the module is synchronised, but this has no affect
on the current sharing circuit’s operation at this time as RL-K3 remains open in
the second (shut-down) module.

Current sharing operating under balanced conditions

When the second module is started, its current sense signal is applied to the cur-
rent sharing parallel control bus X2/3 pin 27 (via its RL-K3).
Assuming that both modules are supplying exactly the same amount of load cur-
rent, the current sense signal produced by N1a will be of the same amplitude and
phase in both modules; therefore there will be no net current flow through R21 in
either module and thus no net voltage dropped across it.

Figure 8-9:

Module 1 Module 2

X1 N1a 1Vac 1Vac N1a CN1

Sense Sense
Amp 1 1 Amp
15 15
N1c X2/X3 X2/X3 N1c
R21 R21
8 RL-K3 8
Dv-R 20 9 RL-K3 1Vac 9 20 Dv-R
27 27
Error 10 10 Error
Amp Unbalanced current Amp

This is illustrated in Figure 8-9, where a current sense signal of 1Vac is assumed
in both modules. Under these conditions the input signals to the error amplifier
(N1c) are equal and produce zero [Dv-R> ‘error’ signals to the Inverter Logic
Board –these conditions are the same in both modules.

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Current sharing operating under unbalanced conditions

Figure 8-10:

Module 1 Module 2

X1 N1a N1a CN1

Sense Sense
Amp 1 2Vac 1Vac 1 Amp
15 15
N1c X2/X3 X2/X3 N1c
R21 R21
8 RL-K3 8
Dv-R 20 9 RL-K3 1.5Vac 9 20 Dv-R
27 27
Error 10 10 Error
Amp Unbalanced current Amp

If the two modules supply different amounts of load current their current sense
signals at N1a will be different and there will be a net current flow along the cur-
rent sharing parallel control bus, resulting in a voltage drop across R21 in each
module proportional to the degree of current imbalance.
This is depicted in Figure 8-10, which shows the situation where Module 1 is sup-
plying more current than module 2.
In this case the current sharing control bus voltage (1.5Vac) is less than the cur-
rent sense signal (2Vac) in module 1 but greater than the current sense signal
(1Vac) in module 2. In Module 1 the voltage dropped across R1 produces a great-
er voltage at N1c inverting input with respect to its non-inverting input and the
[Dv-R> error signal (X1-20) will be a sinusoidal signal in anti-phase with the cur-
rent sense signal.
In Module 2 however these conditions are reversed, with the greater voltage being
applied to the non-inverting input of N1c, resulting in a [Dv-R> error signal which
is in-phase with the current sense signal.
The respective [Dv-R> error signals are applied to each module’s Inverter Logic
Board; and in this case the signal to Module 1 will cause a reduction of the output
voltage and that to Module 2 will cause a corresponding increase – thus restoring
a balanced load current condition.
Note: the above action is dynamic in operation and in practice the circuit effec-
tively maintains a balanced state, with zero current flowing along the current shar-
ing bus, at all times.

2.5.3 Current-sharing relay control (K3/K4)

Under normal circumstances, relays K3 and K4 are energised and de-energised at
the same time as the VCO-in-loop relays (K1/K2); in fact all four relay share a
common control signal – i.e. the [O_PAR_SYN> output from D30 pin 14 (see par-
agraph [Link] on page 8-28).
The only control difference between these two relay groups is that in the case of
the current-sharing relays the [O_PAR_SYN> signal is gated with the TEST mode
logic within D31 and the ultimate relay control signal ( [PAR_INV>) is produced at
D31 pin 7. [PAR_INV> is driven to a logic high to energise K3/K4 – this is inverted
to a logic low at the relay driver D24 pin 13.
When the Parallel Logic Board is placed in its TEST mode (D31 in 43 taken low)
the [PAR_INV> control signal at D31 pin 7 is forced to a permanent low logic state
to prevent the current sharing relays being energised. This is required in a redun-

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dant module system to allow an off-line module to be tested without affecting the
current-sharing function of the second (on-line) module.

2.5.4 Selective shutdown

The Selective Shutdown circuit, which is shown on sheet 3 of the circuit dia-
grams, monitors the current-sharing circuit output signals together with output
phase voltage sense signals and detects three types of current-related fault condi-
tions:
1. It detects when the current sharing is in error and calling for the local module
to provide an excessive amount of current in comparison to the other module.
2. It detects an excess ‘reverse power’ condition whereby a fault in the local
module is causing it to draw current into its output terminals from the other
module.
3. It detects an excess ‘forward power’ condition whereby a fault in the local
module is causing it to feed current into the output terminals of the other
module.

Considering the R phase circuit: the current error signal produced at N1c pin 8
([Dv-A>), described on the previous pages, is fed to N1d pin 13 via R48 where it
is summed with a sense signal proportional to the module’s output R-phase volt-
age ([VO_A>). The ‘VA-proportional’ output from N1d pin 14 is connected to a
three-phase full-wave rectifier, along with the corresponding S and T phase sig-
nals (V1-V6), which then produces a single VA-related signal across R61 which
is proportional to the module’s three phase output.
Under balanced conditions the current error signal [Dv-A> is negligible; and the
output from N1 pin 14 is directly proportional to the voltage sense signal. Under
such circumstances the bridge rectifier produces approximately 4.1V at N5 pin 1.

[Link] Current-sharing error

If the current sharing function fails to operate correctly and calls for this module
to produce an excessive amount of current in comparison to the second module,
the [DV-R> [DV-S> [DV-T> signal(s) add to the voltage-related signals and result in
an increased output from IC5a pin 1.
This is monitored by N5d whose output goes high if N5a pin 1 rises above 5.0V
(equivalent to 30% of nominal current sharing imbalance) – i.e. if the module is
being asked to produce 30% of nominal load capacity more than the second mod-
ule. The resulting logic high [IN_SEL> signal flags D31 pin 4 which turns off the
inverter and trips the output contactor (see paragraph [Link] on page 8-13).

Calibration
N5d’s switching threshold is determined by a reference voltage generator (N11)
whose output voltage is calibrated by R19. This resistor should be adjusted ac-
cording to the module’s working voltage to obtain the following dc voltage at the
top of R68 (junction with R72):
380V = 5.0 Vdc
400V = 5.26 Vdc
415V = 5.46 Vdc

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[Link] Reverse Power detector

If the local module’s output voltage suddenly decreases due to an internal fault
condition it will begin to take reverse current from the second module. Under
these circumstances the current sense signals will be out of phase with, and there-
fore subtract from, the voltage sense signals. The VA signal at N5a pin 1 will
therefore reduce and ultimately fall below the operating threshold of N5c, whose
output will in turn go high and invoke the [IN_SEL> shutdown signal with the same
results as the current error situation described above.
Due to the current imbalance, the current-sharing circuit in the second module
will call for it to reduce its output voltage, and the falling voltage sense signals
will cancel out the increasing forward current signals. Thus the [IN_SEL> signal is
not triggered in the second module and the healthy module will not be tripped off-
line in a ‘redundant module’ system. However, in a ‘non-redundant’ system the
second module will trip of line automatically along with the faulty local module.

Calibration
This function shares the same calibration features as the current-sharing error cir-
cuit described previously.

[Link] Forward Power detector

If the local module’s output voltage suddenly increases due to an internal fault
condition it will attempt to supply all the load current and also feed a reverse cur-
rent into the second module. Under these circumstances, in the local module, the
summation of the VA signals at N5 pin 1 triggers the upper level detector N5d and
the [IN_SEL> signal is activated in the same manner as described for a ‘current-
sharing’ fault.
Due to the current imbalance, the current sharing circuit in the second module will
call for it to increase its output voltage and the rising voltage sense signals will
cancel out the decreasing reverse current signals. Thus the [IN_SEL> signal is not
triggered in the second module and the healthy module is not tripped off-line in a
‘redundant module’ system.
In a non-redundant system the second module will trip of line automatically along
with the faulty local module. However, in a ‘non-redundant’ system the second
module will trip of line automatically along with the faulty local module.

2.5.5 On-line module counter

This circuit, shown on sheet 2 of the circuit diagrams, detects the number of on-
line modules and is used in a ‘redundant system’ to inhibit the selective shutdown
circuit within D31 when only one module is on-line – i.e. if only one module is
running, and by definition providing all the load current, there is no valid reason
to allow its current sharing circuit to produce a selective shutdown and trip the
module off-line (see paragraph [Link] on page 8-13).
When a module is brought on-line, the signal used to energise the VCO-in-loop
relays (K1/K2) is also fed to the module counter circuit as [PAR_INV>. This signal
goes high when the module is on-line, whereupon it turns on V43 and V42 which
provides a current source whatever resistance value is selected by jumpers X5. In
a standard configuration X5 jumpers 1/2/3 are made. This in turn causes a voltage
rise to the non-inverting input of comparator N9b (pin 5) via R130.
<O_N_INV> is connected to the parallel control bus via X2/3 pin 24, therefore
when both modules are on-line the current passing through the selected resistance
doubles, with a corresponding increase to the voltage offered to the comparator.

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The comparator’s operating threshold is determined by the resistance selected by

X4. In a standard 1+1 configuration X4 jumper 1 only is fitted, which sets the cir-
cuit operation such that [C_N_INV> switches high only when both modules are on
line, and is low at all other times.
Note: the reason for the additional jumper positions on X4 and X5 is to allow this
board to be used in a multi-module system, where up to six modules can co con-
nected in a parallel-operating configuration. Where such a system is used, X4 and
X5 permit the minimum number of on-line modules necessary to retain system in-
tegrity to be programmed.

2.6 Parallel rectifier operation

2.6.1 Rectifier current-sharing control

If a single stand-by battery bank is used by both modules the installation is de-
scribed as having a ‘common battery’, and in this situation steps are taken to
ensure that both modules contribute an equal amount of battery charge current.
A current sharing circuit, similar to that used to control the output current sharing,
is employed to ensure that both modules’ rectifiers take an equal amount of input
current. Consequently, if the modules’ input currents are equal and their output
currents are equal this implies that they are properly sharing the battery charge
current.
The local module’s input current sense signal ([I_RECT_T>) enters X1 pin 24 and
is buffered by N6a. The signal at N6a pin 1, is then connected to N6b pin 6 and
also to N6c pin 10 via R66.
If the local module is the only module on-line, as part of a redundant module sys-
tem, the inputs to N6b pins 5 and 6 will cancel each other as they are both obtained
from the same source – e.g. pin 6 monitors the current sense signal from N6 pin
1 and pin 5 monitors the same signal via a second buffer (N6c). Under such cir-
cumstances the output from N6b pin 7 is zero, which then produces a zero error
signal output ([DB>) at X1 pin 25. X1 pin 25 is connected to the voltage regulation
control circuit on the Rectifier Logic Board, via a through connection on the UPS
Logic Board, and trims the rectifier voltage as necessary to adjust its input cur-
rent.
Rectifier current sharing is enabled by energising relay K5. This removes the
ground inhibit from N6d non-inverting input and also connects the local current
sense signal (<IM_R>) passing through R66 to the current sharing bus connected
to X2/3 pin 26.
When the second module is started, its input current sense signal is applied to the
parallel control bus X2/3 pin 26 in the same manner as described for the local
module. Assuming that both modules are drawing exactly the same amount of
input current, there will be no net current flow through R55 in either module, re-
sulting in zero output from IC8b pin 7.
If the modules draw different amounts of input current their current sense signals
differ and there will be a net current flow along the parallel control bus resulting
in a volts drop across R66 proportional to the current imbalance in each module.
This will be detected by N6c, whose output will increase [DB> in the module
drawing less current and decrease [DB> in the other. This processes is continuous
and results in close input current sharing between the two modules at all times
under normal conditions.

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Relay K5 control
As mentioned above, relay K5 must be energised in order to activate the rectifier
current sharing function; this is achieved by the [O_PAR_REC> output from D30
pin 17 going high. D30 pin 17 is itself controlled by the [PAR_REC> input to D30
pin 32 which is derived from the UPS Logic Board micro controller system and
goes high to select parallel rectifier operation – i.e. when the UPS Logic Board is
programmed to invoke rectifier current sharing (common battery) it sends a logic
high [PAR_REC> signal to D30 pin 32 whose [O_PAR_REC> output then switches
high to energise relay K5. This can be overridden by jumper X6-2 which, when
made, clamps [O_PAR_REC> to a logic low. X6-2 is used to select ‘parallel’ or
‘non-parallel’ rectifier operation (open for non-parallel operation) and also affects
the boost charge and battery test functions as described below.

2.6.2 Boost charge control

In a common battery system it is not permissible to have one module operating in
the boost charge mode while the other is in float charge, otherwise they will be
unable to share the battery charge current.
‘Boost’ charge is requested by the UPS Logic Board’s micro controller system
which applies a logic high [O_BST_BAT> input to X1 pin 47. This is connected to
the parallel control bus via X2/3 pin 8 ([B_BST_BAT>), and also to D30 pin 24
([BST_BAT>). Sending the signal through the parallel control bus thus drives the
[BST_BAT> signal high in both modules if either module requests boost charge.

When [BST_BAT> goes high it drives D30 pin 16 high, which is then connected
back to the UPS Logic Board via X1 pin 35 ([I_BST_BAT>) to inform the UPS
Logic Board that the request has been acknowledged. The UPS Logic Board will
then initiate the boost charge mode via appropriate signalling to the Rectifier
Logic Board. Therefore, in a parallel rectifier configured system both rectifiers
are triggered into the boost mode.
If parallel rectifier operation is not required then jumper X6-2, when fitted, will
override the boost charge request logic within D30 and clamp the output on D30
pin 16 at logic low. In this situation the signal passed along the parallel control
bus will have no effect in either module and the boost mode will be independently
controlled for each rectifier.

2.6.3 Battery test control

In a common battery system it is not permissible to have one module operating in
the battery mode without the other, otherwise they will be unable to share the bat-
tery charge current. A control mechanism similar to the boost charge circuit de-
scribed immediately above is therefore used to prevent this from happening.
‘Battery Test’ is requested by the UPS Logic Board’s micro controller system
which applies a logic high [O_TST_BAT> input to X1 pin 46. This is connected to
the parallel control bus via X2/3 pin 13 ([B_TST_BAT>), and also to D30 pin 21
([TST_BAT>). Sending the signal through the parallel control bus thus drives the
[TST_BAT> signal high in both modules if either module requests a Battery Test.

When [TST_BAT> goes high it drives D30 pin 19 high, which is then connected
back to the UPS Logic Board via X1 pin 36 ([I_TST_BAT>) to inform the UPS
Logic Board that the request has been acknowledged. The UPS Logic Board will
then initiate the Battery Test via appropriate signalling to the Rectifier Logic
Board. Therefore, in a parallel rectifier configured system both rectifiers are trig-
gered into the Test mode.

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SECTION 8 - "1+1" Configured UPS System Control 7200 Series UPS Service Manual
CHAPTER 2 - "1+1" Configuration Control Principles

If parallel rectifier operation is not required then jumper X6-2, when fitted, will
override the Battery Test request logic within D30 and clamp the output on D30
pin 19 at logic low. In this situation the signal passed along the parallel control
bus will have no effect in either module and the Battery Test mode will be inde-
pendently controlled for each rectifier.

2.7 Other Features and functions

2.7.1 Ribbon cable connection monitor

As mentioned on page 8-13, the Parallel Logic Board senses the parallel control
bus integrity by monitoring the continuity of the two ribbon cables fitted X2 and
X3, which are cross connected between the two modules. The modules’ parallel
operation can be maintained if one of these cables becomes disconnected (in
which event Led H2 illuminates), but if both cables become disconnected then the
Parallel Logic Board demands that the module inverters are shut-down and the
load transferred to bypass.
Monitoring the cables’ continuity is made possible due to the way that the cables
are cross-connected between the two modules; the error detection signals are an-
notated [A_CON> and [B_CON> (see page 4 of the circuit diagrams). For example,
the [A_CON> signal at X2 pin 1 is held at 0V due to the fact that pin 1 of X3 in the
second module is grounded – the same principle applies to the [B_CON> signal at
X3 pin 2. Thus, the Parallel Logic Board can detect if a ribbon cable is discon-
nected at either end.

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7200 Series UPS Service Manual SECTION 8 - "1+1" Configured UPS System Control
CHAPTER 2 - Parallel Logic Board

Section 8:

2.8 Parallel Logic Board circuit operation during start-up

When the UPS system is started, there are distinct phases that the module goes
through before the load is connected to the inverter(s). These can broadly be de-
scribed as:
• Initialisation/reset
• Run-up & inverter synchronisation
• Connecting to the parallel control bus
• Load transfer procedure (depending on system redundancy)
These phases are described in detail below and aims to give a full understanding
of the system start-up process to facilitate system troubleshooting.

2.8.1 Initialisation/reset
When a module is first started, its UPS Logic Board micro-system goes through
a power-up reset and initialisation routine which applies a 1-second logic high
pulse to X1-42 ([V_AUX>). The effects of this are:
1. D31-5 goes high to reset the ‘selective shutdown’ circuit latch (D31-37 set
low and led H1 = off) (See paragraph [Link])
2. D30-4 goes high which:
a) drives D30-29 ([SYN_INT>) high which forces the GVCO to its ‘internal
sync’ mode – (See paragraph [Link]).
b) drives D30-38 & D30-14 low to reset the VCO-in-loop control logic and
ensure the VCO-in-loop relays (K1/K2) are de-energised ([O_PAR_SYN> =
low) – (See paragraph [Link]).
3. D30-14 ([O_PAR_SYN>) going low is connected to D31-24 where it drives
D31-21 ([RIP>) high which is inverted to a logic low [PAR_INV> at D28-4
which then:
a) de-energises the current-sharing relays (K3/K4).
b) informs the ‘available modules counter’ circuit that the module is off-line.
c) places a logic low input to D31-7 which enables the ‘load-on-bypass’
request from D31-18 (low) and disables the ‘load-on-inverter’ request
from D31-12 (high) (See paragraph 2.3.2).
d) feeds a logic low input to D30-26 which enables the [INV_OK> signal
applied to D31-39 within D31.

2.8.2 Inverter run-up and synchronisation

1. Provided the UPS power switches and parallel bus cables are positioned cor-
rectly, at the culmination of the reset action D31-19 ([OFF_INV>) should go
low, requesting the inverter to run (See paragraph 2.3.1)
2. If other parameter on the UPS Logic Board are satisfactory, the inverter
should now start and its voltage should begin to rise to nominal value; during
which time the following events occur:
a) [O_MNS_SYN> to D30 pins 8 and 18 go low when the Inverter Logic
Board’s master oscillator gains internal sync. The input to pin 8 is associ-

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SECTION 8 - "1+1" Configured UPS System Control 7200 Series UPS Service Manual
CHAPTER 2 - Parallel Logic Board

ated with the bypass frequency validation circuit (See paragraph [Link])
and the input to pin 18 with the GVCO ‘internal sync’ logic – although
[SYN_INT> is still high, requesting “internal sync” at this time due to the
still logic low [INV_OK> input to D30 pin 34 (See paragraph [Link]).
b) The [BLK_INV> input to D30 pin 34 is high, indicating that there is no fault
detected on the Inverter Logic Board – once again this has no effect on
D31 internal operation due to the logic low [INV_OK> input to D30 pin 34.

2.8.3 Connecting to the parallel control bus

When the inverter output voltage rises to its nominal value the [INV_OK> input to
D30 pin 39 will go high, and initiate the following sequence of events:
1. The [SYN_INT> output from D30-29 will go low to enable the GVCO’s ‘angle
regulator’ circuit, allowing the GVCO to synchronise to the selected
[FRQ_REF> signal (See paragraph [Link]).

2. Provided the synchronisation functions are satisfied, the VCO-in-loop relays

(K1/K2) will be energised by D30-14 ([O_PAR_SYN>) going high. The syn-
chronisation functions vary according to whether the module is the “first” or
“second” module to be started and is described in details in paragraph [Link].
If K1/K2 fail to energise at this stage it is recommended that you read and
thoroughly understand paragraph [Link] before going further.
3. D30-14 ([O_PAR_SYN>) going high is connected to D31-24 where it drives
D31-21 ([RIP>) low which is inverted to a logic high [PAR_INV> at D28-4
which then:
a) energises the current-sharing relays (K3/K4).
b) feeds a logic high input to D30-26 which disables the effects of the
[INV_OK> input to D31-39 within D31.

c) informs the ‘available modules counter’ circuit that the module is con-
nected to the parallel control bus and available for use.
d) places a logic high [PAR_INV> input to D31-7 which disables the ‘load-on-
bypass’ request from D31-18 (now switches high) and enables the ‘load-
on-inverter’ request from D31-12 (although D31-12 is not driven low due
to this signal at this point – see below).

2.8.4 Load transfer to inverter

The point at which the load is transferred to the inverter depends on whether the
Parallel Logic Board is configured for a ‘redundant’ or ‘non-redundant’ system
operation – i.e. jumper X6-3 closed = ‘redundant’ configuration and X6-1 closed
= ‘non-redundant’.
The difference between these configuration is that in a ‘redundant’ system the
load can be allowed to transfer to inverter when only one module is running, but
in a ‘non-redundant’ system both modules have to be running before the load is
allowed to transfer. The effects of the configuration on the transfer circuit opera-
tion are described below.

‘Redundant’ system transfer operation

1. In a ‘redundant module’ configuration the ‘available module counter’ circuit
is configured such that its [C_N_INV> output switches high when only one
module is connected to the parallel control bus. Thus, in such a system this

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7200 Series UPS Service Manual SECTION 8 - "1+1" Configured UPS System Control
CHAPTER 2 - Parallel Logic Board

occurs at this point in the start-up sequence.

2. The effects of the logic high [C_N_INV> input to D31-27, coupled with the
logic high [PAR_INV> input to D31-7 now make D31-12 ([C_L_INV>) switch
low, sending a ‘load-on-inverter’ request to the UPS Logic Board.
3. If the UPS Logic Board conditions are normal it should now send a ‘transfer
to inverter’ command to the Static Switch Driver Board which will closed the
inverter output contactor and turn off the static bypass SCRs.

‘Non-redundant’ system transfer operation

4. In a ‘non-redundant’ system two sets of signals, each of which detects the
availability of both modules on the parallel control bus, are required by the
transfer control logic before the load is allowed to transfer to the inverter.
a) In a ‘non-redundant module’ configuration the ‘available module counter’
circuit is configured such that its [C_N_INV> output switches high only
when both modules are connected to the parallel control bus
b) The logic high [PAR_INV> input to D31-7 is inverted to a logic low
[O_INV_IND> at D31-8. This is inverted to a high at D24-17 from where it
is connected to the parallel control bus via X2/X3 pin 12. Due to the paral-
lel control bus, the [INV_IND> input to D31-29 is thus logic low only if
both modules are available (i.e. if [O_INV_IND> is low in both modules).
5. The effects of the logic high [C_N_INV> input to D31-27, coupled with the
logic high [PAR_INV> input to D31-7 and low [INV_IND> input to D31-29, now
make D31-12 ([C_L_INV>) switch low, sending a ‘load-on-inverter’ request to
the UPS Logic Board.
6. If the UPS Logic Board conditions are normal it should now send a ‘transfer
to inverter’ command to the Static Switch Driver Board which will closed the
inverter output contactor and turn off the static bypass SCRs.

Applicable to both system configurations

7. Once the load has transferred to the inverter two key signals are sent back
from the UPS Logic Board to the Parallel Logic Board:
a) First, a lockout signal slaved to the inverter output contactor auxiliary con-
tacts applies a logic high [N_AUX_CONT> input to D31-34 which prevents
the ‘load on bypass’ request from being generated at D31-18 while the
contactor is closed.
b) Second, a logic high ‘inverter on load’ status signal ( [INV_L>) is fed back
to X1-52 which is connected to:
– D31-31 (low) to enable the ‘selective shutdown’ circuit within D31.
– D31-25 (high) to provide a second lockout to the ‘load on bypass’
request circuit within D31 in the same manner as [N_AUX_CONT>
described above.
– via a debounce circuit, [INV_L> produces a logic high [ABIL_RIP> signal
which energises the current-sharing circuit solid-state switches to activate
the current-sharing facility (See paragraph 2.5.2).
8. The UPS Module is now running and on-line, and its synchronisation and
load-sharing signals are connected to the second module via the parallel con-
trol bus.

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SECTION 8 - "1+1" Configured UPS System Control 7200 Series UPS Service Manual
CHAPTER 2 - Parallel Logic Board

2.8.5 Load retransfer back to bypass

Under normal circumstances the load should remain on inverter at all times, and
transfer back to the bypass supply only if inverter is no longer available. There are
several mechanisms which can initiate a ‘transfer to bypass’ request, as outlined
below.

Loss of one module in a ‘non-redundant’ system

This condition will be detected by the ‘available module counter’ circuit
([C_N_INV> = low) – and once the faulty module has tripped off-line, also by the
parallel bus line X2/X3-12 which will produce a low [INV_IND> to D31-29.
Either of these signals will send D31-12 high, removing the ‘load on inverter’ re-
quest to the UPS Logic Board which will respond by providing a logic low
[INV_L> signal to D31-25 which drives D31-18 low to produce a ‘load on bypass’
request.
Note: Once the inverter output contactor opens the ‘load on bypass’ request is sus-
tained by the inverter output contactor auxiliary contacts which now hold D31-34
high.

Inverter Block [BLK_INV>

If the [BLK_INV> input to D30-34 is driven low by the UPS Logic Board, either
due to an inverter fault or selected shutdown etc, it drives D30-14 ([O_PAR_SYN>)
low which then drives D31-21 ([RIP>) high and releases K1/K2 (and by associa-
tion also K3/K4) to trip the module off the parallel control bus.
This also provides a low [PAR_INV> input to D31-7 which disables the ‘load on
inverter’ request. The effects of this are as described above.
Note: if any of the signals which affect the [O_PAR_SYN> output from D30-12
switch to a fault level it has the same effects as the [BLK_INV> signal going low, as
described,

2.9 Test mode of operation:

A test facility is built into the Parallel Logic Board control system which allows
the module to be fully run up without its output being connected to the system –
i.e. in a ‘redundant module’ system this facilitates the full testing of one module
whilst the other remains on-line to provide the load supply.
The test mode is activated by fitting jumper X6-1, which pulls D31-43 down to
0v (logic low) with the following affects:
1. It interlocks with the [SW_OUT> input to D31-14 such that the [OFF_INV> out-
put at D31-19 is allowed to turn the inverter on (low) only if the module’s out-
put switch is open.
2. It forces D31-21 ([RIP>) high which ensures that relays K1/K2 (and by asso-
ciation K3/K4) remain open. This prevents placing a faulty module onto the
parallel control bus synchronisation and current-sharing lines.
3. If forces D31-12 ([C_L_INV>) low to provide the UPS Logic Board with a
continuous ‘load on inverter’ request. This overrides all other inputs to D31
normally required to generate such a request.
4. It disables the selective shutdown logic within D31.

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 Section 9: Optional Equipment

Chapter 1 - Alarm Interface Board 4590055P

1.1 General description ................................................................................... 9-1
1.1.1 Remote control inputs .................................................................. 9-2
1.1.2 AS400 Interface ........................................................................... 9-2
1.1.3 Alarm outputs ............................................................................... 9-3
1.1.4 X2 Extension ................................................................................ 9-3
Chapter 2 - Remote Alarm Interface 4590056Q
2.1 Introduction .............................................................................................. 9-5
2.2 Alarm outputs ........................................................................................... 9-6
2.3 Alarm inputs ............................................................................................. 9-6
Chapter 3 - Remote Alarm Monitor 4305001Z
3.1 General description ................................................................................... 9-9
3.1.1 Connections .................................................................................. 9-9
3.2 Detailed circuit description .................................................................... 9-11
3.2.1 Power supply .............................................................................. 9-11
3.2.2 Alarm indications ....................................................................... 9-11
3.2.3 Audible alarm control ................................................................ 9-12
Chapter 4 - Battery cabinets
4.1 General introduction ............................................................................... 9-15
4.2 Type ‘D' (85 Ah) Battery cabinet assembly and installation ................. 9-15
Chapter 5 - Battery Breaker Boxes
5.1 Introduction ............................................................................................ 9-23
5.2 Circuit breaker details ............................................................................ 9-23
5.3 Battery Circuit Breaker Interface Board (4520067-T) ........................... 9-25
5.3.1 Circuit breaker ‘close’ operation ............................................... 9-25
5.3.2 Auxiliary contacts ...................................................................... 9-25
5.3.3 Temperature sensor .................................................................... 9-25
Chapter 6 - Input Harmonic Filters
6.1 General Introduction ............................................................................... 9-27
6.1.1 Specification .............................................................................. 9-27
6.1.2 Notes on connection ................................................................... 9-27
Chapter 7 - RS232 Comms Kit 4645101T
7.1 Hardware and Installation Requirements ............................................... 9-31
7.2 UPS Hardware and Software Configuration .......................................... 9-32
7.2.1 Master UPS Set-Up .................................................................... 9-32
7.2.2 Slave UPS Set-Up ...................................................................... 9-33
7.2.3 Installing the Software program ................................................. 9-33
7.2.4 Running the Software ................................................................ 9-35
7.2.5 Accessing the Data ..................................................................... 9-37
S-8.FM5 - Issue 2 Dated 21/08/97 i
SECTION 9 - Optional Equipment 7200 Series UPS Service Manual

ii S-8.FM5 - Issue 2 Dated 21/08/97

 Section 9:

Chapter 1 - Alarm Interface Board 4590055P

1.1 General description

The Alarm Interface board is fitted in the right hand side of the unit, on the front
lower face (see Figure 9-1) near the auxiliary terminal block (X3), and is connect-
ed to the UPS control electronics (UPS Logic board) by a ribbon cable (W10)
which is normally stowed in the cable loom when not in use. The board has sev-
eral functions as described below:

Figure 9-1: Alarm Board location

4530025T

4550007H

Alarm Board

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SECTION 9 - Optional Equipment 7200 Series UPS Service Manual
CHAPTER 1 - Alarm Interface Board 4590055P

1.1.1 Remote control inputs

The Interface Board has facilities to accept three remote control inputs, as shown
in Figure 9-2. The external control signals (12Vd.c. or 12Va.c.), which are opto-
coupled to the electronics, should be connected to terminal block X5 as shown in
Figure 9-2.

Important The control voltages applied to these terminals must be generated by an external
power source and not taken from the UPS internal low voltage supplies.

The remote input to X5 pins 1 and 2 is not used. The input to pins 3 and 4 enable
the inverter to be shut down remotely – transferring the load to the bypass supply.
The third remote input, to X5 pins 5 and 6, is most often used in conjunction with
a stand-by generator which may be activated when the input mains supply fails.
The effects of this input can be configured from the Operator Control Panel to a
combination of the following; reduce the input current limit; reduce the battery
current limit; inhibit the inverter/bypass synchronisation.

1.1.2 AS400 Interface

The AS400 Interface connects the five most operationally critical UPS alarms to
an IBM AS400 computer, which is designed to monitor such alarms and respond
to their appearance.
Connection to the AS400 is provided on the Interface Board via a terminal block
X3. These alarm signals are provided by volt-free relay contacts, maximum con-
tact rating is 50 Vcc @ 1 Amp.
The alarms in question are:

Load On Static Bypass [AS400BY>

When high, this signal energises relay K6 and connects X3 pin 5 to pin 1 (0V).
This occurs when the maintenance bypass switch is open and a “transfer-to by-
pass” request is present (alarm [#18]).

Low Battery Warning [AS400BL>

When high, this signal energises relay K7 and connects X3 pin 4 to pin 1 (0V).
This alarm is enabled only if the maintenance bypass switch is open, the load is
“on-inverter” [#01], and the rectifier is stopped [#22] for any reason. The alarm
then activates when the battery voltage falls below the minimum programmed
Low Battery Level [#56] (usually set to occur at 355Vdc).

Maintenance Bypass Breaker Open [AS400ON>

When high, this signal energises relay K8 and connects X3 pin 3 to pin 1 (0V).
This occurs when the maintenance bypass switch is open.

Mains or Rectifier Failure [AS400UE>

When high, this signal energises relay K9 and connects X3 pin 2 to pin 1 (0V).
This alarm is enabled only if the maintenance bypass switch is open and the load
is “on-inverter” [#01]. The alarm then activates when the rectifier is stopped
[#22] for any reason.

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CHAPTER 1 - Alarm Interface Board 4590055P

1.1.3 Alarm outputs

In addition to the AS400 alarm outputs the Interface Board also contains a number
of relays whose contacts provide a set of volt-free alarm outputs that are connect-
ed to terminal block X4 - as shown in Figure 9-2. These outputs can be used to
drive an external alarms monitoring device. Maximum contact rating on M1 ter-
minals = 50 Vcc @ 1 Amp. Note:- When using the above contacts for remote
alarm annunciation, the power supply for the remote indicators must be obtained
from an external power source and not taken from the UPS internal low voltage
supplies.
The alarms in question are:

Bypass Supply Failure [MNS_KO>

When high, this signal energises relay K1 and connects X4 pin 14 to pin 15. This
alarm is active when the bypass voltage is low (undervoltage alarm [#12]), the
bypass voltage is high (overvoltage alarm [#11]) or absent (alarm [#10]); or the
bypass-side static switch is selected blocked [#17] via the Operator Control Panel
menuing system.

Low Battery Warning [BATED>

When high, this signal energises relay K2 and connects X4 pin 11 to pin 12. This
alarm is active when the battery breaker is open [#05], the bypass fuse is open
[#57]) or the Low Battery alarm is active [#56]). The Low Battery alarm threshold
is programmable via the Operator Control Panel menuing system, and is usually
set at 360Vdc (i.e. 1.82V/Cell).

Load -on Bypass [MNS_L>

When high, this signal energises relay K3 and connects X4 pin 8 to pin 9. This
alarm is active when the Static Switch bypass-side SCRs are triggered by the UPS
Logic Board (alarm [#18]).

Maintenance Bypass Breaker closed [SW_BYP>

When high, this signal energises relay K4 and connects X4 pin 5 to pin 6. This
alarm is active when the Maintenance Bypass breaker is closed as sensed via the
UPS Logic Board (alarm [#06]).

Load on Inverter [INV_L>

When high, this signal energises relay K5 and connects X4 pin 2 to pin 3. This
alarm is active when the inverter output contactor is closed, as controlled by the
UPS Logic Board (alarm [#01]).

1.1.4 X2 Extension
The X2 connection on the board is provided to interface the UPS systems with the
remote alarms board part number 4590056Q which contains additional alarms.

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CHAPTER 1 - Alarm Interface Board 4590055P

Figure 9-2: Interface Board inputs/outputs

X5
6 On generator = apply 12V
ON_GEN
5
4
INV_OFF Inverter off = apply 12V
3
2 Not Used
1

X4
RL-K1 15
MNS_KO 14 Mains or Rectifier Failure
13

RL-K2 12
BATED 11 Low Battery (pre-alarm)
10

RL-K3 9
MNS_L 8 Load on Bypass
7

RL-K4 6
Load on Maintenance
X2 SW_BYP 5 Bypass
4

RL-K5 3
INV_L 2 Load on Inverter
1

X3
RL-K6 5 Load on Bypass
AS400BY

RL-K7 4 Low Battery

AS400BL

RL-K8 3 Maintenance Bypass

AS400ON Open

RL-K9 2 Mains or Rectifier Failure

AS400UE

Common (0V)
1
Maximum Contact Rating = 50Vcc @ 1 ampere

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 Section 9:

Chapter 2 - Remote Alarm Interface 4590056Q

2.1 Introduction
The Remote Alarms Interface board is fitted in the right hand side of the unit and
is connected (piggy back style) directly via connector X1 onto the Alarm Interface
Board (4590055P) connector X2. This board therefore can only be used in con-
junction with the Interface Board (4590055P).
All alarms are generated via software routines on the UPS Logic Board and output
from the micro data bus via a series of controlled output buffers. The signals then
pass via a piggy-back connection through the Alarm Interface Board (4590055P)
to the Remote Alarm Interface Board where they energise appropriate relay coils
via N-P-N switching transistors – i.e. any UPS Logic flag (e.g. [OVL>) going high
(+5V) will energise the relay coil.

Figure 9-3: Location of Alarm Interface Boards

4530025T

4550007H

Alarm Interface Board

Part Number 4590055P
Remote Alarm Interface Board
Part Number 4590056Q

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SECTION 9 - Optional Equipment 7200 Series UPS Service Manual
CHAPTER 2 - Remote Alarm Interface 4590056Q

2.2 Alarm outputs

The Remote Alarms Interface board output relays all have changeover contacts
which can be used to provide ‘make’ or ‘break’ volt-free alarm outputs via termi-
nal blocks X2 and X3 - as shown in Figure 9-4. The contacts are rated at 50Vdc
@ 1 amp and can be connected to an external remote alarms signalling system.

Important The power supply for any remote indicators must be provided from an external
power source. Under no circumstances should the UPS internal low voltage sup-
plies be used for this purpose.

2.3 Alarm inputs

Any of the following UPS Logic Board alarm flags (e.g. [OVL>) going high (+5V)
will energise the relay coil.

Battery discharging alarm [BAT-DSC>

When high, energises relay K1 and connects X2 pins 14 and 15.
This alarm is enabled when the battery breaker is closed and the battery fuse in
intact and then active when rectifier block (alarm #22) signal is present.

Inverter overload alarm [OVL>

When high, energises relay K2 and connects X2 pins 11 and 12.
This alarm is active when either the 150% current limit (alarm # 33) or the over-
load timer (alarm 66) is enabled.

Overtemperature alarm [OVT_DIS>

When high, energises relay K3 and connects X2 pins 8 and 9.
This alarm is active when a rectifier overtemperature (alarm # 24) or an inverter
overtemperature (alarm #34) is enabled.

Inverter unsynchronised alarm [SYN_KO>

When high, energises relay K4 and connects X2 pins 5 and 6.
This alarm is active when the R phase of the bypass supply and inverter are dis-
placed by more than ±11° (alarm #35).

Common alarm [ALL_GEN>

When high, energises relay K5 and connects X2 pins 2 and 3.
This is a general alarm facility and is activated from any of the following:
• Bypass-side static switch is blocked (inhibited) by hardware (alarm #16)
• Inverter is unsynchronised (alarm # 35)
• Overtemperature is active (alarm #24 or # 34)
• Battery is discharging (alarm #52)
• Maintenance Bypass Breaker is closed (alarm #06)
• Low Battery/ Open Battery warning (alarm #05 or #56 or #57)
• Bypass supply failure (alarm #10 or #11 or #12 or #17)
• Overload is active (alarm #33 or #66)

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Battery overtemperature alarm [OVT_BAT>

Excessive ambient air temperature within the battery cabinet (not programmed).

Bypass-side Static Switch blocked [CS_KO>

When high, energises relay K7 and connects X3 pins 11 and 12.
This alarm is active if the UPS Logic Board is hardware-blocking a transfer to
bypass (alarm #16) – e.g. Emergency power off (#63); Open SCR (#15); Bypass
phase rotation error (#14), PCB Power supply failure; UPS Logic Board Q1 se-
lected to inhibit.

Rectifier input voltage failure [MNS_REC>

When high, energises relay K8 and connects X3 pins 8 and 9.
This alarm is active when the rectifier input voltage drops below -20% of nomi-
nal; as sensed by the Rectifier Logic Board (H9 illuminated).

Ambient air overtemperature [OVT_AMD>

Excessive ambient air temperature within the UPS cabinet (not programmed).

Rectifier inhibited [CHG_INH> or [OUT_01>

Rectifier shut-down (not programmed).

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SECTION 9 - Optional Equipment 7200 Series UPS Service Manual
CHAPTER 2 - Remote Alarm Interface 4590056Q

Figure 9-4: Remote Alarms Interface Board Part No 4590056Q

X2

RL-K1 15
BAT_DSC 14 Battery on Load
13

RL-K2 12
OVL 11 Overload
10

RL-K3 9
OVT_DIS 8 Overtemperature
7

RL-K4 6
SYN_KO 5 Inverter Unsynchronised
Connect piggy-back to X2 of 4590055P

4
X1
RL-K5 3
ALL_GEN 2 Common Alarm
1

X3
RL-K6 15 Battery Cabinet
OVT_BAT(N/A) 14 Ambient overtemp
Not Used
13
RL-K7
12
Bypass Static Switch
CS_KO 11 Blocked
10
RL-K8 9
MNS_REC 8
Rectifier input volts
failure (-20%)
7

RL-K9 6 UPS Cabinet

OVT_AMB (N/A) 5 Ambient overtemp
4 Not Used

RL-K10
3
CHG_INH Not Used
2
OUT_01
1

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 Section 9:

Chapter 3 - Remote Alarm Monitor 4305001Z

3.1 General description

When used in conjunction with the Alarms Interface Board (4590055P) described
previously, the Remote Alarm Monitor (R.A.M.) enables the auxiliary alarm sig-
nals to be displayed at a remote station up to 200 metres from the main equipment.
The R.A.M. can be mounted either horizontally or vertically and contains a
mains-driven power supply to power the alarm LEDs. The following alarm indi-
cations are displayed:

Table 9-1: LED Indications

Panel Normal
Interpretation
Indication Colour state

Inverter ON: green ON Normal operating condition indicating that

the load is being supplied by the inverter.
This is not an ‘alarm' indicator.

Utility Failure: red OFF When lit, it indicates that the input mains are
out of tolerance or rectifier has failed.

Battery low: red OFF When lit, it indicates that the battery voltage
is below minimum or that the battery circuit
breaker is open.

Bypass ON: red OFF When lit, it indicates that the load is being
fed from the bypass supply possibly due to a
UPS failure.

Maintenance: red OFF When lit, it indicates that the UPS has been
selected to operate on the maintenance
bypass and the load is unprotected.

Alarm: red OFF This is a ‘common alarm' and is lit when any
of the red leds described above are lit.

An audible warning accompanies any of the above alarm conditions. This is, how-
ever, subject to a short time delay when activated in conjunction with the ‘Utility
Failure' and ‘Bypass ON' alarms, to prevent the warning being activated by tran-
sient conditions. Pressing the ‘reset' push-button cancels the audible warning but
the alarm indications remain until the condition returns to normal operation.

3.1.1 Connections

[Link] Power supply

The R.A.M. contains a single phase 220-240Va.c. mains-driven power supply.
Power is applied through a standard three-pin mains connector located in the
R.A.M. back panel (plug provided) - using 3-core 0.5mm cable (minimum). The
supply is rated at approximately 4 Watts and fused at 1A.
To guarantee that the R.A.M. remains active following a mains failure, it is ad-
vised that the power supply is fed from the UPS output (critical bus).

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SECTION 9 - Optional Equipment 7200 Series UPS Service Manual
CHAPTER 3 - Remote Alarm Monitor 4305001Z

[Link] Alarm connections

A soldered 9 pin D-type connector (provided with the option kit) fits into the 9
pin socket on the back of the RAM and should be wired to the Alarms Interface
Board (4590055P), fitted in the UPS, using 9 core, 0.22mm. (minimum) shielded
cable as shown. The maximum recommended distance is 200 metres.

Figure 9-5: Remote Alarm Monitor connection details

X4
Mains RL-K1 15
Supply- 14
Failure
13
Low RL-K2 12
Battery 11
(pre-alarm) 10
Load on RL-K3 9
Static bypass 8
supply 7
Load on RL-K4 6
Maintenance 5
Bypass 4
RL-K5 3
Load on
2
Inverter
1
220/240V a.c. 50 Hz

5 4 3 2 1

9 8 7 6

INVERTER UTILITY BATTERY

ALARM
ON FAILURE LOW

BYPASS
ON MAINTENANCE

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7200 Series UPS Service Manual SECTION 9 - Optional Equipment
CHAPTER 3 - Remote Alarm Monitor 4305001Z

3.2 Detailed circuit description

The following description refers to the R.A.M. circuit diagram SE-4530021P.

3.2.1 Power supply

The 220/240Vac power supply is stepped down by isolation transformer T1,
whose secondary output is then rectified by D1/D2 and smoothed by C13 to pro-
vide an unregulated nominal +12V supply rail which is used by the audible alarm
annunciator. This rail is also connected to a standard three-terminal +5V regulator
whose output is smoothed by C14 and then provides a stable +5V rail that is used
by the remainder of the board’s electronic circuits. The supply is not fused on-
board but a 1A fuse should be fitted in the external connector.

3.2.2 Alarm indications

All the alarms are activated via volt-free relay contacts on the Alarms Interface
Board (4590055P) – (See Figure 9-5).

Load-on-inverter
This indication (not an alarm, as it is normally on) is connected to CN1 pin 5 and
is 0V when the load is connected to the inverter (i.e. the output contactor is
closed). The 0V supply to pin 5 is obtained from pin 4. This alarm input drives
the indicator led LS1 only (normally ON) and is not connected to the audible
alarm circuit.

Load-on-Bypass
This alarm is connected to CN1 pin 9 and is 0V when the load is connected to the
bypass supply (i.e. the bypass-side static switch is closed). The 0V supply to pin
9 is obtained from pin 2. This alarm input drives the indicator led LS4 immedi-
ately and also activates the audible alarm circuit via IC1 pin 4 after a delay of ap-
proximately 11 seconds. which is introduced to avoid nuisance alarms.

Load-on-Maintenance Bypass
This alarm is connected to CN1 pin 8 and is 0V when the maintenance bypass
contactor is closed. The 0V supply to pin 8 is obtained from pin 1. This alarm
input drives the indicator led LS5 and inhibits the audible alarm operation when
the Maintenance Bypass isolator is closed (IC1 pin 3 = low).

Low battery
This alarm is connected to CN1 pin 7 and is 0V when the battery is at its “low-
voltage” threshold – i.e. approaching its end-of-discharge voltage. The 0V supply
to pin 7 is obtained from pin 3. This alarm input drives the indicator led LS3 im-
mediately and also activates the audible alarm circuit via IC1 pin 2 after a delay
of approximately 11 seconds, which is introduced to avoid nuisance alarms.

Utility Failure
This alarm is connected to CN1 pin 6 and is 0V when the mains supply voltage is
low (-20%). The 0V supply to pin 6 is obtained from pin 3. This alarm input drives
the indicator led LS2 immediately and also activates the audible alarm circuit via
IC1 pin 1 after a short (11sec) delay to avoid nuisance alarms.

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SECTION 9 - Optional Equipment 7200 Series UPS Service Manual
CHAPTER 3 - Remote Alarm Monitor 4305001Z

Summary alarm
The summary alarm is produced by a four-input and gate within IC1 (See Figure
9-6) whose output pin 19 goes low if either one of the above four alarm conditions
are present. This output illuminates LS6 and also places a logic high on IC1 pin
5, which resets the audible alarm automatically when the alarm condition is re-
moved (described later).

Figure 9-6: Internal logic diagram of IC1

Utility Fail 1 17 RES-C1

Load-on-bypass 4
18 RES-C2
Battery Low 2
13 OC2

Maint. Bypass 3 12 OC1

19 ALARM
(LS6)
ID1 8
ID2 9

6 16 Buzzer
IC1
IC2 7

RAL 5
15 N.I.U.
RES 14
Stop 11

3.2.3 Audible alarm control

Alarm latch operation

The audible warning device is controlled from a latch within IC1, as show above.
The alarm is activated by a logic high applied to any of the input pins 6, 7, 8 or 9:
this “sets” the latch, which drives IC1 pin 16 high and energises the warning
device by turning on TR1. Once set, the latch will activate the audible alarm until
it is reset by a logic high input to IC1 pin 5, 11 or 14.
The signals to IC1 pins 6, 7, 8 and 9 are driven by the four alarm signals produced
at pins 12, 13, 17, and 18 which are connected to the latch “set” inputs via timing
and debounce circuits.
For example: pin 6 is driven by the Maintenance Bypass alarm output at pin 12
and debounced by R7 and C9. Pin 7 is driven by the Battery Low alarm output at
pin 13 and debounced by R8 and C8. Pins 8 and 9 are driven via controlled time
delays which are introduced to overcome nuisance audible warnings in response
to Load On Bypass and Utility Failure alarms on pins 17 and 18 respectively.

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7200 Series UPS Service Manual SECTION 9 - Optional Equipment
CHAPTER 3 - Remote Alarm Monitor 4305001Z

Time delays
The time delays are implemented by IC2 and IC3. IC2 is a dual binary counter,
both sections of which are clocked by a free-running 555 timer, IC3, at approxi-
mately 1.4 second intervals. The circuit is best understood by considering the fol-
lowing operation of IC2a in response to the Load-on-bypass alarm output from
IC1 pin 18.
Under normal conditions, IC1 pin 18 is logic high which applies a permanent reset
to IC2 pin 7 and holds it at zero-count – i.e. Q0 to Q3 all low. If a Load-on-bypass
alarm condition arises, the reset condition is removed and IC2 will count up on
successive clock pulses applied to its enable input (pin 2). On the eighth clock
pulse the Q3 output will switch high, which disables further counting and flags
the alarm condition to IC1 in 9 via debounce circuit R10/C6. Hence, the Load-on-
bypass alarm output from IC1 pin 18 must be present for approximately 11 sec-
onds before it annunciates the audible warning. If the alarm condition disappears
before the completion of eight clock cycles IC2 is reset to zero by the logic high
signal being reapplied to pin 7.
The second section of IC2 works in an identical manner for the Bypass Mains Fail
alarm output at IC1 pin 18.

Alarm latch reset

As explained above, the audible alarm latch can be reset by any one of three sig-
nals applied to IC1 pins 5, 11, 14 (high to reset).
The input to pin 5 is driven directly from the summary alarm output at pin 19 and
resets the audible alarm automatically when Load On Bypass, Battery Low and
Utility Failure alarm conditions all revert to normal, provided the maintenance
bypass breaker is open. If the maintenance bypass breaker is closed the Load On
Bypass, Battery Low and Utility Failure alarms are prevented from activating the
audible warning. That is, if the UPS is undergoing maintenance there will be no
audible warnings at the Remote Alarms Monitor station; but once maintenance is
complete, and the load is transferred back to the normal UPS supply, the audible
warning is automatically re-enabled.
The input to pin 14 is driven from a power-up reset debounce circuit which en-
sures that the audible warning is inhibited when power is first applied.
The input to pin 11 is driven from the mimic panel reset button (PS1) which
allows the operator to reset the audible warning once the alarm has been recog-
nised. Note that the mimic display alarm leds will not reset until the alarmed con-
dition has reverted to normal.

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CHAPTER 3 - Remote Alarm Monitor 4305001Z

9-14 S8-c3.fm5 - Issue 2 Dated 21/08/97

 Section 9:

Chapter 4 - Battery cabinets

4.1 General introduction

HAZARD Only qualified personnel should install or service batteries.

WARNINGS Batteries may present a risk of shock or burn from high short circuit currents.
Eye protection should be worn to prevent injury from accidental electrical [Link]-
move rings, watches and all metal objects.
Only use tools with insulated handles.
Wear rubber [Link] a battery leaks electrolyte, or is otherwise physically dam-
aged, it should be placed in a container resistant to sulphuric acid and disposed
of in accordance with local [Link] electrolyte comes into contact with the
skin the affected area should be washed immediately.
Batteries MUST be disposed of in accordance with local environmental laws.

There are three types of battery cabinet offered with the Series 7200 UPS which
are graded according to their recommended ampere hour capacities. Type B is
rated at 38 Ah; Type C is rated at 50 Ah and Type D is rated at 85 Ah. The cabinets
are of the same height as the UPS and can be sited on either side of the UPS cab-
inet. Where higher autonomy times are required additional cabinets can be added
to the system.
Due to the type and size of cells which can be used in battery installations it would
be impracticable to provide specific installation instructions in this manual. How-
ever as a general guide:-
• Always install the batteries starting from the bottom and work upwards.
Leave the inter row links identified as (C) and connections to the circuit
breaker until last (see Figure 9-8, Figure 9-10 and Figure 9-12).
• After each connection is made fit the insulation shroud for that terminal
into position.
• Please refer to the battery manufacturers instructions and the drawings
supplied with the module for specific installation instructions.

Figure 9-7 to Figure 9-12 give suggested layouts for the three types of cabinet.
The following instructions refer to a Type D (85 Ah) cabinet installation. Instal-
lation of the other cabinets would follow a similar method. If you use a different
type of battery these instruction may be invalid due to the terminal orientation of
the cells in use and their terminal fixture.

4.2 Type ‘D' (85 Ah) Battery cabinet assembly and installation
The battery cabinet can be fitted with either a 100 Amp circuit breaker for use
with 30-40 kVA modules, or with a 160 Amp circuit breaker for use with 60kVA
modules. It houses thirty-four maintenance free batteries connected in series to
provide a 460V battery bank. The batteries are housed on rails and there are
eleven sets of rails in the complete cabinet as shown in Figure 9-11.
Before proceeding with the following instructions please study Figure 9-11 and
Figure 9-12, note that batteries should be fitted from the lower level up and the

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SECTION 9 - Optional Equipment 7200 Series UPS Service Manual
CHAPTER 4 - Battery Cabinets

battery interconnecting links starting with the (A) links and the last connection
must be the (G) link.
1. Unpack each battery and check its terminal voltage with a DVM. If any bat-
tery terminal voltage is less than 2.13 volts per cell (12.8V per 6 cell block)
it must be recharged before continuing with the battery cabinet assembly.
2. Gain full access to the battery cabinet interior, remove the battery fitting
hardware stowed, ensure the interior is clean of any transit debris.
3. Starting at the rear of the lower level fit the nine batteries on this level.
4. Connect the inter-battery (A) links (6 off) and the inter-row (B) link (1 off).
Connect one end of the inter-level (C) links (2 off) to the positive terminal of
the right hand rear battery in both cabinets and safely stow the other end.
5. Fit the thirteen batteries into place on the middle level.
6. Connect the inter-battery (A) links (9 off) then the inter-row (B) links (2
off). Connect one end of the inter-level (C) links (2 off) to the positive termi-
nal of the right hand rear battery in both cabinets and safely stow the other
end.
7. Fit the twelve batteries into place on the top level.
8. Connect the inter-battery (A) links (8 off) followed by the inter-row (B)
links (2 off).
9. Take the previously stowed inter-level (C) link connected to the bottom level
of the right hand cabinet and connect it to the negative terminal of the left
hand front battery on the middle level. Then repeat for the left hand cabinet.
10. Take the previously stowed inter-level (C) link connected to the middle level
of the right hand cabinet and connect it to the negative terminal of the left
hand front battery on the top level. Then repeat for the left hand cabinet.
11. Ensure the battery circuit breaker is selected to the OFF position.
12. Locate the (D) link (1 off) and connect it between the positive terminal of
the front right hand battery on the upper level in the right hand cabinet and
the left hand input connection of the battery circuit breaker.
13. Locate the (E) link (1 off) and connect it between the positive terminal of the
front right hand battery on the upper level in the left hand cabinet and the
centre +ve output connection of the battery circuit breaker.
14. Locate the (F) link (1 off) and connect it between the negative terminal of
the front left hand battery on the lower level in the right hand cabinet and the
right hand -ve output connection of the battery circuit breaker.
15. Locate the (G) link (1 off) and connect it between the negative terminal of
the front battery on the lower level in the left hand cabinet and the left hand
output connection of the battery circuit breaker.
16. Connect the battery power cables and Circuit Breaker Controller Board con-
trol cables between the battery cabinet and UPS cabinet if they are not yet
connected - see Figure 9-12. To maintain EMC standards the Battery cabinet
must be bonded to the UPS cabinet and the control cables must be screened
and run in a separate trunking from the power cables.
17. Fit the safety screen to the front of the battery cabinet and close the doors.

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7200 Series UPS Service Manual SECTION 9 - Optional Equipment
CHAPTER 4 - Battery Cabinets

Figure 9-7: 38Ah Battery cabinet - Battery Assembly and Layout

Battery Supply
to UPS
Battery CB
Controller Board BATTERY CABINET FRONT VIEW (DOOR OPEN)
(4520067T) AND SIDE VIEW

A A

A A

+ve

PLAN VIEW OF BATTERY CABINET BOTTOM ROW

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SECTION 9 - Optional Equipment 7200 Series UPS Service Manual
CHAPTER 4 - Battery Cabinets

Figure 9-8: 38Ah Battery cabinet - Battery Layout and Connection Detail
‘Double positive’ pole method

B
A
A

A
A

B
A
C A

A
A

B
A
NT C A
F RO

A
E A

C A
A
A
A
F

Battery CB

Battery Supply to
UPS Cabinet

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7200 Series UPS Service Manual SECTION 9 - Optional Equipment
CHAPTER 4 - Battery Cabinets

Figure 9-9: 50Ah Battery cabinet - Battery Assembly and Layout

Battery CB Battery Supply BATTERY CABINET FRONT VIEW (DOOR OPEN)

Controller Board to UPS AND SIDE VIEW
(4520067T)

B B B

A A A A A

E C

PLAN VIEW OF BATTERY CABINET TOP ROW

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SECTION 9 - Optional Equipment 7200 Series UPS Service Manual
CHAPTER 4 - Battery Cabinets

Figure 9-10: 50Ah Battery cabinet - Battery Layout and Connection

’Double positive’ pole method

A
B

A A

C
B
A

A A

A
A
NT
FRO
C
B
A

A A

A
F

C B
Battery CB A

A A

Battery Supply to A
UPS Cabinet

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7200 Series UPS Service Manual SECTION 9 - Optional Equipment
CHAPTER 4 - Battery Cabinets

Figure 9-11: 85Ah Battery cabinet - Battery Layout and Connection

Battery Supply
to UPS
Battery CB
Controller BATTERY CABINET FRONT VIEW (DOORS OPEN)
Board
(4520067T)

B
A B

A A A
A

A A A
A

C C C
C

PLAN VIEW OF BATTERY CABINET MIDDLE ROW

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SECTION 9 - Optional Equipment 7200 Series UPS Service Manual
CHAPTER 4 - Battery Cabinets

Figure 9-12: 85Ah Battery cabinet - Battery Layout and Connection

‘Half Potential’ method

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 Section 9:

Chapter 5 - Battery Breaker Boxes

5.1 Introduction
The battery circuit breaker box houses the battery circuit breaker and its controller
board, as shown in Figure 9-13. It is used to connect the battery to the UPS in in-
stallations where the batteries are not contained in a standard battery cabinet and
is usually fitted as close to the batteries as possible.
Two types of Battery Breaker Boxes are available: these are similar in design and
listed below:
• 100 Amp C/B Part No 4641027 B for use with 30 - 40 kVA models.
• 160 Amp C/B Part No 4641028 C for use with 60kVA+ model.

The battery circuit breaker box offers the following features:

• Battery temperature compensation.
• Undervoltage cut-off (battery trip) controlled by the UPS.
• Low battery safety cut-off.
• Battery circuit breaker status information to the UPS.
• Over current protection.
• Three pole circuit breaker - which can be connected in either a ‘Double-
positive pole’ or ‘half-potential’ configuration.

The connections are similar to the connections made to the battery cabinet.

Safety Notes: 1. The Battery Circuit Breaker Box must be earthed.

2. Remove the battery fuse in the UPS before making the battery circuit breaker
power connections.

5.2 Circuit breaker details

The circuit breaker main contacts are typically rated at >22kA @ 380Vac and
7.5kA @ 500Vdc for 10 milliseconds. The auxiliary contacts are rated at 5A
@220Vac.
The circuit breaker coil is rated at 110Vdc. Typically, it closes at a coil voltage of
93Vdc and drops-out when the coil voltage falls to 40Vdc.
The coil resistance is approximately 9kOhms.

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SECTION 9 - Battery Breaker Boxes 7200 Series UPS Service Manual
CHAPTER 5 - Battery Breaker Boxes

Figure 9-13: Battery box layout and connections

‘Double positive’ pole method
Power cables To
to Battery Temperature
Sensor
Maximum dimensions in mm:
Height 470
Width 300
Depth 146

Control Board 4520067T terminal block X1

connections to the UPS auxiliary terminal block X3
4520067T BCB System UPS
X1-5 Temperature Sensing Signal X3-2
X1-4 Temperature Sensing Signal X3-3
X1-3 Control Signal Common X3-4
X1-2 CB Status Control X3-5
X1-1 CB Control Signal X3-6
Black

Red

Temp Sensing Signal to UPS

Earth
Power cables
To UPS Control/Monitoring Signals Temperature Sensor
To Battery
0835047F
0540032M

Screened Cable

X10 X2

X5

<V 4520067T
X6

X8

X9

Black X3

Red X4
X1
1 2 3 4 5

Screened Cable

To UPS To UPS auxiliary

terminal block X3

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7200 Series UPS Service Manual SECTION 9 - Battery Breaker Boxes
CHAPTER 5 - Battery Breaker Boxes

5.3 Battery Circuit Breaker Interface Board (4520067-T)

The purpose of this board (see diagram SE 4520067 T) is to provide an interface
between the UPS control logic and the circuit breaker itself. The board provides
galvanic isolation for the ‘close’ signal to the circuit breaker coil, and also
presents a path for the circuit breaker’s auxiliary contacts and temperature sensor
signals back to the UPS.

5.3.1 Circuit breaker ‘close’ operation

The circuit breaker (CB) coil is connected to terminals X5 and X6, and its’ ener-
gising voltage is obtained from the rectifier output (DC bus), which is connected
to X4(+) and X3(-). The battery bus positive voltage at X4 is thus connected di-
rectly to one side of the CB coil at X5. It also provides a stabilised 13V rail at
opto-isolator V6 collector, due to the action of R4, R5 and zener V3.
When the UPS control logic issues a battery circuit breaker ‘close’ command, it
applies a logic high signal between X1-1(+5V) and X1-3(0V). This turns ON
opto-isolator V6, whose emitter now pulls-up V4’s gate to the 13V rail and causes
it to turn ON. With V4 turned ON, the CB coil’s connection at X6 is effectively
connected to the battery bus negative voltage at X3 via R7, R5 and V4.
V2 is a flywheel diode for the CB coil and protects V4 against large regenerative
currents. V1 and V5 similarly protects the opto-isolator against reverse voltage
transients.

5.3.2 Auxiliary contacts

The circuit breaker’s auxiliary contacts are connected to X8 and X9. These con-
tacts are ‘normally open’ and close when the circuit breaker is closed to provide
a CB status input to the UPS control logic.
Note: the line to X9 from X1-3 is connected to the 0V rail within the UPS.

5.3.3 Temperature sensor

The temperature sensor is connected to the battery charge control logic where it
reduces the charge voltage proportionally with battery temperature if it rises
above 25°C. The sensor is connected between X2 and X10 and should produce a
voltage in the region of 2.98Vdc between these points at 25°C.

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SECTION 9 - Battery Breaker Boxes 7200 Series UPS Service Manual
CHAPTER 5 - Battery Breaker Boxes

9-26 s8-c5.fm5 - Issue 2 Dated 21/08/97

 Section 9:

Chapter 6 - Input Harmonic Filters

6.1 General Introduction

An optional input harmonic filter can be added to the 7200 series UPS to improve
the UPS input power factor and reduce the amount of electrical noise reflected
into the input three phase supply.
The filter components are contained within the UPS cabinet therefore extra cool-
ing is required (see Figure 9-15). The filters are matched to the UPS capacity, re-
sulting in different part numbers for each system as follows:
30kVA filter 4641015 P
40 kVA filter 4641016 Q
60kVA filter 4641017 R

6.1.1 Specification

Input voltage 380-400-415, three phase

Input voltage tolerance ±15%
Nominal frequency 50Hz
Input frequency tolerance ±5%
UPS input current distortion 10% max
UPS input power factor >0.9

6.1.2 Notes on connection

This option is normally factory fitted with the harmonic filter becoming an inte-
gral part of the UPS as shown in the block diagram Figure 9-14 and the compo-
nent location diagram Figure 9-15. Therefore, connection of the input power
supplies does not change from that shown in section 2 Figure 2-5.
Note:- The input Neutral connection must always be connected to the bypass
input ‘N3' on the UPS.

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SECTION 9 - Optional Equipment 7200 Series UPS Service Manual
CHAPTER 6 - Input Harmonic Filters

Figure 9-14: Block diagram of Input Filter and UPS

Q3 Maintenance Bypass Power Switch
Q2 Bypass Power Switch
ac input
L5
supplies Q1 RECTIFIER INVERTER STATIC
SWITCH
Rectifier
Input Power
Switch L6

C21 BATTERY
to
C29
Optional Input
Harmonic Filter

40/60kVA units 30kVA units

E8 E7 E1 E4 E1
additional fan additional fan
connections connections

Figure 9-15: Harmonic Filter Component Part Locations

REAR VIEW TOP VIEW - Section A-A

f e d c

h g C29 C26 C23

A A
L6 L5
C28 C25 C22

C27 C24 C21

b a

L6 L6

h g

Fan Identifier from Diagram

T1 L1 Model
a b c d e f g h

30kVA E1 - - - E2 E3 E4 -

40kVA E1 E2 E3 E4 E5 E6 E7 E8

60kVA E1 E2 E3 E4 E6 E6 E7 E8

Fans (g) and (h) are additional when the

input harmonic filter is added.

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 Section 9:

Chapter 7 - RS232 Comms Kit 4645101T

The RS-232 Communications kit offers the necessary cable assembly and fixings
for connection into the communications socket (X8) on the operator logic board
(part no. 4550005F) to a DB25 male connector (X4), located adjacent to the cable
access panel as shown in Figure 9-16.
Using the wiring configurations shown in Figure 9-17 the UPS can be connected
to either a personal computer or a modem.
Additional software will be required to gain maximum advantage from the fea-
tures offered.

Caution Note:-The communications wiring for this option must be kept separate from the
power wiring. This is to maintain the integrity of ‘Safety Extra Low Voltage'
(S.E.L.V.) circuits.

Figure 9-16: Installing the RS232 communication cable

W9

4550005F

X5 X8 X4

4645101T

X4

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SECTION 9 - Optional Equipment 7200 Series UPS Service Manual
CHAPTER 7 - RS232 Comms Kit 4645101T

Figure 9-17: RS232 connections to PC or Modem

DB25M DB25F

1 1
A
TD 2 2
RD 3 3
RTS 4 4 Wiring details for
CTS 5 5 connection of UPS
to Modem via
DSR 6 6
DB25 socket.
GND 7 7
DCD 8 8
DTR 20 20
RI 22 22
X4
UPS MODEM

DB25M DB25F

1 B 1
TD 2 2 TD
RD 3 3 RD
RTS 4 4 RTS Wiring details for
5 CTS connection of
CTS 5
UPS to personal
DSR 6 6 DSR computer via
GND 7 7 GND DB25 socket.

DCD 8 8 DCD
DTR 20 20 DTR
RI 22 22 RI
X4
UPS PC
DB25M DB9F
C 1 DCD
1
TD 2 2 RD

RD 3 3 TD
Wiring details for
RTS 4 4 DTR connection of
UPS to personal
CTS 5 5 GND
computer via DB9
DSR 6 6 DSR socket.
GND 7 7 RTS
DCD 8 8 CTS
DTR 20 9 RI

RI 22
X4
PC
UPS

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7200 Series UPS Service Manual SECTION 9 - Optional Equipment
CHAPTER 7 - RS232 Comms Kit 4645101T

7.1 Hardware and Installation Requirements

1. Qty 1 Part Nº 4645101T Interface Option for ‘Master’ unit.
a) Fit the DB25 way Female connector to X8 of the operator logic PCB Part
Nº 4550005F. As shown in Figure 9-16.
2. IBM compatible PC for connection to the RS232 port X4 on the option PCB
Part Nº 4645101T.
Minimum specification:
a) Processor 386 or higher.
b) 512kB of RAM.
c) DOS version 3.1 or higher.
d) Windows 3.1 or Windows 95.
3. RS232 Cable to connect to the ‘D’ type 25 pin plug X4 on the option board
Part Nº 4645101T and the ‘D’ type 25 or 9 way plug PC Communication port,
as shown in Figure 9-17.

Note Each end of the cable will require ‘D’ type sockets. The maximum length is to be
no longer than 15 meters.

4. Associated installation software provided with the option kit Part Nº

4645101T on a 1.44 3.5” floppy diskette and user manual Part Nº 4645101T.
5. RS485 cables to interconnect each additional ‘Slave’ unit in a series string
with the ‘Master’ unit, via the 9 pin ‘D’ type plug X4 on each units operator
logic PCB Part Nº 4850005F. As shown in Figure 9-18.

Note The maximum number of UPS in the complete string must not exceed 8.

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SECTION 9 - Optional Equipment 7200 Series UPS Service Manual
CHAPTER 7 - RS232 Comms Kit 4645101T

Figure 9-18: Master Slave communication cable connections

UPS 3 Slave

RS485 cable
linking X4 to
UPS 2 Slave
X4 on next unit
Maximum of 8

UPS 1 Master

RS485 cable
linking X4 to X4

RS485 cable
linking X4 to X4

RS232 cable Max length=15meters

7.2 UPS Hardware and Software Configuration

7.2.1 Master UPS Set-Up

Hardware
1. Ensure that Link X26 7-8 on the UPS logic PCB Part Nº 4550007H is closed
to over-ride the password security system.
2. Ensure that Links X20 2-3; X21; X22; X25 1-2 are closed on the operator
logic PCB Part Nº 4550005F to enable the RS485 port X4 to communicate to
the Slave Units if required.

Software
1. Ensure that version 3.0 Software or better is installed on both the UPS logic
and Operator logic PCB’s, by checking the appropriate mimic screens.
2. Using the appropriate Mimic Panel buttons and ‘ FUNCTION’ menu map gain
access to the following windows and set as appropriate.

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CHAPTER 7 - RS232 Comms Kit 4645101T

a) ‘PC CONN’ – Select ‘LOCAL’ and press ‘ENTER’.

b) ‘RESET’ – Select ‘YES’ and press ‘ENTER’.
c) ‘UPS TYPE’ – Select ‘MASTER’ and press ‘ENTER’.
d) ‘GROUP’ – Select ‘1’ and press ‘ENTER’.
e) ‘UPS’ – Select ‘1’ and press ‘ENTER’.
3. Return to the main menu by pressing ‘ESCAPE’.
4. If required remove Link X26 7-8 to re-enable the password security system.

7.2.2 Slave UPS Set-Up

Hardware
1. Ensure that Link X26 7-8 on the UPS logic PCB Part Nº 4550007H is closed
to over-ride the password security system.
2. Ensure that Links X20 2-3; X21; X22; X25 1-2 are closed on the operator
logic PCB Part Nº 4550005F to enable the RS485 port X4 to communicate to
the Slave Units if required.

Software
1. Ensure that version 3.0 Software or better is installed on both the UPS logic
and Operator logic PCB’s, by checking the appropriate mimic screens.
2. Using the appropriate Mimic Panel buttons and ‘ FUNCTION’ menu map gain
access to the following windows and set as appropriate.
a) ‘PC CONN’ – Select ‘LOCAL’ and press ‘ENTER’.
b) ‘RESET’ – Select ‘YES’ and press ‘ENTER’.
c) ‘UPS TYPE’ – Select ‘SLAVE’ and press ‘ENTER’.
d) ‘GROUP’ – Select ‘1’ and press ‘ENTER’.
e) ‘UPS’ – Select ‘2’ for the second unit and press ‘ENTER’.
f) ‘UPS’ – Select ‘3’ for the second unit and press ‘ENTER’.
g) Repeat steps e) and f) for each additional slave unit as require, selecting
number ‘2’ to ‘8’ up to a maximum of 8 units.
3. Return to the main menu by repeatedly pressing ‘ ESCAPE’.
4. If required remove Link X26 7-8 to re-enable the password security system.

7.2.3 Installing the Software program

1. Start the PC as normal and switch to the DOS operating system.
The DOS prompt will show C:\> (indicating that the root directory of the hard
drive has been selected)
2. Insert the operating software floppy diskette supplied with the option kit into
the PC 3.5” drive.
3. Access the floppy drive by typing A: at the C:\> DOS prompt and pressing
‘ENTER’ ↵.

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SECTION 9 - Optional Equipment 7200 Series UPS Service Manual
CHAPTER 7 - RS232 Comms Kit 4645101T

4. Install the 7200 software by typing the following at the DOS prompt.
A:\>installa C: C: /E ↵

A:\> installa C: C: /E

A drive command space Target drive space Driver letter space Enter upper case letter
DOS letter for containing the for language selection.
prompt Note: this installation [Link] D = German
is an Ital- file normally C: I = Italian
ian com- E = English
mand F = French
S = Spanish

5. The attention message screen shown in Figure 9-19 will be displayed.

6. Follow the instructions on the screen to either:
a) Continue the installation by pressing any key.
b) Or exit the installation by pressing ‘CONTROL C’

Figure 9-19: Installation attention screen

!!! Attention!!!

If necessary the following directory is created:

C:\AL30\

If the environment is already present, all old files there are destroyed except:

C:\AL30\ [Link]

C:\AL30\[Link]

That remain unchanged

In order to use in future the default filters present on floppy disk, is sufficient over-
write them on the hard disk in the directory C:\AL30

The database file [Link], isn’t modified

Press key CTRL C for finish or any key to continue

Press any key to continue...

7. When the software installation has been successfully installed the PC will
give the following message shown in Figure 9-20.

Figure 9-20: Installation successfully completed

ALAMO30 V_3.0 1996

∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
∗∗∗∗ Installation completed ∗∗∗∗
∗∗∗∗ Thank you for your choice by Emerson SICE ∗∗∗∗
∗∗∗∗ Restart the system in order to use the programme∗∗∗
∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗

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7200 Series UPS Service Manual SECTION 9 - Optional Equipment
CHAPTER 7 - RS232 Comms Kit 4645101T

After the software has been successfully installed the directory C:\AL30\ will be
created on the selected drive, and will contain the following files.
[Link] [Link] [Link] [Link]
[Link] [Link] [Link] [Link]
[Link] [Link] [Link] [Link]
[Link] [Link] [Link] [Link]

7.2.4 Running the Software

The program can now be accessed by running the ‘[Link]’(for local PC con-
nection) or ‘[Link]’ (for remote PC connection) executable files, from the
new directory C:\AL30.
1. Enter the directory C:\AL30. by typing CD AL30 at the DOS prompt.
e.g. C:\>CD AL30
2. Run the programme by entering the remote or local execute command at the
DOS prompt
e.g. C:\AL30>[Link] and pressing ‘ENTER’ ↵.
or C:\AL30>[Link] and pressing ‘ENTER’ ↵.
3. The PC will now display the message shown in Figure 9-21 indicating that
the programme is running.

Figure 9-21: Software program active indication message

Information UPS 123776

About
LIEBERT - - UPS Network
Local Connection
Version 3.0 _ 1996

OK

4. Press ‘ENTER’ ↵.
The PC will then set up the communication to the UPS units and indicate that
there is a transmission in progress with a bargraph prompt on the display. As
shown in Figure 9-22.

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SECTION 9 - Optional Equipment 7200 Series UPS Service Manual
CHAPTER 7 - RS232 Comms Kit 4645101T

Figure 9-22: Transmission executing bargraph

Information UPS 123776

Information

Transmission executing Wait

5. At the end of the transmission the PC will return to the default screen and
indicate all the measured parameters.
An example of a typical UPS interrogation is shown in Figure 9-23.

Figure 9-23: UPS default screen showing typical measured parameters

Information UPS
General Window
<>
Node UPS1 UPS2 UPS3 UPS4 UPS5 UPS6 UPS7 UPS8
V out AB [V] 230 ---- ---- ---- ---- ---- ---- ----
V out BC [V] 230 ---- ---- ---- ---- ---- ---- ----
V out CA [V] 230 ---- ---- ---- ---- ---- ---- ----
V out AN [V] 0000 ---- ---- ---- ---- ---- ---- ----
V out BN [V] 0000 ---- ---- ---- ---- ---- ---- ----
I out A [A] 0000 ---- ---- ---- ---- ---- ---- ----
I out B [A] 0000 ---- ---- ---- ---- ---- ---- ----
I out C [A] 0000 ---- ---- ---- ---- ---- ---- ----
I out N [A] 0000 ---- ---- ---- ---- ---- ---- ----
Pot. A [kW] 0000 ---- ---- ---- ---- ---- ---- ----
Pot. B [kW] 0000 ---- ---- ---- ---- ---- ---- ----
Pot. C [kW] 0000 ---- ---- ---- ---- ---- ---- ----
Fin [Hz] 50.4 ---- ---- ---- ---- ---- ---- ----

mode configuration
U1 : M1V03.0 - V03.0 U2 : NC U3 : NC U4 : NC
U5 : NC U6 : NC U7 : NC U8 : NC

F10: Exit PgUp/Dn: Scroll measures <->: Sel UPS Enter: Receive configuration Tab: UPS

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7200 Series UPS Service Manual SECTION 9 - Optional Equipment
CHAPTER 7 - RS232 Comms Kit 4645101T

7.2.5 Accessing the Data

The information displayed in the default window Figure 9-23 is dependent on the
number of groups and individual UPS connected to the interface, it will vary ac-
cording to the site configuration.
The UPS parameters are shown in the General Window and can be scrolled using
the Key board commands outlined below.
The mode configuration window will display a coded number which indicates the
UPS detail. The coded number can be interpreted as follows:

M 1 V03.0 - V03.0

M or S = Master or Slave
1 = Number of the UPS group
Vxx-Vyy = Software Version for Operator Panel - UPS logic PCB.
N.C = Not Connected

Information in the display window can be changed from the keyboard using the
following commands:
a) F10
Allows the operator to ‘EXIT’ the communication software and return to the
AL30 directory DOS prompt c\AL30\>
b) PgUp/Dn
Operation of the page up and page down keys will scroll through the
parameters shown in the ‘General Window’.
c) <-> (Space Bar)
Operation of the space bar steps through each UPS shown in the ‘mode
configuration’ window.
d) ENTER ↵
Operation of the ‘ENTER' key will initiate an interrogation of the unit
selected. The transmission in progress bargraph will appear, as the Soft-
ware down loads the relevant data.
The display will then return to the ‘Main Interrogation Menu’ shown in
Figure 9-24.
e) Tab
Operating the Tab key allows the UPS group to be selected.
Up to nine groups each a maximum of eight units can be supported.

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SECTION 9 - Optional Equipment 7200 Series UPS Service Manual
CHAPTER 7 - RS232 Comms Kit 4645101T

Figure 9-24: Main data interrogation menu screen

Information UPS

Alarm Status
Alarm History
Event History
Programmable Parameters
Programmable Alarms
Control Commands
Modem Programming

mode configuration
U1 : M1V03.0 - V03.0 U2 : NC U3 : NC U4 : NC
U5 : NC U6 : NC U7 : NC U8 : NC

Esc: Back Up/Dn Arrow: Chose from menu Enter: Excecute

Once an interrogation of the UPS system has been carried out the menu screen
shown in Figure 9-24 will be displayed. Access to the many data information
screens can now be made from the keyboard:
a) Esc
Return back to the ‘Default Measurment’ screen.
b) Up/Dn Arrow
Operation of the ‘UP’ and ‘DOWN’ arrow keys allows selection of the data
to be viewed from the choice menu.
c) ENTER ↵
Operating the ‘ENTER’ key will execute the choice made with the up and
down arrows.

9-38 S8-c7.fm5 - Issue 2 Dated 21/08/97

 Section 10: Scheduled Maintenance

Chapter 1 - Scheduled Maintenance

1.1 Introduction ............................................................................................ 10-1
1.2 Safety Precautions .................................................................................. 10-1
1.3 Scheduled Maintenance .......................................................................... 10-1
1.3.1 Daily checks ............................................................................... 10-1
1.3.2 Weekly checks ........................................................................... 10-2
1.3.3 Annual service ........................................................................... 10-2
1.3.4 Extended service ........................................................................ 10-3
1.3.5 Battery maintenance ................................................................... 10-3
1.4 UPS Operating status and working parameters ...................................... 10-3

S-9.FM5 - Issue 2 Dated 21/08/97 i

SECTION 10 - Scheduled Maintenance 7200 Series UPS Service Manual

ii S-9.FM5 - Issue 2 Dated 21/08/97

 Section 10:

Chapter 1 - Scheduled Maintenance

1.1 Introduction
This section contains the procedures necessary to effect general maintenance of
the UPS module and battery. Certain procedures entail gaining internal access to
the UPS, and should be undertaken only by a competent engineer who is familiar
with the operation and layout of the equipment and understands the areas of po-
tential hazard. If you have any doubts concerning safety or the method of carrying
out any procedure then contact an approved service agent for assistance or advice.
If the locally approved agent is not known to you, then you should contact the
Customer Services & Support department at the address shown at the front of this
manual. The manufacturer offers customer training, at a nominal fee, if required.
Such training can range from a one-day operator course to in-depth training on
maintenance and troubleshooting lasting several days, and can be carried out at
the manufacturer's plant or at the customer premises.

1.2 Safety Precautions

When working on the UPS remember that the equipment contains live voltages at
ALL TIMES unless it is externally isolated from the mains supply, bypass supply
and batteries. It is essential that the safety and precautionary notes contained
throughout this manual are read and FULLY UNDERSTOOD before touching
any UPS internal component part.

1.3 Scheduled Maintenance

The UPS utilises solid-state components which are not subject to wear, with the
only moving parts being the cooling fans. Scheduled maintenance requirements,
beyond ensuring that the environmental conditions remain suitably cool and
clean, are therefore minimal. However, a well documented periodic program of
inspection and preventive maintenance, as suggested below, will help to ensure
optimum equipment performance and may serve to detect certain minor malfunc-
tions prior to them developing into a major fault. To monitor the various param-
eters follow the instructions provided in paragraph 1.4.

1.3.1 Daily checks

Carry out a daily walk-by inspection of the UPS, checking the following points:
1. Carry out a spot check of the Operator Control Panel; ensuring that all mimic
LED indications are normal, all metered parameters are normal and no warn-
ing or alarm messages are present on the display panel.
2. Check for obvious signs of overheating.
3. Check for continuous exit air flow from the extractor fans.
4. Listen for any noticeable change in audible noise.
5. Ensure that the ventilation grills around the UPS are unobstructed.
6. If possible, log the results of the inspection, noting any discrepancies from the
norm.

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SECTION 10 - Scheduled Maintenance 7200 Series UPS Service Manual
CHAPTER 1 - Maintenance Procedures

1.3.2 Weekly checks

Perform the following checks from the Operator Control Panel and log the results:
1. Measure and record the battery charge voltage.
2. Measure and record the battery charge current.
3. Measure and record the UPS output voltage on all three phases.
4. Record the temperature values indicated in the appropriate menu screens.
5. Measure and record the UPS output line currents.
If these are significantly different from the values previously logged then, if
possible, record the size, type and location of any additional load connected
to the UPS supply since the previous inspection. This type of information
could prove useful to the troubleshooting engineer should a problem occur.
6. If any of the above indications differ greatly from the previously logged val-
ues for no apparent reason you should contact the Customer Service & Sup-
port Department at the address given at the front of this manual for advice.

1.3.3 Annual service

The equipment should be thoroughly cleaned and the following checks carried out
annually. This entails working inside the equipment in regions containing hazard-
ous voltages.
We strongly recommend that the annual service is carried out by a manufacturer-
trained engineer who is fully aware of the hazards concerned and will carry out
this procedure with the load connected to the maintenance bypass supply.
If an untrained customer decides to carry out this service procedure it is impera-
tive that the UPS is totally shut down and isolated from the input mains supply,
bypass supplies and batteries.
1. Carry out the weekly checks detailed above.
2. Shut down the UPS following the recommended operating procedure.
3. Isolate the UPS input mains supply externally (also the bypass supply if a
split bypass system is in use) and isolate the battery.
4. Ensure that the UPS is totally powered down by checking for voltage at the
rectifier input connections (U1, V1 & W1), the battery connection terminals,
the output connections (U2, V2 & W2) and the bypass input connections (U3,
V3 & W3).
5. Gain access to the UPS interior by opening its internal hinged safety panel.
6. Carry out a thorough examination of the UPS power components and sub-
assemblies, paying particular attention to the following:
Electrolytic capacitors – check for signs of leakage, buckling etc.
Magnetic components – check for signs of overheating, security of fixture and
delamination.
Cables and connections – check cables for chaffing, fraying and signs of
overheating. Check that all printed circuit board connectors are secure.
Printed circuit boards – check the cleanliness and integrity of the circuit
boards and replace if any signs of deterioration are found.
7. Thoroughly clean inside the equipment enclosure using a vacuum cleaner and
low pressure air to remove any foreign debris.

10-2 s9-c1.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual SECTION 10 - Scheduled Maintenance
CHAPTER 1 - Maintenance Procedures

8. Reconnect the UPS input mains power.

9. Start the UPS and transfer the load to the inverter following the appropriate
operating procedure.
[Link] possible, carry out a battery check (See section 2 paragraph 2.5.4). Ensure
that the available battery autonomy time meets the installation specifications.

1.3.4 Extended service

We recommend that ALL the input/output power cables and their connections are
checked periodically. As this requires the UPS to be completely shut down such
a check should be carried out on an ‘opportunity' basis but at an interval not ex-
ceeding 2 years.

1.3.5 Battery maintenance

The batteries used with the UPS are generally of a sealed, ‘valve-regulated’ type,
and the only maintenance requirement is to ensure that the cells are kept clean and
dry. Maintenance procedures appropriate to both ‘valve-regulated’ and ‘non-
sealed’ batteries vary, and should be obtained from the battery manufacturer.

1.4 UPS Operating status and working parameters

The UPS operating status and working parameters are displayed on the Operator
Control Panel LCD screen. and can be accessed by selecting the appropriate menu
path from the default screen as illustrated in Figure 10-1.

NORMAL OPERATION

11.16.10 01.01.96
Default
Screen

From the default screen press ENTER to display the main menu screen:

> MEASUREMENT <

FUNCTION
Main menu
MAINTENANCE Screen
SETUP

With the cursor aligned with ‘MEASUREMENT’, press ENTER once again.
Note: The FUNCTION, MAINTENANCE and SETUP menu options are accessible
only with a password and are not required for general maintenance procedures.

OUTPUT

INPUT

BATTERY
Measurement menu
> TEMPERATURE < Screen

With reference to Figure 10-1, using the DOWN and ENTER buttons enable all the
monitored parameters to be viewed at the LCD display panel. For example to
view the system temperatures press the DOWN button until the cursors are oppo-

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SECTION 10 - Scheduled Maintenance 7200 Series UPS Service Manual
CHAPTER 1 - Maintenance Procedures

site TEMPERATURE then press the ENTER to display the TEMPERATURE screen
shown below – where:

TEMPERATURE [c]

Tt +27,4 To +25,4

Ta +22,6 Tb +20,7

Tt is transformer temperature
To is UPS cabinet out-going ambient air temperature;
Ta is UPS cabinet incoming ambient temperature;
Tb is battery cabinet ambient temperature.

Figure 10-1: Parameter access menu map (Issue 5.0 software)

MAIN MENU SCREEN DEFAULT SCREEN

=51CEB5=5>D
6E>3D9?> >?B=1<ð?@5B1D9?>
=19>D5>1>35
C5DE@ !!â!&â! ð !â !â)&

?ED@ED F?<D175 ?ED@ED* ?ED@ED*

9>@ED 3EBB5>D F?<D175ðððððKFb]cM F?<D175ðððððKFb]cM
21DD5BI @?G5B <!ã<"ð<"ã<#ð<#ã<! <!ã>ððð<"ã>ððð<#ã>
D5=@5B1DEB5 6B5AE5>3I ^^^ðððð^^^ðððð^^^ ^^^ðððð^^^ðððð^^^

MEASUREMENT
MENU SCREEN 3EBB5>D*ðððððK1b]cM <?14*ðððððððððKëM
ðð<!ðððð<"ððððð<# ðð<!ðððð<"ðððð<#
ð^^^^ðð^^^^ððð^^^^ ðð^^^ððð^^^ððð^^^
ðð>ðððð^^^^ ððð

B51<ð@?G5B*ððððK[GM 1@@âð@?G5B*ðððK[F1M
ðð<!ððððð<"ððððð<# ðð<!ðððð<"ðððð<#
å^^^^ððå^^^^ððå^^^^ð ð^^^^ðð^^^^ðð^^^^ð

6B5AE5>3I*ðððK8jM
9^fUbdUbððððð% ä
2i`Qccððððððð% ä

?ED@ED 9>@ED*
9>@ED F?<D175ðððððKFb]cM
21DD5BI <!ã<"ð<"ã<#ðð<#ã<!
D5=@5B1DEB5 ð^^^ððð^^^ðððð^^^

?ED@ED 21DD5BI*
9>@ED F?<D175ððððð^^^KFM
3EBB5>Dððððå^^^K1M
21DD5BI 381B75ðððððð! KëM
D5=@5B1DEB5

?ED@ED D5=@5B1DEB5*ððððKSM
9>@ED
21DD5BI Ddðå"'ä$ððD_ððå"%ä$
D5=@5B1DEB5 DQðå""ä&ððDRð
---#-

10-4 s9-c1.fm5 - Issue 2 Dated 21/08/97

 Section 11: Troubleshooting & Repair

Chapter 1 - Basic Troubleshooting Procedure

1.1 About Troubleshooting ........................................................................... 11-1
1.1.1 Introduction ................................................................................ 11-1
1.1.2 Troubleshooting aids .................................................................. 11-1
1.2 Basic troubleshooting (from Operator Control Panel metering) ............ 11-1
1.3 General troubleshooting procedure ........................................................ 11-2
1.3.1 Test equipment ........................................................................... 11-2

Chapter 2 - Fault diagnosis

2.1 Introduction ............................................................................................ 11-5
2.2 Interpreting the Operator Control Panel indications .............................. 11-5

Chapter 3 - Board Replacement & Calibration Procedures

3.1 Rectifier Logic Board replacement (Part Nº 4520074A) ..................... 11-27
3.2 Inverter Logic Board replacement (Part Nº 4530025T) ....................... 11-29
3.3 UPS Logic Board replacement (Part Nº 4550007H) ............................ 11-33
3.4 Operator Logic Board replacement (Part Nº 4550005F) ...................... 11-34
3.5 Static Switch Driver Board replacement (Part Nº 4542043Z) ............. 11-35
3.6 High Voltage Interface Board replacement (Part Nº 4590054O) ......... 11-36
3.7 DC – DC Power Supply Board replacement (Part Nº 4503028K) ....... 11-37
3.8 AC – DC Power Supply Board replacement (Part Nº 4503030M) ...... 11-38
3.9 Parallel Logic Board replacement (Part Nº 452007H) ......................... 11-39

Chapter 4 - Functional Check Procedures

4.1 Introduction .......................................................................................... 11-41
4.2 How to check the rectifier power components ..................................... 11-41
4.2.1 Short-circuit rectifier SCR ....................................................... 11-41
4.2.2 Open-circuit rectifier SCR ....................................................... 11-42
4.2.3 Shorted DC filter capacitor ...................................................... 11-42
4.2.4 Open-circuit DC filter capacitor .............................................. 11-43
4.3 How to check the inverter power components ..................................... 11-44
4.3.1 Short-circuit and Open-circuit IGBT ....................................... 11-44
4.3.2 How to check the inverter IGBTs ............................................ 11-45
4.3.3 Shorted AC filter capacitor checks .......................................... 11-47
4.3.4 Open-circuit AC filter capacitor checks .................................. 11-48
4.4 How to check the Static Bypass power components ............................ 11-49
4.4.1 Short-circuit bypass SCR checks ............................................. 11-49

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SECTION 11 - Troubleshooting & Repair 7200 Series UPS Service Manual

4.4.2 Open-circuit bypass SCR ......................................................... 11-50

4.4.3 Output contactor failure ........................................................... 11-51

ii S-10.FM5 - Issue 2 Dated 21/08/97

 Section 11:

Chapter 1 - Basic Troubleshooting Procedure

1.1 About Troubleshooting

1.1.1 Introduction
The UPS equipment contains complex electronic control circuits which require a
firm understanding, and often specialist microprocessor monitoring test equip-
ment, in order to carry out comprehensive fault diagnosis and repair. The trouble-
shooting information contained in this chapter therefore aims to provide sufficient
guidance to assist a trained engineer to locate and replace a faulty major compo-
nent, or printed circuit board. All faulty circuit boards should be returned to the
nearest service centre for repair.

1.1.2 Troubleshooting aids

The UPS contains numerous indicators to assist in fault diagnosis. These take the
form of:
• Operator Control Panel metering –
provides indication of battery (DC Bus) voltage and charge/discharge cur-
rent; and output voltage, current and frequency.
• Operator Control alarm messages –
provides various alarm and status information.
• Operator Control module status leds –
provides an indication of the operational status of the module isolators and
functionality of the major assemblies.
• Circuit board mounted leds –
indicates the status of various internal control logic signals

CAUTION It is necessary to gain internal access to the UPS to observe circuit board mount-
ed indicators; this should be undertaken only by trained personnel.

1.2 Basic troubleshooting (from Operator Control Panel metering)

Most UPS problems do not emerge as a gradual performance degradation; gener-
ally the UPS either works correctly or it will shut down - and transfer the load to
the bypass supply if applicable. However, it is important to maintain a regular
record of the UPS meter indications, as suggested in the maintenance instructions,
in order that any change in the system or load characteristics are readily identified.
In general, the output voltage on all three phases should be within 2% of nominal,
and the output line currents should not normally differ by more than 20%. If a
greater difference is noted, the load is likely to be unbalanced and should be re-
distributed more equally if possible.
Where the UPS has not operated on battery power within the previous ten hours
the battery charge current should typically be less than 10A.
If any meter indication differs significantly from normal the cause should be in-
vestigated.

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SECTION 11 - Troubleshooting 7200 Series UPS Service Manual
CHAPTER 1 - Basic Troubleshooting Procedure

Information concerning prevailing load conditions can prove useful when dis-
cussing problems with the service agent: for example, details of any particular
load being started or shed at the time of the fault occurrence.

1.3 General troubleshooting procedure

Troubleshooting should be carried out methodically along the following guide-
lines:

Fault Identification
When first summoned to the scene of a UPS fault, the immediate action should be
to observe and record the Operator Control Panel status and alarm messages, led
indications, meter indications and power isolator switch configuration. This
should be completed before touching ANY switch.

Corrective Action
When the mimic panel leds and meter indications have been noted, the next step
is to determine whether any led condition is abnormal. If an abnormal indication
exists then refer to the troubleshooting charts - beginning at the ‘TOP LEVEL’
chart.
If the mimic panel messages and led indications appear normal, but the meter dis-
play shows one or more of the operating parameters to be incorrect (for example,
incorrect output voltage), then refer to the ‘calibration procedures’ and carry out
the appropriate PCB adjustment.
If the mimic panel messages, led and meter indications all appear normal but a
problem still exists (for example the UPS is emitting unusual noises), then contact
the nearest service centre for advice or assistance.

Fault Reporting
Irrespective of whether fault rectification is successful or not, please report all
fault occurrences to the nearest service centre who will then forward details to the
manufacturer. This type of ‘user’ feedback is an important factor in maintaining
high product reliability.

1.3.1 Test equipment

As mentioned above, some of the microprocessor-base control boards require
specialist test equipment to analyse on-board problems, and is unlikely to be
available during standard site troubleshooting exercises. In order to carry out gen-
eral troubleshooting to board-replacement level, and undertake the check proce-
dures contained later in this section, the following test equipment will be
required:-

Oscilloscope
A dual-beam oscilloscope is essential as is the ability to sum the two channels for
making differential voltage measurements. A storage facility is useful but not es-
sential.

DVM
The a.c. voltages quoted in the check procedures assume that a ‘true r.m.s.’ read-
ing a.c. voltmeter is used.

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7200 Series UPS Service Manual SECTION 11 - Troubleshooting
CHAPTER 1 - Basic Troubleshooting Procedure

Frequency meter
If a digital frequency meter is not available an oscilloscope may be used to meas-
ure waveform periods, although this is obviously less accurate.

Logic Probe
A general TTL / CMOS logic probe will be useful in detecting LF pulses etc.

Current meter
An AC/DC current meter is useful for checking internal current readings. Unbal-
anced, or incorrect, readings can assist in isolating faulty components and UPS
power section, and is especially useful for identifying faulty filter capacitors. An
appropriate current outlet to the oscilloscope is also beneficial.

WARNING Some of the instructions in the charts at the end of this chapter involve checking
internal fuses. This should be undertaken (after the equipment has been shut
down) only by a trained electrician who is familiar with the layout and operation of
the equipment and fully conversant with the areas of potential hazard.

Caution The following diagnostic charts are designed for 'first aid' trouble shooting only. If
a problem cannot be resolved by taking the actions given then fully trained assist-
ance should be sought immediately.
Do not under any circumstances make internal circuit adjustments or interfere
with the circuit boards in any other way.

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SECTION 11 - Troubleshooting 7200 Series UPS Service Manual
CHAPTER 1 - Basic Troubleshooting Procedure

11-4 S10-C1.FM5 - Issue 2 Dated 21/08/97

 Section 11:

Chapter 2 - Fault diagnosis

2.1 Introduction
This chapter provides information necessary for carrying out initial fault diagno-
sis through the correct interpretation of the Operator Control Panel LED indica-
tors and alarm messages.
Detailed troubleshooting charts are not provided at this stage; but appropriate
cross-references are made to the following text and procedures in order to further
trace the cause of an abnormal condition:
• Circuit board replacement procedures (chapter 3)
• Functional check procedures (chapter 3)
• Detailed circuit operation and adjustment information (earlier sections)

2.2 Interpreting the Operator Control Panel indications

LED Indicators
The Operator Control Panel LED indicators are shown in Figure 11-1 and de-
scribed in detail in Table 11-1, on the following page.

Figure 11-1: Operator Control Panel LED indications

1 2 3 4 5 6 7 8 9

Display panel message interpretation

The messages displayed on the 7200 can be categorised into two types:
a) ALARM messages - are messages which need urgent attention and warn
of a UPS shutdown or imminent shutdown - the load would normally
transfer to the bypass supply if it is available. All alarm messages are
accompanied by an audible warning.
b) WARNING messages - these are messages generated to warn or confirm
to the operator of actions taken (i.e. if the rectifier a.c. input supply power
switch was opened the Warning message would read - RECTIF. SWITCH
OPEN).
Table 11-2 lists the various messages displayed on the Operator Control Panel to-
gether with a description of their interpretation

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 .
11-6

CHAPTER 2 - Alarms & Indications

SECTION 11 - Troubleshooting
Table 11-1: Operator Control Panel LED indication (Sheet 1 of 2)

Item Normal
Interpretation Diagnostic - Action
Number State

1 ON If this green led is OFF it signifies a problem with the bypass input a.c. Check the following:
mains supply. a) Bypass input power switch Q2 is closed.
b) Input supply voltage is within 20% of nominal.
c) Power supply fuses are OK - LS1, LS2 on the a.c. Power Supply
board will extinguish if either fuse is ruptured.
If the above checks prove unsatisfactory then seek qualified assistance.

2 ON If this green led is OFF it signifies that the inverter is not producing its Check the following:
correct output voltage. a) If [OVER TEMPERATURE] OR [OVERLOAD] alarm messages
are active then (after allowing the UPS to cool, checking that the
load current on the bypass line is not excessive) press the reset
switch (S1) on the UPS Logic Board.
b) If the d.c. busbar is below 320V d.c. for 380 V a.c. system, 330V
d.c. for 400 V a.c. system or 340 V d.c. for a 415 V a.c. system
then do the checks as per ‘Rectifier Block'- input failure items
15,16,17 & 18 in Table 11-2.
c) If the inverter works OK when mains is available but not when
mains is unavailable then check the battery power fuse F13.
If the above checks prove unsatisfactory then seek qualified assistance.
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7200 Series UPS Service Manual

3 OFF If this yellow led is ON (flashing) then it signifies that the load has been If this is an automatic change over it will be accompanied by a fault
transferred to the static bypass supply. warning on the display panel, take the appropriate actions for the display
indication (See Table 11-2).

4 OFF If this yellow led is on it signifies that the battery is not available. This Check the following:
could be due either to, the battery circuit breaker being open or that the a) Battery circuit breaker is closed.
d.c. busbar voltage is below the figures stated in (2) above. b) DC busbar voltage - if not above 320V then carry out checks as
The battery circuit breaker will open automatically if the d.c. voltage falls per 1 (mains failure) above. If the d.c. busbar voltage is greater
below these levels. than 320V but you are unable to close the battery circuit breaker
then seek qualified assistance.
Continuously ON = DC undervoltage c) If the battery circuit breaker trips as soon as mains power is dis-
Flashing = CBB open or Battery fuse failure connected then check the battery power fuse (F13).
 Table 11-1: Operator Control Panel LED indication (Continued) (Sheet 2 of 2)
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7200 Series UPS Service Manual

Item Normal
Interpretation Diagnostic - Action
Number State

5 N/A This is a bar graph indicating the% of the total load that is being applied None
to the system. Under normal running conditions several of these LEDs
would be ON – i.e. the LEDs indicate in 20% steps the current drawn
from the greatest loaded phase.

6 N/A This is a bar graph indicating the battery charge state and would nor- During battery charge, examine the % Battery Charge state using the
mally have four or five of the LEDs ON. When the unit runs on battery, MEASURMENT menu on the Operator Control Panel. The number of
this bargraph changes to give an indication of the time remaining on bat- illuminated segments should approximate to the displayed valued.
tery as a percentage of the total autonomy time.
When charging, each segment indicates 20% available capacity. When During battery discharge, the “autonomy time” remaining should auto-
discharging each segment indicates 2 minutes autonomy remaining – matically be displayed on the DEFAULT menu screen
with all 5 segments being illuminated if the autonomy time is above
10minutes.

7 OFF If this yellow led is ON it signifies that the applied load has exceeded the Reduce the load immediately.
maximum. It will be accompanied by all five load bargraph LEDs being The overload algorithm follows an inverse time/load characteristic and, if
ON (item 5), the Alarm warning indication flashing RED (item 9) and an exceeded, the load is transferred to the bypass and the overload latch is
OVERLOAD message on the visual display. This will be accompanied by triggered. Reset the latch by means of the RESET switch on the UPS
an audible warning. Logic Board.

CHAPTER 2 - Alarms & Indications

8 OFF If this yellow led is ON it signifies that the battery voltage is low and that
the end of battery discharge is near (normally two minutes). This will be

SECTION 11 - Troubleshooting
accompanied by an audible warning.

9 OFF This red LED indicates that the UPS has detected a fault, and will be
accompanied by a message on the display panel. Take the required
actions for the display panel message (See Table 11-2). This will be
accompanied by an audible warning.

Continuously ON = ALARM message

Flashing = WARNING message

Table 11-2: Alarm messages

11-7
11-8

CHAPTER 2 - Alarms & Indications

SECTION 11 - Troubleshooting
Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

01 [ NORMAL OPERATION ]
02 [ BYPASS SWITCH OPEN ] The state of the Circuit Breakers is sensed by monitoring their 1. If the indicated circuit breaker status does not agree with the
auxiliary contacts, which in all cases are closed when the true position then carry out a check of the auxiliary contact
03 [ OUTPUT SWITCH OPEN ] associated circuit breaker is closed. monitoring circuit and rectify as required.
04 [ RECTIF. SWITCH OPEN ]
The sense signal route passes from the circuit breakers, 2. If a fault is found on the HVIB then replace it – (see para-
05 [ BATTERY SWITCH OPEN ] through the HVIB (see paragraph 2.3.7 on page 7-8) , to the graph 3.6 on page 11-36).
UPSLB, where they are buffered by D2 (see paragraph
06 [ MANUAL BYPASS CLOSED ] [Link] on page 7-39) and D1 (see paragraph [Link] on 3. If the inputs are correct to the UPSLB buffers then replace
(maintenance bypass page 7-40). the UPSLB – (see paragraph 3.3 on page 11-33).
breaker closed) The resulting digital sense signals are processed by the micro
which then passes the alarm data to the Operator Logic Board
and then on to the LCD Display.

NOTES:

If [#02] is active it disables [#10], [#11], [#12], [#13] and [#16]

If [#04] is active it disables [#22]
If [#05] is active it disables [#52], [#53], [#56], & initiates the
mimic display battery fault LED4 to flash
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7200 Series UPS Service Manual

s10-c2.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual

Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

10 [ BYP: ABSENT ] These alarms are enabled only if the bypass circuit breaker is 1. First verify that the bypass voltage presented to the module
(bypass supply <50Vac) closed (see alarm #2) and indicates a voltage error on the is within the selected voltage range, and rectify the external
bypass supply. supply if it is found to be faulty.
11 [ BYP: OVERVOLTAGE ]
(bypass supply over voltage) The alarms are triggered by a bypass voltage monitoring func- 2. Verify that the input MAX. and MIN values programmed in
tion of the UPSLB’s micro (see paragraph [Link] on page 7- the SETUP/VOLTAGE menu screen are appropriate and re-
12 [ BYP: UNDERVOLTAGE ]
59) which senses the three-phase bypass supply via buffered program if necessary.
(bypass supply under voltage)
attenuators the HVIB (see paragraph 2.3.6 on page 7-8).
3. If step 1 & 2 are OK then measure the sense signals to the
The alarm thresholds are programmable via the SETUP/ UPSLB. If these are correct then replace the UPSLB (see par-
VOLTAGE menu screen (+10% -15% default setting) (see par- agraph 3.3 on page 11-33); if the monitored voltages are incor-
agraph 2.4.5 on page 2-33). rect then check the wiring/connections to HVIB and if this is
correct then replace the HVIB (see paragraph 3.6 on page 11-
In addition to controlling these alarms, the monitoring function 36).
also controls the “bypass supply” LED (green) on the mimic
display.

13 [ BYP: FREQUENCY ERROR ] This alarm is triggered by a bypass frequency monitoring func- 1. First verify that the bypass voltage presented to the module
(bypass supply is tion of the UPSLB’s micro (see paragraph 3.3.13 on page 7- is within the selected frequency range.
over/under freq) 55) which senses the bypass supply R-phase via the same sig-
nals used by the Input Voltage monitoring alarms described in 2. Verify that the SYNC WINDOW value programmed in the
alarms #10 - #12 above (see page 7-59). SETUP/FREQUENCY menu screen is appropriate and re-

CHAPTER 2 - Alarms & Indications

program if necessary.
The alarm window threshold is programmable via the SETUP/

SECTION 11 - Troubleshooting
FREQUENCY menu screen (±2% default setting) 3. If step 1 & 2 are OK then measure the R-phase sense signal
(see paragraph 2.4.5 on page 2-33). to the UPSLB. If this is correct then replace the UPSLB (see
paragraph 3.3 on page 11-33); if the monitored voltage is
In addition to controlling the alarm, the monitoring function also incorrect then check wiring/connections to HVIB and if this is
controls the “bypass supply” LED (green) on the mimic display. correct replace the HVIB (see paragraph 3.6 on page 11-36).

The alarm is disabled if the bypass supply isolator is opened.

11-9
11-10

CHAPTER 2 - Alarms & Indications

SECTION 11 - Troubleshooting
Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

14 [ BYP: PHASE ROT. ERROR ] This alarm is triggered by a detection circuit on the UPSLB 1. First verify that the rotation of the bypass supply presented
(bypass phase rotation error) which monitors the R and S phase bypass voltages and sig- to the module is correct, and rectify if found to be in error.
nals an error to the micro control system (see page 7-60). The
sensed voltages are the same as those used by the Input Volt- 2. check for cross-wiring of R & S on the HVIB connector X6.
age monitoring alarms (see page 7-59).
3. If the R-phase or S-phase sense signal to the UPSLB is
The alarm threshold is fixed by component values. missing there will be other active alarms concerning the
bypass voltage. If no such alarm is present then the problem is
In addition to controlling the alarm, the monitoring function also with the UPSLB phase-rotation monitor circuit.
controls the “bypass supply” LED (green) on the mimic display.
4. Check-out the monitor circuit (see page 7-60) or replace the
This alarm also enables alarm [#16]. UPSLB (see paragraph 3.3 on page 11-33).

15 [ BYP: SCR FAILURE ] This latched alarm is triggered by a detection circuit on the 1. Attempt to reset the alarm using S1 on the UPSLB.
(bypass scr open cct) UPSLB which monitors the voltage drop across the bypass 2. With the module shut-down (maintenance bypass). Check
SCRs (see page 7-31). It monitors both the 3-phase bypass the bypass SCR for open circuit ( (see paragraph 4.4 on page
voltage and UPS output voltage (see page 7-63). 11-49)). Also check the gate drive connections.
3. If the SCRs are OK then check the bypass voltage and out-
Analogue circuits on the UPSLB process the sense voltages put voltage sense inputs to UPSLB via the HVIB, and repair/
via attenuator circuits on the HVIB – (see paragraph 2.3.4 on replace as necessary.
page 7-7) and also (see paragraph 2.3.6 on page 7-8). 4. If the signals to the UPSLB are OK then replace the SSDB
(see paragraph 3.5 on page 11-35).
s10-c2.fm5 - Issue 2 Dated 21/08/97

16 [ BYP:HARDWARE BLOCK ] This alarm is triggered by i.c. D22 on the UPSLB (see para- 1. Check the following (any one instigates this alarm) and carry

7200 Series UPS Service Manual

(bypass supply blocked) graph 3.3.7 on page 7-29) which, via the micro, inhibits the out the associated rectification:
static bypass circuit (BLK_MNS) in response to the presence a) Manual inhibit switch S1 is open (OFF) on the UPSLB.
of various fault conditions. b) Emergency Stop active (alarm #63).
The alarm is inhibited when the bypass power isolator is open c) Open Bypass SCR (alarm #15).
– i.e. when [#02] is active. d) Incorrect bypass phase rotation (alarm #14).

When [#16] is active it disables [#17] 2. If no fault is found with the above checks then replace the
UPSLB (see paragraph 3.3 on page 11-33).
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7200 Series UPS Service Manual

Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

17 [ BYP:OFF VIA DISPLAY ] This alarm is triggered by the micro on the UPSLB when the 1. Verify that the bypass has not been selected off via the
(bypass blocked via operator Static Bypass has been inhibited manually, either from the FUNCTION/NEXT_PAGE/LINE menu screen – return the
menu) Operator Control Panel or remotely from the External Alarms selection to [ ON ] if required.
Interface Board (optional).
2. Verify that a remote “bypass inhibit” is not being applied via
This alarm is enabled only if [#16] is inactive. the Alarm Interface Board 4590055P

If this alarm is active it will also activate [#16] 3. If neither of the above is calling for the bypass inhibit then
replace the UPSLB (see paragraph 3.3 on page 11-33).

18 [ LOAD ON BYPASS ] This is a status alarm generated by the UPSLB’s micro when 1. Tend to any other active alarm that might be the cause of a
the load is transferred to the static bypass supply either inten- load transfer and rectify as necessary.
tionally or due to an inverter fault. It also causes the bypass led
(amber) on the mimic panel to be flashing. If ON continuously, 2. If no other fault alarm is present and the inverter is working
then the load is being held “on bypass” due to the UPS being correctly but the load has not automatically transferred back to
in the “manual retransfer” operating mode the inverter the UPSLB might be configured in the “manual
retransfer” mode – check the position of link X26 on the
UPLSB (See Table 7-8).

3. If no fault found then suspect faulty transfer control logic.

Replace the UPSLB (see paragraph 3.3 on page 11-33).

CHAPTER 2 - Alarms & Indications

19 [ BYP: OVERTEMPERATURE ] This alarm is triggered by the UPSLB’s micro in response to a If the alarm is active, check that link X11 on the Static Switch
(static bypass temperature monitoring thermostat on the Static Switch heat- Driver Board is made 1-2.

SECTION 11 - Troubleshooting
overtemperature) sink passed via the SSDB. This facility is not normally used.

Note: 1 minute after the alarm is activated the static bypass is

stopped and alarm[#62] is latched on.

20 [ RECT: SOFTWARE BLOCK ] This alarm is triggered by a UPSLB software routine con- Check the following conditions (any one of which instigates this
(software block via the micro) cerned with rectifier control, and is present when the input to alarm) and carry out the necessary rectification:
D23 pin 14 (REC-ON) is active (low) – (See Figure 7-7) and 1. Is the rectifier selected ON on the Operator Control Panel?
also (see page 7-33). This signal also triggers alarm #22. 2. Is the Rectifier Fuse Fail alarm [#25] active?
3. Is the Rectifier Block active on the RLB (e.g. H7 = Power
supply fail; H8 = Ph. rotation error; H9 = input undervolts)? (If
11-11

problem then check out RLB and replace if necessary).

4. Is H10 lit on RLB only? (If so then problem is on the UPSLB
- replace if necessary).
11-12

CHAPTER 2 - Alarms & Indications

SECTION 11 - Troubleshooting
Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

21 [ RECT: OFF VIA DISPL. ] This alarm is triggered by the micro on the UPSLB when the 1. Verify that the rectifier has not been selected off via the
(rectifier blocked via Rectifier has been inhibited manually, either from the Operator FUNCTION/NEXT_PAGE/RECTIFIER menu screen –
operator menu) Control Panel or remotely from the External Alarms Interface return the selection to [ ON ] if required.
Board (optional).
2. Verify that a remote “rectifier inhibit” is not being applied via
This alarm is disabled if alarm [#22] is active. the Alarms Interface Board 4590055P
If this alarm is active then alarm [#22] is blocked.
3. If neither of the above is calling for the rectifier inhibit then
replace the UPSLB (see paragraph 3.3 on page 11-33).

22 [ RECT: HARDWARE BLOCK ] This latched alarm is triggered by a UPSLB rectifier control 1. Check the following (any one instigates this alarm) and carry
(hardware block via the logic, and is present when the output from D23 pin 19 out the associated rectification:
UPSLB) (ON_REC) is in its “blocking” state (low) – (See Figure 7-7). a) Manual inhibit switch S3 is open (OFF) on the UPSLB.
This output is affected by several rectifier inhibit signals (see b) Emergency Stop active (alarm #63).
page 7-33). c) Fast/Slow DC Overvoltage (alarm #58 or #55).
d) Software rectifier inhibit (alarm #20).
This alarm is disabled if alarm [#21] is active. e) Circuit Board power supply failure
If this alarm is active then alarm [#21] is blocked.
2. If no fault is found with the above checks then replace the
UPSLB (see paragraph 3.3 on page 11-33).

23 [ RECT: CURRENT LIMIT ] This alarm is triggered by the UPSLB’s micro in response to an 1. If there is a genuine overload check out the rectifier SCRs,
(rectifier input current limit) input current limit fault signal generated on the RLB. The oper- DC filter caps, shorted battery, shorted inverter [Link] filter
s10-c2.fm5 - Issue 2 Dated 21/08/97

ating threshold is calibrated by R17 on the RLB and led H6 illu- capacitors (see paragraph 4.3.3 on page 11-47).

7200 Series UPS Service Manual

minates on the RLB when an overload is detected – (see
paragraph [Link] on page 4-29). 2. If no genuine overload but H6 is illuminated, check out/
replace RLB (see paragraph 3.1 on page 11-27).

3. If H6 is extinguished the problem is likely to be either the

RLB issuing an erroneous fault signal (see page 4-29) or the
UPSLB is faulty: repair/replace as necessary.
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7200 Series UPS Service Manual

Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

24 [ RECT: OVERTEMPERAT. ] This alarm is triggered by the UPSLB’s micro in response to a 1. A genuine overtemperature condition may be due to:
(rectifier overtemperature) temperature monitoring thermostat on the rectifier heatsink a) Increased ambient air temp.
passed via the RLB. The alarm can be overridden by fitting a b) Restricted cooling air flow.
jumper link to X10 pins 2-3 on the RLB. This facility is not nor- c) Prolonged rectifier overload under raised ambient temp.
mally used d) Fan failure.
Note: 1 minute after the alarm is activated the rectifier is 2. If not a genuine overtemp condition then check out wiring of
stopped and alarm[#62] is latched on. thermostats (n/c) through RGDBs and RLB to UPSLB.

25 [ RECT: FUSE FAIL ] This alarm is triggered by the UPSLB’s micro in response to a As a genuine fuse fail condition is not normally monitored, any
failure of a rectifier input fuse. This facility is reserved for larger activation of this alarm channel is usually caused by a “false”
UPS modules and is not normally used for modules up to alarm. If the alarm activates:
60kVA. When not used, the facility is disabled by fitting a a) check the signal path from the HVI X17 pins 1-2 to the
jumper link to X17 pins 1-2. UPSLB.
b) Replace the UPS Logic Board

30 [ INV: SOFTWARE BLOCK ] This alarm is triggered by the UPSLB’s software routine and is Check the following (any one of which instigates this alarm)
(software block via the micro) present when the input to D23 pin 6 [INV_ON> is active (low) and carry out any necessary rectification:
(See Chart 7-3).
a) Is the DC Bus is within its permissible range?
When this alarm is present is disables alarm #31 and enables b) Is the inverter selected ON on the Operator Control Panel?

CHAPTER 2 - Alarms & Indications

alarm #32. c) Is there an “inverter block” signal active on the Inverter Logic
Board (H11 = PCB power supply fail; H13 = Base drive lead

SECTION 11 - Troubleshooting
disconnected; H5-H10 = Desaturation detector active, investi-
gate reason on ILB.
d) Is H12 (only) lit on the ILB? If so then replace the UPSLB.
e) Are any “external blocks” being applied to the UPS?

31 [ INV: OFF VIA DISPLAY ] This alarm is triggered by the UPSLB when the inverter has 1. Verify that the inverter has not been selected OFF via the
(inverter blocked via operator been inhibited manually; either from the Operator Control FUNCTION/NEXT_PAGE/INVERTER menu screen – return
menu) Panel or remotely from the external Alarms Interface Board. the selection to [ON] if required.

This alarm is disabled if alarm #30 is active. 2. Verify that a remote inhibit is not being applied via the
Alarms Interface board (See Section 9 Chapter 1).
11-13

3. If neither of the above are commanding the inverter OFF

then replace the UPSLB.
11-14

CHAPTER 2 - Alarms & Indications

SECTION 11 - Troubleshooting
Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

32 [ INV: HARDWARE BLOCK ] This alarm is triggered by the UPSLB inverter control logic and Check the following (any one of which instigates this alarm)
(hardware block via UPSLB) is present when the output from D23 pin 15 [ON_INV> is in its and carry out any necessary rectification:
blocking state (low) This output is affected by several inverter a) Is the manual inhibit switch (S2) open (OFF) on the UPSLB?
inhibit signals (see paragraph 3.3.7 on page 7-29). b) Is the Emergency Stop line active (alarm #63)?
c) Is the Fast/Slow Overvolts alarm active (alarms #58 & #55)?
This alarm is disabled if alarm #31 is active. d) Is the software calling for an inverter inhibit (alarm #30)?
e) Has the PCB power supply failed?

33 [ INV: CURRENT LIMIT ] This alarm is triggered by the UPSLB’s micro in response to an 1. Check for a genuine reason for the fault indication by exam-
(inverter current limit) inverter >150% current limit fault signal generated on the ILB. ining for shorts/burns etc. in the:
The operating threshold is calibrated by R246 on the ILB and a) output transformer and associated cabling.
LED H14 illuminates on the ILB when the threshold has been b) output filter capacitors and associated wiring.
exceeded, and the current limit is therefore active. c) inverter power stacks and associated cabling.

Note: the IGBT PWM pattern is limited appropriately to reduce 2. If no reason for genuine alarm is apparent then:
the inverter output voltage. This may lead to an increase in a) if H14 is illuminated on the ILB determine the cause of the
pulsed current in the output transformer which causes an erroneous overload detection and repair/replace as necessary.
increased audible noise. b) if H14 is extinguished then replace the UPSLB.

34 [ INV: OVERTEMPERATURE ] This alarm is triggered by the UPSLB’s micro in response to 1. If overtemperature is genuine then check for and rectify:
(inverter overtemperature) the opening of a thermostat on one of the inverter power stack a) any increase of ambient air temperature.
heatsinks. This is designed to occur if the power stack reaches b) restricted cooling air flow.
90°C – the inverter is shut down (Alarm #62) if the condition c) fan failure.
s10-c2.fm5 - Issue 2 Dated 21/08/97

prevails for 1 minute following the alarm activation. d) prolonged inverter overload.

7200 Series UPS Service Manual

2. If overtemperature is not genuine then check continuity (n/c)
of thermostats and wiring through HVI to UPSLB. Replace/
repair cause of any open-circuit found. If no open-circuit is
found then replace UPSLB.

3. Verify that jumper X12 0-1 on the ILB is open (standard).

s10-c2.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual

Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

35 [ INV: UNSYNCHRONIZED ] This alarm is triggered by a UPSLB’s software routine which 1. If non-sync condition is genuine then check for and rectify:
(inverter unsynchronised to detects when the inverter and bypass waveforms are mis- a) bypass breaker open (alarm #02)
bypass) aligned by more than ±9°. The alarm resets automatically b) bypass supply error (alarms #10, #11, #12, #13, #14)
when this condition is no longer true.
1. If non-sync condition is not genuine then check for and rec-
tify:
a) recalibrate inverter phase displacement (R247 on the ILB)
b) increase the inverter “slew-rate” by use of the “SPEED”
selection in the SETUP menu.
c) Replace the UPS Logic Board.
d) Replace the Inverter Logic Board

36 [ INV: OVERVOLTAGE] This alarm is triggered by a UPSLB’s software routine which 1. If the alarm operation is genuine:
(inverter overvoltage warning) detects when the inverter voltage goes above a maximum level a) verify that the programmed “% UPPER LIMIT” on the Oper-
which is set by the “% UPPER LIMIT” menu selection on the ator Control Panel is suitable.
Operator Control Panel. b) check the inverter feedback to the ILB voltage control loop
Note: if the load is “on-bypass” the inverter is given 10 seconds on the ILB at X9-1, X9-2, X9-3. If the voltage feedback signal is
to recover, otherwise the inverter is latched off. Use the reset missing then trace the open circuit via X5 on the HVI board;
button to restart the inverter. If the bypass is available when ribbon cable W8 to the UPSLB; ribbon cable W5 to ILB.
the fault occurs the load is transferred to bypass by the critical Replace faulty component as applicable.
bus monitor (alarm #39).
2. If there is no genuine reason for the alarm condition then

CHAPTER 2 - Alarms & Indications

replace the UPSLB.

SECTION 11 - Troubleshooting
37 [ INV: UNDERVOLTAGE ] This alarm is triggered by a UPSLB’s software routine which 1. If the alarm operation is genuine:
(inverter undervoltage warning) detects when the inverter voltage goes below a minimum level a) verify that the programmed “% LOWER LIMIT” on the Oper-
which is set by the “% LOWER LIMIT” menu selection on the ator Control Panel is suitable.
Operator Control Panel. b) check for an open-circuit output filter capacitor and associ-
Note: if the load is “on-bypass” the inverter is given 10 seconds ated wiring to the output contactor.
to recover, otherwise the inverter is latched off. Use the reset c) replace the ILB
button to restart the inverter. If the bypass is available when
the fault occurs the load is transfered to bypass by the critical 2. If there is no genuine reason for the alarm condition then
bus monitor (alarm #39). replace the UPSLB.
11-15
11-16

CHAPTER 2 - Alarms & Indications

SECTION 11 - Troubleshooting
Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

38 [ INV: FUSE FAIL ] This alarm is triggered by the UPSLB micro in response to an As a genuine fuse fail condition is not normally monitored, any
inverter fuse failure. activation of this alarm channel is usually caused by a “false”
This facility is reserved for larger UPS modules and is not nor- alarm. If the alarm activates:
mally used in models up to 60kVA. It is disabled by fitting a link a) check the signal path from the HVI X16 pins 1-2 to the
to jumper X16 pins 1-2 on the HVI. UPSLB.
b) replace the UPS Logic Board

39 [ OUTPUT: OVERVOLTAGE ] This alarm is triggered by a UPSLB’s software routine which 1. If the alarm operation is genuine:
(critical bus overvoltage trip) detects when the critical bus voltage goes above a maximum a) verify that the programmed “% UPPER LIMIT” on the Oper-
level which is set by the “% UPPER LIMIT” menu selection on ator Control Panel is suitable.
the Operator Control Panel. b) check the critical bus feedback to the UPSLB voltage control
Note: when the load is “on-inverter”; if the bypass is available loop. If the voltage feedback signal is missing then trace the
when the fault occurs the load is transferred to bypass. If the open circuit via X4 on the HVI board; ribbon cable W8 to the
bypass is unavailable then the output contactor K1 will be UPSLB. Replace faulty component as applicable.
opened and the load powered-down.
2. If there is no genuine reason for the alarm condition then
replace the UPSLB.

40 [ OUTPUT UNDERVOLTAGE ] This alarm is triggered by a UPSLB’s software routine which 1. If the alarm operation is genuine:
(critical bus undervoltage trip) detects when the critical bus voltage goes below a minimum a) verify that the programmed “% LOWER LIMIT” on the Oper-
level which is set by the “% LOWER LIMIT” menu selection on ator Control Panel is suitable.
the Operator Control Panel. b) check for an open-circuit output filter capacitor and associ-
Note: when the load is “on-inverter”; if the bypass is available ated wiring to the output contactor.
s10-c2.fm5 - Issue 2 Dated 21/08/97

when the fault occurs the load is transferred to bypass. If the c) replace the ILB

7200 Series UPS Service Manual

bypass is unavailable then the output contactor K1 will be
opened and the load powered-down. 2. If there is no genuine reason for the alarm condition then
replace the UPSLB.

41 [ OUTPUT: NO VOLTAGE ] This alarm is triggered by the UPSLB if the inverter is running 1. Check that the unit is selected to “Auto” mode by ensuring
(UPS in off-line mode) at nominal output voltage but the output contactor (K1) is open. that jumper X26 pin 1-2 is not linked (standard) on the UPSLB.

2. Check the control wiring to the output contactor coil via the
Static Switch Trigger Board at X8, X9, X10. Check contactor
coil resistance for open-circuit or short-circuit.

3. If no genuine reason can be found for the alarm then replace

the UPSLB.
s10-c2.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual

Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

42 [ OUTPUT: WAVEFORM ERR.] This alarm is triggered by a UPSLB software routine which Check to see if the alarm is genuine by monitoring each output
(low inverter peak volts) monitors the peak voltage waveform of each output voltage waveform with an oscilloscope.
envelope.
1. If the problem is genuine:
a) check the output filter capacitors for correct function.
b) check for open circuit wiring between the inverter output and
the output contactor (K1)
c) check the inverter feedback to the ILB voltage control loop
on the ILB at X9-1, X9-2, X9-3. If the voltage feedback signal is
missing then trace the open circuit via X5 on the HVI board;
ribbon cable W8 to the UPSLB,; ribbon cable W5 to ILB.
Replace faulty component as applicable.

2. If the problem is not genuine then replace the UPSLB.

43 [ INV: FREQUENCY ERROR ] This alarm is triggered by a UPSLB software routine which Check the true inverter frequency to determine if the alarm is
(inverter frequency error) detects when the inverter frequency is outside its window lim- genuine.
its. This is automatically set at twice the bypass frequency win-
dow limits set via the Operator Control Panel menuing system. 1. If the alarm is genuine:
a) check that the mimic display nominal operating frequency is
entered correctly (e.g. 50Hz).
b) recalibrate/replace the ILB and necessary.

CHAPTER 2 - Alarms & Indications

2. If the alarm is not genuine then replace the UPSLB.

SECTION 11 - Troubleshooting
44 [ INV: PARALLEL ERROR ] This alarm is triggered in a 1+1 configured system if the Paral- If fault is genuine then led H1 should be illuminated on the Par-
(inverter selected off) lel Logic Board’s ‘selective shutdown’ circuit is active. allel Logic Board.

Attempt to reset using the reset switch on the UPS Logic

Board. If this does not solve the problem then investigate
cause for any load current sharing problem.

45 [ CONTACTOR ERROR ] This alarm is triggered if the state of the monitored auxiliary Check the operation of the contactor power poles and auxillary
contacts do not agree with the output contactor control status – contacts
e.g. contacts indicate that the contactor is open when it should Check contactor control logic on Static Switch Driver Board
11-17

be closed and state of auxiliary contacts/wiring.

Check the impedence of the contactor coil is wthin the range
30-38kω (see paragraph 4.4.3 on page 11-51)
11-18

CHAPTER 2 - Alarms & Indications

SECTION 11 - Troubleshooting
Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

50 [ BATTERY: UNDER TEST ] This warning is triggered by a UPSLB software routine in Check the mimic display window under BATTERY TEST, and
response to a user-initiated BATTERY TEST selected via the reset the warning if necessary. Otherwise replace the UPSLB.
Operator Control Panel menuing system.

51 [ BATTERY: TEST FAILED ] This latched alarm is activated by a UPSLB software routine in 1. Press the reset button (S1) on the UPSLB to unlatch the
response to the results of the BATTERY TEST routine. alarm.

2. If the alarm fails to reset then check the battery test parame-
ters indicated on the Operator Control Panel display screen.
If the parameters are correct then replace the UPSLB; if the
parameters are faulty then check the battery for a genuine
fault.

52 [ BATTERY: DISCHARGING ] This alarm is triggered by a UPSLB software routine and is Confirm the alarm is genuine by measuring the battery dis-
(battery is discharging) enabled only when the battery breaker is closed. The battery charge current.
current must be negative (discharging) for longer than 10 sec-
onds before the alarm is activated. 1. If the alarm is genuine check the rectifier function and float
voltage level. Also observe the instructions appropriate to any
other active alarms.

2. If the alarm is not genuine:

a) check the battery discharge current from the Operator Con-
trol Panel “MEASUREMENT” screen.
s10-c2.fm5 - Issue 2 Dated 21/08/97

b) ensure that the battery parameters are correctly set: i.e. NO

7200 Series UPS Service Manual

OF BATT. EL.; CAPACITY etc., under the appropriate display
menu screen.
c) check the rectifier float voltage.
d) Replace the UPSLB.
s10-c2.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual

Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

53 [ BATTERY: E.O.D. ] This alarm is triggered by a UPSLB software routine which Confirm the alarm is genuine by measuring the battery volt-
(battery end_of_discharge trip) trips the battery breaker at the appropriate low battery discon- age, and check the battery circuit breaker trip status.
nect voltage (i.e. when the battery discharges to its “end-of-
discharge” voltage. 1. If the alarm is genuine:
Note 1: the exact trip level is programmable via the display a) reset the UPS system by carrying out a re-start.
menu screen. b) Check the rectifier float voltage level and observe the
Note 2: If the load is less than 15% of nominal rating, the instructions appropriate to any other active alarms.
E.O.D. trip level is automatically increased by 10%.
2. If the alarm is not genuine:
a) check that the “END DIS.” trip level programmed via the
Operator Control Panel “SETUP” menu is correct.
b) replace the UPSLB.

54 [ BOOST: TIME EXPIRED ] This latched alarm is triggered by a UPSLB software routine if Confirm that the alarm is genuine by checking that the “AUTO-
the Boost Charge timer has been exceeded. At some time pre- MATIC” boost facility is enabled, and that the boost parameters
viously, the unit has automatically entered its Boost Charge are correctly selected (See Figure 2-17).
regime and continued to boost the batteries for the pro-
grammed number of hours. 2. If the alarm is genuine:
a) check the battery string for faulty cells.
b) press the reset button (S1) on the UPSLB to clear the alarm.

3. If the alarm is not genuine, replace the UPSLB.

CHAPTER 2 - Alarms & Indications

55 [ DC BUS: SLOW OVERVOL. ] This latched alarm is triggered by a UPSLB software routine if Confirm that the alarm is genuine by checking that the DC Bus

SECTION 11 - Troubleshooting
(dc overvoltage warning) the DC Bus voltage rises above the programmed “MAX.” level. voltage does not exceed the programmed overvoltage level.
(See Figure 2-16)
1. If the alarm is genuine:
When activated, the rectifier and inverter are turned off. a) check the rectifier float voltage level and observe the
instructions appropriate to any other active alarms.
b) check that the DC Bus filter capacitors are healthy.
c) check the DC Bus voltage feedback path to the RLB for an
open-circuit fault.

2. If the alarm is not genuine:

a) verify that the DC Bus “MAX.” parameter is correctly set in
11-19

the display menu screen.

b) replace the UPSLB.
11-20

CHAPTER 2 - Alarms & Indications

SECTION 11 - Troubleshooting
Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

56 [ DC BUS: UNDERVOLTAGE ] This latched alarm is triggered by a UPSLB software routine if Confirm that the alarm is genuine by checking that the DC Bus
(low battery warning) the DC Bus voltage falls below the low voltage ( “BATT. LOW”) voltage is not below the programmed undervoltage level.
warning level (See Figure 2-16).
This is a warning that the battery is approaching its end-of-dis- 1. If the alarm is genuine, check the rectifier float charge and
charge voltage, and does not in itself affect the inverter/load recalibrate/replace the RLB as necessary. Also, observe the
operation. instructions appropriate to any other active alarms.

2. If the alarm is not genuine:

a) verify that the DC Bus “BAT. LOW.” parameter is correctly
set in the display menu screen.
b) replace the UPSLB.

57 [ BATTERY: FUSE FAIL ] The battery fuse condition (F13) is monitored by a normally- Confirm that the alarm is genuine by checking the state of the
open micro-switch which is connected to the fuse. If the fuse mechanical pin on the fuse body and then carry out a continu-
ruptures, a mechanical pin is released which operates (closes) ity check of the fuse itself using an ohmmeter.
the micro-switch.
1. If the alarm is genuine:
The resulting digital low signal is processed by the UPSLB a) investigate the battery string for faulty (short-circuit) cells.
micro which then passes the alarm data via the Operator Logic b) check incorrect operation of the battery circuit breaker (e.g.
to the LCD Display. attempted closure when the rectifier is OFF).

2. If the alarm is not genuine:

a) check the micro-switch for correct operation.
s10-c2.fm5 - Issue 2 Dated 21/08/97

b) check the wiring from the micro-switch back to the HVI

7200 Series UPS Service Manual

board and UPSLB (and associated ribbon cables).
c) replace the UPSLB and/or HVI board as required.
s10-c2.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual

Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

58 [ DC BUS: FAST OVERVOL. ] This latched alarm is triggered by a UPSLB software routine 1. Transfer the load to the maintenance bypass; open the static
(fast dc overvoltage) which detects the DC Bus voltage rising above 620Vdc. This bypass breaker; and “block” the inverter by closing Q2 on the
instantaneously shuts down the rectifier and inverter; and also UPSLB.
trips the battery breaker.
The 620V threshold is fixed by hardware. 2. Start the rectifier and record the DC Bus float voltage.
a) if the float voltage is correct then check for a shorted static
The load will be transferred to the bypass if it is available bypass SCR (using 3. below).
b) if the DC Bus voltage rises to the “fast overvoltage” thresh-
old then there is a fault in the rectifier voltage regulation loop:
– check the DC Bus voltage feedback path to the RLB for an
open circuit fault (X2 on HVI; ribbon cable W8 to UPSLB; rib-
bon cable W6 to RLB). Note that on the RLB, test point X1 pins
1-3 should equal 3Vdc at nominal 432Vdc on the DC Bus.

3. If the rectifier is OK, start the inverter and check for no volt-
age at Q2 bypass isolator. If the inverter voltage is present, a
shorted bypass SCR exists. If no voltage is present then the
alarm is not genuine and the UPSLB should be replaced.
Note: a shorted bypass SCR can also be detected by turning
off the inverter and static bypass section using Q1 and Q2 on
the UPSLB, then closing the static bypass breaker and check-
ing for voltage on the UPS output terminals.

CHAPTER 2 - Alarms & Indications

SECTION 11 - Troubleshooting
60 [ BYP: XFER COUNT BLOCK ] This latched alarm is triggered by a UPSLB software routine Confirm that the alarm is genuine by resetting the UPS and
which counts the number of transfers between the inverter and check for transfer recurrences.
bypass. If the count exceeds 8 within 1 minute, the load is
latched onto the bypass-side. The alarm must be reset by the 1. If the alarm is genuine:
reset switch (S1) on the UPSLB. a) check for open circuit power wiring between the inverter out-
put and the critical bus – e.g. via the output transformer and
The transfer-count and time is not variable. output contactor.
b) check for open circuit control wiring to X5 on the HVI board
and X10 on the Static Switch Driver Board.
11-21

2. If the alarm is not genuine than replace the UPSLB.

11-22

CHAPTER 2 - Alarms & Indications

SECTION 11 - Troubleshooting
Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

61 [ CUT-OFF: OVERLOAD ] This latched alarm is triggered by a UPSLB software routine Confirm that the alarm is genuine by checking the amber led of
which detects if an overload condition is present for longer the appropriate % bargraph or check for % load indicated on
than the permissible inverse-time characteristic: the Display menu “Measurement” screen. If an overload is indi-
e.g. 110% for 1 hour; 125% for 10 minutes 150% for 1 minute. cated then check the load, and investigate any additional load
The alarm must be reset by the reset switch (S1) on the connected prior to the alarm (if applicable).
UPSLB.
1. If the alarm is genuine:
Note 1: If the overload timer is active then alarm #66 should a) check the load equipment and rectify as necessary.
also be active as the load is above nominal.
2. If the alarm is not genuine:
Note 2: When the timer has counted-out, the output contactor a) verify that the correct UPS kVA rating has been entered via
(K1) is opened and the load transferred to bypass, but the the Display menu “SET UP” screen.
inverter is not switched off. b) verify that the correct CT burden resistance is selected on
the HVI board, and ensure that there is no open circuit via X19,
Note 3: The activation of alarm #66 and the time-out period are X20, X21 on the HVI board.
factory set and not adjustable. c) replace the UPSLB.

62 [ CUT-OFF: OVERTEMPER. ] This latched alarm is triggered by a UPSLB software routine Confirm that the alarm is genuine by checking for a tempera-
which detects if an overtemperature fault has been registered ture increase using the appropriate Display menu “MEASURE-
for longer than 1 minute. When this is true, the rectifier and MENT” screen.
inverter are turned off.
The alarm must be reset by the reset switch (S1) on the 1. If the alarm is genuine:
UPSLB. a) check for restricted air flow and fan failure
s10-c2.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual

Note 1: The alarm will occur only upon receipt of alarm #19, 2. If the alarm is not genuine:
#24 or #34. a) check the appropriate rectification under alarms #19, #24 or
#34, as applicable.
Note 2: The 1 minute time-out period is factory set and not b) replace the UPSLB.
adjustable.
s10-c2.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual

Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

63 [ CUT-OFF: EMERGENCY ] This latched alarm is triggered by a UPSLB software routine in Confirm that the alarm is genuine by checking the integrity of
response to the operation of the External Emergency Power the external EPO circuit at the customer terminal block (X3)
Off (Emergency Stop) circuit. The external circuit should com- pins 10-11.
plete a closed circuit between pins 10 & 11 of the Customer
Terminal Block (X3). 1. If the alarm is genuine then check the reason for the EPO
The alarm must be reset by the reset switch (S1) on the circuit activation and repair as necessary.
UPSLB.
2. If the alarm is not genuine:
a) check for normally closed connection to HVI board X8
between pins 6 and 7.
b) replace the UPSLB.

66 [ OVERLOAD PRESENT ] This alarm is triggered by the UPSLB micro once the load cur- Confirm that the alarm is genuine by verifying that the amber
rent rises above the UPS 100% nominal rating. The overload overload LED is activated on the % load bargraph; and check
timer is started, as described in alarm #61. the Display menu “MEASUREMENT” screen to determine
which phase is being overloaded. Then measure the actual
Note 1: the operating level is factory set and not adjustable. output current to verify that the indications are valid.

Note 2: the alarm automatically resets once the overload con- 1. If the alarm is not genuine:
dition is removed. a) verify that the correct UPS kVA rating has been entered via

CHAPTER 2 - Alarms & Indications

the Display menu “SET UP” screen.
b) verify that the correct CT burden resistance is selected on

SECTION 11 - Troubleshooting
the HVI board, and ensure that there is no open circuit via X19,
X20, X21 on the HVI board.
c) replace the UPSLB.

67 [ CUT-OFF: OVERLOAD ]
11-23
11-24

CHAPTER 2 - Alarms & Indications

SECTION 11 - Troubleshooting
Display Alarm Messages
CODE Details Rectification
(Correct Meaning)

70 [ BAD EEPROM PROGRAM. ] This alarm is triggered by the UPSLB micro if there is an error 1. Verify that the correct UPS kVA rating has been entered via
during writing the UPS parameters into the EEPROM (D20) the Display menu “SET UP” screen. Turn the UPS off for 5 sec-
during initialisation. onds and then back on again to reinitialise the software.

Note: the rectifier, inverter and bypass are all disabled if this 2. Try to “RELOAD” the UPS data via the appropriate display
alarm is active. Menu “FUNCTION” screen. Turn the UPS off for 5 seconds
and then back on again to reinitialise the software, re-enter the
module’s KVA value.

3. Replace the UPSLB.

71 [ ERR0R LRC PAR. PAG 1 ] These alarms are triggered by the UPSLB micro if there is an 1. Try to “RELOAD” the UPS data via the appropriate display
error with the operating parameters during the software initiali- Menu “FUNCTION” screen. Turn the UPS off for 5 seconds
72 [ ERROR LRC PAR. PAG 2 ] sation routines. and then back on again to reinitialise the software, re-enter the
module’s KVA value.
73 [ ERROR LRC PAR. PAG 3 ]
Note: the rectifier, inverter and bypass are all disabled if either
of these alarms are active. 2. Replace the UPSLB.

74 [ ERROR LRC ALARM HIS. ]

75 [ ERROR LRC EVENT HIS. ]

76 [ INTERNAL BATTERY LOW ]

s10-c2.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual

80 [ ERROR LRC TABLE ]

81 [ ERROR LRC PANEL ]

82 [ MODEM WRONG CONFIG. ]

83 [ ERROR LRC ALARM MEM. ]

84 [ MODEM NO RESPONSE ]

85 [ MODEM FALSE COMMAND ]

86 [ MODEM TIMEOUT TRASM. ]

87 [ CAN BUS NO RESPONSE ]

7200 Series UPS Service Manual SECTION 11 - Troubleshooting
CHAPTER 2 - Alarms & Indications

Rectification
Details
Display Alarm Messages

[ AUTONOMY XXXX min ]

(battery autonomy time)
(Correct Meaning)
CODE

89

90
88

s10-c2.fm5 - Issue 2 Dated 21/08/97 11-25

SECTION 11 - Troubleshooting 7200 Series UPS Service Manual
CHAPTER 2 - Alarms & Indications

11-26 s10-c2.fm5 - Issue 2 Dated 21/08/97

 Section 11:

Chapter 3 - Board Replacement & Calibration Procedures

Important Note: Throughout these procedures, reference is made to switches Q1, Q2 and Q3 on
the UPS Logic Board which are used to manually enable/inhibit the Static Bypass,
Inverter and Rectifier power sections respectively.

When instructed to “close” a switch this should be interpreted as “apply the inhibit”
(or block the power section) – e.g. “turn off the rectifier by closing Q3”. Similarly,
“opening” a switch “enables” the relevant power section.

3.1 Rectifier Logic Board replacement (Part Nº 4520074A)

1. Using the correct power switching sequence, transfer the load to the Mainte-
nance Bypass (see Operator’s Manual if required).
2. Totally power down the UPS (see Operator’s Manual if required).
3. Remove the faulty Rectifier Logic Board.
4. Note and record the position of the jumper ‘X’ links on the removed board.
5. Ensure the jumper ‘X’ links on the replacement Board are positioned identi-
cally to those on the board being replaced.
Note: For further details of the jumper functions, refer to Table 4-5 (on page
4-37) if necessary.
6. Fit the replacement Rectifier Logic Board.
7. Block all the power sections by closing the inhibit switches Q1, Q2 and Q3
on the UPS Logic Board.
8. Close the UPS Input Power Isolator Q1.
a) The control power supply will energise.
b) The UPS Logic Board will carry out a self-test and then display associ-
ated alarms on the Operator Control Panel LCD display screen.

3.1.1 Calibration

Rectifier input current limit

1. Connect a DVM between test point X8 pin 7 and the 0V rail (X12/X13).
2. Adjust R17 (clockwise to increase) to obtain the following indication:
a) 30kVA = -0.8Vdc
b) 40kVA = -1.2Vdc
c) 60kVA = -1.6Vdc

Battery current limit

3. Connect a DVM between test point X8 pin 8 and the 0V rail (X12/X13).

S10-C3.FM5 - Issue 3 Dated 09/11/98 11-27

SECTION 11 - Troubleshooting 7200 Series UPS Service Manual
CHAPTER 3 - Board Replacement & Calibration

4. Adjust R18 (clockwise to increase) to obtain the following indication:

a) 30kVA = 0.1Vdc per Amp for the required battery current limit.
b) 40kVA = 0.1Vdc per Amp for the required battery current limit.
c) 60kVA = 0.1Vdc per Amp for the required battery current limit.

Battery temperature compensation

5. Connect a DVM between test point X5 pin 1 and the 0V rail (X12/X13).
6. Adjust R121 to obtain an indication of 2.98Vdc (equivalent to 25°C).
Note: this sets the temperature above which the DC bus voltage will
decrease by 1Vdc for every 1° C rise in battery temperature. For a different
threshold temperature setting the value is adjusted linearly.

DC float voltage settings (range = 200 to 500 volts)

7. Connect a DVM (500V range) to the UPS +ve and –ve battery connections.
8. Open the inhibit switch Q3 on the UPS Logic Board to remove the manual
inhibit on the rectifier.
9. The rectifier should start in a controlled manner and the DC busbar should
ramp up to the battery float charge voltage.
10. On the Rectifier Logic Board:
a) LED H3 (green) should illuminate.
b) Adjust R21 to obtain an indication of 2.25V/cell – i.e. 2.25V x the total
number of cells contained in the battery blocks (clockwise to increase).

DC manual voltage setting (range = 0 to 600V volts)

11. Using standard screen navigation techniques, gain access to the charge mode
selection screen via the FUNCTION – NEXT PAGE – ON/OFF UPS BLOCK
menu path (see figure 2-28 on page 2-67).
12. Scroll through the menu options and select manual charge mode (‘MAN’).
13. On the Rectifier Logic Board:
a) Ensure led H4 (yellow) illuminates (H3 extinguishes).
b) Adjust R22 to obtain an indicated charge voltage appropriate to ‘form-
ing’ open vented cells (if applicable). If sealed cells are used then set this
voltage to equal the float voltage set previously (2.25V/cell) (clockwise
to increase).

DC boost voltage setting (Range = 200 to 550 volts)

14. With the MANUAL charge mode still selected from the previous test;
on the Rectifier Logic Board:
a) Fit a jumper link X9 pin 0–2 (to initiate the BOOST mode).
b) Ensure that the LED H2 (green) illuminates.
c) Adjust R20 to obtain an indicated DVM voltage appropriate to the
required battery boost charge voltage (clockwise to increase). If sealed

11-28 S10-C3.FM5 - Issue 3 Dated 09/11/98

7200 Series UPS Service Manual SECTION 11 - Troubleshooting
CHAPTER 3 - Board Replacement & Calibration

cells are used then set this voltage to equal the float voltage set previ-
ously (2.25V/cell).

DC test voltage setting (Range 0 - 600Volts)

15. This setting is used to reference the rectifier voltage during a battery auton-
omy test. It should be set at 20V below the battery fail voltage as selected by
the ‘BATTERY TEST’ software screen during the ‘FUNCTION’ setup (see figure
2-23 on page 2-52) – e.g. if the ‘battery fail’ value is set at 1.9V/cell this
value should be set at 1.8V/cell.
16. On the Rectifier Logic Board:
a) Fit a jumper link to X9 pins 0–1 (leave jumper on 0–2).
b) Ensure that LED H1 (amber) illuminates.
c) Adjust R19 to obtain an indicated voltage on the DVM equivalent to the
desired battery “Test Fail” voltage (e.g. 1.8V/cell).
17. Using standard screen navigation techniques, gain access to the charge mode
selection screen via the FUNCTION – NEXT PAGE – ON/OFF UPS BLOCK
menu path (see figure 2-28 on page 2-67).
18. Scroll through the menu options and select float charge mode (‘FLO’).
19. On the Rectifier Logic Board:
a) Remove the jumper links from X9 0-1 & 0-2
b) Ensure led H3 (green) illuminates.
c) Verify that the battery voltage returns to the float charge value.

3.1.2 Returning the UPS to service

1. Open the UPS Input Power Isolator Q1 & Bypass Power Isolator Q2.
2. On the UPS Logic Board open Q1, Q2 and Q3 to ‘enable’ the inverter, recti-
fier and static switch power sections.
3. Disconnect and remove all test equipment.
4. Refit any other connections and/or components disturbed during the above
procedure.
5. Start the UPS following the standard operating procedure contained in the
Operator’s Manual and verify that the UPS parameters are correct during the
start-up sequence.
6. Return the faulty Rectifier Logic Board to the nearest Liebert Service Centre
for repair.

3.2 Inverter Logic Board replacement (Part Nº 4530025T)

1. Using the correct power switching sequence, transfer the load to the Mainte-
nance Bypass (see Operator’s Manual if required).
2. Totally power down the UPS (see Operator’s Manual if required).
3. Remove the faulty Inverter Logic Board.
4. Note and record the position of the jumper ‘X’ links on the removed board.

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5. Ensure the jumper ‘X’ links on the replacement Board are positioned identi-
cally to those on the board being replaced.
Note: For further details of the jumper functions, refer to Table 5-4 (on page
5-53) if necessary.
6. Fit the replacement Inverter Logic Board.
7. Block all the power sections by closing the inhibit switches Q1, Q2 and Q3
on the UPS Logic Board.
8. Close the UPS Input Power Isolator Q1.
a) The control power supply will energise.
b) The UPS Logic Board will carry out a self-test and then display associ-
ated alarms on the Operator Control Panel LCD display screen.
9. Open the inhibit switch Q3 on the UPS Logic Board to ‘enable’ the rectifier
– allow sufficient time for the DC busbar to rise and stabilise at the float
charge voltage.

3.2.1 Calibration

Inverter current limit

1. Connect a DVM between test point X10 pin 4 and the 0V rail (X17/X18).
2. Adjust R248 (clockwise to increase) to obtain an indication of 0.6Vdc on
the DVM – this is equivalent to 150%.

Inverter PWM reference tri-wave.

Note: Adjust the triangular waveform shown below only if necessary.

Figure 11-2: Inverter PWM reference tri-wave

+2 volts

–2 volts

3. On the Inverter Logic Board:

a) Connect an oscilloscope to the right hand side of resistor R27 (use X17/
X18 for 0V reference).
b) If necessary, adjust potentiometer R241 to obtain a triangular waveform
of 4 volts peak to peak, as shown above.

Inverter starting
4. Open the inhibit switch Q2 on the UPS Logic Board to ‘enable’ the inverter.
a) The inverter should ramp up to nominal voltage.
b) The output contactor (K1) should close.
5. Close the Bypass Power Isolator Q2.
a) The inverter should synchronise to the bypass supply.

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b) Verify that the ‘INVERTER UNSYNCHRONISED’ alarm is no longer shown on

the Operator Panel LCD display.
6. Ensure that the inhibit switch Q1 on the UPS Logic Board remains closed to
disable the static bypass.

Inverter output voltage adjustment.

Important Note: R242 simultaneously adjusts all three output L-N voltages while R244, R245
and R246 independently adjusts all three phases non-linearly.
Ensure that R242 is adjusted first to set all three line voltages before
making the final line to neutral adjustments.
7. Connect a DVM to the inverter output terminals ‘R’ and ‘N’.
8. Adjust potentiometer R246 (clockwise to increase) to obtain the required
output L-N voltage, as indicated by the appropriate operating mode – i.e. led
H1= 220V, H2=230V, H3=240V.
9. Connect the DVM to the inverter ‘S’ and ‘N’ terminals.
10. Adjust potentiometer R244 (clockwise to increase) to obtain the required
output L-N voltage as indicated by the appropriate operating mode – i.e. led
H1= 220V, H2=230V, H3=240V.
11. Connect the DVM to the Inverter ‘T’ and ‘N’ terminals.
12. Adjust potentiometer R245 (clockwise to increase) to obtain the required
output L-N voltage, as indicated by the appropriate operating mode – i.e. led
H1= 220V, H2=230V, H3=240V.

Inverter bypass phase lock adjustment

13. Connect a dual channel oscilloscope probe 1 to monitor the bypass ‘R’
phase voltage and probe 2 the inverter output phase ‘R’ voltage (use the
chassis earth for 0V reference).
14. Adjust potentiometer R247 until both sine waves are perfectly in phase.

Inverter manual voltage adjustment (range = 0 to 500 volts AC)

Note: this mode is used for inverter testing only so adjust only if required.
15. Turn off the inverter by closing the inhibit switch Q2 on the UPS Logic
Board.
16. On the Inverter Logic Board
a) Turn R243 fully clockwise – this is equivalent to 0V output.
b) Fit jumper links to X12, 0-3 and 0-4.
a) Verify that the amber LED H4 is illuminated (indicating ‘manual’ mode).
17. Connect a DVM (500Vac) between the inverter output ‘R’ and ‘S’ phases.
18. ‘Enable’ the inverter by opening the inhibit switch Q2 on the UPS Logic
Board.
19. On the Inverter Logic Board
a) Slowly turn R243 anti-clockwise until the inverter just starts to generate
an output AC voltage.

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CHAPTER 3 - Board Replacement & Calibration

b) Continue adjusting R243 until the nominal output voltage is reached –

the output contactor (K1) should closed.

Important Note: Do not run the inverter on low voltage for extended periods as it may
adversely affect the cooling fans’ operation.

Inverter overvoltage test

20. Using R243, continue to (slowly) increase the inverter voltage above its
nominal value and verify the following output overvoltage actions:
a) At 110% nominal voltage the ‘INV: OVERVOLTAGE’ alarm (#36) should
annunciate on the Operator Control Panel LCD display panel.
Note: Equivalent to 418V/440V/457V for 380V/400V/415V systems.
b) At 112% nominal output voltage the ‘OUTPUT: OVERVOLTAGE’ alarm (#39)
should annunciate on the Operator Control Panel LCD display panel.,
and the output contactor K1 should open.
Note: Equivalent to 426V/448V/465V for 380V/400V/415V.

Inverter undervoltage test

21. Using R243, decrease the inverter output voltage and verify the following
output undervoltage actions (note that contactor K1 should re-energise as
the voltage is reduced):
a) At 90% nominal output voltage, ‘INV: UNDERVOLTAGE’ alarm (#37) should
annunciate on the Operator Control Panel LCD display panel.
Note: Equivalent to 342V/360V/373V for 380V/400V/415V.
b) At 88% nominal output voltage, the ‘OUTPUT: UNDERVOLTAGE’ alarm (#40)
should annunciate on the Operator Control Panel LCD display panel, and
the output contactor K1 should open.
Note: Equivalent to 335V/352V/365V for 380V/400V/415V.
22. Using R243, increase the inverter output to nominal voltage once again
(note that contactor K1 should re-energise as the voltage is increased):

3.2.2 Returning the UPS to service

1. Open the UPS Input Power Isolator Q1 and Bypass Power Isolator Q2.
2. On the UPS Logic Board:
a) Open the inhibit Q1, Q2 & Q3 to ‘enable’ the UPS power sections.
b) Remove the jumper links fitted to X12 pins 0-3 & 0-4.
3. Disconnect and remove all test equipment.
4. Refit any other connections and/or components disturbed during the above
procedure.
5. Start the UPS following the standard operating procedure contained in the
Operator’s Manual and verify that the UPS parameters are correct during the
start-up sequence.
6. Return the faulty Inverter Logic Board to the nearest Liebert Service Centre
for repair.

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3.3 UPS Logic Board replacement (Part Nº 4550007H)

1. Using the correct power switching sequence, transfer the load to the Mainte-
nance Bypass (see Operator’s Manual if required).
2. Totally power down the UPS (see Operator’s Manual if required).
3. Remove the faulty UPS Logic Board.
4. Note and record the position of the jumper ‘X’ links on the removed board.
5. Ensure the jumper ‘X’ links on the replacement Board are positioned identi-
cally to those on the board being replaced. Note: For further details of the
jumper functions, refer to Table 7-8 (on page 7-72) if necessary.
6. Fit the replacement UPS Logic Board.
7. Block all the power sections by closing the inhibit switches Q1, Q2 and Q3
on the UPS Logic Board.
8. Close the UPS Input Power Isolator Q1.
a) The control power supply will energise.
b) The UPS Logic Board will carry out a self-test and then display associ-
ated alarms on the Operator Control Panel LCD display screen – note
that the ‘ERROR HISTORY’ alarms will be active as no settings have yet
been installed in the NVRAM.

3.3.1 Calibration

Power supplies
1. Connect the internal battery by fitting a jumper link to X32 – LED H8 may
illuminate to indicate that the internal battery charger is active.
2. Connect a DVM between X20 pin 1 and the 0V rail (X18-8), and adjust
potentiometer R209 to obtain a DVM indication of 5.00Vdc.
3. Connect a DVM to diode V45 anode and the 0V rail (X18-8), and adjust
potentiometer R212 to obtain a DVM indication of 2.50Vdc.

Software set-up
In order to reset the ‘ERROR HISTORY’ alarm it is necessary to re-program the non-
volatile RAM (NVRAM).
4. Ensure that the unit kVA is set. (see paragraph [Link] on page 2-34)
5. Carry out the following software commissioning procedures:
a) Ensure that link X26 7-8 is closed. This will overide the password secu-
rity system.
b) Language selection (if necessary) (see paragraph 2.4.4 on page 2-31)
Note: This procedure includes details for setting the PASSWORD.
c) UPS Setup parameters (see paragraph 2.4.5 on page 2-33). This includes
the following:-
– Basic UPS Configuration and kVA vcalue (see paragraph [Link] on
page 2-34).
– UPS Working voltage parameters (see paragraph [Link] on page 2-34)

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– UPS Frequency parameters (see paragraph [Link] on page 2-35).

– Battery Parameters (see paragraph [Link] on page 2-36).
d) ‘MAINTENANCE’ Data entry (see paragraph 2.4.6 on page 2-39).
6. The ‘ERROR HISTORY’ alarm will not reset until the UPS is powered down and
restarted – the internal battery will maintain the re-programmed parameters.

3.3.2 Returning the UPS to service

1. Open the UPS Input Power Isolator Q1 and the Bypass Power Isolator Q2.
2. On the UPS Logic Board, close the inhibit switches Q1, Q2 and Q3 to ‘ena-
ble’ the rectifier, inverter and static switch power sections.
3. Disconnect and remove all test equipment.
4. Refit any other connections and/or components disturbed during the above
procedure.
5. Start the UPS following the standard operating procedure contained in the
Operator’s Manual and verify that the UPS parameters are correct during the
start-up sequence.
6. Return the faulty UPS Logic Board to the nearest Liebert Service Centre for
repair.

3.4 Operator Logic Board replacement (Part Nº 4550005F)

1. Using the correct power switching sequence, transfer the load to the Mainte-
nance Bypass (see Operator’s Manual if required).
2. Totally power down the UPS (see Operator’s Manual if required).
3. Remove the faulty Operator Logic Board.
4. Note and record the position of the jumper ‘X’ links on the removed board.
5. Ensure the jumper ‘X’ links on the replacement Board are positioned identi-
cally to those on the board being replaced. Note: For further details of the
jumper functions, refer to Table 7-19 (on page 7-146) if necessary.
6. Fit the replacement Operator Logic Board.
7. Block all the power sections by closing the inhibit switches Q1, Q2 and Q3
on the UPS Logic Board.
8. Close the UPS Input Power Isolator Q1.
a) The control power supply will energise.
b) The UPS Logic Board will carry out its self-test and the associated
alarms will be shown on the LCD display screen.

3.4.1 Calibration
1. Ensure that the internal power supply is active – i.e. LED H1 is illuminated.
2. Adjust potentiometer R21 to give the appropriate contrast on the display
LCD screen.

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3.4.2 Returning the UPS to service

1. Open the UPS Input Power Isolator Q1 and the Bypass Power Isolator Q2.
2. On the UPS Logic Board, open the inhibit switches Q1, Q2 and Q3 to ‘ena-
ble’ the rectifier, inverter and static switch power sections.
3. Refit any other connections and/or components disturbed during the above
procedure.
4. Start the UPS following the standard operating procedure contained in the
Operator’s Manual and verify that the UPS parameters are correct during the
start-up sequence.
5. Return the faulty Operator Logic Board to the nearest Liebert Service Cen-
tre for repair.

3.5 Static Switch Driver Board replacement (Part Nº 4542043Z)

1. Using the correct power switching sequence, transfer the load to the Mainte-
nance Bypass (see Operator’s Manual if required).
2. Totally power down the UPS (see Operator’s Manual if required).

Caution Full DC busbar (battery) voltage is present on the Static Switch Driver Board dur-
ing normal operation. Wait for at least 2 minutes then ensure that the DC capac-
itors have fully discharged before proceeding

3. Remove the faulty Static Switch Driver Board.

4. Note and record the position of the jumper ‘X’ links on the removed board.
5. Ensure the jumper ‘X’ links on the replacement Board are positioned identi-
cally to those on the board being replaced. Note: For further details of the
jumper functions, refer to Table 6-1 (on page 6-15) if necessary.
6. Fit the replacement Static Switch Driver Board.
7. Block all the power sections by closing the inhibit switches Q1, Q2 and Q3
on the UPS Logic Board.
8. Close the UPS Input Power Isolator Q1.
a) The control power supply will energise.
b) The UPS Logic Board will carry out its self-test and the associated
alarms will be shown on the LCD display screen.

3.5.1 Calibration
There is no calibration necessary on the Static Switch Board, however the board
should be functionally checked by carrying out a load transfer in both directions
between the inverter and bypass supply.
1. Open the inhibit switches Q1, Q2 and Q3 on the UPS Logic Board – this
will energise the rectifier, inverter and static bypass sections.
2. The UPS will power-up normally and display ‘MANUAL BYPASS CLOSED’ on
the default screen.

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CHAPTER 3 - Board Replacement & Calibration

3. Turn off the inverter by closing the inhibit switch Q2 on the UPS Logic
Board.
4. Verify that the ‘Load on Bypass’ amber LED is flashing on the Operator
Control Panel mimic display.
5. Restart the inverter by opening Q2 on the UPS Logic Board.
6. Verify that the inverter output ramps up to nominal voltage and the output
contactor K1 closes.
7. Verify that the ‘Load on Inverter’ green LED is illuminated on the Operator
Control Panel mimic display.

3.5.2 Returning the UPS to service

1. Open the UPS Input Power Isolator Q1 and the Bypass Power Isolator Q2.
2. On the UPS Logic Board, ensure that the inhibit switches Q1, Q2 and Q3 are
open to ‘enable’ the rectifier, inverter and static switch power sections.
3. Refit any other connections and/or components disturbed during the above
procedure.
4. Start the UPS following the standard operating procedure contained in the
Operator’s Manual and verify that the UPS parameters are correct during the
start-up sequence.
5. Return the faulty Static Switch Driver Board to the nearest Liebert Service
Centre for repair.

3.6 High Voltage Interface Board replacement (Part Nº 4590054O)

1. Using the correct power switching sequence, transfer the load to the Mainte-
nance Bypass (see Operator’s Manual if required).
2. Totally power down the UPS (see Operator’s Manual if required).

Caution Full DC busbar (battery) voltage is present on the High Voltage Interface Board
during normal operation. Wait for at least 2 minutes then ensure that the DC ca-
pacitors have fully discharged before proceeding.

3. Remove the faulty High Voltage Interface Board.

4. Note and record the position of the jumper ‘X’ links on the removed board.
5. Ensure the jumper ‘X’ links on the replacement Board are positioned identi-
cally to those on the board being replaced. Note: For further details of the
jumper functions, refer to Table 7-2 (on page 7-12) if necessary.
6. Fit the replacement High Voltage Interface Board.
7. Block all the power sections by closing the inhibit switches Q1, Q2 and Q3
on the UPS Logic Board.
8. Close the UPS Input Power Isolator Q1.
a) The control power supply will energise.
b) The UPS Logic Board will carry out its self-test and the associated
alarms will be shown on the LCD display screen.

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CHAPTER 3 - Board Replacement & Calibration

3.6.1 Calibration
No calibration is necessary on the High Voltage Interface Board; however, some
of its functions may be checked by verification of the metered parameters on the
Operator Control Panel.
1. Open the inhibit Q1, Q2 and Q3 on the UPS Logic Board to energise the
Rectifier, Inverter and Bypass sections – the UPS will power-up normally
and display ‘MANUAL BYPASS CLOSED’ on the default screen.
2. Press the ‘ENTER’ button to display the ‘main menu’ screen and then select
‘MEASUREMENT’.
3. Check the expected nominal parameters using the ‘MEASURMENT’ menu map
(see figure 2-21 on page 2-48).

3.6.2 Returning the UPS to service

1. Open the UPS Input Power Isolator Q1.
2. Refit any other connections and/or components disturbed during the above
procedure.
3. Start the UPS following the standard operating procedure contained in the
Operator’s Manual and verify that the UPS parameters are correct during the
start-up sequence.
4. Return the faulty High Voltage Interface Board to the nearest Liebert Serv-
ice Centre for repair.

3.7 DC – DC Power Supply Board replacement (Part Nº 4503028K)

1. Using the correct power switching sequence, transfer the load to the Mainte-
nance Bypass (see Operator’s Manual if required).
2. Totally power down the UPS (see Operator’s Manual if required).

Caution Full DC busbar (battery) voltage is present on the DC-DC Power Supply Board
during normal operation. Wait for at least 2 minutes then ensure that the DC ca-
pacitors have fully discharged before proceeding

3. Remove the faulty DC-DC Power Supply Board.

4. Ensure that the soldered links CV1 & CV2 are made on the replacement
board.
5. Fit the replacement DC-DC Power Supply Board.
6. Block all the power sections by closing the inhibit switches Q1, Q2 and Q3
on the UPS Logic Board.
7. Close the UPS Input Power Isolator Q1.
a) The control power supply will energise.
b) The UPS Logic Board will carry out its self-test and the associated
alarms will be shown on the LCD display screen.

3.7.1 Calibration
1. Ensure that LS1 and LS2 are illuminated on the DC – DC Power Supply

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CHAPTER 3 - Board Replacement & Calibration

Board.
2. Connect a DVM to the Inverter Logic Board (Part Nº 4530025T) to check
the DC voltage levels as follows:
Note: 0V DC ground can be found at test point X18.
a) V14 anode = 12.2Vdc.
Adjust using potentiometer TM1 on the DC – DC Power Supply Board.
b) V15 cathode = -12.2Vdc.
3. Open the inhibit switches Q1, Q2 and Q3 on the UPS Logic Board to ener-
gise the Rectifier, Inverter and Bypass sections – the UPS should power-up
normally and display ‘ MANUAL BYPASS CLOSED’ on the default screen.

3.7.2 Returning the UPS to service

1. Open the UPS Input Power Isolator Q1.
2. Refit any other connections and/or components disturbed during the above
procedure.
3. Start the UPS following the standard operating procedure contained in the
Operator’s Manual and verify that the UPS parameters are correct during the
start-up sequence.
4. Return the faulty DC-DC Power Supply Board to the nearest Liebert Service
Centre for repair.

3.8 AC – DC Power Supply Board replacement (Part Nº 4503030M)

1. Using the correct power switching sequence, transfer the load to the Mainte-
nance Bypass (see Operator’s Manual if required).
2. Totally power down the UPS (see Operator’s Manual if required).

Caution Full AC bus voltage is present on the AC-DC Power Supply Board during normal
operation. Wait for at least 2 minutes then ensure that the power at the input fuses
has fully discharged before proceeding

3. Remove the faulty AC-DC Power Supply Board.

4. Fit the replacement DC-DC Power Supply Board (There are no configura-
tion links fitted to the replacement board).
5. Block all the power sections by closing the inhibit switches Q1, Q2 and Q3
on the UPS Logic Board.
6. Close the UPS Input Power Isolator Q1.
a) The control power supply will energise.
b) The UPS Logic Board will carry out its self-test and the associated
alarms will be shown on the LCD display screen.

3.8.1 Calibration
1. Ensure that power supply LED’s LS1 and LS2 are illuminated on the AC –
DC Power Supply Board.

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2. Connect a DVM to the Rectifier Logic Board (Part Nº 4520074A) to check

the voltage levels as follows.:
Note: 0V DC ground can be found at test point X13.
a) V46 cathode = –12.1V dc.
Adjust using potentiometer TM2 on the AC – DC Power Supply Board.
b) V45 anode = 12.1V dc.
Adjust using TM1 on the AC – DC Power Supply Board.
3. Open the inhibit switches Q1, Q2 and Q3 on the UPS Logic Board to ener-
gise the Rectifier, Inverter and Bypass sections – the UPS should power-up
normally and display ‘MANUAL BYPASS CLOSED’ on the default screen.

3.8.2 Returning the UPS to service

1. Open the UPS Input Power Isolator Q1.
2. Refit any other connections and/or components disturbed during the above
procedure.
3. Start the UPS following the standard operating procedure contained in the
Operator’s Manual and verify that the UPS parameters are correct during the
start-up sequence.
4. Return the faulty AC-DC Power Supply Board to the nearest Liebert Service
Centre for repair.

3.9 Parallel Logic Board replacement (Part Nº 452007H)

1. Using the correct power switching sequence, transfer the load to the Mainte-
nance Bypass (see Operator’s Manual if required).
2. Totally power down the UPS (see Operator’s Manual if required).
3. Remove the faulty Parallel Logic Board.
4. Note and record the position of the jumper links on the removed board.
5. Ensure the jumper links on the replacement board are positioned identically
to those on the board being replaced. Note: For further details of the jumper
functions, refer to Table 2-10 on page 2-26 if necessary.
6. Fit the replacement Parallel Logic Board.
7. Block all the power sections by closing the inhibit switches Q1, Q2 and Q3
on the UPS Logic Board.
8. Close the UPS Input Power Isolator Q1.
a) The control power supply will energise.
b) The UPS Logic Board will carry out its self-test and the associated
alarms will be shown on the LCD display screen.

3.9.1 Calibration
1. Ensure that switches Q1, Q2, Q3 on the UPS Logic Board are selected OFF –
i.e. to disable the rectifier, inverter, and bypass operation.

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CHAPTER 3 - Board Replacement & Calibration

2. Ensure that all power isolators on both module are OPEN, take particular
care that the bypass isolator Q2 is OPEN.
3. Close the rectifier power isolator Q1 to energise the control electronics.
4. Connect a DVM to X8 pin 1 and check that the level is high (+5V) to ensure
that the G.V.C.O. is free running (0V is available at TP10).
5. Adjust R18 to obtain a 50Hz square wave at X8 pin 2. Note: for 60Hz opera-
tion connect jumper X7 to 1-2 and adjust R18 for 60.00Hz @ X8 pin 2.
6. Connect a DVM to the lower end of R68.
7. Adjust R19 to obtain the appropriate voltage for the expected nominal output
current as shown in Table 11-3.
Table 11-3:

UPS Rated Voltage R68 Lower End Value

220/380V 5.90V
230/400V 6.20V
240/415V 6.45V

3.9.2 Returning the UPS to service

1. Open the UPS Input Power Isolator Q1.
2. On the UPS Logic Board, ensure that the inhibit switches Q1, Q2 and Q3 are
open to ‘enable’ the rectifier, inverter and static switch power sections.
3. Refit any other connections and/or components disturbed during the above
procedure.
4. Start the UPS following the standard operating procedure contained in the
Operator’s Manual and verify that the UPS parameters are correct during the
start-up sequence.
5. Return the faulty Parallel Logic Board to the nearest Liebert Service Centre
for repair.

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 Section 11:

Chapter 4 - Functional Check Procedures

4.1 Introduction
This chapter contains detailed procedures intended to be used in conjunction with
the troubleshooting tables in chapter 3. Sample oscilloscope waveforms are pro-
vided in Volume 2 (Drawings).

4.2 How to check the rectifier power components

Most rectifier power problems can be due to faulty SCRs or DC filter capacitors
as detailed in table below and the following check procedures.

Table 11-4: Power rectifier component checks

Symptoms Possible cause

Input fuse failure Short-circuit rectifier SCR

Short-circuit DC filter capacitor

Tripped input supply distribution circuit breaker Short-circuit rectifier SCR

Short-circuit DC filter capacitor

Unbalanced input current. Open-circuit rectifier SCR

Increased DC ripple voltage – the degree of Open-circuit rectifier SCR

ripple reduces as the load increases above 30%. Open-circuit DC filter capacitor

Unexpected decrease in battery autonomy Open-circuit rectifier SCR

performance; with possible shortened life. Open-circuit DC filter capacitor

Unexplained DC filter capacitor failure. Open-circuit rectifier SCR

Intermittent inverter saturation detected on Open-circuit rectifier SCR

different power poles – attenuated when the Open-circuit DC filter capacitor
inverter is on load for a period of time.

Rectifier runs continuously in its input current- Short-circuit DC filter capacitor

limit mode.

4.2.1 Short-circuit rectifier SCR

1. Transfer the load to the Maintenance Bypass supply.
2. Totally power-down the UPS.
3. Ensure that the DC Filter capacitors have fully discharged.
4. Using a DVM set to measure resistance, check each rectifier SCR device for a
short-circuit between its anode and cathode.
5. Replace any faulty device.

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CHAPTER 4 - Functional Check Procedures

4.2.2 Open-circuit rectifier SCR

1. With the rectifier running, check for a balanced input current. A lower current
indication on one of the input phases would indicate an open-circuit SCR.
2. Scope the input current on all three phases and interpret the results according
to Figure 11-3 below. The upper illustration shows that the input current
waveform normally consists of two peaks during both the positive half and
negative half voltage waveforms, occurring as the SCRs in the other two
phases are turned on. If an SCR is open-circuit (or not receiving a gate drive
signal) its current peak will disappear from the current waveform, as shown in
the lower diagram (which shows the effect of a missing S+ SCR on the R-
phase current waveform).

Figure 11-3: Illustration of input current waveforms

R+ Volts S+ current
T+ current
R+ S+ T+

R (load)
S- current
T- current R– S– T–

R- Volts

R+ S+ current missing
T+ current
R+ S+ T+

R (load)
S- current
T- current R– S– T–

R–

3. If a non-conducting SCR is found, it could be due to it being open-circuit or

not receiving a gate drive current. Using a suitable current clamp, measure the
current in the yellow wire connected to the SCR gates. A current of 200mA or
more is satisfactory.

4.2.3 Shorted DC filter capacitor

1. Transfer the load to the Maintenance Bypass supply.
2. Totally power-down the UPS.
3. Allow sufficient time for the DC filter capacitors to fully discharge – verify
with DC voltmeter (DVM) that the capacitors are safe to touch.
4. Isolate each capacitor by disconnecting their positive and negative DC Busbar
connections.
5. Using an ohmmeter (DVM):
a) Measure the resistance between the capacitor positive (+) and negative (-)
terminals – the capacitor should charge up due to the meter voltage to
eventually indicate overload (OL).

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7200 Series UPS Service Manual SECTION 11 - Troubleshooting
CHAPTER 4 - Functional Check Procedures

b) Measure the resistance between the (+) terminal and ground – this should
indicate open circuit (note the capacitor case is grounded via the threads of
its base mounting stud).
c) Measure the resistance between the (-) terminal and ground – this should
indicate open circuit (note the capacitor case is grounded via the threads of
its base mounting stud).
6. Replace any capacitor whose resistance indications fail the above checks.

4.2.4 Open-circuit DC filter capacitor

1. Transfer the load to the Maintenance Bypass supply.
2. Totally power-down the UPS.
3. Allow sufficient time for the DC filter capacitors to fully discharge – verify
with DC voltmeter (DVM) that the captors are safe to touch.

Check Method 1
1. Isolate each capacitor by disconnecting their positive and negative DC Busbar
connections.
2. Connect a shorting link between the capacitor positive (+) and negative (-)
terminals, and at the same time connect an ohmmeter (DVM) across the
shorted terminals (i.e. meter should indicate 0 Ohms – short-circuit).
3. Remove the shorting link and note the time taken by the meter indication to
rise from 0 Ohms to OL as the capacitor charges up to the meter voltage – this
should be of the order of 20 seconds on a suitable meter range.
4. Perform this check on all the DC filter capacitors and compare the results. If
any capacitor has a seriously reduced time constant compared to the others
then it should be replaced.

Check Method 2
1. Isolate each capacitor by disconnecting their positive and negative DC Busbar
connections.
2. Individually charge each capacitor to a low dc voltage (e.g. to 12Vdc from a
single battery) – ensure that the charging source is connected with the correct
polarity.
3. Disconnect the charging source once the capacitors are charged to the applied
voltage.
4. Measure and record the initial capacitor terminal voltage.
5. Wait 15-30 minutes then repeat the capacitor voltage measurements and com-
pare the result with the initial values. If any capacitor has a greatly reduced
voltage when compared with the others then it is unable to hold its charge and
should be replaced.

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SECTION 11 - Troubleshooting 7200 Series UPS Service Manual
CHAPTER 4 - Functional Check Procedures

4.3 How to check the inverter power components

Most inverter power problems are due to faulty IGBTs or AC Filter Capacitors.
An overview of these problems is given in the following table.
Table 11-5: Inverter power component problems

Symptoms Possible cause

Continuous inverter current limit and/or Short-circuited AC filter capacitor or

intermittent “Vsat” failure. shorted output transformer.

Bad/incorrect inverter sine-wave output, Open-circuited output AC filter capacitor.

becoming more pronounced as load is Open-circuit base drive lead.
increased.

Continuous Vsat on the same power pole Sort-circuited IGBT (80%)

on each attempt at starting the inverter. Open-circuited IGBT (10%)
Faulty Base Driver Board (10%)

Intermittent Vsat on different power pole Faulty DC Hall-effect CT on output

on each attempt at starting the inverter. transformer.
Faulty DC filter capacitor
Faulty rectifier SCR
Faulty DC-DC Power Supply Board
Faulty Inverter Logic Board

4.3.1 Short-circuit and Open-circuit IGBT

It is difficult to check for an open-circuit IGBT with the device in-situ. To this
end, it is convenient to check the Vsat detection indication (H5 - H12) on the In-
verter Logic Board before proceeding.
The Vsat detector (one for each power IGBT on each Base Driver) attempts to
measure the voltage drop across the IGBT when it is turned ON. It therefore indi-
cates the following latched conditions:
a) Shorted IGBT on this device (80% chance).
b) Open IGBT on this power pole but not this device (10% chance).
c) Faulty power supply/device fets on this Base Driver Board (10% chance).

Figure 11-4: Vsat example

Positive Bus

Vsat = LS2 OFF on Base Drive Board

H5 ON on Inverter Logic Board
R+

R- Vsat = LS2 OFF on Base Drive Board

H6 ON on Inverter Logic Board

Negative Bus

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7200 Series UPS Service Manual SECTION 11 - Troubleshooting
CHAPTER 4 - Functional Check Procedures

1. Transfer the load to the Maintenance Bypass supply.

2. Totally power-down the UPS.
3. Allow sufficient time for the DC filter capacitors to fully discharge – verify
with DC voltmeter (DVM) that the captors are safe to touch.
4. Check the impedance across R+ IGBT terminals (See paragraph 4.3.2).
a) If a short circuit is found then replace the R+ IGBT
b) If no short circuit is found then it is likely that the R- IGBT is open-circuit.
therefore replace the R- IGBT.
5. Restart the UPS following the Start procedure in the Users Manual. and allow
the rectifier to run up to float voltage.
a) The DC-DC Power Supply should now energise each of the Base Drive
Boards.
b) Check the intensity of all six green Power Supply leds on the Base Drive
Boards. A low intensity would indicate a poor Base Drive Board, which
should be replaced.

4.3.2 How to check the inverter IGBTs

In the event of an inverter failure it is possible that the power IGBTs might have
been damaged. It is therefore expedient to test the devices following any form of
inverter fault.
Two types of IGBT devices may be fitted to the inverter heatsink, as shown
below: “dual-pack” devices, containing two transistors are fitted to 30kVA mod-
els; and “single-pack” devices are used in 40/60kVA models.

Figure 11-5: IGBT Layout and internal circuit

G2
G2 E2
C2/E1 E2 C1 E2

C1
C2/E1 E2

E1 E1
G1 G1

Dual-Pack Device

E
E C E C
E

G G

Single-Pack Device

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SECTION 11 - Troubleshooting 7200 Series UPS Service Manual
CHAPTER 4 - Functional Check Procedures

When testing an IGBT, the measured values may vary slightly from those given
below.

Check Procedure
1. Ensure the power rectifier is shut-down and battery circuit breaker is open.
2. Wait 2 minutes to allow the DC Busbar capacitors time to discharge: verify
that the bus voltage is zero before proceeding.
3. Disconnect the cables from the IGBT to be tested.
4. With reference to Table 11-7 and Figure 11-5; carry out a check of the imped-
ances across the IGBT terminals using a DVM set to the “Diode” range.
Note: Table 11-7 describes the method of checking the two IGBTs in a “Dual
Pack” device independently.
5. If the indicated values are different those shown, or if the device fails to
switch ON/OFF then it must be regarded as unserviceable and replaced.

Caution When replacing an IGBT ensure that the new component is of the correct type
and part number (do not “mix” IGBTs in an inverter section). Smear the mating
surface of the replacement part with suitable heat-sink compound before fitting.

Table 11-6: Single-Pack device checks

DVM DVM DVM

Action +ve -ve Indication Interpretation
Lead Lead (mV)

Connect DVM across the emitter-collector C E OL IGBT switched off in a

junction serviceable condition

reverse DVM leads to check internal diode E C 0.388 Diode Forward Resistance

Reconnect DVM to original polarity C E OL

Touch the +ve DVM lead to the gate G E The device should turn ON

Recheck the Emitter-Collector junction C E 0.445 This low reading indicates

that the device is turned on
(Note it will remain ON
under the present
circumstances due to its
internal Cge capacitance

Turn the device OFF by shorting G and E C E OL High resistance indicates

that the device is OFF

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7200 Series UPS Service Manual SECTION 11 - Troubleshooting
CHAPTER 4 - Functional Check Procedures

Table 11-7: Dual-Pack device checks

DVM DVM DVM

Action +ve -ve Indication Interpretation
Lead Lead (mV)

Checking IGBT2

Connect DVM across the emitter-collector C2 E1 E2 OL IGBT switched off in a

junction serviceable condition

reverse DVM leads to check internal diode E2 C2 E1 0.388 Diode Forward Resistance

Reconnect DVM to original polarity C2 E1 E2 OL

Touch the +ve DVM lead to the gate G2 E2 The device should turn ON

Recheck the Emitter-Collector junction C2 E1 E2 0.445 This low reading indicates

that the device is turned on
(Note it will remain ON
under the present
circumstances due to its
internal Cge capacitance

Turn the device OFF by shorting G2 and E2 C2 E1 E2 OL High resistance indicates

that the device is OFF

Checking IGBT1

Connect DVM across the emitter-collector E2 C1 OL IGBT switched off in a

junction serviceable condition

reverse DVM leads to check internal diode E2 C1 0.388 Diode Forward Resistance

Reconnect DVM to original polarity E2 C1 OL

Touch the +ve DVM lead to the gate G1 E1 The device should turn ON

Recheck the Emitter-Collector junction E2 C1 0.445 This low reading indicates

that the device is turned on
(Note it will remain ON
under the present
circumstances due to its
internal Cge capacitance

Turn the device OFF by shorting G1 and E1 E2 C1 OL High resistance indicates

that the device is OFF

4.3.3 Shorted AC filter capacitor checks

1. Transfer the load to the Maintenance Bypass supply.
2. Totally power-down the UPS.
3. Allow sufficient time for the DC filter capacitors to fully discharge – verify
with DC voltmeter (DVM) that the DC filter capacitors are safe to touch.
4. Verify with DC voltmeter (DVM) that the AC filter capacitors are safe to
touch.
5. Isolate each capacitor by disconnecting each terminal connection.
6. Using an ohmmeter (DVM on Resistance range) check the following:

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SECTION 11 - Troubleshooting 7200 Series UPS Service Manual
CHAPTER 4 - Functional Check Procedures

a) Connect the ohmmeter between the capacitor terminals and verify that the
capacitor charges up (eventually the meter will indicate OL).
b) Measure the resistance between each capacitor terminal and ground
(capacitor body earth) – this should indicate open circuit in each case.
7. Replace any capacitor that fails the above checks.

4.3.4 Open-circuit AC filter capacitor checks

1. Transfer the load to the Maintenance Bypass supply.
2. Totally power-down the UPS.
3. Allow sufficient time for the DC filter capacitors to fully discharge – verify
with DC voltmeter (DVM) that the DC filter capacitors are safe to touch.
4. Verify with DC voltmeter (DVM) that the AC filter capacitors are safe to
touch.

Check method 1
1. Isolate each capacitor by disconnecting each terminal connection.
2. Connect a shorting link across both capacitor terminals, and at the same time
connect an ohmmeter (DVM) across the shorted terminals (i.e. meter should
indicate 0 Ohms – short-circuit).
3. Remove the shorting link and note the time taken by the meter indication to
rise from 0 Ohms to OL as the capacitor charges up to the meter voltage – this
should be of the order of 20 seconds on a suitable meter range.
4. Perform this check on all the AC filter capacitors and compare the results. If
any capacitor has a seriously reduced time constant compared to the others
then it should be replaced.

Check method 2
The expected filter current on each delta-connected main power wire with the in-
verter running on no-load is approximately 80% of the units nominal kVA rating
– e.g. on a 60kVA unit wires 9, 10, 11 should carry approximately 48A.
1. If possible, run the inverter (following the standard start-up procedure
described in the Users Manual).
2. Measure the filter current on all three phases and verify that the spread is bal-
anced to within 80%. An unbalanced, or low, indication indicates an open cir-
cuit capacitor on the appropriate filter leg – replace as necessary.
3. If the inverter cannot be started, it is possible to connect the filter’s delta
power wires directly to the 3 phase mains supply using appropriate fusing
(e.g. rectifier fuses) and check for a balanced current as described above.

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7200 Series UPS Service Manual SECTION 11 - Troubleshooting
CHAPTER 4 - Functional Check Procedures

4.4 How to check the Static Bypass power components

Most static bypass power problems are likely to be due too faulty bypass SCRs,
as detailed in the table below.

Figure 11-6: Static Bypass power component checks

Symptoms Possible causes

Inverter overload or high DC bus Short-circuit bypass SCR

overvoltage upon taking over the load
from the bypass.

Load failure when load transferred to Open-circuit bypass SCR

bypass.
Alarm #15 [BYP: SCR FAILURE]
annunciated

Bypass-to-inverter transfer count exceed. Output contactor K1 failure

Alarm #60 [BYP: XFER COUNT
BLOCK] annunciated

4.4.1 Short-circuit bypass SCR checks

When the UPS is started, the load is initially connected to the static bypass. Once
the inverter has run-up to full voltage (approximately 5 seconds), the preferred
action is to close the output contactor (K1) and open the bypass SCRs. However,
if a bypass SCR is short-circuited (or slow to turn off), the mains will back-feed
through the inverter to the DC bus in an uncontrolled manner (the inverter chang-
es the mains to DC). This will cause the DC bus voltage to either decrease (caus-
ing DC undervoltage trip or inverter overloading), or increase (causing DC
overvoltage trip).
1. Transfer the load to the Maintenance Bypass supply and open the output iso-
lator.
2. Turn the Inverter OFF and the Static Bypass ON using Q2 & Q1 on the UPS
Logic Board.
3. Using a dual-channel oscilloscope, monitor the output lines ahead of the out-
put isolator – i.e. on the inverter/static switch side of the output isolator. That
is, monitor the three output phases in “pairs” to compare their waveforms.
4. Using Q1 on the UPS Logic Board, turn OFF the bypass SCRs and check that
the traces on the oscilloscope indicate an instantaneous cut-off of the mains
voltage when the bypass SCRs cease their conduction – see the waveforms
illustrated below.
5. From the following waveforms, determine the SCRs’ status and replace if
necessary, after first powering down the UPS.

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SECTION 11 - Troubleshooting 7200 Series UPS Service Manual
CHAPTER 4 - Functional Check Procedures

Figure 11-7: Output voltage waveforms

Good blocking characteristics

Slow/lazy SCR on negative side

Replace the faulty device

Shorted SCR on negative side

Replace the faulty device

4.4.2 Open-circuit bypass SCR

An open-circuit bypass SCR will only be recognised by the electronics when the
load is on bypass. The voltage drop across the device is monitored when it is con-
ducting, and if the voltage rises above 50V (approx.) the bypass is latched off after
a few cycles. Alarm #15 [BYP: SCR FAILURE] is annunciated.
1. Transfer the load to the Maintenance Bypass supply and open the output iso-
lator.
2. Turn the Inverter OFF and the Static Bypass ON using Q2 & Q1 on the UPS
Logic Board.
3. Using a dual-channel oscilloscope, monitor the output lines ahead of the out-
put isolator – i.e. on the inverter/static switch side of the output isolator. That
is, monitor the three output phases in “pairs” to compare their waveforms.
4. Run the inverter and check the output for a true three-phase ac sinewave.
5. Using Q2 on the UPS Logic Board, turn OFF the inverter and check that the
traces on the oscilloscope indicate a true three-phase ac sinewave from the
bypass mains. If any SCR is open-circuit it will fail to conduct and the miss-
ing half-wave will be instantly recognisable from the output waveform.
6. If a faulty SCR is identified, replace it after first powering down the UPS.

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7200 Series UPS Service Manual SECTION 11 - Troubleshooting
CHAPTER 4 - Functional Check Procedures

4.4.3 Output contactor failure

If it is not possible to energise, and therefore close, the output contactor (K1), the
transfer control logic will attempt to, by repeatedly transferring between inverter
and bypass, as described below.
1. The inverter voltage monitor will detect that the inverter voltage is valid and
initiate a load transfer by closing K1 and opening the static bypass SCRs.
2. If K1 fails to close, the critical bus (output) voltage monitor will sense a lack
of voltage due to the non-closure of K1 and immediately re-energise the
bypass SCRs.
3. The inverter voltage monitor still “sees” a valid inverter voltage and will
attempt to energise K1 again after a delay of 5 seconds.
4. Once again, if K1 fails to close, the critical bus (output) voltage monitor will
sense a lack of voltage due to the non-closure of K1 and immediately re-ener-
gise the bypass SCRs.

As you can see, this cycle is repetitive and would lead to 12 transfer attempts over
a one minute period. However, this exceeds the “transfer lock-out” circuit’s max-
imum of 8 transfers in one minute, and will cause the circuit to latch out and an-
nunciate alarm #60 [BYP: XFER COUNT BLOCK]. Note that this condition must
be reset by pressing PS1 on the UPS Logic Board.

1. Transfer the load to the Maintenance Bypass supply.

2. Totally power-down the UPS.
3. Allow sufficient time for the DC filter capacitors to fully discharge – verify
with DC voltmeter (DVM) that the DC filter capacitors are safe to touch.
4. Using a DVM, check the resistance of the output contactor’s coil (440V).
This should be approximately 30-38kOhms. Replace the coil if found faulty.
5. Check the connections from the Static Switch Driver Board to the contactor
coil (wires 37/38), also wires 39/40 from the Static Switch Driver Board to
the DC Bus.
6. If the above checks prove satisfactory, start the inverter in the usual manner
but open the static bypass input isolator. This forces the electronics to select
“load-on-inverter”, and attempt to close K1 (if the inverter voltage is valid).
7. Carefully, measure the DC voltage across K1 coil at terminals A1-A2. This
should equal the DC Busbar float voltage. If this voltage is not present then
replace the Static Switch Driver Board.

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SECTION 11 - Troubleshooting 7200 Series UPS Service Manual
CHAPTER 4 - Functional Check Procedures

11-52 S10-c4.fm5 - Issue 2 Dated 21/08/97

 Section 12: Spare Parts

Chapter 1 - Spares Parts

1.1 7200 Series 30kVA Part Nº 5410305-R ................................................. 12-1
1.2 7200 Series 30kVA Part Nº 5410303-P ................................................. 12-2
1.3 7200 Series 40kVA Part Nº 5410307-T ................................................. 12-3
1.4 7200 Series 40kVA Part Nº 5410304-Q ................................................. 12-4
1.5 7200 Series 60kVA Part Nº 5410310-W ................................................ 12-5
1.6 7200 Series 60kVA Part Nº 5410308-U ................................................. 12-6
1.7 7200 Series 30-60kVA Distributor Parts ................................................ 12-7

s-11.fm5 - Issue 2 Dated 21/08/97 i

SECTION 12 - Spare Parts 7200 Series UPS Service Manual

ii s-11.fm5 - Issue 2 Dated 21/08/97

 Section 12:

Chapter 1 - Spares Parts

1.1 7200 Series 30kVA Part Nº 5410305-R

Note: This parts list applies to 30kVA models manufactured after March 1997.

Part No Description Qty

0010701P Output Contactor 3P/55A 440VDC (K1) 1*

0134005B Current Tranducer 100A (T9,T10,T11) 1

0301004C Fuse 1A-500VDC Size 10.5x38 (F1-F9) 9*

0304209J Fuse 100A-660V Extra Fast (F10-F13) 4*

0602096O Resistor 6.8k - 50W - T5% (R1,R2) 1

0700007J Axial Fan 220V - 160m3/h (E1-E3) 1*

0804114M IGBT Module 2X150A 1200V (V1-V3) 2*

0821016O SCR Assembly 40A 1400V (V4-V6 bypass) 3

0821017P SCR Assembly 60A 1400V (V1-V3 rectifier) 3

1100115D Transformer 1Ph 60VA (T2,T3) 1

4503028K DC Power Supply PCB 1

4503030M AC/DC Power Supply PCB 1

4519015H IGBT Driver PCB 1*

4520074A Rectifier Logic PCB 1

4530025T Inverter Logic PCB 1

4540043B RC Board For SCR 1

4542040W Rectifier Impulse PCB 1

4542043Z Static Switch Impulse PCB 1

4550007H UPS Logic PCB 1*

4550005F Microprocessor Display PCB 1

4590054O High Voltage Interface PCB 1*

4520067T Battery Breaker Control PCB 1

0562057P AC Filter Capacitor – 50µF 550V (C5-C10) 2*

0527154K DC Filter Capacitor (C1-C4) 2

0001712W Power Isolator (Q1-Q4) 1

0313006S Heatsink Thermostat (E1) 1

1906012E DC Fuse Micro-switch 1

Note: * recommended minumum holdings for 3 modules or less

s11-c1.fm5 - Issue 2 Dated 21/08/97 12-1

SECTION 12 - Spares Parts 7200 Series UPS Service Manual
CHAPTER 1 - Recommended Spares Kits

1.2 7200 Series 30kVA Part Nº 5410303-P

Note: This parts list applies to 30kVA models manufactured before March 1997.

Part No Description Qty

0010701P Output Contactor 3P/55A 440VDC (K1) 1*

0134005B Current Tranducer 100A (T9,T10,T11) 1

0301004C Fuse 1A-500VDC Size 10.5x38 (F1-F9) 9*

0304209J Fuse 100A-660V Extra Fast (F10-F13) 4*

0602096O Resistor 6.8k - 50W - T5% (R1,R2) 1

0700007J Axial Fan 220V - 160m3/h (E1-E3) 1*

0804114M IGBT Module 2X150A 1200V (V1-V3) 2*

0821016O SCR Assembly 40A 1400V (V4-V6 bypass) 3

0821017P SCR Assembly 60A 1400V (V1-V3 rectifier) 3

1100115D Transformer 1Ph 60VA (T2,T3) 1

4503028K DC Power Supply PCB 1

4503030M AC/DC Power Supply PCB 1

4519015H IGBT Driver PCB 1*

4520074A Rectifier Logic PCB 1

4530024S Inverter Logic PCB 1

4540043B RC Board For SCR 1

4542040W Rectifier Impulse PCB 1

4542041X Static Switch Impulse PCB 1

4550004E UPS Logic PCB 1*

4550005F Microprocessor Display PCB 1

4590054O High Voltage Interface PCB 1*

4520067T Battery Breaker Control PCB 1

0562057P AC Filter Capacitor – 50µF 550V (C5-C10) 2*

0527154K DC Filter Capacitor (C1-C4) 2

0001712W Power Isolator (Q1-Q4) 1

0313006S Heatsink Thermostat (E1) 1

1906012E DC Fuse Micro-switch 1

Note: * recommended minumum holdings for 3 modules or less

12-2 s11-c1.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual SECTION 12 - Spares Parts
CHAPTER 1 - Recommended Spares Kits

1.3 7200 Series 40kVA Part Nº 5410307-T

Note: This parts list applies to 40kVA models manufactured after March 1997.

Part No Description Qty

0010703R Output Contactor3P/90A 440VDC (K1) 1*

0134006C Current Tranducer 300A (T9-T11) 1

0301004C Fuse 1A-500VDC Size 10.5x38 (F1-F9) 9*

0304211L Fuse 160A-660V Extra Fast (F10-F13) 4*

0602093L Resistor 3.3k - 50W - T5% (R1,R2) 1

0700007J Axial Fan 220V - 160m3/h (E1-E6) 1*

0804112K IGBT Module 300A 1200V (V1-V6) 2*

0821015N SCR Assembly 90A 1400V (V1-V3 rectifier) 3

0821017P SCR Assembly 60A 1400V (V4-V6 bypass) 3

1100115D Transformer 1Ph 60VA (T2,T3) 1

4503028K DC Power Supply PCB 1

4503030M AC/DC Power Supply PCB 1

4519015H IGBT Driver PCB 1*

4520074A Rectifier Logic PCB 1

4530025T Inverter Logic PCB 1

4540043B RC Board For SCR 1

4542040W Rectifier Impulse PCB 1

4542043Z Static Switch Impulse PCB 1

4550007H UPS Logic PCB 1*

4550005F Microprocessor Display PCB 1

4590054O High Voltage Interface PCB 1*

4520067T Battery Breaker Control PCB 1

0562058Q AC Filter Capacitor – 66µF 550V (C5-C10) 2*

0521160Q DC Filter Capacitor (C1-C4) 2

0001712W Power Isolator (Q1-Q4) 1

0313006S Heatsink Thermostat (E1) 1

1906012E DC Fuse Micro-switch 1

Note: * recommended minumum holdings for 3 modules or less

s11-c1.fm5 - Issue 2 Dated 21/08/97 12-3

SECTION 12 - Spares Parts 7200 Series UPS Service Manual
CHAPTER 1 - Recommended Spares Kits

1.4 7200 Series 40kVA Part Nº 5410304-Q

Note: This parts list applies to 40kVA models manufactured before March 1997.

Part No Description Qty

0010703R Output Contactor3P/90A 440VDC (K1) 1*

0134006C Current Tranducer 300A (T9-T11) 1

0301004C Fuse 1A-500VDC Size 10.5x38 (F1-F9) 9*

0304211L Fuse 160A-660V Extra Fast (F10-F13) 4*

0602093L Resistor 3.3k - 50W - T5% (R1,R2) 1

0700007J Axial Fan 220V - 160m3/h (E1-E6) 1*

0804112K IGBT Module 300A 1200V (V1-V6) 2*

0821015N SCR Assembly 90A 1400V (V1-V3 rectifier) 3

0821017P SCR Assembly 60A 1400V (V4-V6 bypass) 3

1100115D Transformer 1Ph 60VA (T2,T3) 1

4503028K DC Power Supply PCB 1

4503030M AC/DC Power Supply PCB 1

4519015H IGBT Driver PCB 1*

4520074A Rectifier Logic PCB 1

4530024S Inverter Logic PCB 1

4540043B RC Board For SCR 1

4542040W Rectifier Impulse PCB 1

4542041X Static Switch Impulse PCB 1

4550004E UPS Logic PCB 1*

4550005F Microprocessor Display PCB 1

4590054O High Voltage Interface PCB 1*

4520067T Battery Breaker Control PCB 1

0562058Q AC Filter Capacitor – 66µF 550V (C5-C10) 2*

0521160Q DC Filter Capacitor (C1-C4) 2

0001712W Power Isolator (Q1-Q4) 1

0313006S Heatsink Thermostat (E1) 1

1906012E DC Fuse Micro-switch 1

Note: * recommended minumum holdings for 3 modules or less

12-4 s11-c1.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual SECTION 12 - Spares Parts
CHAPTER 1 - Recommended Spares Kits

1.5 7200 Series 60kVA Part Nº 5410310-W

Note: This parts list applies to 60kVA models manufactured after March 1997

Part No Description Qty

0010703R Output Contactor 3P/90A 440VDC (K1) 1*

0134006C Current Tranducer 300A (T9-T11) 1

0301004C Fuse 1A-500VDC Size 10.5x38 (F1-F9) 9*

0304212M Fuse 200A-660V Extra Fast (F10-F13) 4*

0602093L Resistor 3.3k - 50W - T5% (R1,R2) 1

0700007J Axial Fan 220V - 160m3/h (E1-E6) 1*

0804112K IGBT Module 300A 1200V (V1-V6) 2*

0821011J SCR Module 130A 1400V (V1-V3 rectifier) 3

0821015N SCR Assembly 90A 1400V (V4-V6 bypass) 3

1100115D Transformer 1Ph 60VA (T2,T3) 1

4503028K DC Power Supply PCB 1

4503030M AC/DC Power Supply PCB 1

4519015H IGBT Driver PCB 1*

4520074A Rectifier Logic PCB 1

4530025T Inverter Logic PCB 1

4540043B RC Board For SCR 1

4542040W Rectifier Impulse PCB 1

4542043Z Static Switch Impulse PCB 1

4550007H UPS Logic PCB 1*

4550005F Microprocessor Display PCB 1

4590054O High Voltage Interface PCB 1*

4520067T Battery Breaker Control PCB 1

0562059R AC Filter Capacitor – 100µF 550V (C5-C10) 2*

0521161R DC Filter Capacitor (C1-C4) 2

0001712W Power Isolator (Q1-Q4) 1

0313006S Heatsink Thermostat (E1) 1

1906012E DC Fuse Micro-switch 1

Note: * recommended minumum holdings for 3 modules or less

s11-c1.fm5 - Issue 2 Dated 21/08/97 12-5

SECTION 12 - Spares Parts 7200 Series UPS Service Manual
CHAPTER 1 - Recommended Spares Kits

1.6 7200 Series 60kVA Part Nº 5410308-U

Note: This parts list applies to 60kVA models manufactured before March 1997

Part No Description Qty

0010703R Output Contactor 3P/90A 440VDC (K1) 1*

0134006C Current Tranducer 300A (T9-T11) 1

0301004C Fuse 1A-500VDC Size 10.5x38 (F1-F9) 9*

0304212M Fuse 200A-660V Extra Fast (F10-F13) 4*

0602093L Resistor 3.3k - 50W - T5% (R1,R2) 1

0700007J Axial Fan 220V - 160m3/h (E1-E6) 1*

0804112K IGBT Module 300A 1200V (V1-V6) 2*

0821011J SCR Module 130A 1400V (V1-V3 rectifier) 3

0821015N SCR Assembly 90A 1400V (V4-V6 bypass) 3

1100115D Transformer 1Ph 60VA (T2,T3) 1

4503028K DC Power Supply PCB 1

4503030M AC/DC Power Supply PCB 1

4519015H IGBT Driver PCB 1*

4520074A Rectifier Logic PCB 1

4530024S Inverter Logic PCB 1

4540043B RC Board For SCR 1

4542040W Rectifier Impulse PCB 1

4542041X Static Switch Impulse PCB 1

4550004E UPS Logic PCB 1*

4550005F Microprocessor Display PCB 1

4590054O High Voltage Interface PCB 1*

4520067T Battery Breaker Control PCB 1

0562059R AC Filter Capacitor – 100µF 550V (C5-C10) 2*

0521161R DC Filter Capacitor (C1-C4) 2

0001712W Power Isolator (Q1-Q4) 1

0313006S Heatsink Thermostat (E1) 1

1906012E DC Fuse Micro-switch 1

Note: * recommended minumum holdings for 3 modules or less

12-6 s11-c1.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual SECTION 12 - Spares Parts
CHAPTER 1 - Recommended Spares Kits

1.7 7200 Series 30-60kVA Distributor Parts

Part No Description Qty

0010701P Output Contactor 3P/55A 440VDC (30kVA) (K1) 1*

0010703R Output Contactor 3P/90A 440VDC (40/60kVA) (K1) 1*

0134005B Current Tranducer 100A (30kVA) (T9-T11) 1

0134006C Current Tranducer 300A (40/60kVA) (T9-T11) 1

0301004C Fuse 1A-500VDC Size 10.5x38 (30-60kVA) (F1-F9) 9*

0304209J Fuse 100A-660V Extra Fast (30kVA) (F10-F13) 4*

0304211L Fuse 160A-660V Extra Fast (40kVA) (F10-F13) 4*

0304212M Fuse 200A-660V Extra Fast (60kVA) (F10-F13) 4*

0602096O Resistor 6.8k - 50W - T5% (30kVA) (R1,R2) 1

0602093L Resistor 3.3k - 50W - T5% (40/60kVA) (R1,R2) 1

0700007J Axial Fan 220V - 160m3/h (30-60kVA) (E1-E6) 1*

0804114M IGBT Module 2 x 150A 1200V (30kVA) (V1-V6) 2*

0804112K IGBT Module 300A 1200V (40/60kVA) (V1-V6) 2*

0821016O SCR Module 40A 1400V (30kVA Bypass) (V4-V6) 3*

0821017P SCR Module 60A 1400V (30kVA Rect. / 40kVA Byp.) 3*

0821015N SCR Module 90A 1400V (40kVA Rect. / 60kVA Byp.) 3*

0821011J SCR Module 130A 1400V (60kVA Rect.) (V1-V3) 3*

1100115D Transformer 1Ph 60VA (30-60kVA) (T2,T3) 1

4503028K DC Power Supply PCB (30-60kVA) 1*

4503030M AC/DC Power Supply PCB (30-60kVA) 1

4519015H IGBT Driver PCB (30-60kVA) 1*

4520074A Rectifier Logic PCB (30-60kVA) 1*

4530025T Inverter Logic PCB (30-60kVA) 1*

4540043B RC Board For SCR (30-60kVA) 1

4542040W Rectifier Impulse PCB (30-60kVA) 1

4542043Z Static Switch Impulse PCB (30-60kVA) 1*

4550007H UPS Logic PCB (30-60kVA) 1*

4550005F Microprocessor Display PCB (30-60kVA) 1*

4590054O High Voltage Interface PCB (30-60kVA) 1*

4520067T Battery Breaker Control PCB (30-60kVA) 1

0562057P AC Filter Capacitor – 50µF 550V (30kVA) (C5-C10) 2*

0562058Q AC Filter Capacitor – 66µF 550V (40kVA) (C5-C10) 2*

0562059R AC Filter Capacitor – 100µF 550V (60kVA) (C5-C10) 2*

0521154K DC Filter Capacitor (30kVA) (C1-C4) 2

s11-c1.fm5 - Issue 2 Dated 21/08/97 12-7

SECTION 12 - Spares Parts 7200 Series UPS Service Manual
CHAPTER 1 - Recommended Spares Kits

Part No Description Qty

0521160Q DC Filter Capacitor (40kVA) (C1-C4) 2

0521161R DC Filter Capacitor (60kVA) (C1-C4) 2

0001712W Power Isolator (30-60kVA) (Q1-Q4) 1

0313006S Heatsink Thermostat (30-60kVA) (E1) 1

1906012E DC Fuse Micro-switch (30-60kVA) 1

Note: * recommended minimum holdings for 10 modules or less (approximately 3 of

each module rating)

12-8 s11-c1.fm5 - Issue 2 Dated 21/08/97

 Section 13: Appendices

Appendix A - Device specifications

Appendix B - CAN Bus
Appendix C - PCB Layout diagrams
Appendix D - PCB Link selection details
Appendix E - UPS Module General Specifiication

S-12.fm5 - Issue 2 Dated 21/08/97 i

SECTION 13 - Appendices 7200 Series UPS Service Manual

ii S-12.fm5 - Issue 2 Dated 21/08/97

 A:

Appendix A : Device Specifications

A.1 74HCT245 – Octal 3-state, non-inverting bus transceiver

The HCT245 is a 3-state non-inverting transceiver that is used for 2-way asyn-
chronous communication between data busses. The device has an active-low
Output Enable pin, which is used to place the I/O ports into high-impedance
states. The Direction control determines whether data flows from A-to-B or from
B-to-A.

Figure A-1: 74HCT245

2 18 Direction 1 20 Vcc (+5V)
A0 B0
3 17 A0 2 19 OE
A1 B1
4 16 A1 3 18 B0
A2 B2
5 15 A2 4 17 B1
A3 B3
6 14 A3 5 16 B2
A4 B4
7 13 A4 6 15 B3
A5 B5
8 12 A5 7 14 B4
A6 B6
9 11 A6 8 13 B5
A7 B7
A7 9 12 B6
Gnd 10 11 B7

1
Direction
Output 19
Enable

CONTROL INPUTS

Output
Direction Operation
Enable

L L Data transmitted from bus B to bus A

L H Data transmitted from bus A to bus B

H X Busses isolated – (Hi-impedance state)

App-a.fm5 - Issue 2 Dated 21/08/97 A-1

Appendix A 7200 Series UPS Service Manual
Device specification

A.2 74HCT273 Octal D-type Flip-Flop

The HCT273 consists of eight D-type flip-flops with common Clock and Reset
inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input.
Reset is asynchronous (i.e. at any time) and active low.

Figure A-2: 74HCT273

2 3 Reset 1 20 Vcc
D0 Q0
4 5 Q0 2 19 Q7
D1 Q1
7 6 D0 3 18 D7
D2 Q2
8 9 D1 4 17 D6
D3 Q3
13 12 Q1 5 16 Q6
D4 Q4
14 15 Q2 6 15 Q5
D5 Q5
17 16 D2 7 14 D5
D6 Q6
18 19 D3 8 13 D4
D7 Q7
Q3 9 12 Q4
Gnd 10 11 Clock

11
Clock
Reset 1

INPUTS OUTPUTS

Reset Clock D Q

L X X L

H H H

H L L

H L X No change

H X No change

A-2 App-a.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual Appendix A
Device specification

A.3 Type 4052 Dual 4-channel Multiplexer

The 4052 device contains two 4-way multiplexer switches controlled by two ad-
dress (select) inputs. Each switch is identified as “X” or “Y”. An ‘inhibit’ input
turns off both switches when set high.

Figure A-3: 4052 Multiplexer

6 1Y 1 16 Vdd
Inhibit
10 3Y 2 15 3X
Select (A)
9 Y 3 14 2X
Select (B)
4Y 4 13 X
12
1X 2Y 5 12 1X
14
2X 13 Inhibit 6 11 4X
15 X
3X Vee 7 10 Sel (A)
11
4X Vss 8 9 Sel (B)
1
1Y
5
2Y 3
2 Y
3Y
4
4Y

INPUTS OUTPUTS

Inhibit A B X Y

L L L 1X 1Y

L L H 2X 2Y

L H L 3X 3Y

L H H 4X 4Y

H X X None None

App-a.fm5 - Issue 2 Dated 21/08/97 A-3

Appendix A 7200 Series UPS Service Manual
Device specification

A.4 74HC573 Octal D-type Flip-Flop

The 74HCT573 consists of eight D-type flip-flops with common Latch Enable
and Output Enable inputs. Each flip-flop is loaded with a low-to-high transition
of the Latch Enable input. Output Enable is asynchronous and active low.

Figure A-4: 74HCT573

2 19 O/enable Vcc
D0 Q0 1 20
3 18 D0 2 19 Q0
D1 Q1
4 17 D1 3 18 Q1
D2 Q2
5 16 D2 Q2
D3 Q3 4 17
6 15 D3 5 16 Q3
D4 Q4
7 14 D4 6 15 Q4
D5 Q5
8 13 D5 Q5
D6 Q6 7 14
9 12 D6 8 13 Q6
D7 Q7
D7 9 12 Q7
Gnd 10 11 Latch Enable

11
Latch Enable
Output Enable 1

INPUTS OUTPUTS

Output Enable Latch Enable D Q

L H H H

L H L L

L L X No change

H X X Hi-Z

A-4 App-a.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual Appendix A
Device specification

A.5 SN75176A Differential Bus Transceiver

The SN75176 differential bus transceiver is designed for bi-directional data com-
munication on multi-point bus transmission lines. It is designed for balanced
transmission lines and meets EIA Standard RS-422A.

Figure A-5: SN75176A

3 RD 1 8 Vcc
DE Driver
RE 2 7 DD/RI
DI 4 DE 3 6 DD/RI
DI 4 5 GND
RE 2
6 DD/RI
RD 1 BUS
7 DD/RI
Receiver

Function Table (Driver)

INPUTS OUTPUTS

Data In (DI) Data Enable (DE) DD/RI DD/RI

H H H L

L H L H

X L Hi-Z Hi-Z

Function Table (Receiver)

DIFFERENTIAL INPUTS OUTPUTS

A–B RE RD

VID > 0.2V L H

-0.2V < VID < 0.2V L ?

VID < -0.2V L L

X H Hi-Z

The device combines a 3-state differential line driver and a differential-input line
receiver, both of which operate from a single +5V power supply. The driver and
receiver have active-high and active-low enables, (DE) and (RE) respectively,
that can be externally connected together to function as direction control.
The driver differential outputs and the receiver differential inputs are connected
together internally to form a differential I/O bus port which is designed to offer
minimum loading to the bus whenever the driver is disabled. The receiver oper-
ates on a differential input greater then 0.2mV, as shown in the above table.
These ports feature good common-mode noise rejection when used on a balance
line making them ideal for use over party-line applications.

App-a.fm5 - Issue 2 Dated 21/08/97 A-5

Appendix A 7200 Series UPS Service Manual
Device specification

A.6 SN75155 Line Driver and Receiver

The SN75155 is a line driver and receiver that is designed to satisfy the require-
ments of the standard interface between data terminal equipment (DTE) and data
communication equipment (DCE) as defined by EIA standard RS232.
A Response Control input (RTC) is provided for the receiver. A resistor, or resis-
tor and bias voltage, can be connected between the Response Control input and
ground to provide noise filtering.

Figure A-6: SN75155

1 Vcc- 1 8 Vcc+
Vcc-
8 DA 2 7 DY
Vcc+
RY 3 6 RTC
2 7 GND 4 5 RA
DA DY

4 REFERENCE
GND
REGULATOR

5 3
RA RY

6
RTC

A-6 App-a.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual Appendix A
Device specification

A.7 MAX232 Dual EIA-232 Driver/Receiver

The MAX232 is a dual driver/receiver that includes a capacitive voltage generator
to supply EIA-232 voltage levels from a single +5V supply.
Each receiver converts the EIA-232 inputs to 5V TTL/CMOS levels. These re-
ceivers have a typical threshold of 1.3V and a typical hysteresis of 0.5V, and can
accept ±30V inputs.
Each driver converts TTL/CMOS input levels into EIA-232 levels.

Figure A-7: MAX232

Vcc

16

1 C1+ 1 16 Vcc
C1+ C1+
VS+ 2 15 GND
2
3 2Vcc -1.5V VS+ C1- 3 14 T1OUT
C1- C1-
4 C2+ 4 13 R1IN
C2+ C2+ 6 C2- 5 12 R1OUT
-2Vcc +1.5V VS-
5 VS- 6 11 T1IN
C2- C2-
T2OUT 7 10 T2IN
11 14 R2IN 8 9 R2OUT
T1IN T1OUT

10 7
T2IN
T2OUT

12 13
R1OUT R1IN

R2OUT 9 8
R2IN

15

GND

App-a.fm5 - Issue 2 Dated 21/08/97 A-7

Appendix A 7200 Series UPS Service Manual
Device specification

A.8 8251A Programmable Communications interface

Figure A-8: 8251A

Data
DB0....DB7 Bus
Buffer Transmit
D2 1 28 D1
Buffer TxD
(P to S) D3 2 27 D0
RST RXD 3 26 Vcc(+5V)
CLK Read/Write GND(Vss) 4 25 RxC
C/D Control TxRDY
Transmit D4 5 24 DTR
RD Logic TxE
Control D5 6 23 RTS
WR TxC
D6 7 22 DSR
CS D7 8 21 RST
TxC 9 20 CLK
Receive WR 10 19 TxD
DSR Buffer RxD
CS 11 18 TxE
DTR (S to P)
Modem C/D 12 17 CTS
CTS Control
RD 13 16 SYNDET/BD
RTS RxRDY RxRDY 14 15 TxRDY
Receive
Control RxC
Internal SYNDET
Data Bus

A.8.1 Introduction
The 8521A is a Universal Synchronous/Asynchronous Receiver/Transmitter
(USART) designed for use with a wide range of microcomputers (CPUs).
In a communication environment, the device converts parallel data on the system
data bus into a serial format for transmission and also converts the incoming serial
communication line data into parallel form acceptable to the data bus. In carrying
out these transformations the 8251A also deletes or inserts ‘framing’ bits or char-
acters that are required by the communication mode in use. Data is passed be-
tween the ‘transmit’ or ‘receive’ sections and the ‘data bus buffer’ by means of an
internal 8-bit data bus, with the transfer between these sections being controlled
by the ‘read/write control logic’ block at a rate determined by its clock input.
However the serialised information is clocked into the ‘transmit buffer’ (from the
internal bus) and ‘receive buffer’ (from communications line) by independent ex-
ternal clock signal – TxC and RxC respectively.
Like other I/O devices in a microcomputer system, the 8251A functional config-
uration is programmed by the system’s software for maximum flexibility. Thus in
addition to the system data the 8251A also receives Mode/command words from
the CPU which determines its operating parameters such as baud-rate, character
length, number of start/stop bits, parity and synchronous/asynchronous mode of
operation. The device differentiate between system data and Mode/command
words by observing the state of its (C/D) input, as described below.
The 8251A has facilities that allow the CPU to read the status of the device at any
time during its functional operation – activated when (RD)=0 and (C/D) =1 (see
table below). Some of the bits in the status register have identical meanings to ex-
ternal output pins, so that the 8251A can be used in a completely polled or inter-
rupt-driven environment. The following information is available from the status
register (described in more detail later):

A-8 App-a.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual Appendix A
Device specification

• Transmitter section ready (TxRDY) (not identical to external TxRDY pin)

• Receiver section ready (RxRDY)
• Transmit buffer empty (TxE)
• Parity error
• Overrun error (CPU fails to read a character before the arrival of the next)
• Framing error (stop/start bit detection error)
• Synchronisation (SYNDET)
• Data Set Ready (DSR)

A.8.2 Functional description

Following is a description of the 8251A device based on the block diagram at the
top of the previous page:

Data Bus Buffer

This tri-state, bi-directional, 8-bit buffer interfaces the 8251A to the system data
bus. All transmitted and received data passes though the buffer together with
‘control words’ and ‘command words’.

Read/Write Control Logic

This functional block accepts inputs from the system control bus and generates
control signals for the overall device operation. It contains the ‘control word’ and
‘command word’ registers that store the various control formats for the device’s
functional definition. The control inputs are described below:
Chip Select (CS). This input allows the device to be individually selected from
other devices within its address range, and is active low. When this input is high
it is not possible to read from (or write to) to the device, and its data bus outputs
are driven to a high impedance state.
Read (RD). This input is taken low when the associated processor wishes to
read the data held in the 8251A’s Data Bus Buffer.
Write (WR). This input is taken low when the associated processor wishes to
transfer data from the system data bus to the 8251A’s Data Bus Buffer.
Control/Data (C/D). This input, in conjunction with the (RD) and (WR) in-
puts, informs the 8251A that the word on the system data bus is either a ‘data char-
acter’ or a ‘control/status’ information. A logic high indicates ‘data’ and low
indicates ‘control//status’ word.
As the above four inputs all affect the Read/Write functions these are summarized
in the table below:
Table A-1:

C/D RD WR CS DATA FLOW

0 0 1 0 CPU Reads Data from 8251A Data Bus Buffer

0 1 0 0 CPU Writes Data to 8251A Data Bus Buffer

1 0 1 0 CPU Reads Status Byte from 8251A Data Bus Buffer

1 1 0 0 CPU Writes Control Byte to 8251A Data Bus Buffer

X 1 1 0 Data Bus Buffer = High Z

X X X 1 Data Bus Buffer = High Z

App-a.fm5 - Issue 2 Dated 21/08/97 A-9

Appendix A 7200 Series UPS Service Manual
Device specification

Reset (RST). The 8251A assumes an idle state when this input is taken high.
And when it returns low it remains in this state until it receives a new ‘mode con-
trol’ instruction from the associated processor.
Clock (CLK). This input is used for internal timing within the 8251 and does
not control the transmit or receive rate. Generally, it should be at least 30 times
the transmit or receive rate.

Transmit buffer
The ‘transmit buffer’ accepts parallel data from the ‘data bus buffer’, converts it
to a serial bit-stream, inserts the appropriate characters or bits required by the
communication protocol in use, and outputs a composite serial data-stream on the
TxD output pin.

Transmit control
The ‘transmit control’ block manages all the activities associated with the trans-
mission of serial data. It accepts and issues signals both externally (described
below) and internally to accomplish this function.
Transmit Clock (TxC). The serial data on TxD is clocked out on the falling
edge of the TxC signal.
Transmitter Ready (TxRDY). This output goes high when data in the ‘data
bus buffer’ has been shifted into the ‘transmit buffer’ and informs the CPU that
the 8251A is ready to receive the next data character for transmission. TxRDY is
automatically reset by the leading edge of the WR input when a data character is
loaded from the CPU.
Transmitter Empty (TxE). The TxE output goes high when the transmitter
section has transmitted its data and the ‘transmit buffer’ is empty. It will remain
high until a new data byte is shifted into the ‘transmit buffer’.
This line can be used to indicate the end of a transmission mode, so that the CPU
“knows” when to “turn the line around” in the half-duplex operational mode.

Receive buffer
The ‘receive buffer’ accepts serial data from the transmission line (RxD), con-
verts it to a parallel format, checks for characters or bits required by the commu-
nication protocol in use, and sends an “assembled” character to the CPU via the
‘data bus buffer’.

Receive control
The ‘receive control’ block manages all receiver-related activities, including
‘start’, ‘stop’ and ‘parity’ bit detection and the detection of several error states.
The external signals associated with this block are:
Receiver Clock (RxC). The ‘receiver clock’ (RxD) controls the rate at which
the character is to be received. In “synchronous” mode, the baud rate (1x) is equal
to the actual frequency of (RxD). In “asynchronous” mode the baud rate is a frac-
tion of the actual (RxD) frequency as selected by the “mode” instruction. This can
be set to 1/16th or 1/64th of (RxC).
Receiver Ready (RxRDY). This output indicates to the processor that data has
been shifted into the receiver buffer from the receiver section and may now be
read. The signal is active high and is reset when the buffer is read by the proces-
sor.

A-10 App-a.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual Appendix A
Device specification

Sync Detect (SYN-DET). This signal is used only in the synchronous mode. It
can be either an input or output depending on whether the program is set for in-
ternal or external synchronisation. As an output, a high level indicates when the
sync character has been detected in the received data stream after the Internal
Synchronisation mode has been programmed. SYN-DET is reset when the status
buffer is read or when a reset signal is activated.
SYN-DET performs as an input when the External Synchronisation mode is pro-
grammed. External logic can supply a positive-going signal to indicate to the
8251 that synchronisation has been attained. This will cause it to initialise the as-
sembly of characters on the next falling edge of RxC. To successfully achieve
synchronisation, the SYN-DET signal should be maintained in a high condition
for at least one full cycle of RxC.

Modem control
The 8251A has a set of control inputs and outputs that can be used to simplify the
interface to almost any modem. The modem control signals are general purpose
in nature and can be used for functions other than modem control, if necessary.
Data Terminal Ready (DTR). This signal reflects the state of bit 1 in the
Command Instruction. It is commonly used to signal to an associated modem that
the 8251 is ready.
Data Set Ready (DSR). This input signal forms part of the status byte that may
be read by the processor. DSR is generally used as a response to DTR, by the
modem, to indicate that it too is ready. The signal acts only as a flag and does not
control any internal logic.
Request To Send (RTS). This signal reflects the state of bit 5 in the command
instruction. It is normally used to initiate a data transmission by requesting the
modem to prepare to send.
Clear To Send (CTS). This input is generally used as a response to RTS by a
modem, to indicate that transmission may begin.

App-a.fm5 - Issue 2 Dated 21/08/97 A-11

Appendix A 7200 Series UPS Service Manual
Device specification

A.9 UC3845 Current-mode PWM Controller

Figure A-9: UC3845

7 Type UC3845
Vcc
UVLO Current Mode PWM controller
S/R 5V
GND REF
5
8
Vref
7
2.5V Vref GOOD

OUTPUT
LOGIC
4 6
RT/CT OSCILLATOR
Toggle
V Error
S
Amp 2R 5
1
Vfb R

R PWM
2 Current
Comp 1V
Sense
Latch

3 Comparator
Isense

A.9.1 Introduction
The UC3845 integrated circuit provides features necessary to implement off-line
or dc-to-dc fixed-frequency current-mode control schemes with a minimum
number of external components.
Some of the internally implemented circuits are an ‘undervoltage lockout’
(UVLO) featuring a start-up current of less than 1 mA and a precision ‘voltage
reference’ trimmed for accuracy at the error amplifier input. Other internal cir-
cuits include logic to ensure latched operation, a pulse-width modulation (PWM)
comparator (which also provides current-limit control), and a totem-pole output
stage designed to source or sink high-peak current. The output stage, suitable for
driving N-channel MOSFETs, is low when it is in the off state.

A.9.2 Functional description

Input supply
The device can be powered by a single supply rail of up to 30V (Vcc/Gnd); but
when power is first applied the undervoltage lockout (UVLO) comparator holds
off the circuit’s operation until Vcc rises above 8.4V. Conversely, on power-down
UVLO turns off the device when Vcc falls below 7.6V.
If Vcc falls within the permissible operating voltage limits, the UVLO ‘sets’ an
S-R flip-flop which ‘enables’ a 5V reference voltage generator whose output is
presented to the external circuitry via pin 8 (Vref). In practice this stable reference
voltage can be used to bias the oscillator’s external frequency determining com-
ponents. Note that the 5V reference voltage is monitored by the ‘vref good logic’
block which inhibits the output gate if this voltage is in error. Vref is also divided
by two, and the resulting 2.5V reference voltage is internally connected to the
‘voltage error amp’ non-inverting input.

PWM Control
The output PWM signal at pin 6 is controlled by the PWM latch which is ‘set’ (pin
6 driven high) by the internal oscillator output going high. As the oscillator is of
fixed frequency this means that the leading edge of the output PWM pulses appear
at a regular interval irrespective of their adopted pulse-width.

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Device specification

The oscillator frequency is determined by external R-C components connected to

pin 4 (RT/CT). Generally, the timing resistor is connected between pin 8 (Vref)
and pin 4 (RT/CT); and the timing capacitor between pin 4 (RT/CT) and pin 5
(Gnd). The oscillator frequency is then calculated as:
1.72
F = -------------------
RT × C T
Note: In the UC3845 version of this device range the output PWM frequency is
only half the oscillator frequency due to the implementation of an extra T (toggle)
flip flop connected ahead of the output gate, which is included to limit the output
mark-to-space to 2:1 (i.e. maximum 50% duty cycle).
The PWM latch is ‘reset’ (pin 6 driven low) by the ‘current sense comparator’
when the current sense signal applied to pin 3 exceeds the level set by the ‘voltage
error amp’ output.
The ‘voltage error amp’ output is in turn determined by a voltage feedback signal
applied to pin 1 (Vfb) and its gain is set by the value of an external resistor con-
nected between pins 1 & 2. The Vfb signal therefore sets the threshold for the
‘current sense comparator’ which in then determines the PWM switching point.

Start Stop Control

The ‘demand’ output from the ‘volts error amp’ to the ‘current sense comparator’
is connected via two diodes and a 2:1 resistive attenuator; and is limited by a zener
to 1V at the comparator’s input. It is possible therefore to ‘stop’ the i.c’s internal
operation by either making pin 1 less than two diode drops (<1.2V) with respect
to ground, or by taking pin 3 greater than 1V.
In the former case, the ‘current sense comparator’ is effectively ‘seeing’ zero
demand from the ‘volts error amp’ and applies a permanent ‘reset’ to the ‘PWM
latch’. In the latter case the current sense signal is permanently greater than the
‘demand’ signal from the ‘volts error amp’ and the ‘current sense comparator’
again permanently resets the ‘PWM latch’.

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Appendix A 7200 Series UPS Service Manual
Device specification

A.10 PCA82C250 CAN Controller Interface

Figure A-10: PCA82C250

TxD 1 8 Rs(SI)
GND 2 7 CANH
Vcc 3 6 CANL
RxD 4 5 Vref

Vcc
3

1
TxD Protection

8 Slope/ Driver
Rs
Standby

CANH

CAN BUS
7
4
RxD 6
CANL

5 Reference
Vref
Voltage

2
GND

Table A-2: Truth table of CAN transceiver.

TxD CANH CANL RxD

0 CANH > (CANL+0.9V) 0

1 (or floating) Floating Floating 1

X Floating Floating X

>0.75VCC Floating Floating X

X floating if floating if X
VRs > 0.75VCC VRs > 0.75VCC

A.10.1 Introduction
The device combines a 3-state differential line driver and a differential-input line
receiver, both of which operate from a single +5V power supply.
The driver differential outputs and the receiver differential inputs are connected
together internally to form a differential I/O bus port which is designed to offer
minimum loading to the bus whenever the driver is disabled. The receiver oper-
ates on a differential input greater then 0.9V, as shown in the above table.
These ports feature good common-mode noise rejection when used on a balance
line making them ideal for use over party-line applications.

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Device specification

A.10.2 Functional Description

The PCA82C250 is the interface between the CAN protocol controller and the
physical bus. The device provides differential transmit capability to the bus and
differential receive capability to the CAN controller.
Pin 8 (Rs) allows three different modes of operation to be selected: high-speed,
slope control or standby. For high-speed operation, the transmitter output transis-
tors are simply switched on and off as fast as possible. In this mode, no measures
are taken to limit the rise and fall slope. Use of a shielded cable is recommended
to avoid RFI problems. The high-speed mode is selected by connecting pin 8 to
ground.
For lower speeds or shorter bus length, an unshielded twisted pair or a parallel
pair of wires can be used for the bus. To reduce RFI, the rise and fall slope should
be limited. The rise and fall slope can be programmed with a resistor connected
from pin 8 to ground. The slope is proportional to the current output at pin 8.
If a HIGH level is applied to pin 8, the circuit enters a low current standby mode.
In this mode, the transmitter is switched off and the receiver is switched to a low
current. If dominant bits are detected (differential bus voltage >0.9 V), RxD will
be switched to a LOW level. The microcontroller should react to this condition by
switching the transceiver back to normal operation (via pin 8). Because the re-
ceiver is slow in standby mode, the first message will be lost.
Table A-3: Rs Summary

CONDITION FORCED RESULTING VOLTAGE OR

MODE
AT Rs(SI) CURRENT AT Rs(SI)

VRs > 0.75VCC standby IRs < |10µA|

10 mA < IRs < 200 µA slope 0.4VCC < VRs < 0.6VCC
control

VRs < 0.3VCC high- IRs < -500µA

speed

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Appendix A 7200 Series UPS Service Manual
Device specification

A.11 80C166 Microcontroller

A.11.1 Introduction
The SAB 80C166 is the first representative of the Siemens SAB 80C166 family
of full featured single-chip CMOS microcontrollers. It combines high CPU per-
formance (up to 10 million instructions per second) with high peripheral function-
ality and enhanced I/O-capabilities; and offers the following major features:
• High performance 16-bit CPU with 4-stage pipeline
• Up to 256 KBytes linear address space for code and data
• 1 KByte on-chip RAM
• 32 KBytes on-chip ROM (SAB 83C166 only)
• Programmable external bus characteristics for different address ranges
• Multiplexed or demultiplexed, 8-Bit or 1 6-Bit external data bus
• 512 Bytes on-chip special function register area
• Idle and power down modes 8-channel interrupt-driven single-cycle data
transfer facilities via Peripheral Event Controller (PEC)
• 16-Priority-level interrupt system
• 10-Channel 10-bit A/D converter with 9.7µS conversion time
• Two multi-functional general purpose timer units with 5 timers
• Two serial channels (USARTs)
• Programmable watchdog timer
• Up to 76 general purpose I/O lines

A.11.2 Functional description

Figure A-11: 80C166 Internal block diagram

16

Internal 32 16 Internal
ROM CPU-Core
RAM
Area

16

16 PEC

Interrupt Controller

XTAL OSC Watchdoog

16

GPT1 GPT2 CAPCOM

16 Ext.
Port 10-Bit USART USART
Bus [T2] [T5] [T0]
0 ADC ASC0 ASC1
Control [T3] [T6] [T1]
[T4]

2 Port
4 Port 1 Port 5 Port 3 Port 2

16 10 16 16

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Device specification

A.11.3 Memory organization

The memory space of the 80C166 is configured in a Von Neumann architecture
which means that code memory, data memory, registers and I/O ports are organ-
ized within the same 256 KBytes linear address space. The entire memory space
can be accessed byte wise or word wise. Particular portions of the on-chip
memory have additionally been made directly bit addressable.
1 KByte of on-chip RAM is provided as a storage for user-defined variables, for
the system stack, general purpose register banks and even for code. A register
bank can consist of up to 16 word wide (R0 to R15) and/or byte wide (RL0, RHO,
..., RL7, RH7) so-called General Purpose Registers (GPRs).
512 bytes of the address space are reserved for the Special Function Registers,
which are used for controlling and monitoring functions of the different on-chip
units. To meet the needs of designs where more memory is required than is pro-
vided on chip, up to 256 KBytes of external RAM and/or ROM can be connected
to the microcontroller.

A.11.4 External Bus Controller

All of the external memory accesses are performed by a particular on-chip Exter-
nal Bus Controller (EBC). It can be programmed either to Single Chip Mode
when no external memory is required, or to one of four different external memory
access modes, which are as follows:
- 16-/18-bit Addresses,16-bit Data, Demultiplexed
- 16-/18-bit Addresses, 16-bit Data, Multiplexed
- 16-/18-bit Addresses, 8-bit Data, Multiplexed
- 16-/18-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on Port 1 and data is input/
output on Port 0. In the multiplexed bus modes both addresses and data use Port
0 for input/output.
Important timing characteristics of the external bus interface (Memory Cycle
Time, Memory Tri- State Time, Read/Write Delay and Length of ALE, i.e. ad-
dress setup/hold time with respect to ALE) have been made programmable to
allow the user the adaption of a wide range of different types of memories. In ad-
dition, different address ranges may be accessed with different bus characteris-
tics. Access to very slow memories is supported via a particular ‘Ready’ function.
A HOLD/HLDA protocol is available for bus arbitration.
For applications which require less than 64 KBytes of external memory space, a
non-segmented memory model can be selected. In this case all memory locations
can be addressed by 16 bits and Port 4 is not required to output the additional seg-
ment address lines. Semiconductor Group.

A.11.5 Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arith-
metic and logic unit (ALU) and dedicated SFRs. Additional hardware has been
spent for a separate multiply and divide unit, a bit-mask generator and a barrel
shifter.
Based on these hardware provisions, most of the 80C166’s instructions can be ex-
ecuted in just one machine cycle which requires 100ns at 20-MHz CPU clock. For
example, shift and rotate instructions are always processed during one machine

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Appendix A 7200 Series UPS Service Manual
Device specification

cycle independent of the number of bits to be shifted. All multiple-cycle instruc-

tions have been optimized so that they can be executed very fast as well: branches
in 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10
cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reduc-
ing the execution time of repeatedly performed jumps in a loop from 2 cycles to
1 cycle.
A system stack of up to 512 bytes is provided as a storage for temporary data. This
is allocated in the on-chip RAM area, and is accessed by the CPU via the stack
pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly
compared against the stack pointer value upon each stack access for the detection
of a stack overflow or underflow.

A.11.6 Interrupt System

With an interrupt response time within a range from just 250ns to 600ns (in case
of internal program execution), the 80C166 is capable of reacting very fast to the
occurrence of non- deterministic events.
The 80C166 architecture supports several mechanisms for fast and flexible re-
sponse to service requests that can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be pro-
grammed to being serviced by the Interrupt Controller or by the Peripheral Event
Controller (PEC).
In contrast to a standard interrupt service where the current program execution is
suspended and a branch to the interrupt vector table is performed, just one cycle
is ‘stolen’ from the current CPU activity to perform a PEC service. A PEC service
implies a single byte or word data transfer between any two memory locations
with an additional increment of either the PEC source or the destination pointer.
PEC services are very well suited, for example, for supporting the transmission or
reception of blocks of data, or for transferring A/D converted results to a memory
table. The 80C166 has 8 PEC channels each of which offers such fast interrupt-
driven data transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt
enable flag and an interrupt priority bit field exists for each of the possible inter-
rupt services. Via its related register, each source can be programmed to one of
sixteen interrupt priority levels. Once having been accepted by the CPU, an inter-
rupt service can only be interrupted by a higher prioritized service request. For the
standard interrupt processing, each of the possible interrupt sources has a dedicat-
ed vector location.
The 80C166 also provides an excellent mechanism to identify and process excep-
tions or error conditions that arise during run-time; so-called ‘Hardware Traps’.
Hardware traps cause immediate non-maskable system reaction which is similar
to a standard interrupt service (branching to a dedicated vector table location).
Except when another higher prioritized trap service is in progress, a hardware trap
will interrupt any actual program execution. In turn, hardware trap services can
normally not be interrupted by standard or PEC interrupts.

A.11.7 Capture/Compare (CAPCOM) Unit

The CAPCOM unit supports generation and control of timing sequences on up to
16 channels with a maximum resolution of 400ns (@ 20 MHz CPU clock). The
CAPCOM unit is typically used to handle high speed I/O tasks such as pulse and
waveform generation, pulse width modulation (PMW), Digital to Analog (D/A)
conversion, software timing, or time recording relative to external events.

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7200 Series UPS Service Manual Appendix A
Device specification

Two 16-bit timers (T0/T1) with reload registers provide two independent time
bases for the capture/ compare register array.
The input clock for the timers is programmable to several prescaled values of the
CPU clock, or may be derived from an overflow/underflow of timer T6 in module
GPT2. This provides a wide range of variation for the timer period and resolution
and allows precise adjustments to the application specific requirements. In addi-
tion, an external count input for CAPCOM timer T0 allows event scheduling for
the capture/compare registers relative to external events.
The capture/compare register array contains 16 dual purpose capture/compare
registers, each of which may be individually allocated to either CAPCOM timer
T0 or T1, and programmed for capture or compare function. Each register has one
port pin associated with it which serves as an input pin for triggering the capture
function, or as an output pin to indicate the occurrence of a compare event.
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (captured) into the capture/compare
register in response to an external event at the port pin which is associated with
this resister. In addition, a specific interrupt request for this capture/compare reg-
ister is generated. Either a positive, a negative, or both a positive and a negative
external signal transition at the pin can be selected as the triggering event. The
contents of all registers which have been selected for one of the five compare
modes are continuously compared with the contents of the allocated timers. When
a match occurs between the timer value and the value in a capture/compare regis-
ter, specific actions will be taken based on the selected compare mode.

A.11.8 General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multi-functional timer/counter structure
which may be used for many different time related tasks such as event timing and
counting, pulse width and duty cycle measurements, pulse generation, or pulse
multiplication.
The GPT unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently
in a number of different modes, or may be concatenated with another timer of the
same module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individu-
ally for one of three basic modes of operation, which are Timer, Gated Timer, and
Counter Mode. In Timer Mode, the input clock for a timer is derived from the
CPU clock, divided by a programmable prescaler, while Counter Mode allows a
timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where
the operation of a timer is controlled by the ‘gate’ level on an external input pin.
For these purposes, each timer has one associated port pin (TxIN) which serves
as gate or clock input. The maximum resolution of the timers in module GPT1 is
400ns (@ 20 MHz CPU clock).
The count direction (up/down) for each timer is programmable by software. For
timer T3 the count direction may additionally be altered dynamically by an exter-
nal signal on a port pin (T3EUD).
With its maximum resolution of 200ns (@ 20MHz), the GPT2 module provides
precise event control and time measurement. It includes two timers T5, T6, both
of which can be clocked with an input clock which is derived from the CPU clock

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Appendix A 7200 Series UPS Service Manual
Device specification

via a programmable prescaler. The count direction (up/down) for each timer is
programmable by software. Concatenation of the timers is supported.

A.11.9 A/D Converter

For analog signal measurement, a 10-bit A/D converter with 10 multiplexed input
channels and a sample and hold circuit has been integrated on-chip. It uses the
method of successive approximation. The sample time (for loading the capaci-
tors) and the conversion time adds up to 9.7 us @ 20MHz CPU clock.
For applications which require less than 10 analog input channels, the remaining
channel inputs can be used as digital input port pins.
The A/D converter section supports four different conversion modes. In the stand-
ard Single Channel conversion mode, the analog level on a specified channel is
sampled once and converted to a digital result. In the Single Channel Continuous
mode, the analog level on a specified channel is repeatedly sampled and convert-
ed without software intervention. In the Auto Scan mode, the analog levels on a
pre-specified number of channels are sequentially sampled and converted. In the
Auto Scan Continuous mode, the number of pre-specified channels is repeatedly
sampled and converted.
The Peripheral Event Controller (PEC) may be used to automatically store the
conversion results into a table in memory for later evaluation, without requiring
the overhead of entering and exiting interrupt routines for each data transfer.

A.11.10 Parallel Ports

The 80C166 provides up to 76 I/O lines which are organized into five input/output
ports and one input port. All port lines are bit-addressable, and all input/output
lines are individually (bit-wise) programmable as inputs or outputs via direction
registers. The I/O ports are true bidirectional ports which are switched to high im-
pedance state when configured as inputs. During the internal reset, all port pins
are configured as inputs.
All port lines have programmable alternate input or output functions associated
with them. Port 0 and Port 1 may be used as address and data lines when accessing
external memory, while Port 4 outputs the additional segment address bits A17/
A16 in systems where segmentation is enabled to access more than 64 KBytes of
memory. Port 2 is associated with the capture inputs or compare outputs of the
CAPCOM unit and/or with optional bus arbitration signals (BREQ, HLDA,
HOLD). Port 3 includes alternate functions of timers, serial interfaces, optional
bus control signals (WR, BHE, READY) and the system clock output (CLK-
OUT). Port 5 is used for the analog input channels to the A/D converter. All port
lines that are not used for these alternate functions may be used as general purpose
I/O lines.

A.11.11 Serial Channels

Serial communication with other microcontrollers, processors, terminals or exter-
nal peripheral components is provided by two serial interfaces with identical
functionality, Asynchronous/ Synchronous Serial Channels ASC0 and ASC1.
They support full-duplex asynchronous communication up to 625 Kbaud and
half-duplex synchronous communication up to 2.5 Mbaud @ 20 MHz CPU clock.
Two dedicated baud rate generators allow set up of all standard baud rates without
oscillator tuning. For transmission, reception, and erroneous reception, 3 separate
interrupt vectors are provided for each serial channel.

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Device specification

In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preced-

ed by a start bit and terminated by one or two stop bits. For multiprocessor com-
munication, a mechanism to distinguish address from data bytes has been
included (8-bit data + wake up bit mode). In synchronous mode one data byte is
transmitted or received synchronously to a shift clock which is generated by the
80C166.
A number of optional hardware error detection capabilities has been included to
increase the reliability of data transfers. A parity bit can automatically be gener-
ated on transmission or be checked on reception. Framing error detection allows
recognition of data frames with missing stop bits.

A.11.12 Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of
time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the end of initialization; thus, the chip’s start-up
procedure is always monitored. The software has to be designed to service the
Watchdog Timer before it overflows. If, due to hardware or software related fail-
ures, the software fails to do so, the Watchdog Timer overflows and generates an
internal hardware reset and pulls the RSTOUT pin low in order to allow external
hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the CPU clock divided either
by 2 or by 128. Each time it is serviced by the application software, the high byte
of the Watchdog Timer is reloaded. Thus, time intervals between 25µs and 420ms
can be monitored (@ 20MHz CPU clock). The default Watchdog Timer interval
after reset is 6.55 ms (@ 20MHz CPU clock).

A.11.13 Bootstrap Loader

The 80C166 provides a built-in bootstrap loader (BSL) which allows the execu-
tion of the start program outside its internal RAM. The program to be started is
loaded via the serial interface ASC0 and does not require external memory or an
internal ROM.
The 80C166 enters BSL mode when ALE is sampled high at the end of a hardware
reset and if NMI becomes active directly after the end of the internal reset se-
quence. BSL mode is entered independent of the selected bus mode.
After entering BSL mode the 80C166 scans the RXDO line to receive a zero byte,
i.e. one start bit, eight ‘0’ data bits and one stop bit. From the duration of this zero
byte it calculates the corresponding baud rate factor with respect to the current
CPU clock and initializes ASC0 accordingly. Using this baud rate, an acknowl-
edge byte is returned to the host that provides the loaded data.
The 80Cl66 exits BSL mode upon a software reset (ignores the ALE level) or a
hardware reset (remove conditions for entering BSL mode before).

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Device specification

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 B:

Appendix B : Controller Area Networking (CAN)

B.1 Introduction
The CAN (Controller Area Network) is an ISO defined serial communications
bus that was originally developed during the late 1980’s for the automotive indus-
try. Its basic design specification called for a high bit rate, high immunity to elec-
trical interference and an ability to detect any errors produced. Not surprisingly,
due to these features the CAN serial communications bus has become widely used
throughout the automotive, manufacturing and aerospace industries.

B.2 CAN Architecture

The CAN communications protocol describes the method by which information
is passed between devices. It conforms to the Open Systems Interconnection
model which is defined in terms of layers (See Figure B-1). Each layer in a device
apparently communicates with the same layer in another device, but actual com-
munication is between adjacent layers in each device and the devices are only
connected by the physical medium via the physical layer of the model. In practice,
the physical medium consists of a twisted-pair or optical coupling with appropri-
ate termination.
The CAN architecture defines the lowest two layers of the model – i.e. the data
link and physical layers. The application levels are linked to the physical medium
by the layers of various emerging protocols, dedicated to particular industry areas
plus any number of propriety schemes defined by individual CAN users.

Figure B-1: Open Systems Interconnection model

The 7200 Series UPS system uses a type 80C200 standalone CAN controller
which directly interfaces to the microcontrollers, and the connection to the phys-
ical medium is implemented with the 82C250 integrated circuit.

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Appendix B 7200 Series UPS Service Manual
Controller Area networking (CAN)

B.3 Varieties Of CAN

CAN exists in two forms; ‘Basic CAN’ and ‘Full CAN’. The difference between
the two types of controller are mainly cost. Basic CAN is cheaper because it re-
quired less buffer space and CPU workload: Full CAN is less demanding on the
work required by the CPU.

‘Basic CAN’
Basic CAN has a tight coupling between the CPU and the CAN controller, where
all messages broadcast on the network have to be individually checked by the mi-
crocontroller. With Basic CAN, the messages are held in the CPU’s memory, and
the CPU must do all the work in keeping track of messages. The CPU must also
handshake with the 82C200 controller (using ‘message sent’ and ‘message ar-
rived’ interrupt handlers) to send and receive messages. This results in the CPU
being ‘tied up’ checking messages rather than processing them; all of which tends
to limit the practicable baud rate to 250kBaud.

‘Full CAN’
With Full CAN, all the messages are held in the CAN controller (82C200) and ac-
cessed by the CPU as dual-ported RAM. Acceptance filters mask out the irrele-
vant messages, using identifiers (ID), and presents the CPU with only those
messages that are of interest. The CPU therefore has little work to do in handling
the messages.
For example, the CAN protocol has a special type of message that means “whoever
holds this message, please send it now”. With Full CAN, the controller automatically
listens for these messages and sends them only if it happens to contain the request-
ed message: if the message Id is masked out then no action is taken.
In the basic CAN specification, it has a transmission rate of up to 250 kbaud whilst
full CAN runs at 1MBaud

B.4 CAN Bus protocol

B.4.1 CAN Addressing

There are no source and destination addresses in a CAN message. Message iden-
tifiers are used to tag a message type, and each node decides, using bit-masks,
which messages it retrieves from the bus – this process is called acceptance filter-
ing, and different controller chips provide different levels of filtering sophistica-
tion.
The Full CAN protocol allows for two lengths of message identifiers: Part A
(standard CAN) allows for 11 message identification bits, which yield 2,032 dif-
ferent identifiers, whilst extended CAN (Part B) has 29 identification bits, produc-
ing 536,870,912 separate identifiers.
Part A devices such as the 82C200 can only transmit and receive standard CAN
protocol. If used on an extended CAN system in which 29 bit IDs are present, the
device will cause errors and crash the entire network.
The data-link layer defines the format and timing protocol with which the mes-
sages are transmitted. There are two descriptor bytes and up to eight data bytes.
The descriptor bytes are particularly important as they define the priority and type
of message being transmitted.

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7200 Series UPS Service Manual Appendix B
Controller Area networking (CAN)

Figure B-2:

Parity Bits

B.5 Priorities handling

The identifier field contains 11 bits and is used to identify the message as well as
determining its bus access priority. Bits 7-10 of the identifier field define the mes-
sage priority, with the highest priority having for the smallest identifier binary
value. This means that messages can have a priority number between 0 (high pri-
ority) and 15 (low priority). Allocation of message priorities is a feature of the
CAN bus that makes it particularly attractive for use within a strongly real time
control environment.

B.5.1 Coping with message collisions

As has been said, a fundamental CAN characteristic is that the lower the message
number, the higher its priority - an identifier consisting entirely of zeros is there-
fore deemed to be the highest possible priority message.
A node can start transmitting at any time when the bus is silent (idle), with the
first part of a message transmitted being the message identifier field – most sig-
nificant bit first. The node constantly monitors the CAN bus and if it is the only
node currently transmitting it will receive back the message bit-by-bit as it sends
it.
The bus has the property that if any node transmits a ‘0’ (called a dominant bit)
then all nodes read back a zero. Thus if two nodes begin to transmit simultaneous-
ly, the first source to send a zero, when the other source attempts one, gets control
of the CAN bus and goes on to complete its message.
Thus if a transmitter ‘A’ is overruled by a source ‘B’ sending a higher priority
message, the fact that the message read back by ‘A’ does not match the message
it attempted to send means that it will temporarily halt. Another attempt will sub-
sequently be made to send it once the bus is released and returns to an ‘idle’ state.
Any collisions will always be resolved because the CAN protocol requires that
message identifiers are unique (which is why there are so many priorities).
This functionality is part of layer 1 and is contained entirely within the 82C200
CAN controller device and is therefore transparent to the CAN user.

B.5.2 Interactive Communication

It is possible to send a request for data to a specified address, and the remote trans-
mission request (RTR) bit defines whether the message sent is a request for data
or the actual data itself. The data-length code tells the receptor how many data

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Appendix B 7200 Series UPS Service Manual
Controller Area networking (CAN)

bytes the message contains. In the case of data requests, no data bytes follow and
therefore the data-length code has no direct relation to the number of data bytes.
The maximum number of nodes on a CAN bus is 32. The limit of messages per
second ranges from about 2000 to about 5000 on a bus with 250kbaud transmis-
sion rate, depending on the number of bytes per message.

B.6 The Physical Layer

CAN can use a number of physical media such as twisted wire-pairs, fibre-optics
etc. The commonest method is the former. Signalling is carried out using differ-
ential voltages and it is from this that CAN derives much of its noise immunity
and fault tolerance. The two signal lines are termed ‘CAN_H’ and ‘CAN_L’ and, in
the quiescent state, sit at 2.5V. A logic high (1) is denoted by CAN_H being above
CAN_L and as such is termed a ‘dominant’ bit; whilst a logic low (0) has CAN_L
above CAN_H, yielding a ‘recessive’ bit.
The use of voltage differentials allows CAN networks to function when one of the
signalling lines is open, or in extremely noisy environments. With a simple twist-
ed pair, the differential CAN inputs effectively cancel out noise, provided it is
within the common mode range.

B-4 app-b.fm5 - Issue 2 Dated 21/08/97

 C:

Appendix C : PCB Layout diagrams

C.1 Overview
This appendix contains layout diagrams for the major circuit boards fitted across
the entire 7200 product range. The diagrams are highlighted to show the location
of the configuration jumpers, indicator LEDs and variable resistors; the input/
output connectors are also identified.

Figure C-1 - Rectifier logic board Part Nº4520074A assembly

Figure C-2 - Inverter logic board Part Nº 4530025T assembly (Post March 1997)
Figure C-3 - Inverter logic board Part Nº 4530024S assembly (Post March 1997)
Figure C-4 - UPS logic board Part Nº4550007H assembly (Post March 1997)
Figure C-5 - UPS logic board Part Nº4550004E assembly (Pre March 1997)
Figure C-6 - Static switch trigger PCB Part Nº 4542043Z (Post March 1997)
Figure C-7 - Static switch trigger PCB Part Nº 4542041X (Pre March 1997)
Figure C-8 - Operator Interface PCB Part Nº 4550005F assembly
Figure C-9 - High voltage interface PCB Part Nº 4590054O assembly
Figure C-5 - UPS logic board Part Nº4550004E assembly (Pre March 1997)

app-c.fm5 - Issue 3 Dated 09/11/98 C-1

 Appendix C 7200 Series UPS Service Manual
PCB Layout Diagrams

Figure C-1: Rectifier logic board Part N º4520074A assembly

R22
Manual DC voltage Adj
(10-500V)

R21
Battery float voltage Adj
(200 - 500V)

R20
Battery boost voltage Adj
(200 - 500V)

R19
Battery test voltage Adj X7 = 2 - 3
(0 - 550V)

X6 = 1 - 2

H9 (R)
Input undervoltage
(-20%) H4 (A)
Rectifier in manual
mode
H10 (R)
External rectifier off H3 (G)
(UPS logic) Rectifier in float
mode

H8 (R) H2 (G)
Incorrect phase rotation Rectifier in boost
on rectifier input mode

H1 (A)
H7 (R) Rectifier under
PCB power supply battery test mode
failure

R17
Rectifier current limit
Adjust

H6 (R)
Rectifier current limit
active
R18
Battery current limit
Adjust
H5 (G)
Battery current limit
active

R121
Battery voltage
compensation Adj.
X10 = 2 - 3 w.r.t. to temperature
2.98 volts at X5 pin1
= 25° C

X5 = 1 - 2
X13 = 0v = gnd

X12 = 0v = gnd X9 = 0 - 5 X8 = Test points

C-2 app-c.fm5 - Issue 3 Dated 09/11/98

 7200 Series UPS Service Manual Appendix C
PCB Layout Diagrams

Figure C-2: Inverter logic board Part Nº 4530025T assembly (Post March 1997)
R27 R247 R242 R243
R241 Tri-wave Amplitude φ displacement Adj Inv 3ph volts adj. Man inv volts Adj.
Amplitude of Tri-wave measurement Inv to Mains (clockwise = min.)

H1(G)
X15 0 - 1 380v operation
2400 Hz switching X6 H2(G)
Aux Inv Logic PCB 400v operation
H3(G)
415v operation
H4(A)
Man operation

H11(R) = PCB
power supply fail

Test Point X8 H12(R) = Inv off µP

H13(R) =
Ribbon cable block

R248 H14(R) =
150% Inv I Limit Overload 150%
(0.6V @ X10 pin 4)
H5(R) = R + sat

H6(R) = R – sat
Test Point X10
H7(R) = S+ sat

H8(R) = S– sat

H9(R) = T + sat

H10(R) = T – sat

X1 X2 X3
To Base Drive PCBs

X18
OV = gnd

X17
OV = gnd

R245
Volts C-N Adj

X12 1-2
X4
0-1(closed)=temp enable
X16 R244 Test Point X9 To UPS Logic PCBs
0-2(open) =Ribbon cable enable
0-1 Volts B-N Adj
= 6 pulse Inv I feedback
0-2 R246
Volts A - N adjustment

app-c.fm5 - Issue 3 Dated 09/11/98 C-3

 Appendix C 7200 Series UPS Service Manual
PCB Layout Diagrams

Figure C-3: Inverter logic board Part Nº 4530024S assembly (Post March 1997)

R246
R241 150% Inv I limit (0.6v @ X10 pin4)
Amplitude of Tri-wave

Test Point X11 R247

φ displacement Adj Inv to Mains
X15 0 - 1
2400 Hz switching

H5(R) = R + sat

Test Point X10 H6(R) = R – sat

H7(R) = S+ sat

H8(R) = S– sat
Test Point X8

Test Point X9 H11(R) = PCB

power supply fail
H12(R) = Inv off µP

H13(R) =
Ribbon cable block
H14(R) =
Overload 150%

X13 2-3 Temp enable

X12 1-2 Ribbon cable

enable
H9(R) = T + sat
H10(R) = T – sat

R244
Volts B-N Adj
R242
Inv volts ref. set

R243
Man inv volts Adj.
R245 (clockwise = min.)
Volts C-N Adj
H1(G)
380v operation
H2(G)
400v operation
H3(G)
415v operation
H4(A)
Man operation
X16
X18 X14 X17
0-1
= 6 pulse Inv I feedback OV = gnd Not Used OV = gnd
0-2

C-4 app-c.fm5 - Issue 3 Dated 09/11/98

 S1 RESET BUTTON X33 = 1-2 Q1 Q2 X12 Q3 H11 & H12
For Overtemp: Overcurrent: Calendar P.S Bypass ON/OFF Inv ON/OFF NO Links Fitted Rect ON/OFF Error Code display
EPO; DC Overvoltage 01 = normal operation

X35
1-2 = Seperate Bat
2-3 = Common Bat
X36
1-2 = Seperate Bat
H8 (Amber) 2-3 = Common Bat
Internal battery charger
(Active)
X28 open =Standard
closed =Hardware
Reset
7200 Series UPS Service Manual

app-c.fm5 - Issue 3 Dated 09/11/98

X31
Linked = enable internal
battery charger
X14
open
R209 @ 20 pin 1
5 Volt adjust

X13 R212 @ Anode V45

2-3 = RAM enabled 2.5 Volt adjust
V45
X19
open = not used X20 1-2 = Power supply rail
µPs reference
X21
2-3 = RAM enabled X29 open = Power supply
monitor enabled
X22
1-2 = EPROM enabled

X23
2-3 = EPROM enabled
X16 1-2 = Display
X24 enabled
1-2 : 3-4 = RAM enabled
Figure C-4: UPS logic board Part Nº4550007H assembly (Post March 1997)

X32 X34 = X18 pin 8 = 0V X15 = 2 - 3 X25 = 2 - 3 X17 = 2 - 3 = Power supply fail save data
Appendix C
PCB Layout Diagrams

Linked = RS485 enabled 1-2 1+1 & Parallel

C-5
2-3 Single module X26 = 1-2 = Open = Standard
3 - 4 = Closed = Standard
7 - 8 = Password over-ride open = standard
 S1 RESET BUTTON Q1 Q2 Q3 H11 & H12
(o/temp; Overload; Bypass ON/OFF Inv ON/OFF Rect ON/OFF Error Code display
EPO; DCovervolts 01 = normal operation

C-6
X11 = open
RS232 enabled
Appendix C

H8 (R)
Internal battery charger
(Active)
PCB Layout Diagrams

X28 open =Standard

closed =Hardware
Reset
X31
Linked = enable internal
battery charger

X14
open

R209 @ X20 pin 1

5 Volt adjust

X13 R212 @ Anode V45

2-3 = RAM enabled 2.5 Volt adjust
V45
X19
open = not used X20 1-2 = Power supply rail
X21
µPs reference
2-3 = RAM enabled
X29 open = Power supply
X22 monitor enabled
1-2 = EPROM enabled

X23
2-3 = EPROM enabled
X161-2 = Display
X24 enabled
Figure C-5: UPS logic board Part Nº4550004E assembly (Pre March 1997)

1-2 : 3-4 = RAM enabled

X32 X18 pin 8 = 0V X15 = 2 - 3 X25 = 2 - 3 X26 = 3 - 4 X17 = 2 - 3 = Power supply fail save data
7200 Series UPS Service Manual

Linked = RS485 enabled

app-c.fm5 - Issue 3 Dated 09/11/98

7-8 = Password protection
 7200 Series UPS Service Manual Appendix C
PCB Layout Diagrams

C:

Figure C-6: Static switch trigger PCB Part Nº 4542043Z (Post March 1997)

SCR Trigger Leads

X14 = 0v = gnd

X11
= 0 - 3 closed
= 0 - 5 closed

N/A
To UPS Logic X5 DC To contactor
K1

Contactor Aux Feedback DC feed for contactor

K1

APP-C1.FM5 - Issue 2 Dated 21/08/97 C-7

 Appendix C 7200 Series UPS Service Manual
PCB Layout Diagrams

Figure C-7: Static switch trigger PCB Part Nº 4542041X (Pre March 1997)

SCR Trigger Leads

X14 = 0v = gnd

X12 = 0 - 3

X11 = 1 - 2

N/A

To UPS Logic X5 To contactor

Contactor Aux Feedback DC feed for contactor

C-8 APP-C1.FM5 - Issue 2 Dated 21/08/97

 X1 = To display R21 = Contrast X11 = open H1 (G)
Adjust Internal DC/AC
power supply OK

X23 = 2 - 3
Power supply input
to UPS logic X4

X24 = 1 - 2

X14 = open
7200 Series UPS Service Manual

APP-C1.FM5 - Issue 2 Dated 21/08/97

To UPS logic X19 = open
X6 CAN bus
X12 = 2 - 3

X3 N/A CAN bus aux

N/A

X21 = 2 - 3
X15 = 1 - 2
X22 = 2 - 3
X18 = 2 - 3
X20 = 1 - 2
Figure C-8: Operator Interface PCB Part Nº 4550005F assembly

X13 = 2 - 3

N/A

X26 = open
Appendix C
PCB Layout Diagrams

X5 = RS232 X8 = RS232 X4 X17 = 1 - 2 : 3 - 4

C-9
Aux 9 pin socket Main 25 pin socket X25 = 1 - 2 RS232 9 pin or
RS485 socket X16 = 2 - 3
 Appendix C 7200 Series UPS Service Manual
PCB Layout Diagrams

Figure C-9: High voltage interface PCB Part Nº 4590054O assembly

X13 : Inverter heat-sink
X31 to X40 : CT burden settin
X12 : Transformer ambient temperature
x11 Output temperature
x10 : Input temperature
X8 : Battery breaker & EPOx9 : Battery temperature

X7 : Manual isolation x14: N/A

Q1 - Q4

x15 : Batt Fuse

x16 : N/A

x17 : N/A
X6 : Bypass volts

x18 : Rectifier

x19 : I out C

X5 : Inverter volts
x20 : I out B

x21 : I out A

: Critical Bus volts x22 : I Batt

x23 : Inv A

Rectifier input volts x24 : Inv B

x25 : Inv C

2 : Battery volts
x26 : IDC 1

x27 : IDC 2

x1 to UPS logic PCB

C-10 APP-C1.FM5 - Issue 2 Dated 21/08/97

 X12 = Test point X8 = Test point
1 = VCO in loop (low) X9 1 = Internal Sync OK (high)
2 = Current share enabled (low) Digital ground 2 = Frequency GVCO
3 = Rectifier paralleled (low) To UPS logic 3 = 4.00V R20 = 4.00 volt adjust @ X 8-3
4 = N/A
5 = Ground R18 = Frequency adjust @ X 8-2

X6
0-1 open = redundancy
closed = capacity
0-2 open = common battery X7
closed = seperate battery 1-2 = 60Hz operation
0-3 open = standard 2-3 = 50Hz operation
0-4 open = No MSSC (1+1)
closed = MSSC (multi)
0-5 open = standard
0-6 open = standard X11
7200 Series UPS Service Manual

0-7 open = No contactor in MSSC open = slow slew

APP-C1.FM5 - Issue 2 Dated 21/08/97

closed = contactor in MSSC rate (0.1Hz/Sec)
0-8 open = normal operation closed = Fast slew
closed = Test mode active rate (0.2Hz/Sec)

H1 (red)
= Parallel error (select) (Off)

H2 (red)
= Parallel cable error (Off)
X10 = Analogue ground

H3 (green)
= Slave mode active (Off)

R68 (lower)
Figure C-10: Parallel logic PCB Part Nº 4520075B

X13
2-3 = Parallel screen common

R19
X5 Parallel error (adjust
Appendix C
PCB Layout Diagrams

To X2 on other module
0-1 closed X4 for R68 lower)

C-11
To X3 on other module 0-2 closed 0-1 closed 380V = 5.90V
0-3 closed 400V = 6.20V
Appendix C 7200 Series UPS Service Manual
PCB Layout Diagrams

C-12 APP-C1.FM5 - Issue 2 Dated 21/08/97

 D:

Appendix D : PCB link selection

D.1 Introduction
The tables in this appendix provide details of the configuration jumpers fitted to
the various control printed circuit boards, and indicates their “default” settings.
Layout diagrams are provided in Appendix C which give details of the links’
exact location.

D.2 Rectifier Logic PCB Part Nº 4520074A. 30 to 60kVA

Table D-1: Rectifier logic board jumper link position

Link
Jumper Function
Position

X5 1-2 Disable battery temperature/voltage compensation

(Standard)

2-3 Enable battery temperature/voltage compensation

X6 1-2 Increased DC regulation speed for units below 60kVA

2-3 Decreased DC regulation speed for units above 80kVA

X7 1-2 Fast walk-in: 1 Second

2-3 Slow walk-in: 5 Seconds

X9 0-1 open
Rectifier in Auto mode (Standard)
0-2 open

0-1 closed
Rectifier in Float mode
0-2 open

0-1 open
Rectifier in Boost mode
0-2 closed

0-1 closed
Rectifier in ‘Test’ mode
0-2 closed

0-3 closed Reduced input current limit forced on

open (Standard)

0-4 closed Rectifier forced on - Ignore UPS Logic

open UPS Logic control enabled (Standard)

0-5 open Disable driver IC - D6

closed Enable driver IC - D6 (Standard)

X10 1-2 Enable rectifier temperature monitor

2-3 Disable rectifier temperature monitor (Standard)

App-d.fm5 - Issue 2 Dated 21/08/97 D-1

Appendix D 7200 Series UPS Service Manual
PCB Link Selection

D.3 UPS Logic PCB Part Nº4550007H. 30 - 60kVA

Table D-2: UPS logic board jumper link positions

Jumper Position Function

Open (Standard)

X12 1-2 Not Required

3-4 Not Required

1-2 EPROM Enable

X13
2-3 RAM Enable (Standard)

1-2 Not Required

normally open
Testing only
3-4 Not Required
X14
5-6 Not Required

7-8 Not Required

1-2 PLL option with CAP IN

X15
2-3 PLL option with FIN AUX (Standard)

Open CAN Bus to display disabled

X16
1-2 CAN Bus to display enabled (Standard)

1-2 ALE enable data save

X17
2-3 Power supply fail enable data save (Standard)

1-2 EPROM II enable (not required)

X19
2-3 RAM II enable (not required)

+5V PCB enables microprocessor ref. For VA calculations

1-2
X20 (Standard)

2-3 V ref. enables microprocessor ref. For VA calculations

1-2 Not Required

X21
2-3 RAM enable (Standard)

1-2 EPROM enable (Standard)

X22
2-3 Not Required

1-2 Not Required

2-3 EPROM enable (Standard)

X23
3-4 Not Required

4-5 Not Required

D-2 App-d.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual Appendix D
PCB Link Selection

Jumper Position Function

1-2 RAM enable (Standard)

2-3 EPROM enable (not required)

X24
3-4 RAM enable (Standard)

4-5 EPROM enable (not required)

1-2 Manual reset of output buffers

X25
2-3 Microprocessor reset of output buffers (Standard)

OPEN = Inverter operation in ‘Auto’ mode (Standard)

1-2
CLOSED = Inverter operation in ‘Manual’ mode

CLOSED = Inverter voltage error lockout (10s) enabled

3-4 (Standard)
X26 OPEN = Inverter voltage error lockout (10s) disabled

CLOSED = Reset event history buffer to zero

5-6
OPEN = Event history buffer enabled (Standard)

OPEN = Password security enabled

7-8
CLOSED = Password security disabled (Standard)

Open Power up reset enabled (Standard)

X28
Closed Power up reset disabled

Open 2.5V power supply monitor enabled (Standard)

X29
1-2 2.5V power supply monitor disabled

Open Internal battery disabled

X31
1-2 Internal battery installed and charger enabled (Standard)

Open RS485 port disabled

X32
1-2 RS485 port enabled (Standard)

1-2 Calender IC supply from VRAM (Standard)

X33
2-3 Calender IC supply from internal battery

1-2 G.V.C.O. to inverter logic = parallel module

X34
2-3 Micro V.C.O. to inverter logic = single module

1-2 Seperate battery per module (parallel system)

X35
2-3 Common battery (parallel system)

1-2 Seperate battery per module (parallel system)

X36
2-3 Common battery (parallel system)

App-d.fm5 - Issue 2 Dated 21/08/97 D-3

Appendix D 7200 Series UPS Service Manual
PCB Link Selection

D.4 Inverter Logic PCB Part Nº4530025T. 30 - 60kVA

Table D-3: Inverter logic board jumper link positions

Jumper Position Function

0-1 Open= Test inverter over-temperature sensors

Closed = Enable Inverter over-temperature sensors (Stand-

0-1
ard)

0-2 Open= Enable ribbon cable detector (Standard)

0-2 Closed = Disable ribbon cable detector

X12 0-3 Closed = Voltage select override.

Open = Standard
Enables manual inverter volts Adj by R243

Testing Only
0-4

0-5 Frequency select override

0-6 Force the Inverter ON => ignore all blocks

0-7 Ignore Inverter ‘On Load’ signal

0-1 2400 Hz switching frequency (Standard)

0-2 4800 Hz switching frequency

X15 0-1
9600 Hz switching frequency
0-2

0-5 1200 Hz switching frequency

0-1
6 pulse Inverter current feedback (Standard)
X16 0-2

0-3 12 pulse Inverter current feedback

D.5 Operator Logic Board Part Nº 4550005F 30-60 kVA

Table D-4: Operator Logic Board jumper link position

Jumper Position Function

Open +5v enable main CPU (Standard)

X11
Closed ALE enable main CPU

1-2 Main CPU enable EPROM

X12
2-3 +5v enable EPROM (Standard)

1-2 Main CPU enable RAM

X13
2-3 +5v enable RAM (Standard)

D-4 App-d.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual Appendix D
PCB Link Selection

Jumper Position Function

1-2 Not Required Testing Only

X14
2-3 Not Required Open = Standard

1-2 Main CPU enable EPROM (Standard)

X15
2-3 Not Required

1-2 Not Required

2-3 Main CPU enable EPROM (Standard)

X16
3-4 Not Required

4-5 Not Required

1-2 Write to RAM enable (Standard)

2-3 Not Required

X17
3-4 Main CPU enable RAM (Standard)

4-5 Not Required

1-2 Not Required

X18
2-3 Main CPU enable RAM (Standard)

1-2 Not Required

RAM extension
X19
2-3 (Normally open)
Not Required

1-2 Read/Write RS232 enable (Standard)

X20
2-3 Read/Write RS485 enable

1-2 Enable port x4 for RS485

X21
2-3 Enable port x4 for RS232 (Standard)

1-2 Enable port x4 for RS485

X22
2-3 Enable port x4 for RS232 (Standard)

1-2 Inhibit buzzer

X23
2-3 Enable buzzer (Standard)

1-2 Enable CAN bus to UPS logic (Standard)

X24
2-3 Disable CAN bus to UPS logic

1-2 Enable RS485 bus to port x4 (Standard)

X25
2-3 Disable RS485 bus to port x4

Open +5v power supply reset enabled (Standard)

X26
Closed +5v power supply reset disabled

App-d.fm5 - Issue 2 Dated 21/08/97 D-5

Appendix D 7200 Series UPS Service Manual
PCB Link Selection

D.6 Static Switch Driver PCB Part Nº 4542043Z 30-60 kVA

Table D-5: Static Switch Driver board jumper link position

Jumper Position Function

0-1 open Enable load on inverter command (Standard)

0-1 closed Disable load on inverter command

0-2 open Enable load on bypass command(Standard)

0-2 closed Disable load on bypass command

0-3 open Disables bypass fire command

x11
0-3 closed Enable bypass fire command (Standard)
0-4 N/A Not used

0-5 open Test static switch temperature monitor

Inhibit static switch temperature monitor (stand-

0-5 closed
ard)

D.7 High Voltage Interface PCB Part Nº 4590054O 30-60kVA

Table D-6: High Voltage Interface Board jumper link position.

Jumper Position Function

— 0-1
30 kVA CT burden
X31 0-2
selection
X31: X32: X33: X34: X35: X37: X38: X39: X40 0-3
— 0-1
40 kVA CT burden
X31: X32: X33: X34 0-2
selection
X35: X36: X37: X38: X39: X40 0-3
— 0-1
60 kVA CT burden
— 0-2
selection
X31: X32: X33: X34: X35: X36: X37: X38: X39: X40 0-3

D.8 Parallel Logic PCB Part Nº 4520075B

D-6 App-d.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual Appendix D
PCB Link Selection

Jumper Position Function

open Priority selector disabled

0-1
closed Priority selector enabled for ≥ 1 module (standard 1+1)
X4
0-2 Priority selector for ≥ 2 modules (multi module only)
to open Link combination sets logic for number of units required
0-8 open = standard for 1+1

open
0 - 1 (1st Unit)
closed (standard)

open
0 - 2 (2nd Unit)
closed (standard)

open Link combination sets logic for number of units

X5 0 - 3 (3rd Unit) operating
closed (standard) For 1+1 operation links 0 - 1, 0 - 2, 0 - 3 are closed.
open (standard)
0 - 4 (4th Unit)
closed

open (standard)
0 - 5 (5th Unit)
closed

open 1 + 1 redundancy (standard)

0-1
closed 1 + 1 capacity

open Common battery for all UPS modules

0-2
closed Separate battery for each UPS module (standard)

open Priority selector enables parallel shutdown (standard)

0-3
closed Priority selector disables parallel shutdown

open No MSSC installed (1 + 1) (standard)

X6 0-4
closed MSSC installed (enables control for multi modules)

0-5 N/A

0-6 N/A

open No contactor in MSSC (standard)

0-7
closed Contactor in MSSC

open Normal operation

0-8
closed Test mode active

1-2 60 Hz operation
X7
2-3 50 Hz operation (standard)

open G.V.C.O. Slow slew rate = 0.1 Hz/Second (standard)

X11
closed G.V.C.O. Fast slew rate = 0.2 Hz/Second

1-2 Parallel cable screen earthed

X13
2-3 Parallel cable screen not earthed (standard)

App-d.fm5 - Issue 2 Dated 21/08/97 D-7

Appendix D 7200 Series UPS Service Manual
PCB Link Selection

D.9 DC – DC power supply PCB Part Nº 4503028K

Table D-7: DC-DC power Supply Board link position

Soldered Link Position Function

CV1 Closed Enables the input voltage 260V – 600V

CV2 Closed Enables input under voltage protection

D-8 App-d.fm5 - Issue 2 Dated 21/08/97

 E:

Appendix E : Specification

Model kVA Rating

MECHANICAL CHARACTERISTICS UNITS
30 40 60
Height mm 1400

Width mm 710

Depth mm 800

Weight kg 480 540 620

Colour (2 tone) – RAL 7001

Protection grade – With enclosure open or shut = IP20

Ventilation – assisted by internal intake fans

Airflow m3/h 480 9600 960

Cable entry – Βοττοµ

Model kVA Rating

Environmental UNITS
30 40 60
Operating temperature °C 0 to +40

Maximum temperature for an 8 hour day – 40°C derate by 1.5% per °C between
+40° and +50°

Mean temperature for a 24 hour day – 35°C max

Relative humidity – <90% at 20°C

Altitude – <1000m a.s.l. (derate by 1% per 100m

between 1000m and 2000m)

Storage temperature °C -25 to +70

Acoustic noise at rated load (taken 1m from the dBA 56.0

apparatus according to ISO3746)

EMC Standard – Designed to meet EN 50091 part 2

Safety standard – Designed to meet EN 50091 part 1

App-e.fm5 - Issue 2 Dated 21/08/97 E-1

 Appendix E 7200 Series UPS Service Manual
Specification

Model kVA Rating

INPUT RATINGS UNITS
30 40 60
Power consumption at rated load while float charging kVA
the battery (400V) 32,8 43,5 64,9

Power consumption at rated load while boost charging kVA

the battery (400) 41,0 54,3 81,1

Input current level normal running (400V) A

47,0 63,0 94,0

Input current level full battery recharge (400V) A

59,0 78,0 117,0

Line voltage V a.c. 380 - 400 - 415 3Ph + N

Current rating of neutral cable A 1,4 times rated current

Permissible input voltage variation % +10 –15

Frequency Hz 50 or 60

Permissible input frequency variation % ±5

Power walk-in — Progressive over 10 seconds

Power factor at 380/400/415 V cos Φ 0,8

with optional input filter fitted >0,9

Model kVA Rating

SYSTEM DATA UNITS
30 40 60
Efficiency at 50% load % 92,0 92,6 93,1

Efficiency at 100% load % 91,5 92,0 92,5

Losses at rated load kW 2,2 2,8 3,9

Losses with battery on boost charge kW 2,8 3,4 4,5

Losses with no load kW 0,9 1,1 1,3

E-2 App-e.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual Appendix E
Specification

Model kVA Rating

OUTPUT RATINGS UNITS
30 40 60
Voltage V a.c. 380/400/415 (preset on commissioning)
3 Ph N

Frequency Hz 50 or 60 (presettable)

Power at 0,8pf kVA 30 40 60

Power at 1,0pf kW 24 32 48

Normal current at 0.8pf A 43 57 87

Overload ability at 0,8pf3 φ — 110% for 60 minutes

125% for 10 minutes
150% for 1 minute

1φ 200% for 30 seconds

Current limiting short circuit (inverter) —

150% rated current (3 phase) for 5 Seconds

220% rated current (1 phase) for 5 Seconds

Maximum permissible non linear load % 100 with 3 : 1 crest factor

Voltage stability — steady state % ±1

Voltage stability — transient state % ±5

Reset time to within ± 1% ms 20

Frequency stability — synchronised — The output will synchronise with the input
supply within ±0.5 Hz of nominal
frequency (adjustable to ±2 Hz)

Frequency stability — unsynchronised — ± 0,1% when the input supply frequency

is outside the synchronising range

Phase voltage asymmetry — balanced load — ± 1%

Phase voltage dissymmetry — 100% unbalanced load — ±2%

Voltage phase shift — with balanced load Angle o 120 ± 1

Voltage phase shift — with unbalanced load Angle o 120 ± 1

Output voltage distortion — linear load — 1% typical 2% max

Output voltage distortion — non–linear load (3:1 crest — ≤ 5% max

factor)

Maximum frequency slew rate Hz/sec 0,1 to 1,0

Synchronised transfer to bypass ms 0 approximately

Unsynchronised transfer to bypass ms 20 approximately

Overload on bypass — 10 x rated current for 100 ms

(without fuses)

App-e.fm5 - Issue 2 Dated 21/08/97 E-3

 Appendix E 7200 Series UPS Service Manual
Specification

Model kVA Rating

INTERMEDIATE DC RATINGS UNITS
30 40 60
Voltage limits of inverter operation for Vdc
380V minimum 320
maximum
460

Voltage limits of inverter operation for Vdc

400V minimum 330
maximum
475

Voltage limits of inverter operation for Vdc 340

415V minimum
maximum 490

Number of lead-acid cells UPS 380 V Nº 192

UPS 400 V Nº 198

UPS 415 V Nº 204

Float charge voltage UPS 380 V V d.c. 432

UPS 400 V V d.c. 446

UPS 415 V V d.c. 459

Boost charge voltage UPS 380 V V d.c. 460

UPS 400 V V d.c. 475

UPS 415 V V d.c. 490

End of discharge voltage UPS 380 V V d.c. 320

UPS 400 V V d.c. 330

UPS 415 V V d.c. 340

Absolute maximum voltage V d.c. 480

(manual charge) UPS 380 V

UPS 400 V V d.c. 495

UPS 415 V V d.c. 510

Rectifier output current rating A 75

Voltage stability with rectifier — ± 1%

Residual alternating voltage — ≤ 1%

Battery charging cycle — Characteristics to DIN 41772 I-U, boost-to-

floating charge switching, with current
measuring criterion plus control of charging
time

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7200 Series UPS Service Manual Appendix E
Specification

Model kVA Rating

INTERMEDIATE DC RATINGS UNITS
30 40 60
Maximum boost charge duration hours 1 - 15 hours ( selectable )

Charging current A 3 - 15 5 - 20 6 - 30

Inverter power at rated load kW 25,7 34,1 50,8

Input current to inverter at minimum voltage A 78 103 154

Efficiency of inverter @50% load % 93,8 94,4 94,8

Efficiency of inverter @100% load % 93,3 93,8 94,4

Model kVA Rating

STATIC SWITCH CIRCUIT UNITS
30 40 60
Overload from stand-by supply A 10 times the rated current for 100ms

current rating of neutral cable A 1,4 time the rated current.

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 Appendix E 7200 Series UPS Service Manual
Specification

BATTERY CABINETS

MECHANICAL UNITS Type B Type C Type D

CHARACTERISTICS 38 Ah 50 Ah 85 Ah
Dimensions (W X H X D) mm 2x
690 x 1400 x 800 1050 x 1400 x 800 855 x 1400 x 800

Weight (without batteries) kg 130 150 250

For use with units 30 - 40 kVA 30 - 40 kVA 30 - 40 - 60 kVA

Battery circuit breaker size Amps 100 100 160

Ventilation — Natural + +

Lifting — trans-pallet entry + +

+ + +

Magnetic
Suitable for
BATTERY CIRCUIT BREAKER No of overload
UPS size Part Nº
BOX Poles setting
(kVA)
(adjustable)
100 A 4 30 - 40 250 – 400

160 A 4 60 500 - 800

Undervoltage trip coil rating all units – 110Vdc (6,7 — 9,2 kOhms)

Auxiliary contacts (for signalling) all – 1 set changeover

units

E-6 App-e.fm5 - Issue 2 Dated 21/08/97