Accepted Manuscript

Real-time power switch fault diagnosis and fault-tolerant operation in a DFIG-

based wind energy system

Mahmoud Shahbazi, Philippe Poure, Shahrokh Saadate

PII: S0960-1481(17)30152-0

DOI: 10.1016/[Link].2017.02.066

Reference: RENE 8573

To appear in: Renewable Energy

Received Date: 16 November 2016

Revised Date: 16 February 2017

Accepted Date: 21 February 2017

Please cite this article as: Mahmoud Shahbazi, Philippe Poure, Shahrokh Saadate, Real-time
power switch fault diagnosis and fault-tolerant operation in a DFIG-based wind energy system,
Renewable Energy (2017), doi: 10.1016/[Link].2017.02.066

This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to
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 ACCEPTED MANUSCRIPT

A real-time power switch fault diagnosis for a DFIG-based wind energy system is proposed

Fault-tolerant operation is performed under open circuit switch fault

The effectiveness of the proposed approach is validated by Hardware in the Loop and
experimental validations
 ACCEPTED MANUSCRIPT

Mahmoud Shahbazi1, Philippe Poure2, Shahrokh Saadate3

1 School of Engineering and Computing Sciences, Durham University, Durham, UK

2 Institut Jean Lamour, Faculté des Sciences et Technologies, Université de Lorraine, Nancy, France
3 GREEN laboratory, Faculté des Sciences et Technologies, Université de Lorraine, Nancy, France

Corresponding author : Philippe Poure, [Link]@[Link],

telephone/fax number: +(33) 6 60 87 89 17 /+ (33) 3 83 68 41 53

Email Mahmoud SHAHBAZI: [Link]@[Link]

Email Shahrokh SAADATE: [Link]@[Link]
 ACCEPTED MANUSCRIPT

1 Real-time power switch fault diagnosis and fault-tolerant operation

2 in a DFIG-based wind energy system
3

4 Mahmoud Shahbazi, Philippe POURE and Shahrokh SAADATE

6 Abstract

7 As wind energy production increases, reliability and fault-tolerant operation capability of

8 wind energy systems are becoming more important. Modern wind energy production
9 systems use power electronic converters which are unfortunately proved to be one of their
10 most fragile parts and responsible for most of the system downtime. Real-time fault
11 monitoring, fault diagnosis and proper system reconfiguration in these converters are
12 therefore mandatory for fault-tolerant operation of the converter and the whole system. In
13 this paper, a comprehensive fault-tolerant power electronics interface for wind energy
14 systems with doubly-fed induction generators is presented and validated. The same power
15 production capability will be guaranteed. The proposed solution also includes a robust and
16 very fast open-circuit switch fault diagnosis algorithm, which is not sensitive to the
17 operation conditions and is therefore suitable for this application. Simulation, Hardware in
18 the Loop validation and experimental tests are carried out to demonstrate the effectiveness
19 of the proposed approach.

20 Keywords: Power switch fault diagnosis, fault tolerant operation, wind energy, Doubly-fed
21 induction generator

22 1. Introduction
23 Wind energy production has been growing rapidly in the recent years. However, with the
24 ever increasing use of wind turbines, many challenges have also appeared. In most cases,
25 the wind turbines are installed in remote areas where their maintenance is costly and time-
26 consuming. Therefore, the reliability of Wind Energy Conversion Systems (WECS) is of
27 paramount importance. On the other hand, Power Electronic (PE) converters are proved to
28 be one of the most fragile parts of a WECS. The proportion of maintenance cost for these
29 devices is high, and they are responsible for approximately 14% of the total downtime of
30 wind turbines [1]. Another study [2] shows that frequency converters cause the longest
31 downtime in the wind farms, being responsible for more than 22% of the overall
32 downtimes. All these data show the importance of their reliability and the usefulness of the
33 continuity of service of these converters, especially considering the fact that such
34 downtimes directly result in financial losses.

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1 When reliability is of major concern, Fault Tolerant Systems (FTS) also become important.
2 Such systems provide the possibility of balanced and controlled operation of the system
3 even after a fault occurrence and therefore preventing operation interrupts. Therefore, in
4 recent years fault tolerant control and Fault Diagnosis (FD) of wind turbines have gained
5 much attention. For example, detection of debris build-up on the wind turbine blades,
6 misalignment of one or more blades and change in the drive train damping due to wear and
7 tear are investigated in [3] and a fault detection problem is tackled using interval nonlinear
8 parameter-varying parity equations. Generator output power and rotational speed of the
9 wind turbine are used in [4] to derive a fault detection signal using a continuous-wavelet-
10 transform-based adaptive filter. Both electrical and mechanical faults were successfully
11 detected. Faults in sensors are investigated in [5-7], considering position, current and
12 voltage sensor faults. Detection of wind turbine drive train faults, including the damage
13 detection of blades through the terminals of the generator is investigated in [8]. A review of
14 many condition monitoring algorithms for different parts of WECSs is presented in [9].

15 Many papers in the recent years have studied fault tolerant operation of power electronic
16 converters in general applications such as electrical drives. For example, several fault-
17 tolerant techniques for two-level and multilevel converters are reviewed in [10]. Another
18 survey of condition monitoring and fault-tolerant operation for electric machines and drives
19 is available in [11]. A fault-tolerant control strategy for a T-type three-level inverter under
20 open-circuit fault conditions is proposed in [12]. No additional components are required,
21 but the inverter operation without output distortions is possible with reduced power at
22 reduced output voltage. Few studies have specifically aimed the converters in WECSs, where
23 most of them have been focused on Permanent Magnet Synchronous Generator (PMSG)-
24 based systems. In [13], a fault-tolerant topology for post-fault operation of the grid side
25 converter of a PMSG-based system is proposed which is based on a five-leg converter with
26 the shared leg connected to a phase of the generator and to the transformer’s neutral point.
27 Another method presented in [14] proposes to connect the output phases to the middle
28 point of the DC link after fault detection, but in this structure the grid-side converter
29 switches will experience two times bigger voltage in the post-fault mode which reduces its
30 practicality. In [15], a fault-tolerant control for open-switch faults in three-level NPC
31 converters of PMSG-based systems is proposed that used d-axis current injection to
32 eliminate current distortion in the post-fault operation mode.

33 The authors of [16, 17] have studied the fault in the converter in a Doubly-Fed Induction
34 Generator (DFIG) and the reconfiguration after fault diagnosis. A fault-tolerant PE structure
35 is proposed in [18] which is developed by replacing the conventional six-switch Grid Side
36 Converter (GSC) with a nine-switch alternative. While the proposed system is designed to
37 address grid faults, converter faults are not considered. Current sensor faults are
38 investigated in [19] and a new current observer is used for improved current sensor fault
39 detection. Faults such as those in generator speed sensor and pitch subsystem are

2
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1 considered in [20] where an observer based active fault-tolerant control approach is

2 proposed.

3 In all fault-tolerant systems, fault detection is the foremost step. The presence of a fault or
4 malfunction in the system must be quickly detected, as well as its location. In recent years,
5 many publications have addressed the fault diagnosis methods, including a number of high
6 quality surveys. For example, in [21, 22] a survey of fault diagnosis and fault-tolerant
7 techniques including fault diagnosis with model-based, signal-based, knowledge-based and
8 hybrid/active approaches for a variety of applications including power electronic converters
9 is presented. More particularly many methods are available for fault diagnosis in power
10 switches in power electronic converters. For example, the fault diagnosis algorithm for a
11 conventional three-phase converter presented in [23] is based on the recognition of Park’s
12 normalized current space vector trajectory. Some papers have specifically targeted the
13 power converters in WECSs. Open switch fault in variable speed situations is studied in [24]
14 where some of the existing fault detection methods are also investigated for this
15 application. It is shown that many of the existing fault diagnosis methods including those
16 based on Park’s vector approach may experience problems in variable wind speeds or in
17 turbulent wind situations. Moreover, many of the current based methods experience
18 problems in very low frequency currents. On the other hand, DFIG-based turbines are one of
19 the most used structures of wind turbines due to the smaller PE rating. In these systems,
20 rotor current can be quite low around the synchronous speed and therefore many of the
21 existing fault detection algorithms are expected to be not efficient in detecting the fault, or
22 even completely unable to detect the fault. However, in [17], a modified method is
23 presented that takes the low frequency nature of rotor current into account. Still, the fault
24 detection is relatively slow, and is not practically validated.

25 In this paper, a fault tolerant converter for a DFIG-based WECS is proposed; it is capable of
26 very fast open-circuit switch fault diagnosis and proper reconfiguration in order to
27 guarantee the seamless operation of the whole system. The employed fault diagnosis
28 algorithm uses voltage rather than current measurement, and therefore is resilient against
29 very low frequency rotor currents. Moreover, it is very fast and minimizes the adverse
30 effects of the fault on the drive train, and the fault detection time does not depend on wind
31 or load conditions.

32 On the other hand, a fault tolerant system could be with or without hard redundancy. If
33 some level of degraded operation is acceptable, then a system without hard redundancy
34 might be enough. For example, [25] presents a DFIG system without redundancy, where the
35 power electronic interface is reconfigured after a switch fault occurrence to continue with
36 the remaining 5 healthy legs. However, in such systems, the power handling capability of
37 the PE converters is quite reduced. Moreover, in such a system the total phase current of
38 both sides of the converter passes through the common leg after reconfiguration, therefore
39 all switches should be overrated to be capable of handling this current. More importantly,

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1 the dc-link voltage in this case may be quite higher than in the pre-fault case; therefore
2 special attention must be paid to the control of the converters as well as to their design in
3 the conception stage.

4 In this paper, however, a quite efficient solution is presented which only needs two
5 additional switches, but enables full rated operation in post fault situations. Moreover, the
6 control system remains unchanged after fault diagnosis and reconfiguration.

7 The rest of the paper is organized as follows: in section 2, the proposed fault tolerant
8 structure, the topology and the fault diagnosis algorithm are presented. A rapid prototyping
9 scheme including Hardware-In-the-Loop (HIL) verification is explained and used for
10 evaluating the proposed system. Experimentations are carried out in section 3 in order to
11 validate the proposed approach. Finally, some conclusions are provided.

12 2. Proposed fault-tolerant system

13 2.1. The topology
14

15 Fig. 1 shows the DFIG-based WECS incorporating the fault-tolerant converter. The fault
16 tolerant converter is in fact a back-to-back converter including an additional leg that can
17 replace any of the other legs in case of a fault in them. This is realized using six bidirectional
18 switches which can connect the output of the redundant leg to all input and output phases
19 of the converter. Triacs are used to realize these bidirectional switches.

20

21 Fig. 1. The fault-tolerant DFIG-based WECS.

22 The DFIG can be controlled by applying proper voltages via the Rotor Side Converter (RSC).
23 Many methods are available in the literature, but a widely used and well known method is

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1 vector control using Park transformation. Using proper decoupling terms, d and q currents
2 can be controlled to control the stator flux and output torque respectively. The GSC is used
3 for controlling the DC link voltage, and also the AC side power factor which is here set to
4 unity. In this work, the voltage-based control method of [26] is used to calculate the
5 reference voltages of the PWM unit of this converter. Fig. 2 shows the block diagram of the
6 RSC control. 𝑄 ∗𝑠 stands for the reference of the stator reactive power, 𝑇 𝑒∗ is the reference
7 for electromagnetic torque of the DFIG, 𝜑𝑠 is the stator flux, and 𝑖𝑟 and 𝑣𝑟 are rotor current
8 and voltage respectively. Subscripts ‘d’ and ‘q’ represent the variable in ‘d’ and ‘q’
9 coordinates of the Park transformation. 𝜔𝑟 is the frequency of rotor waveforms, 𝐿𝑠, 𝐿𝑚 and
10 𝐿𝑟 are total stator inductance, magnetizing inductance and total rotor inductance
11 respectively.

12
13 Fig. 2. Block diagram of the control of rotor voltages and currents.
14

15 2.2- Open-circuit switch fault diagnosis algorithm

16 In all fault-tolerant systems, fault diagnosis is the foremost step. Here a fault diagnosis
17 method is used that is based on voltage rather than current measurement. Combined with a
18 proper hardware implementation, this method which is very fast compared to other existing
19 fault diagnosis methods, minimizes the effect of a fault on the system. More importantly,
20 this method is independent of the system parameters as well as wind conditions, which
21 makes it more resilient and better-suited for fault-tolerant operation.

22 Fig. 3 shows the fault detection block diagram.

23

24 Fig 3. The fault detection block diagram.

25 The fault detection method is based on direct comparison of the measured and estimated
26 pole voltages. Estimated voltages are formed from each leg’s switching commands and the
27 DC link voltage through eq.1. DC-link voltage is anyways measured for control and

5
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1 monitoring purposes, and switching commands are calculated in the controller and are
2 therefore available.
(2𝑇𝑘 ‒ 1) × 𝑉𝑑𝑐
3 𝑉𝑘𝑜,𝑒𝑠 = 2 (1)

4 Where 𝑇𝑘 ∈ {0,1} is the switching command applied to the upper switch of leg ‘𝑘’ (𝑘 ∈
5 {𝑎1,𝑏1,𝑐1,𝑎2,𝑏2,𝑐2} -see Fig.1). The command of lower switch is complementary of the upper
6 one to avoid short circuit and provides a current path. 𝑉𝑘𝑜,𝑒𝑠 is the estimated pole voltage
7 with reference to the middle point of the DC-link capacitor. The difference between the
8 estimated and measured voltages contains information on the health of the leg’s switches.
9 In normal mode of operation and in an ideal converter, this difference is negligible. In
10 reality, however, uncertainties and disturbances should be considered as well. In fact, they
11 are present in the estimation and measurement parts of the system. The estimation is not
12 ideal, partly due to the delays and dead-times in the converters, including the switching
13 turn-on and turn-off delays, and also due to the measurement and discretising errors in
14 measuring 𝑉𝑑𝑐. The measurement of pole voltages (𝑉𝑘𝑜,𝑚) also suffers from these errors.
15 Due to the aforementioned delays, the difference between the measured and estimated
𝑉𝐷𝐶
16 voltages during switching intervals can reach 2 , but for very limited time spans. During
17 other times, there still might be a little difference between measured and estimated
18 voltages due to the mentioned measurement and discretising errors. Therefore, in the fault
19 diagnosis algorithm, the absolute value of the voltage error is first compared to a threshold
20 value of ‘ℎ’, which is chosen appropriately to filter the measurement and quantization
21 errors (Fig.3). The value of ‘h’ is chosen equal to 𝑉𝐷𝐶/4 here, which is normally several times
22 larger than the mentioned errors in normal operation, yet smaller than the voltage error in
23 faulty operation mode. Afterwards, if the voltage error is large enough, its duration is
24 calculated by using a counter. The output of this counter measures the time during which
25 the voltage error has been large enough. This output is again compared to another constant
26 value of N, and therefore voltage errors caused by natural delays and dead-times can be
27 filtered. The overall time that the counter needs to reach N should be adequately larger
28 than the overall delays in the system. When a fault occurs, the voltage error remains large
29 for a long period of time, and therefore the fault can be detected and declared.

30 3. Evaluation of the proposed FTS and FD algorithm

31

32 3.1. FPGA in The Loop” design and prototyping approach

33

34 For validation, a rapid prototyping design approach based on a so-called “FPGA in the loop”
35 prototyping method [27] is used in this paper. Fig. 4 shows the associated design flow. In
36 this method, first continuous time simulations in Matlab/Simulink are carried out. Since the

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1 control and fault diagnosis are going to be implemented on digital targets, the models are
2 discretised and discrete time simulations are carried out. Following this step, the model
3 system is kept unchanged, but all that is going to be implemented on the digital targets
4 (control and fault diagnosis) are replaced by proper blocks from DSP Builder library, which is
5 a library developed by Altera for implementing designs on their FPGAs. These blocks can be
6 compiled to VHDL automatically and are therefore suitable for rapid control prototyping and
7 HIL validation. However, some of the more complicated functions may not be available in
8 the library and can be developed in HDL codes and be integrated in the design.

9 Later on, all DSP Builder blocks can be compiled to produce a single HIL block that
10 represents all those functionalities. This block will then replace all those blocks. Then, FPGA
11 can be programmed using a JTAG interface. At this stage, all the control and FD functions
12 are implemented on the FPGA, while the power system (the turbine, generator, grid and
13 power converters) are simulated in the Matlab/Simulink environment. In each simulation
14 step, the power system sends necessary signals (voltages, currents, etc.) to the FPGA.
15 Control commands and FD signals are then calculated in the FPGA and the necessary data
16 are sent back to Simulink again. In this way, the performance of the controller and FD can be
17 validated experimentally before using them in a real system.

18

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2 Fig. 4. Rapid prototyping implementation flow.

3 3.2. Simulation and HIL results

4 Simulations results are presented here. Table I shows the parameters of the studied system.

5 Table I. Simulated system parameters.

Parameters
𝑈𝑟 = 𝑈𝑠 = 690 𝑉
𝑁𝑟
𝑃𝑛 = 3 𝑀𝑊, 𝑓 = 50 𝐻𝑧, 𝑝 = 2, ≈1
𝑁𝑠
DFIG
𝑅𝑠 = 2,97 𝑚Ω, 𝑅𝑟 = 3,82 𝑚Ω
𝐿𝑠 = 12,241 𝑚𝐻 , 𝐿𝑟 = 12,177 𝑚𝐻
𝐿𝑚 = 12,12 𝑚𝐻, 𝐽𝑚 = 114 𝑘𝑔.𝑚2
DC bus 𝐶 = 38 𝑚𝐹, 𝑉𝑑𝑐 = 1500 𝑉
GSC filter 𝑅𝑓 = 0.075 Ω, 𝐿𝑓 = 0.75 𝑚𝐻
Electric grid 𝑈 = 690 𝑉, 𝑓 = 50 𝐻𝑧
6

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1 Simulation step time and sampling rate are equal to 1𝜇𝑠. For fault diagnosis, N is chosen
2 equal to 30. This parameter is related to the delays in the system, and is chosen in
3 accordance with the experimental system that is explained in Section C.

4 First, an open switch fault is applied to 𝑆3 switch at the RSC (Fig. 1). Fig. 5 shows the stator
5 active and reactive powers before and after fault occurrence, and also the DC-link voltage.
6 Stator reactive power reference has two step changes, before and after fault occurrence, to
7 evaluate the dynamics of the system in pre-fault and post-fault configuration. This figure
8 shows that the fault is properly detected and the topology is reconfigured so that the fault
9 effect is hardly visible, and the WECS can continue producing energy as before. Since the
10 post-fault topology is effectively equivalent to the pre-fault one, the dynamic of the system
11 remains unchanged.

12 Fig. 6 shows the details of the fault diagnosis. Before fault, the measured and estimated
13 voltages difference is limited to the switching intervals, and therefore the fault counter
14 output has small magnitude. However, after fault, this error will be a high value for a longer
15 period of time, therefore allowing the counter to reach values as high as the fault diagnosis
16 limit (here set to 30 which corresponds to 30 𝜇𝑠). As soon as the output counter reaches 30,
17 the fault will be declared. Fault information is then used by the FPGA to reconfigure the
18 topology by appropriately commanding the Triacs and switches.
6
x 10
2

1
Qs
Qs (VAr)

0
Ps (W)

-1
Ps
-2

-3
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3
5
x 10
5

Qr
0
Qr (VAr)
Pr (W)

Pr
-5

-10
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3

1650

1600
Vdc (V)

1550

1500

1450

1400
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3

19 t (s)

20 Fig. 5. Active and reactive stator and rotor powers and DC link voltage for an open-circuit switch
21 fault in 𝑆3 at t=2.5 s with fault detection and reconfiguration.

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Cc1 (V) 1000

-1000

2.499 2.4992 2.4994 2.4996 2.4998 2.5 2.5002 2.5004 2.5006 2.5008 2.501
(a)
40

30

20
nc1

10

-10
2.499 2.4992 2.4994 2.4996 2.4998 2.5 2.5002 2.5004 2.5006 2.5008 2.501
t (s)
1 (b)

2 Fig. 6. (a) Voltage error between measured and estimated voltages; (b) fault diagnosis counter
3 output.

4 Fig. 7 shows the stator and rotor currents. As it is visible, the fault effect has been negligible
5 on these currents. The faulty phase current as well as 𝑇𝑟𝑐1 current are shown in Fig. 8. After
6 reconfiguration, the faulty leg current passes through this Triac and also in the remaining
7 diodes of the faulty leg which are now effectively in parallel with the diodes of the
8 additional leg.

10 Fig. 7. Stator and rotor currents for a fault in 𝑆3.

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3000

2000

1000
ic1 (A)

-1000

-2000

-3000
2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7
(a)

3000

2000

1000
iTrc1 (A)

-1000

-2000

-3000
2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7
(b)

1 t (s)

2 Fig. 8. (a) 𝑖𝑐1 phase current; (b) 𝑖𝑇𝑟𝑐1 Triac current.

3 An open-circuit switch fault in the GSC can also be similarly studied. Fig. 9 shows the GSC’s
4 active and reactive power as well as the DC-link voltage before and after a fault. Fault is
5 again applied at t=2.5 s, but this time in 𝑆3' (Fig.1).

1650

1600
Vdc (V)

1550

1500

1450

1400
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3
(a)
6

8 Fig. 9. Fault in 𝑆3' at GSC at t=2.5s: (a) DC-link voltage; (b) GSC active and reactive powers.

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1 Faulty leg’s current and the corresponding Triac’s current are also shown in Fig. 10.

1000

500
ic2 (A)

-500

-1000
2.46 2.47 2.48 2.49 2.5 2.51 2.52 2.53 2.54
(a)
1000

500
iTrc2 (A)

-500

-1000
2.46 2.47 2.48 2.49 2.5 2.51 2.52 2.53 2.54
(b)

2 t (s)

3 Fig. 10. Fault in 𝑆3' at GSC: (a) 𝑖𝑐2 phase current; (b) 𝑖𝑇𝑟𝑐2 Triac current.

4 HIL results have also been satisfying and in accordance with simulation ones, which shows
5 that the FD algorithm and the controller can be used in an actual system. Since the HIL
6 results have been similar to simulation results, they are not repeated here.

7 3.3. Experimental results

8

9 The control can be implemented on a proper digital device, such as a powerful

10 microcontroller or DSP. Here, a DS1005 dSPACE is used for rapid prototyping. On the other
11 hand, fault diagnosis algorithm must be carried out in parallel with other control tasks of the
12 system, and must be very fast. Therefore, these devices are not the best options for
13 implementation of the fault diagnosis and reconfiguration algorithm. This is mostly due to
14 the fact that all of these processors execute their commands in a sequential manner, and
15 provide limited overall bandwidth. Moreover, the waiting time for Interrupt Service
16 Routines is one of their other shortcomings for this application. Therefore, logic level
17 devices such as FPGA or CPLDs seem to be more suitable for implementation of the fault
18 diagnosis algorithm. FPGAs allow very high speed calculations, and more importantly they
19 are inherently parallel structured. Here for fault diagnosis, an Altera Stratix EP1S80B956C6
20 FPGA is used which includes 79040 logic cells, 12 programmable PLLs and 679 IOs.
21 Moreover, ADS7810U ADCs are used to convert the measured voltages from analog to
22 digital.

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1 Fig. 11 shows the implemented experimental setup. It is worth mentioning that the
2 proposed fault diagnosis and reconfiguration does not depend on the system parameters,
3 therefore a low or medium power lab setup can be used for these evaluations. A DFIG with
4 3 kW nominal power is coupled with a DC machine that emulates the wind turbine. Two
5 three phase AC/DC converters from Semikron which use SKM50GB123D IGBTs and SKHI22A
6 drivers form the PE stage. An additional leg (redundant leg) is added to one of the
7 converters, using the same type of IGBT modules and drivers. Each converter is also
8 equipped with a 2200 𝜇𝐹 capacitor. The converters are connected to the grid using a 3 𝑚𝐻
9 inductance with 0.4 Ω resistance.

10 FPGA sampling and step time is set equal to 1 𝜇𝑠, and dSPACE has a sampling time of 100 𝜇𝑠
11 , equivalent to a switching frequency of 10 kHz. CV3-1200 voltage transducers and PR30
12 current clamps are used for voltage and current measurement, respectively. As mentioned
13 in section 2.B, the choice of the parameter N in the FD algorithm depends on the system
14 parameters. This depends directly on the total time delay in the control loop (including
15 sensors, ADCs, FPGA, converters…). In the studied system, maximum total delay is
16 calculated by adding the maximum delay of each of these elements, and is estimated to 13
17 µs. Therefore the fault observation time is chosen equal to 30 𝜇𝑠 because while it is
18 considerably larger than that total delay, it still allows very fast fault diagnosis. In most
19 practical cases, this value seems to be adequately larger than the total delay of the system,
20 but if necessary, for specific systems it can be reduced. Considering a sampling period of
21 1us, N is then chosen equal to 30.

22

23

24 Fig. 11. Implemented experimental setup.

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1 The dSPACE system includes a DS1005 processor, DS2004 interface board (ADC and DAC)
2 and DS5101 PWM board. A software package called ControlDesk runs on a host PC and acts
3 as an interface for the dSPACE system for data logging, visualisation and control.

4 Table II shows the experimental setup parameters.

5 Table II: experimental setup parameters.

System Parameters
𝑈𝑟 = 𝑈𝑠 = 200 𝑉
𝑁𝑟
𝑃𝑛 = 3 𝑘𝑊, 𝑓 = 50 𝐻𝑧, 𝑝 = 2, ≈ 0,385
𝑁𝑠
DFIG
𝑅𝑠 = 1,68 Ω, 𝑅𝑟 = 0,39 Ω
𝐿𝑠 = 0,309 𝐻 , 𝐿𝑟 = 0,0368 𝐻
𝐿𝑚 = 0,294 𝐻,
DC machine 𝑃𝑛 = 3 𝑘𝑊, 𝑅𝑎 = 1.23 𝛺, 𝐿𝑎 = 0.008 𝐻
DC-link 𝐶 = 2.2 𝑚𝐹, 𝑉𝑑𝑐 = 400 𝑉
GSC filter 𝑅𝑓 = 0.4 Ω, 𝐿𝑓 = 3 𝑚𝐻
Grid 𝑈 = 200 𝑉, 𝑓 = 50 𝐻𝑧
6

7 Experimental results of fault diagnosis signals are recorded using two 4-channel Lecroy
8 oscilloscopes, while DFIG operation ones are recorded by using ControlDesk environment in
9 the host PC in binary format and then are plotted using Matlab.

10 First, the fault-tolerant capability of the system for an open-circuit switch fault in the upper
11 switch of 𝑐1 leg at the RSC is investigated (Fig.1). It is worth mentioning that in all
12 experimental tests, stator active and reactive power references are set at 1 kW and 0 kVAr,
13 respectively. Fault is artificially generated by setting the switching command of the driver to
14 zero.

15 Fig. 12 shows the active and reactive powers before and after fault occurrence. Clearly fault
16 diagnosis has been successful and smooth reconfiguration has taken place. Fig. 13 shows
17 the rotor currents during fault occurrence and shows that they are not affected by the fault.
18 Fig. 14(a) shows the details of fault detection. The fault occurrence moment is visualised
19 when the fault signal goes from 1 to 0. This is in fact the signal that is multiplied in the gate
20 signal of the faulty switch. As soon as fault occurs, the fault diagnosis counter starts
21 increasing, and after 30 us, the fault is declared. Fig. 14(b) shows the faulty phase current,
22 as well as the corresponding Triac’s current.

23

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2 Fig. 12. Active and reactive stator powers before and after a fault in RSC.

4 Fig . 13. Rotor currents for a fault in RSC.

(a) (b)
5

6 Fig. 14. Fault detection and reconfiguration for a fault in RSC: (a) from top to bottom: faulty phase
7 current (20 A/div), Triac 𝑇𝑟𝑐1 current (20A/div), fault signal, fault detection signal- time scale:
8 100ms/div; (b) detailed view of fault detection signals; from top to bottom: Fault signal, fault
9 detection counter’s output, Fault detection signal, switching command applied to 𝑆3 (10V/div) - time
10 scale: 100µs/div.

11 Similar tests are carried out for an open-circuit switch fault in the GSC (Fig.1). Fig. 15 shows
12 stator active and reactive powers and Fig. 16 gives the GSC current before and after fault
13 occurrence. Fig. 17 shows the fault detection signals and faulty phase and the corresponding

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1 Triac’s currents. All these results testify that by using the proposed fault diagnosis and
2 reconfiguration it is possible to detect a fault rapidly and guarantee the continuity of service
3 in the WECS.

1000

500
Ps (W), Qs (VAr)

-500

-1000

-1500
0 1 2 3 4 5 6 7 8 9 10

4 t (s)

5 Fig. 15. Stator active and reactive powers for a fault in GSC.

7 Fig. 16. GSC output currents for a fault in one of GSC’s switches.

(b)
8 (a)

9 Fig. 17. Fault detection and reconfiguration for a fault in GSC: (a) from top to bottom: faulty phase
10 current (5 A/div), triac 𝑇𝑟𝑐1 current (5A/div), fault signal, fault detection signal- time scale:
11 10ms/div; (b) detailed view of fault detection signals; from top to bottom: Fault signal, fault
12 detection counter’s output, Fault detection signal, switching command applied to 𝑆3' (10V/div) -
13 time scale: 100µs/div.

14 In order to better evaluate the effectiveness of the proposed fault tolerant technique and
15 fault detection method, Table III gives the comparison results with some of the existing
16 methods in the literature. Using the proposed fault detection method, the fault can be

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1 detected faster than in other publications. Also, in the proposed fault-tolerant technique
2 only two additional switches are required, while the rated power capability can be
3 preserved in the post-fault operation. This is while other methods have drastic drop in their
4 power handling capability in the post-fault mode, which can limit their operation range.
5 Therefore the proposed method seems to be offering a good compromise between
6 performance and cost.

7 Table III. Comparison of the proposed method with existing methods

Methods Effectiveness Detection Post-fault Additional

time Output components
reported power
Proposed method Independent of rotor 30𝜇𝑠 Rated power Two IGBTs, 6
frequency and wind Triacs
disturbances, same power
output capability in post-
fault mode
Fault-tolerant T-type Limited operating range in Not Reduced No additional
converter [12] post-fault mode, discussed power component

Fault-tolerant PMSG drive Limited operating range in 6 𝑚𝑠 Reduced One Triac

[13] post-fault mode power

Fault-tolerant direct Limited operating range in 1.2 𝑚𝑠 Reduced Three Triacs

controlled PMSG drive [14] post-fault mode or necessary power
to oversize components
System reconfiguration Limited operating range in Not Reduced Six Triacs
under open-switch faults in a post-fault mode, discussed power
doubly fed induction
machine [16]
8

9 For future works, the effect of a second fault on the system and possibility of degraded
10 mode operation in this case can be evaluated. Also, it might be interesting to see if it is
11 possible to decrease the number of voltage measurement circuits, by using modern control
12 techniques based on observers [28].

13

14

15 4. Conclusion
16

17 In this paper, a comprehensive fault tolerant power electronics interface for doubly-fed
18 induction generator-based wind energy systems, including a robust and very fast open-
19 circuit switch fault diagnosis is presented. First the whole system is modelled and

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1 simulations are carried out. In the second step the proposed fault diagnosis method and
2 converter reconfiguration for post fault operation are validated through an approach called
3 "FPGA in the Loop" from Hardware in the Loop family. The switch fault diagnosis method
4 proposed in this paper is extremely fast, in comparison with other methods available in the
5 literature. Moreover, the fault diagnosis is based on voltage rather than current
6 measurement, and therefore is not sensitive to the operation conditions such as variable
7 frequency of rotor currents and variable wind speeds. The fault-tolerant converter uses an
8 additional leg which can replace a faulty one upon the fault diagnosis. Finally, as the
9 proposed fault diagnosis and reconfiguration does not depend on the system parameters,
10 therefore a low power lab setup is built for the experimental validations. The experimental
11 results testify that by using the proposed fault diagnosis and reconfiguration it is possible to
12 detect a fault rapidly and guarantee the service continuity of the studied wind energy
13 system. Moreover, using the proposed method, it is possible to guarantee the same power
14 capability of the system in the post-fault mode.

15 References
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