Microelectronics Journal 41 (2010) 820–826

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Microelectronics Journal
journal homepage: [Link]/locate/mejo

A new quantum-dot cellular automata full-adder

Keivan Navi a,n, Razieh Farazkish b, Samira Sayedsalehi b, Mostafa Rahimi Azghadi c
a
Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, Iran
b
Department of Computer Engineering, Science and Research Branch of Islamic Azad University, Tehran, Iran
c
School of Electrical and Electronic Engineering, The University of Adelaide, Adelaide, SA 5005, Australia

a r t i c l e in f o a b s t r a c t

Article history: A novel expandable five-input majority gate for quantum-dot cellular automata and a new full-adder
Received 12 August 2009 cell are presented. Quantum-dot cellular automata (QCA) is an emerging technology and a possible
Received in revised form alternative for semiconductor transistor based technologies. A novel QCA majority-logic gate is
4 July 2010
proposed. This component is suitable for designing QCA circuits. The gate is simple in structure and
Accepted 7 July 2010
powerful in terms of implementing digital functions. By applying these kinds of gates, the hardware
Available online 9 September 2010
requirement for a QCA design can be reduced and circuits can be simpler in level, gate counts and clock
Keywords: phases. In order to verify the functionality of the proposed device, some physical proofs are provided.
Quantum-dot cellular automata The proper functionality of the FA is checked by means of computer simulations using QCADesigner
Majority gate
tool. Both simulation results and physical relations confirm our claims and its usefulness in designing
Nanoelectronic circuits
every digital circuit.
QCA full-adder
& 2010 Elsevier Ltd. All rights reserved.

1. Introduction Instead of using Boolean logic operators (AND, OR and their

complements), majority logic represents and manipulates digital
Current CMOS technology is going to approach a scaling limit functions on the basis of majority decision [9]. The logic process of
in deep nanometer technologies. The CMOS technology in nano- majority logic is more sophisticated than that of Boolean logic;
scales has some problems because of increase in amounts of consequently, majority logic is more powerful for implementing a
variation in every aspect of a nanometer design. One conventional given digital function with a smaller number of logic gates [10,11].
way to enhance the performance of logical systems is to use In this paper, we propose a new design for majority gates
parallelism [1,2]. But in order to enhance the overall performance resulting in simplification of logical functions. By applying this
of the system new nanotechnologies must be taken into account. form of majority gate, we can simplify logical functions and
Quantum-dot cellular automata (QCA) is one of the promising achieve improved results. The presented method is justified based
new technologies that not only gives a solution at nano-scale, but on physical relation proofs as well as simulation results. In
also it offers a new method of computation and information comparison to other existing implementations, this method has
transformation [3,4]. The basic building block of QCA circuit is demonstrated significant improvements. The proposed majority
majority gate; hence, efficiently constructing QCA circuits using gate resulted in decrease in gate counts and levels in QCA designs.
majority gates has attracted a lot of attentions, but some of them One of the most important components in every arithmetic and
are not realizable or not expandable [5,7]. Several studies have digital circuits in QCA and VLSI is full-adder [7,12,13].
reported that QCA can be used to design general purpose To demonstrate the efficiency of the proposed gate, a QCA full-
computational and memory circuits [8]. Since every QCA circuit adder is implemented using the new presented majority gate.
can be implemented only using majority and inverter gates, Comparisons show that the new full-adder is more efficient in
another important component in constructing QCA circuits is the terms of cell counts, complexity and area in comparison to other
inverter. Hence, efficiently constructing an inverter in QCA is of previous state-of-the-art designs [4,7,14–17].
great importance [6].
As already mentioned, the basic building block of QCA circuit is
majority gate; majority logic is a way of implementing digital
2. Materials and methods
operations in a manner different from that of Boolean logic.

2.1. Background
n
Corresponding author. Tel.: +98 2129902282; fax: + 98 2122431804.
E-mail addresses: navi@[Link] (K. Navi), [Link]@[Link]
Quantum cellular automata is a new device architecture, which
(R. Farazkish), [Link]@[Link] (S. Sayedsalehi), is proper for the nanometer scale [18]. The principle of QCA was
mostafa@[Link] (M. Rahimi Azghadi). first proposed by Lent and Tougaw [18]. A quantum cell can be

0026-2692/$ - see front matter & 2010 Elsevier Ltd. All rights reserved.
doi:10.1016/[Link].2010.07.003
 K. Navi et al. / Microelectronics Journal 41 (2010) 820–826 821

viewed as a set of four charge containers or dots, positioned at the Table 2

corners of a square. The cell contains two extra mobile electrons, Truth table of a five-input majority gate based on sum of inputs.
which can quantum mechanically tunnel between dots but not P
(A,B,C,D,E) M(A,B,C,D,E)
cells [4,19]. The electrons are forced to the corner positions by
Columbic repulsion. The two possible polarization states represent 0 0
logic ‘‘0’’ and logic ‘‘1’’, as shown in Fig. 1(a) [4,20]. 1 0
As shown in Fig. 1(b), an ordinary QCA gate implementing the 2 0
3 1
majority function is as follows: 4 1
Assuming three inputs labeled A, B and C, the logic function of 5 1
majority gate is
MðA,B,CÞ ¼ AB þ AC þ BC ð1Þ
Besides, truth table of a three-input majority gate is shown in
Table 1. As illustrated in Fig. 1(b) each QCA majority gate in
normal form requires only five QCA cells. And in Fig. 1(c) a QCA D
inverter is shown.
B 2
A
2.2. Five-input majority gate B
A 1 3 out C Maj 5 M(A, B, C, D, E)
D
A five pins majority gate must have five inputs and one output. E
A truth table of a five-input majority gate based on sum of inputs C 4
is shown in Table 2.
E

Quantum Dot Electron Fig. 2. (a) Proposed five-input majority gate and (b) Schematic symbol for the
majority gate.

Majority is a voter. In our new structure, a majority gate can be

implemented as shown in Fig. 2(a). In this scheme we have five
inputs labeled A, B, C, D and E and the output cell is shown by out. In
P = +1 P = -1 addition, four middle cells labeled 1, 2, 3 and 4. Polarization of input
cells is fixed and middle cells and output cell are free to change.
In this design the input cell A only has an effect on middle cell
Input a 1. Also, the input cells B and C have only effect on 1, 2, 3 and on 1,
Device A Output 3, 4 middle cells, respectively. In a similar manner, the input cells
cell D and E have effect on middle cells 2 and 4. Through these effects,
A the majority decision of inputs is transferred to the output and
Input c OUT B Maj 3 M(A,B,C) constructs the five-input majority gate, efficiently.
C C The majority voting logic function can be expressed in terms of
fundamental Boolean operator as shown in
B
Input b MðA,B,C,D,EÞ ¼ ABC þ ABD þ ABE þACD þACE þ ADEþ BCD
þBCE þ BDE þ CDE ð2Þ

A schematic symbol of a five-input majority gate is shown in

Fig. 2(b). We can implement a three-input AND gate and also a
1 0 three-input OR gate using this majority gate. These functions are
as
MðA,B,C,0,0Þ ¼ ABC ð3aÞ
Fig. 1. (a) Basic QCA cell and binary encoding, (b) A QCA majority gate and (c) A
QCA inverter.
MðA,B,C,1,1Þ ¼ A þ B þ C ð3bÞ
As it is clear in Fig. 2(a), a five-input majority gate only needs
Table 1
Truth table of a three-input majority gate.
ten cells and by considering some physical relations it is
implemented.
A B C M(A,B,C) Regarding the physical proofs, assume that all cells are similar
and the length of each one is a (a ¼18 nm) and there is a space of x
0 0 0 0
(x ¼2 nm) between each two neighbor cells.
0 0 1 0
0 1 0 0 In all figures, rectangles show a QCA cell and the circles inside
0 1 1 1 show the electrons insides that cell. It should be noted that in order
1 0 0 0 to achieve more stability, electrons of QCA cell are arranged in such a
1 0 1 1 manner that their potential energy reaches the minimum level.
1 1 0 1
1 1 1 1
The potential energy between two electron charges is
calculated using relation (4a). In this equation, U is the potential
822 K. Navi et al. / Microelectronics Journal 41 (2010) 820–826

D D
e7 e7
e8 e8

e4 e4
B 2 B 2
e3 e3

e1 x e1 y
A 1 3 out A 1 3 out
e2 y e2 x

e5 e5
C 4 C 4
e6 e6

e9 e9
e10 e10

E E
Fig. 3. (a) The one value in cell 1 and (b) The zero value in cell 1.

energy, k is fixed colon, q1 and q2 are electric charges and r is the potential energy (UT) in both states using Eq. (5). The comparison of
distance between two electric charges. By putting the values of k total potential energies in both (a) and (b) states shows which state
and q, we obtain Eq. (4b). UT is the summation of potential (a or b) is more stable. The state that has the lower potential energy
energies that is calculated from Eq. (5) [21–23]. level is the one which is more suitable for us. With determining the
value of cell 1 and considering input cells B and C the values of cell 2
kq1 q2 and 4 can be simultaneously computed in a similar manner to that for
U¼ ð4aÞ
r cell 1. Then, with having all values of cells 1, 2 and 4 and also with
considering cells B and C, which have a diagonal effect on cell 3, the
kq1 q2 ¼ 9  109  ð1:6Þ2  1038 ¼ 23:04  1029 ¼ A ¼ cte ð4bÞ value of this cell can be computed and this result is transferred to the
output cell, which give us a majority decision of inputs A, B, C, D and E.
As the proof method is similar for all cells and their values,
X
n
UT ¼ Ui ð5Þ only the first part of this proof is stated and the rest of relations
i¼1 are omitted due to lack of space. (Fig. 3)

Fig. 3(a) (electron x) Fig. 3(a) (electron y)

23:041029 23:041029
U1 ¼ A
r1 ¼ 20109
 1:15  1020 J U1 ¼ A
r1 ¼ 42:04109
 0:55  1020 J
23:041029 23:041029
U2 ¼ A
r2 ¼ 18:11109
 1:27  1020 J U2 ¼ A
r2 ¼ 20109
 1:15  1020 J
23:041029 20 23:041029
U3 ¼ A
r3 ¼ 2109
 11:52  10 J U3 ¼ A
r3 ¼ 26:91109
 0:86  1020 J
23:041029 23:041029
U4 ¼ A
r4 ¼  0:86  1020 J U4 ¼ A
r4 ¼  0:61  1020 J
26:91109 38109
23:041029 23:041029
U5 ¼ A
r5 ¼  1:15  1020 J U5 ¼ A
r5 ¼  1:27  1020 J
20109 18:11109
23:041029
U6 ¼ A
r6 ¼  1:15  1020 J
20109
U6 ¼ A
¼ 23:0410 29
 0:55  10 20
J P
6
r6 42:04109 UT12 ¼ Ui ¼ 5:59  1020 J
X 6 i¼1
UT11 ¼ Ui ¼ 16:5  1020 J
i¼1

P
2
UT1 ¼ U1i ¼ 22:09  1020 J
i¼1

2.3. Physical proof Since cells D and E are in a roughly long distance from cell 1,
their potential energy can be neglected.
As a five-input majority gate has 32 different input states, we
Fig. 3(b) (electron x): Fig. 3(b) (electron y):
should check all the states to verify the correctness of the gate.
P6 P6
Here, only one state (A ¼1, B ¼0, C ¼D ¼E¼1) is proved and the UT21 ¼ Ui ¼ 26:46  1020 J UT22 ¼ Ui ¼ 5:36  1020 J
other states can be proved as well. i¼1 i¼1

First, we calculate the potential energy existing between each P

2
20
UT2 ¼ U2i ¼ 31:82  10 J
electron (e1, e2, e3, e4, e5 and e6) with electrons ‘‘x’’ and ‘‘y’’ in (a) and i¼1
(b) states using (4a) and (4b) equations. For example Ui is the
potential energy existing between electron ei and x (or y). Also, ri is the With comparison of the achieved results, the electrons in cell 1
distance between two electron charges. Then we calculate the total are positioned in state (a) because this state is more stable and
 K. Navi et al. / Microelectronics Journal 41 (2010) 820–826 823

has a lower potential energy. As already mentioned, the It should be noted that in this design, a one-bit full-adder is
computation of potential energies for other cells (2, 3 and 4) is implemented using only inverters and majority gates, whereas in
similar to those which have done for cell 1 and only the final order to implement the sum function based on AND/OR imple-
results are mentioned. It is worth mentioning that in all cells UT1 mentation, the number of gates involved will be increased.
is the potential energy in + 1 polarization and UT2 is the potential
energy in 1 polarization.
cell 2: cell 3: cell 4: 3.2. A QCA full-adder with five gates
UT1 ¼ 20:79  1020 J UT1 ¼ 12:36  1020 J UT1 ¼ 17:94  1020 J
UT2 ¼ 21:35  1020 J UT2 ¼ 41:55  1020 J UT2 ¼ 31:09  1020 J In [14] a method for decreasing the number of majority gates
for QCA circuits has been presented and another form of QCA full-
adder is expressed. In this design there are three three-input
Considering the above computing, we can infer that the majority gates and two inverters (Fig. 5). It is worth mentioning
proposed structure for implementing a five-input majority gate that layout of this full-adder has four clocking phases.
is completely true and resulted in a correct state for the output
cell, which shows the majority decision.
After physical proof, we can also check the proposed design 3.3. A QCA full-adder with three gates
using QCADesigner. Simulation of this majority gate is shown in
Section 4. The next section shows the use of the new majority gate
In one of the last design, a QCA full-adder is implemented only
for implementing a full-adder.
using three gates, two majority gates and one inverter (Fig. 6).
Although this design has used an unconventional form of majority
3. One bit QCA full-adder gates, a gate with five inputs, it has a simpler design scheme in
comparison to other previous design [7]. In this study, authors
have introduced a new design for QCA cells to implement their
The proposed majority design is applied to implement a QCA
proposed majority design. This new cell has a cubic structure and
full-adder. First, other QCA implementations of full-adders are
maybe it is not simply feasible to fabricate. Although these kinds
presented and then our design is introduced. A one-bit full-adder
of cells seem too hard to be implemented, the idea of five-input
is defined as follows:
majority gates is worth considering.
Inputs: operand bits (A, B) and carry bit is shown as C.
Outputs: Sum and Carryout.
3.4. A QCA full-adder with five gates and three clocks

Recently, another design is presented which introduce a new

3.1. A QCA full-adder with seven gates
design for QCA full-adders [15]. This design is the so-called carry
flow adder (CFA), which revised the previous full-adder scheme.
In a classic design in [4], a full-adder with five, three-input
The schematic of this design is shown in Fig. 7.
majority gates and three inverters has been implemented. We can
This design has only three clock phases and also has a lower
simplify this design and reduce one majority gate simply. Thus, an
number of cells in comparison to all previous designs.
easier form for this QCA full-adder can be implemented using four
majority gates and three inverters (Fig. 4).

A B C

A B C Carry out
Maj 3

Maj 3 sum

Maj 3
Mja 3 Carry out

Fig. 5. One-bit QCA full-adder with five gates.

Maj 3
A B C

Maj 3 Carry out

Maj 3 Maj 3 sum

Maj 5 sum

Fig. 4. One-bit QCA full-adder with seven gates. Fig. 6. One-bit QCA full-adder with three gates.
824 K. Navi et al. / Microelectronics Journal 41 (2010) 820–826

B A

Maj 3

Maj 3 C

Carry out Maj 3

sum

Fig. 7. One-bit QCA full-adder with five gates and three clocks.

Fig. 10. Layout of the proposed full-adder in three layers and using three clock
phases.

diagram for the full-adder in this paper uses two inverters and
two majority gates and in comparison with the previous design
(Fig. 6) in [7], it has one more inverter gate, the efficient layout of
the new schematic worth tolerating one more inverter gate.
Because of the new design for five-input majority gate, it would
be better to use two inverters rather than one inverter and some
wires for transferring inverted values to another point. Also, the
previous design uses single electron box (SEB) structure that
consists of two cells and four capacitors. In the proposed design,
Fig. 8. (a) A QCA cell and (b) SEB structure. we used conventional form of cells that has an efficient layout to
be simply fabricated. Fig. 8 shows the differences between QCA
cell and SEB structure.
A B C The proposed full-adder is implemented only using conven-
tional cells and in three layers. It has 73 cells and it longs three
clock phases to generate correct outputs (Sum and Carryout). In
Maj 3 Carry out
comparison to other previous design this full-adder resulted in
significant improvements in terms of area, complexity and has a
similar structure in terms of delay. Simulation results section
Maj 5 sum compares all previous designs and shows the prosperity of the
new presented design.

4. Simulation and practical results

Fig. 9. Schematic design of the proposed full-adder with two majority gates and
two inverters.
For the proposed circuit layout and functionality checking, a
simulation tool for QCA circuits, QCADesigner version 2.0.3 [24], is
used. The following parameters are used for a bistable approx-
3.5. Proposed QCA full-adder imation: cell size ¼18 nm, number of samples¼50,000, conver-
gence tolerance¼ 0.0000100, radius of effect¼65.000000 nm,
As already mentioned, in order to implement a new five-input relative permittivity¼12.900000, clock high¼ 9.800000e 022 J,
majority gate, a new structure is introduced in this paper. This clock low¼3.800000e 023 J, clock shift¼0, clock amplitude
design realizes a five-input majority gate in a planar structure factor¼2.000000, layer separation ¼11.500000 and maximum
(Fig. 2). By means of this new five-input majority gate, a new and iterations per sample¼ 100. Most of the mentioned parameters
efficient full-adder is designed. The schematic design of the are default values in QCADesigner.
proposed full-adder is presented in Fig. 9. In addition, Fig. 10 Figs. 11and 12 show simulation results of proposed five-input
illustrates the layout of the proposed full-adder, which uses a majority gate and one-bit full-adder is constructed using this new
planner five-input majority gate. Although the proposed logic device.
 K. Navi et al. / Microelectronics Journal 41 (2010) 820–826 825

Fig. 11. Simulation results for proposed five-input majority gate.

Fig. 12. Simulation results for proposed one-bit full-adder.

Layout of the previous designs and their simulation results are in the proposed design we used multilayer interconnection by
prepared and compared in this section. Simulation results reveal stacking cells one on top of another that can transmit signal on
that the proposed full-adder cell is better than previous ones. Several another layer. In this paper we applied the inputs on upper layer.
studies about multilayer design in QCA have been proposed [25,26]. Table 3 demonstrates the differences among all the designs
In the traditional QCA design, cells are placed on a single plane, but discussed in this paper.
826 K. Navi et al. / Microelectronics Journal 41 (2010) 820–826

Table 3 [5] K. Navi, S. Sayedsalehi, R. Farazkish, [Link] Azghadi, Five-input majority

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