AD-A 153 744

RADC-TR-84-254
Final Technical Report
December 1984

RELIABILITY DERATING PROCEDURES

Martin Marietta Aerospace

Donald J. Eskin and Carolyn R. McCanlesz

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~ *~4
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RADC-TR-84-25 4 has been reviewed and is approved for

APPROVED:

BRUCE DUDLEY
Project Engineer

"APPROVED: ,).A,.

ANTHONY J. FEDUCCIA, Acting Chief

Reliability & Compatibility Division

FOR TIE COMMANDER:

JOHN A. RITZ
Acting Chief, Plans Office

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It. TITLE eIncluide Security Clamiflceuaon)
RELIARILITY DERATING PROCEDURES
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*13e. EORAT
CYEO CODS TIM SUBJRECT TEMS 4on. oAT OFe,REOR (Yr..weNd. Dea~y) b bPoGE
S. COUNT

17. ASRCICOSAIUCueOil .Iotiid bywr

I&I SUBJEC blockner
umber)yb~cknm
TERMSUOI onnhf an

electronic parts, development of thermal models, creation of temperature verification

methods, and the development of the framework leading to the creation of a military
standard for derating of parts. The results of the study revealed that derating data on
compl~ex devices are difficult to obtain so an alternate approac'h was used Involving failure
rate data from MIL-11DBK-217 6nd' specific failure mode information. Thermal models, both
internal and nodal, were developed for six package types and temperature test results for
one of these types were compared to the theoretical value. The comparison was extremely
favorable. *~ - -

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22s. NAME OF RESPONSIBLE INDIVIDUAL 220. TGLEPIIO*I NUMBER M2. of tIca SVYMBoL
Itntftd* Awee Cede,
Bruce W. Dudley (315) 330-2608. I RADC (IRBEJR)
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 FOREWORD

This final study contract technical report was prepared by Martin

Marietta Orlando Aerospace as a part of the engineering services to the
Rome Air Development Center (RADC), Griffiss AFB, New York, under contract
F30602-83-C-0006, CDRL A003. The RADC technical monitor for this program
is Mr. Bruce Dudley.

Accession For
NTI S GRA&I
DTIC TA3
Uncrmnnounced C]
- ~Jtis ti • icat ion

A ,I ;.'ity Codes Co,

;rtt

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 CONTENTS

1.0 EXECUTIVE SUMMARY .. . . ..... . . . ..... ..... .. 1

2.0 DEVICE DERATING GUIDELINES .............. ................... 3

2.1 Derating Definitions ............... ................... 3
2.1.1 Derating Levels ............. ................... 3
S2.1.2 Part Quality levels ........... ................. 3
2.1.3 Environments ................ .................... 4

2.2 Hybrid Devices ................. ....... .............. 4

2.3 Complex Integrated Circuits ..... ....... ................ 5
2.4 Memory Devices ................. ....................... 6
2.5 Microwave Devices ..... ........... ..................... 7

2.5.1 GaAs FET....................... 8

2.5.2 Transistors/IMPATT/Gunn ......... ............... 9
2.5.3 Varactor/Step Recovery/PIN/Tunnel . ... . . . . . .. 9
2.5.4 Silicon and Germanium Detectors/Mixers (Schottky) 9

2.6 Surface Acoustic Wave (SAW) De1ices.............11

3.0 BASIS FOR DEVICE DERATING ............... ........... ....... 13

"3.1 Rationale of Device Derating ...... ................ ... 13
3.2 Basis for Hybrid Derating ..... ..... ........... .... ... 18
3.3 Basis for Complex Integrated Circuit Derating ......... ... 21
3.4 Basis for Memory Device Derating ..... .............. ... 26
3.5 Basis for Microwave Device Derating ........ ............ 33
-' 3.5.1 GaAs FET .............. ..................... ... 34
3.5.2 Transistor/INPATT/Gunn .. ..... ........ . . . . .. 35
3.5.3 Varactor/Step Recovery/PIN/Tunnel .... ......... ... 36
3.5.4 Silicon and Germanium Detectors/Mixers .. ....... ... 38

3.6 Basis for SAW Device Derating ....... ............... ... 42

"4.0 FAILURE MODES/MECHANISMS .............. ............. ....... 51

4.1 General ..... ............. ........................ ... 51
- 4.2 Application Guidelines .... ........ ................ 51
5.0 TEMPERATURE MODELING AND VERIFICATION ..... .............. ... 58

* 5.1 Objectivw .................. ......................... 58

5.2 Approach ............. .......................... ... 58
5.3 Internal l.o.. ....... ....................... ... 59
5.3.1 Square Chip Model ...... ..... .............. ... 60
5.3.2 Rectangular Model ....... .................. ... 66
* 5.3.3 Circular Model ................... .......... ... 89
"•..5.3.4 Hybrid Modek .......... 9
534 ybrid-.....................96

iiv

. .. . ., ...
 5.4 External Model .
....................
. . 101

5.4.1 Nodal Programs .. ...................... ...........

108
5.4.2 External Model Correlation. ............ ............
1l
5.4.3 Package Derating Curves . . . . . . . . . . . . . . .117

[Link] Side-Brazed Package. ............ .........

118
[Link] Ceramic Chip Carrier .. ............ .......
119
[Link] Cerdip Package .. ............ .............
119
[Link] Flatpack Package.. .. .......... ...........
122
[Link] Hybrid Package .. .. .. .. .. .. .. .. 122
[Link] Axial Stud Package .. .......... ...........
127

5.5 Measurement Equipment .. ........................

.........
127

6.0 COST VERSUS RELIABILITY. .. ......................

.............
130

7.0 MILITARY STANDARD FRAMIEWORK. ........................

.........
137

8.0 CONCLUSIONS AND RECOMMENDATIONS. .. ......................

.....
138

8.1 Conclusions .. ..........................

.................
138
8.2 Recommendations . .. .. .. .. .. .. .. .. .. .. .139

Append ices

1.0 BIBLIOGRAPHY. ............ ..........................

.........
141

2.0 POTENTIAL DATA SOURCES .. ..........................

...........
145

3.0 LITERATURE SEARCH AND DATA SURVEY .. .......... .. .. .. .. .153

4.0 DATA GROUPING .. ............ ..........................

.......
168

5.0 INTERN4AL MODEL .. ............. . .. .. .. .. .. .. .. .. 170

5.1 Square Surface Programs .. ........................ ....... 170

5.2 Rectangular Surface Programs .t. .. .. .. .. .. ... 178
5.3 Circular Surface Programs. ............ ................... 187
5.4 Spreading Angle Analysis. .. .............. ....... ....... 195

6.0 EXTERNAL MODEL. .............. .......................... ..... 197

6.1 Side-Brazed Package .. ........................ ........... 197

6.2 Ceramic Chip Carrier. .. ........................ ......... 209
6.3 Cerdip Package. .. ......... .............. ............... 217
6.4 Flatpack .. ............ ............................ .....
227
6.5 Hybrid Package. .. ........................ ............... 234
6.6 Axial Stud Package. .. ........................ ........... 241

7.0 MEASUREMENT TESTS. .. ........................

.................
250

7.1 Temperature Measurement Tests. ............ ...............

251
7.2 Hermetic Chip Carrier Thermal Test .. ............ ......... 291

* '4
 ILLUSTRATIONS

1 Quality Level Impact on Failure Rate . ... 14

2 Environmental Impact on Failure Rate ............. 14
3 Environmental Impact on Failure Rate .............. 15
4 Environmental Impact on Failure Rate ......... 16
5 Environmental Impact on Failure Rate ......... 16
"6 Environmental Impact on Failure Rate ...... ............ .. 17
7 Envirppmental Impact on Failure Rate ..... .............. ... 17
8 Microelectronics: Junction Temperature versus Failure Rate . 19
9 Hybrid: Package Temperature versus Interconnections ...... 19
11 Hybrid: Package Temperature versus Package Size
(2 inch perimeter seal) ........ ................... .. 20
12 Hybrid: Density Impact on Failure Rate .......... ......... 21
13 Complex IC: Junction Temperature versus Voltage Stress . . 23
14 Complex IC: Junction Temperature versus Voltage Stress .. 24
9. 15 Gate Count Impact on Failure Rate of Bipolar Devices
(CI Complexity) . ........... ........... ............. ... 24
16 Gate Count Impact on Failure Rate of Bipolar Devices
(C2 Complexity) ............ ... ....................... 25
,17 Gate Count Impact on Failure Rate of MOS Devices
(Cl Complexity) ...... ................. ....... ... 25
18 Gate Count Impact on Failure Rate of MOS Devices
(C2 Complexity) ............ ............. ........... ... 26
19 Bit Count Impact on Failure Rate of Bipolar RAM Devices . ... 28
20 Bit Count Impact on Failure Rate of ROM and PROM Devices. . 28
"21 Memory Devices: Bit Count Impact on Failure Rate of MOS
RAM Devices .......... ............. .............. 29
22 Complexity Factor Impact on Failure Rate of Bubble Memories 31
23 Complexity Factor Impact on Failure Rate of Bubble Memories . 31
24 Duty Cycle Factor Impact on Bubble Memory Failure Rate. .... 32
25 Write-Duty Cycle Factor Impact on Failure Rate of Bubble
* Memory ......... ..... ........................... ... 32
26 Temperature Impact on Failure Rate of GaAs FET ........... ... 34
27 Operating Power and Frequency Impact on Failure Rate of
Microwave Transistors ........ ............... ........... 36
28 Junction Temperature Impact on Failure Rate of Microwave
Transistors ............... .............. 37
29 Funtion Temperature Impact on Failure Rate of Microwave
* Transistors ......... ........................ .. 37
177 30 Temperature Impact on Failure Rate of Varactor, Step,
Recovery, PIN and Tunnel Diodes .......... ............... 38
31 Temperature Impact on Failure Rate of Silicon Microwave
Mixers ............... ............................ ... 39
32 Temperature Impact on Failure Rate of Germanium Microwave
* Mixers ..................................... 40
33 Temperature Impact on Failure Rate of Silicon Microwave
Detectors ............ ............. ............. ....... 4G
34 Temperature Impact on Failure Rate of Silicon Schottky Diode
Detector ........... ... ........................... ... 41

vi
S" V

............ **g*~.... . , " * ..

i'I

ILLUSTRATIONS

35 Temperature Impact on Failure Rate of Germanium Microwave

Detector ....... ......... ........................... 41
36 SAW Transducer. . . . . . . . . . . . ........ . . . . . 43
37 SAW Frequency versus Time...... ....................... 48
38 SAW Frequency versus Time ...... ................... 49
39 The Primary Concerns of Semiconductor Reliability ......... ... 52
40 Reliability Concerns: The Die Fabrication Process ........... 53
41 Reliability Concerns: The Assembly Process .... .......... ... 54
42 Hybrid Model Heat Generating Regions ....... .............. 97
43 Device.. ....... ........... ........... ............. ... 97
44 Single/Multiple Device(s).......... ................... ... 99
45 No title ....... ......... ........................... .. 102
46 No title ....... ......... ........................... .. 107
47 Ambient Air Impact on Package Nodes .. ...................... 109
48 Rdiation Sink Temperature on Package Nodes ........... 110
49 Board Temperature Impact on Package Nodes .... ........... .. 110
* 50 External Model Correlation with Board Measurement Test
(o Measurement Point) .......... .................... ... 112
51 Junction Minus Lid Temperature Versus Power .... .......... .. 113
52 Junction Minus Center Lead Temperature Versus Power -
Measured and Predicted 40 Pin Side Brazed package .... ...... 113
53 Predicted Junction and Lid Comparison to Measured Junction
and Predicted Lid Temperature 40 Pin Size Brazed Package . 115
"54 Junction and Center Lead Pre4icted Temperature Comparison to
Measured Junction and Predicted Center Lead Temperature -
40 Pin Side Brazed Package 40 Pin Side . ..... .... 115
55 Junction Versus Lid Temperature - Predicted 40 Pin Side Brazed
- 56 Package ........ ........... ........................... 118
356 Lid Versus Base Temperature - Predicted 40 Pin Side Brazed
Pa..kage ........ ............. ........... ........... ... 119
[Link] Versus Lid Temperature - Predicted Ceramic Chip
Carrier Package ........ ... ....................... .. 120
58 Lid Versus Base Temperature - Predicted Ceramic Chip Carrier
"Package ........ ............. ........... ........... ... 120
59 Junction Versus Lid Temperature - Predicted Cerdip Package . 121
60 Lid Versus Base Temperature - Predicted Cerdip package . . . 121
61 Junction Versus Lid Temperature - Predicted Flatpack Package. . 122
62 Lid Versus Base Temperature - Predicted Flatpack Package . . 123
63 Junction Versus Lid Temperature - Predicted Hybrid Package . . 123
64 Junction Versus Lid Temperature - Predicted Hybrid Package . . 124
65 Junction Versus Lid Temperature - Predicted Hybrid Package . . 124
66 Junction Versus Lid Temperature - Predicted Hybrid Package . . 125
67 Lid Versus Base Temperature - Predicted Hybrid Package . . . 125
* 68 Lid Versus Base Temperature - Predicted Hybrid Package . * * 126

69 Lid Versus Base Temperature - Predicted Hybrid Package . .126

"70 Lid Versus Base Temperature - Predicted 9lybrid Package . . . 127
71 Junction Versus Ceramic Ring Temperature - Predicted Axial
Stu Package ........................ 128
..Studac........................

•V Vii

,m .. .- - - * * . . ' i*

:6* :.: !* . ~ * 9~ . .
SSW ILLUSTRATIONS

72 Ceramic Ring Versus Base Temperature - Predicted Axial Stud

Package ....... ...................... 128
73 Temperature Impact on Failure Rate ....... .............. .130
* 74 Quality Level Impact on Failure Rate ....... ............. .133
"" 75 Quality Level Impact on Cost ......... ................. .134
76 Silicon Thermal Conductivity Versus Temperature ........... .135
77 Martin Marietta Survey ............. .................... 166
77a Martin Marietta Survey Results ......... ................ ..167
78 Internal Model Predicted Thermal Resistance Spreading Angle
Versus Thermal Resistance 40 Pin Side Brazed Dip Package. . .196
79 Power Dissipation Circuit .............. ................. 252
"80 Transistor Calibration Curve (Typical) . .•..................253
SW 81 System Block Diagram ........... ...................... 254
82 Transistor Calibration Test 2/1/84 ...... ............... .255
83 Transistor Calibration Test .......... .................. 256
84 PWB Configuration ............ ....................... ..257

0?

viii
 "TABLES

1 Derating for Hybrid Devices .. .. ....... . . . . ... .. . 5

2 Derating Criteria for Complex Integrated Circuits (LSI, VHSIC,
LSI, Microprocessors) ...................
3 Derating Criteria for Memory Devices (RAM and ROM) ........ 7
4 Derating Criteria for Memory Devices (Bubble) ...... ........ 7
5 GaAs FET Devices Derating ........ .................. . . .. 8
6 Transistor/IMPATT/Gunn Derating ............ ............... 9
7 Varactor/step Recovery/Pin/Tunnel Derating .... .......... .. 10
8 Silicon Detectors/Mixers (Schottky) Derating ....... ........ 10
9 Germanium Detectors/Mixers Derating .......... ............. 10
10 Saw Device berating .......... ..................... .... 12
11 Design Variables ............. ..... ...................... 45
12 Coupling Coefficients of Coamonly Used Substrate Materials
for Saw Devices . ..................-.... 46
12b Failure Modes of Microelectronic Devices . . . . . ... .. 55
13 Common Diode Failures vith Design Features to Elimindte
Features ........... ..... ......................... .... 57
14 Square Device Sample Calculation ......... ... .............. 61
15 Surface Device-50% Dissipation ............... 62
16 Square Surface Attachment ........ .................. .... 63
17 Square Surface - Intermediate Material .... ........... .... 64
18 40-Pin Ceramic Side Brazed Package ..... ............. .... 65
19 Rectangular Surface Device - 502 Dissipation ..... ......... 66
20 Rectangular Surface Attachment - Ablebond 36-2 Epoxy . . ... 72
21 Rectangular Surface Header - Gold Plate .... .............. 77
22 Rectangular - 40 Pin Ceramic Side Brazed Package .. ....... ... 83
23 Rectangular Device Sample Calculation ..... ............. ... 88
24 Circular Sample ........................ 90
25 Circular Surface Device ............ ................... ... 91
26 Circular Surface Metallization - Platinum .... ........... ... 92
27 Circular Surface Metallization - Titanium . .......... 93
U 28
29
Circular Surface - Gold Plate ........
Circular Surface Heat Sink - Copper ..........
.................
...............
... 94
95
30 Thermal Conductivity of Typical Materials .... ........... .. 104
" 31 Convection Heat Transfer Coefficient.... .
.... ........... 105
. 32 View Factors for Various Configurations. .... ............ .. 106
33 Emissivity of Typical Surfaces ......... ................ ... 06
34 External Model Inputs ............ ..................... .109
35 Ceramic Chip Carrier Test Report and 48-Pad Test Data Summary . 116
36 Ceramic Chip Carrier Test Data Versus Model .... .......... .. 117
37 Infrared Temperature Probes Specifications Available ....... .. 129
38 Failure Rates Used to Derive Multipliers .... ........... .. 131
39 A, Quality Factors .............. .................... .. 133
40 Historicat Versus Actual Results of Data Surveys# ... ....... .. 151
41 Key Words ............ ... ........................... .. 152
42 Test Measurement Response ........ ................... .. 154
43 Industry berating Guidelines ......... ................. .. 156

Ix
 TABLES

44 Survey Guideline Summary ............... . . . .159

45 Survey GuicIeline Summary .......... .................... .160
46 Survey Guideline Summary .......... .................... .161
47 Derating Guidelines Comparison Survey Versus RADC-TR-82-177
"Diodes 162
48 Derating Guidelines Comparison Survey Versus RADC-TR-82-177
Microcircuits ........................................ .163
49 Derating Guidelines Comparison Survey Versus RADC-TR-82-177
Transistors ................. ........................ .164
50 Data Grouping ................. ........................ .168
51 Case Outline Letter Designations .......... ................ 169
52 Internal Model Prediction Versus Circuit Board Measurement
•.- Data . . . . . . .... . . . . . . ...............
Daa.......................... . . . . . . . . . ... 196
19

j: I

N.

S2

gK
 1.0 EXECUTIVE SUMMARY
The objective of the Reliability Derating Procedures program was to
develop the framework leading to the creation of a military standard for
S the derating of electronic and electromechanical devices for Air Force
application. Pripaqry areas of investigation were: I) relationship of case
temperatures to junction temperatures, 2) methods of verifying that derat-
"ing has been accomplished, 3) relationship of reliability to cost, 4) de-
rating standards for complex devices, 5) creation and verification of ther-
mal models, and 6) temperature derating verification techniques through
data collection and testing. -

The specific devices identified for investigation under this program

were hybrids, complex integrated iircuits, memory devices, microwave devices,
and surface acoustic wave (SAW) devices. The overall approach divided the
program into five specific tasks: 1) a literature search and survey data,
*, 2) parts derating standards and application guidelines, 3) case temperature
derating and measurement, 4) reliability versus cost, and 5) development of
a military standard frame iork.

The literature search and survey data task, while being highly suc-
cessful in obtaining industry response, did not produce a meaningful quan-
tity of data. Task 1 results did highlight industry's need and desire for
,- consistent and standard guidance for new or advanced technology derating
and junction temperatures.

The parts derating standards and application guidelines task was plan-
ned to use survey guidance from task 1. As task I progressed, it was evi-
"dent that an alternative approach was needed, due to the lack of firm data.
*'" The approach established was to investigate MIL-HDBK-217D data and algor-
ithms to determine what factors might be considered for derating, task 2.

Each MIL-HDBK-217D factor, such as environment, package size, complex-

ity, temperature, voltage, etc., was investigated in detail to determine
its impact on the subject device. The output of the investigation resulted
in specific derating criteria for each of the devices. The deratlng cri-
ttria specified the parameters to be derated and the amount of derating in
relation to the three-level derating philosophy. The balance of the task
was identification and guidance in relation to the failure modes and mech-
anisms. The approach for this latet portion was to first identify the
failure mode origins, then group the modes, and finally to identify the
point of elimination or control of specific failure modes.

The case temperature derating and measurement task 3 was to develop

and verify models for junction temperature derating to case temperature de-
- rating. This task was also to provide a cost-effective technique for act-
ual measurement of selected integrated circuit and semiconductor case temp-
eratures related to the junction temperatures. The task was accooplished
"with the creation of two specific tyk'es of models. The first model was an
internal one predominately used for new devices to approximate th0. thermal
impedance from the chip Junction to the case bottom (Ojc). The second
model was an external one .ot specific package types (axial studs, ceramic
chip carriers, cerdip., flatpack, hybrid, and side-brazed). Each of the

i "
.4.

............................................................................
J .', specific package types identified a temperature measurement point on the
specific package. In conjunction with curves derived from model runs, the
actual junction temperature of the chip were estimated. Two of the six
package models have been verified for accuracy, through actual test meas-
, urement data (with side-brazed and ceramic chip carriers). These models
were determined to be within 4 degrees centigrade (C) of the measured
value.

Each package model required measurement of the board temperature and

junction temperature in order to determine the temperature value at the
X.• specified device measurement point. Two additional variables, ambient air
and radiation sink temperatures, were considered by providing tolerance
*- bands on each curve. The final portion of the task identified measurement
equipment available, with it's respective advantages, disadvantages, and
accuracies to determine which characteristics could be used to make the
temperature measurements in a system. It needs to be highlighted, to pre-
vent misapplication of the models, that the external models presented are
not universally applicable to all package sizes, mountings, chip sizes,
etc.

The reliability versus cost task (4) addressed the components which
drive the cost of reliability. The primary drivers addressed are the con-
tract requirements, funding level, temperature requirements, quality level,
and device cost.

The final task (5) was to develop a military standard framework which
would be used for the creation of the standard for the derating of elec-
tronics and electromechanical devices for Air Force application.

"NV.
 2.0 DEVICE DERATING GUIDELINES

2.1 Derating Definitions

2.1.1 Derating Levels

The range of derating is

generally defined as a point between the min-
"imum derating point and the point of over-derating.
The optimum derating,
therefore, should occur at or below the point of stress (i.e., voltage,
temperature) where a rapid increase in failure rate occurs for a small
increase in stress. Three derating levels are selected on the basis of the
criticality of the application.

Derating Level I (Maximum Derating)

This level pertains to equipment failure that would substantially

jeopardize the life of personnel, or seriously jeopardize the operational
mission. Repairs are considered unfeasible or economically unjustified at
this level.

Level I derativ, is also considered to be those stress levels below

which further relia L derating gain is negligible, or where further
"derating will create difficult design problems. This derating is intended
for the most critical applications, or where the associated design diffi-
culty can be justified by the reliability requirement.

Derating Level II

• .•This derating level refers to failure that would degrade the

operational mission or would result in unjustifiable repair costs. Level
". II derating is considered to be still in the range where reliability gains
are rapid as stress is decreased. However, achieving designs with these
-
!i• reductions
III. in allowed stress is significantly more difficult than at Level

Derating Level III

"This derating level pertains to equipment that is considered less

"critical than lovel I or II equipment. Level III failure does not
jeopardize the operational mission, or can be quickly and economically
repaired.
-. 4,• Level III derating is also that stress level reduction
which creates
"minor design difficulties, while generating the largest environmental
reliability gain. This gain is realized because the effect of stress
_'0 increases dramatically as the absolute maximum rating is approached.

"2.1.2 Part Quality Levels

Derating cannot be used to compensate for using parts of a lover
quality than necessary to meet usage reliability requirements. The quality
* level of a part has a direct effect on the predicted failure rate.

' ' " 3

•,"w S e . , I%.*. .
 Electrical testing of all parts in a lot is not guaranteed for commercial
or JAN level military parts. For high reliability applications, only fully
tested and screened parts (including bura-in) should be used, in addition
to applying the appropriate derating levels. Section 6.0, Table 39, shows
the part quality levels and the screening requirements as specified in
MIL-HDBK-217D.

2.1.3 Environments

Equipment environments are commonly associated with derating critical-

ity levels. The various operational environments, as defined in MIL-HDBK-
"217D, can be assigned to these levels, as shown below.

"Environment Level

Ground III
Flight II
Space I

These environmental conditions are broad categories to give some guid-

ance in selecting the proper part derating requirements. Tn the ground
environment, equipment required to be mobile or mission criticul in most
cases should be rated in accordance with level II. Flight or airbolne
equipment that may be crew-hazardous should be derated to level I.

The equipment environments versus derating levels in the table are

guidelines only; operational environment, program goals, operational objec-
tives, and life cycle cost may modify or dictate the derating level selec-
-.\ tion.
.'•

2.2 Hybrid Devices

Hybrid devices are composed of elements such as integrated circuits,

transistors, capacitors, and/or resistor chips mounted on a common sub-
strate. This technology combines elements into a high density package to
,4 decrease volume and sometimes power. The hybrid may use thick film or thin
films as interconnections and resistive elements. The primary failure
"modes are failures of active components, integrated circuits or transistor
chips, and interconnection faults.

Application

In hybrids, a deviation frrm the nominal supply voltage will shift

internal bias points. This deviation, coupled with thermal effects, can
result in the device performing erratically. Some hybrid circuits are also
-* susceptible to electrostatic discharge. Since hybrids are affected by
these parameters, design precautions to control supply voltage and
electrostatic discharge handling precautions, such as grounding, should be
taken. However, the primary driver for derating is the junction
temperature.
A..

4
 Derating

These derating criteria for hybrids are summarized in Table 1. Individ-

uil elements or devices contained in the hybrid package should be derated
individually, in accordance with the guidelines of AFSC Pamphlet 800-27.

TABLE 1. DERATING FOR HYBRID DEVICES

Level Level Level
SI If III

Maximum Junction 85 100 110

Temperature (*C)

Thick Film Power <50 <50 <50

Density watts/in2 watts/in2 watts/in
Thin Film Power <40 <40 <40
Density watts/in2 watts/in2 watts/in2

"Note: For every degree C above 100C cast temperature,

derate the power density I watt per square inch
"I below the values shown.

2.3 Complex Integrated Circuits

Tne complex integrated circuits defined for derating guidelines in-

clude four specific groups: 1) iarpe-scale integration (LSI) and custom
LSI, 2) very high speed integrated circuite (VHSTC), 3) very large scale
integrated circuits (VLSI), and 4) microprocessors.
Among the different technologies used fot fibticating the complex
arrays are: I) bipolar, 2) p-channel metal Aide semiconductor (MOS), and
3) complementary metal oxide semiconductor (C4AS). The bipolar and p-chan-
nel MOS techniques require load r-sistors and b,. the nature of their design
have higher static Power diessipation than M•iOS. The CMOS te,.hnology uses
both p- and n-type transistors in series. The signal ttax turns the n-type
transistor on, turns the p-type transi3tot off, and vice versa. There is
never a path to ground for the current, ex._,)t through an external load.
This lack of a path results ir.a saving of operation power, and in turn
reduces overall device tempecature. Howeve , as CMOS is operated at higher
frequencies, power dissipation increasqs significantly resulting in the
same effect as p-channel and bipolar.

eion
Appli s

9 1MOS/CMOS devices tend to be highly sensitive to damage due to electro-

static discharge. This discharge is due to 3xcessive noite on signal
lines. The pcr&ozmance or bipolar devices is affected by supply voltage
deviations from the specified nominal, due to shifting bias points when
coupled with thermal effects. Increased .,ipolar action in COS devices in
particular can lead to latch-top. Design precautions need to be taken to
ensure maximum operability of these complex devices by minimizing or
. eliminating noise on signal lines and control of supply voltage deviations.

!5

". .• ," "' '. 'r ".. " " " . . " " . "h " , ". " ". ' ", " . ; ." . . ... ."I • " " " . " '- '
'S

- *1Derating

N
These derating criteria for complex integrated circuits, LSI, VHSIC,
VLSI, and microprocessors, are summarized in Table 2.

TABLE 2. DERATING CRITERIA FOR COMPLEX INTEGRATED

CIRCUITS (LSI, VHSIC, LSI, MICROPROCESSORS)
Level Level Level
I It [III

Maximum Junction 85 100 125

Temperature (*C)

Supply Voltage 0.75* 0.80 0.85

(of Rated Value)

Output Current 0.70 0.75 0.80

(of Rated Value)

Fan Out (Digital)

(of Maximum
Specified)
"Bipolar 0.70 0.75 0.80
MOS 0.80 0.80 0.90

Operating Frequency
(Digital)
(of Maximum
Specified)
Bipolar 0.75 0.80 0.90
MOS 0.80 0.80 0.80
* *Note: Designing below 75 percent of the supply voltage may
run the device below the recommended operating
voltage.

2.4 Memory Devices

The memory devices defined for derating guidelines include three spec-
* ific technologies. They are 1) bipolar, 2) MOS, and 3) bubble. In the
bipolar and MOS technology, the memory group can be broken up into random
* access memories (RAM) and read only memories (ROM).

The RAMs, in turn, can be categorized as static and dynamic. These

two RAMs differ in how they store data. Static RAMs are easier to use,
while dynamic RAMs are cheaper and use less power. However, dynamic RAMs
"must be refreshed and recycled.

Although the bubble device and material technology is significantly

different from silicon devices, this technology is also based on a batch
manufacturing process. As a device, bubble memory is very well suited to
serial data storage. It is slower than silicon devices, but it is non-
"volatile, and will allow data to be stored and retrieved efficiently.
Bubble memories are light, compact, and low-power devices.

., S* . . * ~*v* %.
-. . .
 Application

The performance of MOS devices is a function of the operating volt-

ages, and their ability to handle high operating voltage decreases very
rapidly with reduced device sizes. Bipolar memory circitits do not suffer
from this limitation. However, they are restricted, based on current drain
and power dissipation limits. Bubble memory operation is dependent upon
the ability of the external support microelectronic devices to function
properly within their specified limits. Design precautions should be taken
to ensure that the proper tolerances are set for the particular device
application in accordance with the device specifications.

Derating

These derating criteria for memory devices (RAM and ROM) are specified
in Table 3. Table 4 represents the derating criteria selected for bubble
memories. Bubble memory derating will also involve the use of the guide-
lines specified within for the individual microelectronic devices. These
devices make up the external support required for bubble memory operation.

TABLE 3. DERATING CRITERIA FOR MEMORY DEVICES

(RAM AND ROM)
Level Level Level
,1 11 IIl

Maximum Junction 85 100 125

Temperature (*C)

Supply Voltage 0.75 0.80 0.85

"(of Rated Value)
Output Current 0.70 0.75 0.80
(of Rated Value)

TABLE 4. DERATING CRITERIA FOR MEMORY DEVICES (BUBBLES)

.'

[Link] Level Loeve l

III Ilt

Maximum Ambient 85 85 85
Operat ing
Temperature ('C)

2.5 Microwave Devices

The microwave devices addressed in this section are 1) GaAs FET, 2)

detectors and mixers, 3) varactor diodes, 4) step recovery diodes, 5YPIN
diodes, 6) tunnel diodes, 7) IMPATT diodes, 8) Gunn diodes, and 9) transis-
tors.

The microwave devices are categorized, based on the amount of elec-

ig trical stress characteristic to a normal operating environment. There are
low and high electrical stressed devices, which are separated into four
groups for derating purposes. These groups are:
 High electrical stressed devices:

Group I - GaAs FET

Group II - Transistors/IMPATT/Gunn Diodes

Low electrical stressed devices:

Group III - Varactor/Step Recovery/PIN/Tunnel

Group IV - Detectors/Mixers

- Silicon
- Germanium

The derating parameters selected for these devices are junction tempera-
ture, voltage, and power. The selection was based on the predominant fail-
ure modes occurring in application. These modes are metal migration caused
by voltage and power stresses, junction shorts, and hermeticity problems,
all of which are predominately temperature-related failures.

2.5.1 GaAs FET Devices

Application

The field-effect transistor is a voltage-controlled device which has a

high input impedance and can perform the switching or amplification func-
tion. GaAs FETs are often used in amplifiers, but are also used in micro-
wave oscillators and mixers. GaAs FETs are subject to damage caused by
switching transients and static discharge.

Derating

These derating criteria for GaAs FETs are listed in Table 5.

TABLE 5. GaAs FET DEVICE DERATING

Level Level Level

Ix II nIx
Junction Temperature 95 105 125
"C)
Power Dissipation 50 60 70
(percent)
Breakdown voltage 60 70 70
* ~(percent)j
 2.5.2 Transistors/IMPATT and Gunn Diodes

Applicatidn

Microwave transistors, IMPATT Diodes, and Gunn diodes are all classi-
%: fied as high electrically stressed devices. In fact, IMPATT diodes are
characterized by their ability to dissipate maximum power per unit volume,
while Gunn diodes and microwave transistors operate most efficiently at
power levels just below the maximum specified. Th.& ,oltage applied to
these devices is a major concern for correct operation. Design precautions
need to be exercised to ensure that recommended specificaiton voltage
levels are not surpassed.

Derating

These derating criteria for microwave transistors, IMPATT diodes, and

Gunn diodes are in Table 6.
TABLE 6. TRANSISTOR/II4PATT/GUNN DERATING

Level Level Level

SI II III

Junction Temperature 95 105 125

=" •,"('c)

Power Dissipated 50 60 70
(percent)

Breakdown voltage 60 70 70
(percent)

2.5.3 Varactor/Step Recovery/PIN/Tunnel Diodes

Application

Varactor, step recovery, PIN, and tunnel diodes are described as being
low electrically stressed devices. They are low power handling devices and
should not be subjected to unusually large power stresses. High junction
temperature is a very destructive stress which should be limited.

Derat ing

These derating criteria for varactor, step recover, PIN, and tunnel
diodes are suarized in Table 7.

2.5.4 Silicon and Germanium Detectors and Mixers (Schottky)

Application

These minimally stressed devices typically operate at low power levels

and low noise figures. They are particularly sensitive to circuit tran-
sients and electrostatic discharges, which result in diode burnout. Pre-
cautions should be taken to safeguard against this.

''•" 9
 TABLE 7. VARACTOR/ STEP RECOVERY/PIN/
TUNNEL DERATING

Level Level Level

,,I -- II III

Junction Temperature 95 105 125

(c)
Power Dissipation 50 60 70
(percent)

Breakdown voltage 70 70 70
I (percent) _

Silicon detectors and mixers aro widely used and are highly accepted.

However, germanium devices are not recommended for use.

Derating

These derating criteria for silicon detectors and mixers (Schottky)

*are summarized in Table 8. Derating for germanium detectors and mixers has
been developed in spite of the negative recommendation. This group's
derating appears in Table 9.

'- TABLE 8. SILICON DETECTORS/MIXERS

(SCHOTTKY) DERATING

Leve I Level Level

r It III

Junction Temperature 95 105 125

(00)
Power Dissipated so 60 70
(percent)

Breakdown vol Lago 70 70 70

(percent)

TABLE 9. GERMANIUM DETECTORSI/MIXERS DERATING

Leve I Level Level

* Junction Temperature 75 90 105

(c0
V Power Dissipated 50 60 70
*I•
j (percent)

Breakdown voltage 70 10 70
(percent)

%+ + ., . • _ , - + , • + , , = , , _ , . • + ,+ - . ..

+ +" _ ~~~~~~~~~~~~~~~.
,. .........
.......... •+ . 4.. m-..w . -. •- ,•l ++ +1i• l
 2.6 Surface Acoustic Wave (SAW) Devices

Surface acoustic wave (SAW) devices are currently being used os de•ay
lines,. oscillators, resonators, and filters. They are tailored to ýhe
[Link] frequency and response desired for each application, with a
frequency range from 50 megahertz to about 2 gigahertz. Interest ..
n SAW
* devices has evolved primarily because of two characteristics inherent to
the waves themselves. The first characteristic is the short wavelength and
related slow propagation velocity of the acoustic wave, as compared to the
electroaqagnetic wave. This characteristic allows signal delay and iilter-
* ing.

The second characteristic is the propagation of the acoustic waves

along the surface of the solid. This characteristic enables the energy
at a depth of one wavelength or less to be sensed and manipulated by the
SAW elements. A SAW device usually consists of the SAW element on its
"piezoelectric substrate plus any auxiliary elements, such as an amplifier
or matching elements, and the packaging of the complete device. The most
commonly used substrate material is quartz due to its demonstrated tempera-
ture stability over a wide range. The input and output electronic inter-
"face is achieved through interdigital transducers. Those transducers
create a strain on the substrate surface, with applied voltage causing the
generation of a physical wave.

Application

SAW devices are passive. They operate at a low power level and are
low heat generators. Since heat generation is minimal, the environment
determines the SAW operating temperature. The devices surrounding the SAW
device become a major concern when environmental temperatures rise. Pre-
cautions should be taken to ensure that the surrounding devices do not
create an unstable operating environment. The frequency stability demon-
N strated by the SAW device is a design requirement which can cause part deg-
radation if it is not controlled. These devices have also exhibited sensi-
tivity to electrostatic discharge. Design attention is required to mini-
mize this stress.

Derat'in&

- The derating level breakdown (U, II, and III) will not be applicable
to SAW devices, due to their passive operative nature. In most cases,
derating is inappropriate for SAW devices. However, input power and
operating temperature are two parameters that require limiting. These
derating criteria for SAW devices are summarized in Table 10.

•.

I?1-
*."I
 TABLE 10. SAW DEVICE DERATING
Center Frequency (MHz)

> 500 < 500

Input Power (dB) 13 18

Temperature (*C) 125 125

(Operating Maximum)

V.

'S.:.

" " • . * . *. *. *
." ,
S--,,•
..
,.
. .
-"•
.
.
. . .
, .Ž
.
. *
. .
.-. .
. .
,
.
-..*.* .
.
S -
.
°
.
•4 '
..
o
.
' o.
9.S..
.,
.
.,'
.
.
.
o
..
o , ••
 3.0 BASIS FOR DEVICE DERATING

3.1 Rationale of Device Derating

This section provides support and rationale for the derating criteria
specified for the particular device types under investigation. A litera-
ture search, along with a survey of the industry via letters and telephone
contacts (see Appendix 3), was implemented as a means of obtaining derating
criteria for the specified devices.

The derating information received did not address the more complex
device types. Therefore, MIL-HDBK-217D was used as the primary basis for
derating for the hybrid devices, complex integrated circuits, memory devices,
and the microwave devices. A survey was conducted within Martin Marietta
to supplement the MIL-HDBK-217D approach. The information received tended
to support the guidelines established using MIL-HDBK-217D. Due to the lack
of information published on SAW devices, the derating criteria was based on
discussions held with those device manufacturers knowledgeable with the
% basic device design and applications. Each of these device types will be
discussed in their respective sections, with derating rationale and sup-
porting charts provided.

Using MIL-HDBK-217D, there are many factors which have to be consid-

ered due to their impact on the failure rate of each device type. The
failure rate drivers and factors investigated were quality level, environ-
ment, failure rate, interconnections, package size, density, complexity,
temperature, voltage, frequency, power, and application.

The failure rate of each device involves the combidation of different

factors. The effect of the factors that are common to all the devices will
be discussed in this section, while the remaining factors will be discussed
as they apply.

The quality factor used in the computation of the failure rate is the
same for all the microelectronic and microwave devices. The exception is
SAW devices, since they are not discussed in MIL-HDBK-217D.

Figure 1 shows a plot of the component quality level impact on failure

rate. The plot shows that the quality level impactineassgifctl
at the levels going from B-2 to B-1 (vendor equivalent to 883 Class B).
The quality level is a direct multiplier in the failure rate calculation,
but is solely dependent on testing and inspection criteria.

The component environmental application factors of MIL-HDBK-217D have

a direct bearing on the individual failure rates. The following discussion
*• will assess the impact of the environment as related to the component level
failure rate. Figure 2 shows a plot of all the application environmental
factors for microelectronic devices as presented in MIL-HDBK-217D, Table
[Link]-3. This table shows that the Cannon Launch (CL) environment over-
shadows all the other environmental factors. For that reason, the CL en-
vironment was removed and the plot was regenerated in Figure 3. This fig-
ure shows that the level III ground environments are all in the lower third
of the curve.

13

t++'l*4+
. . %,. ... . . . . 1 , + + .. . . I + . + i . . . . . .+ A .. . .. . . .. . . . .. ' ..
 40

LLJ
. 30
0.

LJ 20
144
10-

S0
- 0.

D C1 C B2 B1 BO B S
QUAUTY LEVEL
Figure 1. Quality Level Impact on Failure Rate

250"

200.

"0

?• z> so-
LUJ

QEVOiONMENt
Figure 2. Environmental Impact on Failure Rate

i4

4.' ' ,.o.:-. 2• • ':-''! ;" "' ." -. ". "% "••• • . ..-.-. , ..-... ,.: -. ... . .-. •
 4 A4

15

S10

-J
-

Z5

4z

ENVIRONMENT

Figure 3. Environmental Impact on Failure Rate

The next step was to select a typical LSI integrated circuit and per-
form a MIL-HDBK-217D prediction on the typical integrated circuit across
"
the temperature range of 0 to 200C for each environmental application
factor. The circuit selected was a KIL-#-38510 quality level B component,
part numbtr M38510/47001 (Generic 1802). The results of the iterative pre-
diction were plotted in two ways. The first was to establish a failure
rate factor (multiplier) based on the particular environment using 0OC as
its base, and the second was to plot the actual failure rates predicted.
The two sets of curves are shown in Figures 4 and 5, respectively. The
factor plot (Figure 4) shows the driver of failure rate to he the tempera-
ture. For all the environments, the failure rate begins to show signifi-
cant increase as the component temperatures increase above 100"C. The lar-
gest failure rate multiplying factor across the temperature range vas found
to be in the ground benign environment. This factor is calculated to be
30891. In order to investigate and highlight the slopes of the lines, the
temperature range was reduced to 25 to 175C. The regenerated plot is
• shown in Figure 6. Th* reduced temperature range did not reveal any addi-
"A tional information.
The failure rate plot in Figure 5 confirmed that the ambient tempera-
ture is the controllin.A factor for failure rate. All the environments
". except for the CL override one another. The CL environment appears to
approach the rest of the environments at approximately 200C. The temper-
ature range was again reduced and the curves regenerated (Figure 7). The
expanded curves do not add any additional information.

15

A P .** .. .. .
 40000o- Legend
40000•A o0

x SF

30000 AIT

--,-<..i;"........
-I
x AMT
+•;" /~~z o -IIF "-
20000- GM
w 6 MFA
3 0OAIF_
oooo
St /AU
/ 0 ARW

O•~~~
,. ~ ~ ,...+ml
1 00,,•, w... ..............
0L.,
2 0 25 50 75 100 125 150 175 200
AMBIENT TEMPERATURE - degrees C
Figure 4. Envircnmental Impact on Failure Rate

Legend

--501 AIT
N x srT
.100- 0
;,-..........
IF

+ AUF

""A 0 ARW

0 8 ML
V CL
0 25 50 75 100 125 150 175 200
AMBIENT TEMPERATURE - degrees C
Figure 5. Environmental 'Empacc or. F'ailure Ra *

.-. ~.16

--+ 4x%
•,.A . A A , ¼ * . .L"
 • Legend
LAgn
S15000-
A0
x Sr
SOF"

8 AflT
U 10000 a MFr ...
ifL6
x WA

IxO0AIF__
. 50000 I -
R + AUr
-- - / *
*ARW
,,. ,
a .M ".......
:•'~ • .VCL ~
r . . . ...... SO

25 50 75 100 125 150 175

AMBIENT TEMPERATURE - degrees C
"Figure 6. Environmental Impact on Failure Rate

40 Legend
x SF

30. 8 Alt

A' 4A
- MF. ... .
La-
+ AAPT
10 -

:R 50 75 10 25 10 7
,,L

0 - . . . . . . . . . . .

25 50 75 100 125 150 175

AMBIENT TEMPERATURE - degrees C
Figure 7. Environmental Impact on Failure Rate

17

-~j.4
 The result of the investigation of the environmental factors specified
in MIL-HDBK-217D indicates that they do not change the slope of the failure
rate and are not failure rate drivers. The environmental factors are only
multipliers to adjust the magnitude of the failure rate and should not be
the primary drivers for derating. This rationale can be applied to the
environmental factors for the microwave devices. If the curves were re-
plotted for the microwave devices, the new curves would look identical,
with the exception of an upward shift due to factor variations.

3.2 Basis for Hybrid Derating

Establishment of hybrid device derating criteria is not a commonly

addressed area. This is pointed out in the survey derating summary in
appendix 3. Only 4 responses out of 32 addressed hybrids for derating.
Those 4 responses were concerned with junction temperature. The junction
temperature deratings specifically mentioned were 110°C and 105*C. Another
approach reported was to use 75 percent of the specified temperature rat-
ing. The lack of response from the survey led to the derivation of derat-
ing based on the data of MIL-HDBK-217D and knowledge of failure rate driv-
ers from Task 3 (Section 4) thermal models.

"In order to arrive at a reasonable derating criteria, each major driv-

"er in the hybrid failure rate must be investigated. The junction tempera-
ture of the integrated circuit elements can be investigated through the use
of the failure rate temperature acceleration factors for monolithic micro-
electronics. Figure 8 shows the junction temperature impact on the temper-
ature acceleration factor for each technology addressed in 141L-HDBK217D.
The figure shows that there is no significant acceleration factor where
junction temperature is limited between 80*C to 90*C (less than 10) for all
technologies. When the junction temperature rises to approximately 100OC.
the factort for 240S and linear acceleration rises to approximately 16. At
a junction temperature of approximately 110%" for COS and linear acceler-
ation, the temperature acceleration factor begins to increase rapidly to
approximately a value of 27. Thie analysis would tend to indicate signif-
icant breakpoints for hybrid derating criteria.

A second driver to hybrid device failure rate is the quantity and type
of interconnections. Figure 9 shows bimetal and single metal bond inter-
connections. The figure shows the factor based on a single interconnect.
When the prediction is accomplished in accordance with MIL-IIDBK-217D, the
interconnection failure rate contribution facto" (Xi) is multiplied by the
total number of interconnections. Applying the junction temperatures in
Figure 8 to the package temperature of Figure 9 minimizes the impact of
interconnections. Based on the most severe curve in Figure 9, bimetal
bonds, the 85% temperature factor is approximately 14. The factor at
100% is approxrately 30 and at 110% the factor rises rapidly to approxi.-
mately 44. Tht curves of Figure 9 tend to support the breakpoints selected
from the previous curves in Figure 8. (Figure 10 intentionally deleted).
The third driver peculiar to hybrids is the package size impact on
temperature. Figure 11 shows the impact of the seal perimeter (directly
related to package size) on failure rate as the package temperature in-
creases. An analysis showed that an increase in seal perimeter does not
change the shape of the curve, that is, the package failure rate factor is
18

'AV 10-%6 7 t%

~*~*- ~ . .~. *~ME.

 00
500

~400O
z
S~300"
0/

:•. :200.
• o Legend
~A ,M
, M,-• .
X L-m-smo

0 100 5li 200

",, JUJNCTON TEMPERATURE - dg e C

Figure 8. Microelectronics: Junction Temperature versus Failure Rate

200-
-,J 0

-'.50
- - + 'A
70I0'10+ fTRd
- X uwmh
0 5o 100 150
PACKAGE TEMPERATURE - degree C
Figure 9. Hybrid: Package Tenperature versus Interconnections 7

"* 19

m.4
i•+ .•i i1 . 11
ll+i •ii + + ii . i+i 41•
•I:+ + + • - - lr 4p+"Pll II I1•.I• I + +++I iiI l ii ii II @i.I~ T
 the same at a specific temperature regardless of the perimeter value.
Therefore, the figure is calculated on a seal perimeter of two inches. As
with the previous figure, the base temperature of 25@C is used and again
the factors (multipliers) are compared to the same breakpoints of 85, 100,
and 110*C. The factors associated with the three breakpoints are approxi-
mately 15, 33, and 48 respectively. This analysis (figure) again supports
the derating breakpoints established from the junction temperature and
interconnect analysis.

200-

0
*• • 150

S100-
3

50 -5

0 W0 too 150
PACKAGE TMPERATURE - degres C
Figure 11. Hybrid: Package Temperature versus
Package Size (2-inch Perimeter Seal)

The final factor investigated for impact on the hybrid was the density
factor as defined in MIL-HDBK-217D. MIL-HDBK-217D defines density as a
measure of the mechanie.1l otnplexity as a whole. The density formula is:
• Desity number of interconnections
Density (As + 1.0) swhere As - area of the substrate in
•.'•square inches.

This factor is based solely on mechanical complexity and is not related

directly to the common derating of power density. Figure 12 shows the den-
sity impact on the hybrid failure rate. Inspection of the curve shows no
obvious breakpoints to drive the derating criteria. A relationship does
exist however, with earlier figures (8 and 9). Both figures are based on
"interconnections and in turn can be related to temperature. As the density
* and temperature increase, the factor or multiplier will increase dramati-
cally.

20

j. - - * r

% j . 30-:r
 4

0,,3
A

50 100 150 200 250 300

DEN - mechaniod complofy
Figure 12. Hybrid: Density Impact on Failure Rate

The thick/thin film trinmming required to obtain a particular parameter

greatly affects the power density. As the device is trimmed, the power
density increases. MIL-STD-883B restricts triufing to a maximum of 50 per-
cent of the original size, thus creating the need for power density derat-
ing. In establishing the derating requirements for power density, the in-
dividual design limits have to be taken into consideration to allow for
design changes. The power density derating chosen supports the established
one. Based on this rationale, the derating criteria specified in section
2.2 (Table 1) was selected.

9 3.3 Basis for Complex Integrated Circuit Derating

aedThe results of the survey (appendix 3) revealed no specific data re-
lated to integrated circuits. The lack of industry response to integrated
X circuitry has required investigation of derating criteria to be developed
through MIL-HDBK-217D. The majority of the documents that address inte-
4, grated circuitry technology, including MIL-HDBK-217D, consider two factors,
*, circuit complexity and circuit function. Complex integrated circuit devices
begin with the criteria of greater than 100 equivalent gate logic elements.
The different technologies, bipolar, MOS, and CMOS each define the number
of gate equivalents differently, according to MIL-HDBK-217D. Here is the
M14L-lDBK-217D definition of the gate equivalents:

I Bipolar: Gate equivalents - number of transistors

2.5

21

6$

st~mr+,-+++
- 1* i+, .l+. +++•] . p .. + .. * * * ,**'*
. . . . . . .. . . . . . . . . . .
 2 CMOS: Gate equivalents = number of transistors
3.75

3 Gate equivalents = number of transistors.

MOS:
3.0
Each element of MIL-HDBK-217D impacting the failure rate was investi-
tY,! gated to determine breakpoints. The impact of the quality and environ-
- mental factors on the failure rate have previously been discussed in sec-
tion 3.1.

The temperature acceleration factor for complex integrated circuits is

the same factor used for all the microcircuit devices. Figure I previously
[Link] in section 3.2, Basis for Hybrid Derating, shows the temperature
acceleration factor impact in relation to junction temperature for all the
technologies. Analysis of the breakpoints of the curves in Figure 1 con-
cluded that the junction temperature was to be 85, 100, and lOC for lev-
els I, II, and III, respectively. For the present time, we will assume
these points are still valid. They may be modified upon investigation of
other failure rate drivers.

The voltage derating stress factor as presented in MIL-HDBK-217D is

ii applied only to (MOS technology. It is based upon the recommended specifi-
cation supply voltage and the operating supply voltage in actual applica-
% tion. There are two CHOS ranges in which the application voltage affects
the failure rate, a value other than 1.0. These two ranges will be invest-
igated separately. In both cases the numerical value is related to junc-
tion temperature. Figure 13 shows a plot of junction temperature versus
the voltage stress multiplier. The multiplier is based on the minimum val-
ue for each voltage range. For example, the minimum value in the 12 to
15.5 volt CROS range would be 0.11. This is derived by the applicable
formula:
.v = 0.ll0ex

where

+ 273)
-.. j.,298X,- 0.68Vs(Tj

Vs - operating voltage in actual operating

Tj device junction temperature (C).

When the value of x goes to zero, the value of v 0.110.

3. Using the same approach for the 18 to 20 volt recommended specific&-

"tion supply voltage, when x goes to zero in equation wv a 0.068ex, the
minimum is wv - 0.068.

Only one obvious breakpoint is highlighted in the curves in Figure 13.

The breakpoint is associated with the 3 and 8 volt curves. The subject
breakpoints are associated with a junction temperature of approximately

22
JN P,

'4U4
 50-
I
S40.

WNW
.X Lege..

,•+• 20N - -N tAJm..

S0o . .20~~ . . . . . . . H"Ur

0, a6 W 200
NCIO TO AT - *m

• .Figure 13. Complex IC: Junction Temperature versus Voltage Stress

~125°C. SralUBEe
The voltage stress multiplier at this specific po•'.*nt is approxi-
S~mately 27. Using the 125%C and 27 multiplier would tend to fix the level
III derating and translate to an approximate percent of supply voltage de-
S~rating of 0.85 across the application voltage range.

S~The CMOS recommended specification supply voltage in the 18- to 20-volt

.• range is plotted in Figure 14. These curves show several breakpoints.
•.•,• They are at a junction temperature of 125"% with 16 and 18 volts, 1O0"C
_ . with 18 and 19 volts, and approximately 80%C with 20 volts. The voltage
•istress multipliers rnefrom approximately 17 to 25. These three junction
•r• temperature breakpoinlts would tend to suggest temperature derating of 85,
i• 100, and 125%C for Level 1, 11, and 111, respectively. The respective de-
S~rating associated with the supply voltage is approximately 80 percent.
+,• The last term investigated is the circuit complexity factor. This

,• term is solely dependent on the number of gates for the technology. MIL-
HDBK-217D differentiates complexity factors for bipolar and MOS, while
D: there is no separate complexity factor for CHOS technology. Figures 15
through 18 show the gate count impact on the failure rate Vor the bipolar
and OS devices. Each technology, bipolar tOS, and has two complexity copo
-
"ponents, C2 and C2U The results of complexity factor investigation for
both bipolar and tOS produced no outstanding results. The curves (Figure
.4%
"15-18) show that as the number of gates increase the impact on the failure
rate also increased. The general slope of each curve is similar and the
ycomparable factors (el and C2) of MOS technology are less impacted by
increasing gate count than bipolar techn,,logy. An example of this impact

'V temperature breakpoints would tend to°suggtepru drigk'2. of 85,P ",, •..'23
 so

A Lug&
X AXWL

5,•40" / 3L(..l.

I, /m+ NI-

40-4
R 0 a .y
* 20 l'm•.. - U *
20 0
0 U.m
01N- - 011ft¢
5
Figue 1.0 10ISO 200
JUNMTON MO tXE-degree
F [Link] IC. Junction Temperature versus Voltage Stress

'4 10

.. 3-

oaoa
.a nym

5W 4 I

•. 24
S~Bipolar Devices (Cl Complexity)
4* Ii2
- VGAf
:;.-::::•:;
:::: :Figur[Link].::: Gat[Link]
Co:::
t Im:a-t on: of::.......-.
Failure.:
Rate• . •..,.
, ,~~~Bplr
eie ,Cl xity),,...,....,.
C:.omple-. ...
 !3
3.5-

1E

ts

S0 2002 4000 M000 8000

SNUMBER OF GE
Figure 16. Gate Count Impact on Failure Rate of

A Bipolar Devices (C2 Complexity)

0-

*V

?0

1 Figure 17. Gate Count Impact on Failure Rate of

Devices SHMOS
(Cl Complexity) 6000600
..•:,,:••-.q .• ,25
,..--- ., .%,.::• ---.-. ,,-, . ,- ,: .,O F. A,'-
.. .,, . . .., .. .. . , ,,. . . ... .- . . -.. . _
 i5

L2.5

0 00 4OOO0 000 a
NUMBE OF GTES
V. Figure 18. Gate Count Impact on Failure Rate of
MOS Devices (C2 Complexity)
is the Cl factor of bipolar for 7500 gates (Figure 15) is greater than the
Cl factor of MOS (Figure 17) for the same number of gates (9.0 versus 5.6).
The same impact can be observed in Figures 16 and 18 for the C2 factors.
observed in Figures 16 and 18 for the C2 factors.

These derating criteria for complex integrated circuits, LSI, VHSIC,

VLSI, and microprocessors, are summarized in Table 1, section 2.3. The
selection of the specific derating levels was based on the information and
N• analysis conducted within Martin Marietta and the survey response from
Ný industry. The analysis presented herein tends to support the industry
response; that is, it generally correlates with the most often selected
parameter.

3.4 Basis for Memory Device Derating

The industry survey did not produce any information regarding memory
devices. Also, the derating criteria received from other companies did not
cover memory devices. Because of the unavailability of external data and
derating for these devices, Martin Marietta must again resort to internally
available data, analysis, and MIL-IDBK-217D.

"The memory devices defined for derating guidelines include three

specific technologies. They are: 1) bipolar, 2) MOS, and 3) bubble. In
the bipolar and HOS technologies, the memory group can be divided into RAM
"* and ROM memories. The RAMs, in turn, can be categorized as static and
dynamic.
26
.4,Y

Vo
 The basic difference between dynamic and static RAMs is in the way
"they store data. The static RAM uses a flip-flop to store a bit, while the
dynamic RAM uses a capacitor. The static RAM is easier to use because
refresh logic is not required. In addition, static RAM control signals
tend to be easier to generate because cycling is usually unnecessary. The
dynamic RAM draws less power. The static RAM draws power continuously to
sustain its flip-flops, while the dynamic RAM draws minimal power between
cycles. The dynamic RAM die size tends to be smaller than the static RAM
die size. The size is due to the difference in cell designs, and the die
size of the dynamic RAM is often at least 20 percent smaller than that of a
' comparable static RAM from the same manufacturer.

The ROM is a random access memory in which the stored information is

fixed and non-volatile. A semiconductor ROM is a circuit whose stored in-
formation is fixel by a masking operation during wafer processing. Bipolar
ROMs offer access times in the 25 to 50 nanosecond range for transistor,
transistor logic (TTL) and 15 to 20 nanoseconds for (ECL), which represent
an order of magnitude improvement over equivalent MOS circuits. Historic-
ally, MOS ROMs have offered greater bit densities than have bipolar cir-
cuits. Most recently, however, technological advances have narrowed the
gap in bit densities.

Perhaps the most important characteristics of a memory chip are the

number of bits, speed capability, and power dissipation. The supply volt-
age and current play a major role in controlling the power distribution.
Again, since no data collected shed light on memory derating and failure
rate impact, MIL-HDBK-217D was used to derive the memory derating criteria.
The same factors affect memory failure rate as affect integrated circuits
as a whole, with the addition of a number of bits factor. The temperature
acceleration factor (Figure 9), quality level factor (Figure 1), and volt-
age stress factor for Q4OS technology (Figures 13 and 14) previously inves-
tigated will be applicable to this memory discussion.

The derating parameters developed for the complex integrated circuits

based on the effect of these factors (section 3.3) will also be applicable
to the memory device (RAM or ROM) derating. These parameters include the
supply voltage and junction temperature. Due to the similarities with the
complex integrated circuit analysis and the importance of the current to
the operation of the device, the same derating will be specified for the
output current.

"The analysis conducted on memory devices did not discover any substan-
tial information on the operating frequency. Therefore, a conclusion could
"not be drawn as to the effect of derating this parameter.

.* The Cl and C2 factors previously discussed for complex integrated cir-

cuits were based on gate count. They were replaced with Cl and C2 factors
"based Gn a device number of bits complexity for memory devices. Figures 19
through 21 show a plot of the impact of bit count on failure rate of var-
"ious memory types. The curves are interesting, and at several points
appear to have a breakpoint or change of slope, but it is not customary or
practical to derate a memory device based on a percentage of bits.

"27

4'
 60-

S20 00e

x
(/ Legend
0
0• C,FACOR
x C2 FACTOR
0'
. 0 5000 10000 15000 20000
NUMBER OF BITS
Figure 19. Bit Count Impact on Failure Rate of
Bipolar RAM Devices

40

;'•:•~0# * - .A0.•.
0.

0010
20 0020

//« i Legend

x C2 BIPOLAR
0~ OC1 mos

0 20000 40000 60600 80000

NUMBER OF BITS
Figure 20. Bit Count Impact on Failure Rate of
ROM and PROM Devices

28

_to
 150-

100 10000/

50-
9 Legend
0 a C1 FACTOR
X•C2 FACTOR

0 20000 40000 60000 80000

NUMBER OF BITS
Figure 21. Memory Devices: Bit Count Impact on
Failure Rate of MOS RAM Devices
"Based on this analysis, these derating criteria for RAM or ROM de-
vices, as it appaars in Table 2, was selected.
Bubble memory technology (both device and material) is significanLly
different from silicon integrated circuitry. However, they are both based
on a batch manufacturing process, with the cost of a function very strongly
dependent on the functional density per batch and manufacturing yields.
From this point of view, bubble technology has some very major disadvant-
ages, coupled with some potential long-term benefits.

First of all, As a device it is very well suited to serial storage of

data. Although it is slower than any silicon integrated circuit based
storage circuit, it is non-volatile (or at least it can be designed to be).
Secondly, it can also be used to perform very simple logic functions which
allow data to be stored and retrieved efficiently. Thirdly, it can be used
to preamplify the otherwise very small signal magnetically, so it can be
used to design a reasonably self-contained memory chip.

The bubble memory has major disadvantages, which are:

I Very high material cost. caused by both very high initial substrate
cost and a very expensive, difficult, and low productivity liquid
phase epitaxy deposition process. Material cost is approximately
30 to 50 times higher than silicon.

2 A very high packaging cost, since every circuit has to have an

individually adjusted bias field and a rotating magnetic field
limit icto the package.

3 Limited operational temperature range.

29

4
.**.
*- .*.* * ** * * - *~.. *.* % b.*~% e ..
 Potential long-term benefits that stimulate bubble memory development
are:

1 A processing method that typically requires only three masking

* steps, only one of which is critical, compared to the six and more
for silicon.

2 T much room for improvement in bit density, since bubble

memory is based on a relatively simple design.

3 Because it has only one critical masking step and no critical

alignment requirements, it is a technology best positioned to take
advantage of improvements in pattern definition techniques.

Due to the dearth of information received on bubble memory devices,

MIL-HDBK-217D was used in the determination of the derating criteria for
those memory devices. The approach taken by MIL-HDBK-217D is to divide the
overall bubble memory operating failure rate into two parts. They are: (1
control and detection structure, and 2) memory storage area. Each of these
parts has an associated failure rate that is accumulative in order to pro-
"--
¼ duce the overall device failure .rate. The factors affecting the failure
rates of both the control and detection structure, along with the memory
storage area, were then investigated. The analysis performed in section
3.1 (Figures 1 through 6) on the effect of the quality and environmental
factors on failure rate also applies to bubble memories.

The device complexity factors, C01 and C21 for the control and detection
element, and C1 2 and C22 for the memory storage area, were investigated
and their effect plotted in Figures 22 and 23, respectively. These com-
plexity factors are based on the number of bubble chips per device and
therefore do not represent a practical derating parameter.

The next factors reviewed were the duty cycle and the write duty cycle
of the control and detection structure. The duty cycle factor is applica-
tion dependent, since it is a function of the usage the bubble device ex-
periences.

The impact of the duty cycle factor on failure rate is plotted in Fig-
ure 24. The result is a straight line, indicating that thia factor has a
linear relationship with failure rate. It is not practical or customary to
derate a device based on its usage. The write duty cycle is also based on
the usage of the bubble device, and was not used for derating. A plot was
generated showing the impact of the write duty cycle on the failure rate.
It is shown in Figure 25.

03

__.. v _
•V..
':: :•' 3 A
 10

* Z
0-

-0

¾4 *eend
0
C 2If A CT0R
NUIM1ER OF SU13SLE CHIpS
Figure 22. O p1 i
100
Fa t r I a t oN F i
Of Bubble m{emIories ue Rt
1pc nFiueRt

.44

.5.
0

2J

*9n

o 2000 Z400 600 80.00 100C2A~o

Fuirg 23.
NUMER ITSPER CUBICINH 10
Com np
lexity Factor
Of Bubble M(emories m a o Fiue
rpc nFiueRt Rt

*
-31
 0.6-

0.4

0 01 0.4 0.6 0.8 1

DUTY CYCLE -D
Figure 24. Duty Cycle Factor Impact on Bubble
Memory Failure Rate

5 o.s2

I . ,L

0 [Link] 0. C 0.8 W I

Figure 25. Cycle Factor I0pact

-on
.00e
1iue o= */ I
 Based on this analysis of bubble memory devices, it was concluded that
the maximum ambient operating temperature would be the only parameter
specified for derating. Other required derating will be applicable to
those microelectronic devices that compose the external support required
for proper bubble memory operation. The criteria for derating bubble
memories was summarized in Table 4, section 2.4.
3.5 Basis for Microwave Device Derating

The microwave device derating section covers the following device

types:

1 GaAs FETs
2 Transistors (microwave)

3 IMPATT diodes

4 Gunn diodes

5 Varactor diodes

t6 Step recovery diodes

7 PIN diodes

8 Tunnel diodes

9 Silicon detectors or mixers

10 Germanium detectors or mixers.

The industry survey did not reveal any data or information on microwave
devices. Limited information received from the Martin Marietta survey, and
MIL-HDBK-217D, were used as the basis for microwave device derating.

The results of the Martin Marietta survey are summarized in Figure 47

in Appendix 3. The information received via the survey served as a means
of grouping the device types and establishing derating parameters. Actual
derating values were not received, with the exception of a recommended
junction temperature of less than 100C or llOC for all microwave devices.

"After grouping the devices as specified in section 2.5, Microwave

Device Derating, MIL-HDBK-217D was used for the actual development of the
,derating
:% criteria. The device grouping, based on the amount of electrical
stress typically present during operation, is supported by MIL-HDBK-217D.
The part operating failure rates and the factor& that impact them were in-
vestigated for each device grouping in order to determine the derating
criteria. In general, the factors investigated were:

1 Quality level

2 Environment

: 33
•4

"33 0.

•::",>-".'':=."•.•:'.
:"•"'•"">:•"..•"•/;•.", •"••,'•••: '••.-",>•s.• "'-•,-'- : ••W,>.:.
 3 Application

4 Frequency

5 Power

6 Temperature.

These factors are not all applicable to each group of devices. Also, the
discussion in section 3.1 on the effect of the quality level and
environment on the failure rate applies directly to the microwave devices.

3.5.1 GaAs FETs

4i MIL-HDBK-217D indicates that the GaAs FET failure rate is primarily

dependent upon power and temperature stresses. The impact of case or
ambient temperature and the power stress ratio on the GaAs FET failure rate
is plotted in Figure 26. It appears that a break in the curve emerges at a
stress ratio of 0.60 and a temperature of 85°C. This indicates a sharp
"4:• rise ir. the failure rate due to overstressing. The objective of derating
is to minimize failures and to maintain a minimum failure rate, so it would,
be appropriate to select a failure rate factor that would accomplish this
objective. Three is the approximate designated factor. Above this value,
the rise in failure rate is considerably more dynamic. The failure rate
factor associated with the 0.60 stress ratio is 3.34. This was established
as the Level II power dissipation derating value. Level I and Level III
values were 0.50 and 0.70, respectively.

• ., •Legend of
-[Link].//
NL /)
*0
1/OS /s
•I _ o0.1
xJS S =0.3
aO.2

"SO.S
* S :0.7

0 S a 0.5

1 1.0

AMUIEn/CAS1 TDOPRAIUTU -4*9r.. C

""igure 26. Temperature Impact on Failure Rate
of GaAs FET

34

, ,,""•L,.,
PT,,.,•','
kl.,.,,.,',,.,,.-.
0' • ,• ,•r.'. .•, ,..., -"' .. ,.. '-...,.,wu '''h .... ''":",',b "-.: .. .'":
 The relationship between the ambient temperature, junction
temperature, and power dissipation is represented by the following
equation

Tj = TA + eJAPd•

The junction temperature can be controlled by derating the power. Power

derating also assures a low failure rate factor. Junction temperature
derating levels were established by utilizihg vendor specifications for
GaAs FETs. A range of 0jA of 200 to 260 degrees centigrade per watt
was used as an input into the equation, along with their respective power
dissipation values. The power was derated and the resulting junction
temperature computed for the two endpoints of the OjA range.

Here is a summary of the outcome of this work:

Pd = 50 percent yields Tj midpoint = 87.5*C

Pd 60 percent yields Tj midpoint = 100C
=Pd70 percent yields T4 midpoint = 112.5C.

Based on these calculations, the junction temperature derating for levels

I, II, and III were established as 95, 105, and 125°C, respectively.

Breakdown voltage was another electrical characteristic suggested for

derating. Based on the assumption that the power dissipation and junction
temperature values were as stated here, conservative and perhaps standard
breakdown voltage derating levels were established. They were:
Level I - 0.60
Level II = 0.70
Level III - 0.70.

The remaining factors affecting the GaAs FET failure rate are of no
consequence, since the application factor is power related and the assumed
complexity factor is one.

3.5.2 Transistor/IMPATT/Gunn Diodes

IMPATT and Gunn diodes were grouped with microwave transistors. A

suggestion received in the Martin Marietta survey pointed out that since
they are all high electrically stressed devices, diodes and transistors
should be in the same group. Using the failure rate model for microwave
transistors in MIL-RDBK-217D, the factors which were investigated due to
their impact on failure rate were operating power and frequency, and
temperature.

Several observations were made by plotting the impact of failure rate

of the operating power and frequency (Figure 27). First, as the power
level increases, the failure rate factor increases more rapidly at lower
frequencies. Second, as the frequency increases, the failure rate factor
rises sharply to above thirty for all power settings. Accordingly, the
failure rate factor was limited to ten.

"35

S* ~* -f.~5 •
.V ............. , 5
 30-
PCAK OPERATINO POWER/
Of CREATEU rTAN 200 WATTS/
SHOULD K UIMMED 8"LW
[Link] FREQUENCY/
0
20
"Ld Legend
•A /1-5 WATTS
-/ x 10 WATTS

a20 WATTS
3 10 '30 WATTS

'0001i Z 3 WATIS
1.001- ,,0 9 100. WArTS
•Z
- 200 WATTS
!•..•,0 • t 2 '

FREQUENCY - GHz
Figure 27. Operating Power and Frequency Impact
on Failure Rate of Microwave Trarsistors

The junction temperature impact on failure rate based on voltage

stress was plotted in Figures 28 and 29, respectively, for aluminum and
gold transistor material. In both figure;3, a junction temperature of 100*C
represents a sharp, drastic rise in the failure rate factor. The plot for
the aluminum material (Figure 28) attain3 4 failure rate factor of ten at a
junction temperature of approximately 127C. For the gold material (Figure
29), a failure rate factor of two was achieved at a junction temperature of
approximately 130C. Based on the initial rise in the failure rate factor
at T= 100C, Level I and II derating criteria were set at 95C and
I05°*, respectively. Level III was set to 125C.

Figures 28 and 29 show that the maximum operating junction temperature

of 200C cannot be attainei at voltage stress ratios of above 0.60. There-
fore, voltage breakdown d,'rating levels 1, II, and III were set at 0.60,
0.70, and 0.70, respectively.

Based on conventional practice, the power dissipation derating levels

were set as specified in Table 6, Transistor/I14PATT/Gunn Derating.

Ile 3.5.3 Varactor/Step Recovery/PIN/Tunnel

These devices are categorized together, since they are all low elec-
trically stressed devices. They are also addressed in this grouping in
IMIL-HDBK-217D. Figure 30 represents the ambient or case temperature impact
on failure rate based on the power stress ratio. At an ambient or case
temperature of 85C and a power stress ratio of 0.50, a break in the curve

36
" %%:: %

e-r-Y <'
V..
 t
7
I

0ALUMINUM

~30-/ /
S=Legend 0
'I•
~20 i0.0. AIS =0.40
Jx )$a 0.45

S' x S,, 0.40

* S= 0.50
0~ -I

"100 50 200
JUNCTION TEMPERATURE - degrees C
1o' /.• ,se.
Figure 28. Junction Temperature Impact on Failure
Rate of Microwave Transistors

r -

REFRACTORY METAL-COLD I

2- 0
W Legend
3SVA/BVbes 6S 0.40
/~ xu0.45
S.

........ '0 7

50 100 150 200

* *=i v /'I~e-
S/ x• 0.40**-_
0.4
~~ bJ x., JUNCTION TEMPERATURE - degrees C °•
Figure 29. Function Temperature Impact on Failure
Rate of Microwave Transistors

37
 i..t
-= / "Legend
4 I / / A S = 0.1
./ / I ,: ' /, x S 0.2
"2/ w ;I/ / / / /. /
/' S ..
os-0.3
tR - 1 US =0.4
-"" I / X/i./
S=0.7
" /S = 0.9
*,S =.•..
•t,: !//1<5 S =.O.8
4,.
•,'1I / , ...
2 -f-
-,..[• " + S =1.0

AM-IENT/CASE TEMPERATURE -degrees C

Figure 30. Temperature Impact on Failure Rate of

Varactor, Step, Recovery, PIN and Tunnel Diodes

appears which is below the reasonable (in our judgement) failure rate fac-
tar of three. At temperatures above 85*C, the failure rate begins to rise
much more rapidly at the 0.50 stress level. Based on this and conventional
practice, the power dissipation levels (I, II, III) were set at 0.50, 0.60,
and 0.70, respectively.

The derating criteria for the junction temperature was set at 95, 105,
and 125C for Level I, II, and III respectively to be consistent with the
derating already established. There was no information received to dis-
prove these values. The reverse voltage was derated to 0.70 across the
three levels based primarily on convention for these type of devices.

3.5.4 Silicon and Germanium Detectors/Mixers

Detectors and mixers are classified as low electrically stressed

devices. The base failure rate is the main factor affecting the operating
*O failure rate of these devices. The base rate is driven by the power stress
ratio and the ambient or case temperature. The detectors and mixers are
divided into categories based on their material. The silicon devices have
a much wider temperature range than the germanium. The germanium devices
are not recommended for new design. However, the germanium devices were
researched and derating criteria established.

38
 The failure rate factors for each stress ratio, as they changed with
respect to the ambient or case temperature, were plotted in Figures 31
through 35 for the following devices:

1 Silicon mixers

2 Germanium mixers

3 Silicon detectors

V 4 Silicon Schottky detectors

5 Germanium detectors.

The failure rate should be held below three, since a factor above that
results in a rapid increase in the failure rate, due to overstressing. The
curves for both silicon and germanium devices indicate that a power stress
ratio of at least 0.50 will hold the failure rate factor below three and
still provide a sufficient, nonrestrictive derating requirement. It was
established that Level I, II, and III power dissipation derating criteria
would be set at 0.50, 0.60, and 0.70, respectively.

The reverse voltage was set at 0.70 across all three levels for both
- the silicon and germanium devices. The voltage rate was based on the
nature of the devices and their low stress applications.

- /~ Legend
ff/I/7 /A S=0.1
xS 0.2
jC SJ00.3
<3 8 S =0.4

-;- H S = 0.6

TiMPUA.....
. y..C

Fiue31. Temperature Impact on Failure Rate of

U Silicon Microwave Mixers

339
*~~~ - ~ S, 0.9-~

• .. . . 2- * S. =.'D -..
'A%" '••' **.% ''* '•.* '¶' " " '* - '' ' ', • •• 4 , .'. *,, " S'•,
"* " " , Q "•* •'• ' "-*

. . A .* , ,, , . bt hC. A,-
, ,S.- a 0• .
 Legend
• x S$-0.2
, /;/ 77 S= 0.3
bJ=.0....

8 S = 0.4
"' • • / S=O.S
-J S =0.7
Li 2 /

-0 S= 0.9
?,. 1.1

25 30 35 40 45 50 55 60 65 70
SAMBIENT/CASE TEMPERATURE -degrees C
Figure 32. Temperature Impact on Failure Rate of
v. Germanium Microwave Mixers

TI, !I
"I/
Legend
S =0.1
x S a 0.2

•,.• 0 S= 0.3
<3 I, I -
3- / / S =0.8

*J B i iI .j /* AOS S=0.7
0.5

.1~ ii,'.* S =0.9

+ S =1.0

ANMhSV"S YMARIRANN -"fr~o C

Figure 33. Temperature Impactz on Failure Rate of

* Silicon Microwave Detectors

40

".
+
h..
Legend
• 0
!
IDI
! 1
AS =0.1
A

x S-0.2
6 0 S= -0.3

La,. 3, ,/1ix
' /, // S=0.4
S =0.6
"__ I !i
I /~/
,' //
i/I
~
/*-S
4POS- ~//
=0.7
0.8
SoS = 0.9
. -.. " + S = 1.0

AMBIENT/WE TEMPIRATURE -4eres C

Figure 34. Temperature Impact on Failure Rate of

Silicon Schottky Diode Detector

50 I /

4 A S = 0.1

E =0.4
•" i /3//I
3 8 SO.4

:.
S =0.9
a S * 0.8

-• + s ~=t.._o_
S1.

25 30 35 40 45 50 55 60 65 70
AMBENT/CASE TEMPERATURE -degrees C
* Figure 35. Temperature Impact on Failure Rate of
Germanium Microwave Detector

41

. Yt. . .

* ~.t.
~*~-~ am
,,%%~ ~ %
 The junction temperature does vary with material used. Junction temp-
eratures of 95, 105, and 125C for the silicon devices at Levels I, II, and
III, respectively, were selected for consistency. The temperatures were
also selected to conform with the recommendation of limiting Tj to 110"C.
Junction temperatures of 75, 90, and 105C for the germanium devices were
selected at levels I, II, and III, respectively. Temperatures selected
were based on the one industry survey response on. germanium devices.

3.6 Basis for SAW Device Derating

Surface Acoustic Wave (SAW) devices were specified as one of the new-
est technologies requiring derating guidelines and applications. Because
of the absence of published information on SAW devices, the industry survey
was used. The survey revealed that two companies are primarily involved in
the development of these devices. General information about SAW devices
(i.e., design processes, fabrication, etc.) was obtained, but published
derating guidelines were not available, due to the recent technology devel-
opment and the design of the device. Therefore, the suggested derating
parameters and values must be based on discussions held with those know-
ledgeable in the area and the basic device design and applications.

There are two important characteristics about SAW devices which solicit
"interest in terms of their usefulness: 1) the wavelength and the directly
related propagation velocity, and 2) surface propagation. Traits which
make SAW devices attractive are actually features inherent to the waves
themselves.

The wavelength of an acoustic wave of a given frequency is about 10 5

times shorter than that of an electromagnetic wave of the same frequency.
Similarly, the propagation velocity is 105 times sJower. This suggests
that a one or two centimeter long SAW device is equivalent to several
thousand electromagnetic wavelengths. Many kinds of signal manipulations
involve devices measured in wavelengths, thus creating an interest in SAW
device application.

Surface propagation is the other characteristic that makes SAW devices

useful. Acoustic waves propagate along the surface of a solid in a prefer-
red direction. These acoustic waves, for all practical purposes, do not
extend more than two wavelengths below the surface, with most of the energy
at a depzh of one wavelength or less. Therefore, energy can be sensed and
manipulated by metallic elements applied to the surface of the piezoelectric
substrate.

A SAi device usually consists of the SAW element on ite substrate plus
any auxiliary elements, such as an amplifier or matching elements, and the
packaging of the complete device. The electrodes in actual SAW devices are
composed of fingers extending from a common bus, forming a comb-like
appearance. Two combs are placed so that their fingers overlap from oppo-
site sides, with the voltage between the two opposite electrodes creating a
strain on the substrate surface. As this strain varies with a changing
voltage, a physical wave is generated at the surface. This wave has a
frequency corresponding to the finger spacing.

42

*%
4,4................... ........ ......... o ,.
 This particular SAW layout or design is called an interdigital trans-
ducer. Most SAW devices have two transducers - one input and one output.
The fingers in the transducers are spaced a quarter wavelength apart. The
finger width is a quarter wavelength of the desired frequency. Interdigital
transducers normally consists of dozens or hundreds of finger pairs. This
principle is illustrated in Figure 36.

INPUT INPUT NOTEIt: ONLY THREE FINGER PAIRS

TERMINALS TRANSDUCER SSURFACE ARE SHOWN FOR
TRAN5DtJCER EACH
TO ILLUSTRATf.
ACOUSTIC THE PRINCIPLE: TRANSDUCERS
" AACOUTWAVE NORMALLY HAV, HUNDREDS
"SAVOf FINGER PAIRS
"A OUTPUT
-TRANSDUCER

A4 •LI01 TTI'tT --- A--

TFRM'4NALS 8a1-
PREFERRED DIRECTION
OF PROPAGATION IN
•-PIEZOELECTRICA
SUBSTRATE A I2\

TRANSDUCER 8- 14
FINGERS X-WAVELENGTH OF
'•,• ACOUSTIC WAVE
:-T SUBSTRATE SECTION AA

Figure 36. SAW Transducer

Four major applications of SAW devices are currently being used both
commercially and by the military: They are:

1 Delay lines

2 Oscillators

3 Resonators

4 Filters.

A finite travel time for signals between the input and output transducers
is inherent to the design of SAW devices. Due to this finite time, a SAW
device can function as a delay line. The great advantage of a SAW delay
line is the significant amount of delay that can be obtained in a very
small device. [Link] device can also function as an oscillator by placing
an amplifier in the loop between input and output transducers. The ampli-
fier adjusts for the losses in the delay line, while the spacing of the
fingers makes the transducers respond only to the selected vavelengths for
which they were designed.

"ASAW resonator consists of either one or two transducert, vith a

grating extending in both directions of wave propagation. The surface
acoustic wave is launched in both directions from the input transducer and
Sis reflected back and forth by the adjacent gratings. This creates a
standing wave at the designed frequency which is determined by the finger

... 43

7011
IN IN Zo A~ V7-
*I% N.O*
aL -
 width and spacing. Since the finger width and spacing are chosen to reson-
ate only at a desired wavelength, the resonator performs effectively as a
filter.

SAW devices are tailored to the particular frequency and response

desired for each application with a frequency range from 50 megahertz to
about 2 gigahertz. There are a number of basic design variables (Table 11)
which can be employed to obtain a design which complies with a specific set
of requirements. The requirements are generally of the type listed:

1 Frequency

2 Bandwidth

3 Response

4 Insertion loss

. 5 Frequency stability.

"F The frequency of a SAW device is determined by the width and spacing
of the fingers. Finger spacing and width also generate the surface acous-
tic waves. The accuracy to which the desired center frequency is attained
is dependent upon the precision of the mask making and fabrication steps.
If a very exact frequency is required, the center frequency can be adjusted
over a very small range by two techniques. One is to vary the mass of the
fingers. Increasing the finger mass lowers the frequency very
slightly. Another is to rotate the whole pattern very slightly from exact
alignment along the principle axis of propagation. This allows the fre-
*• quency to be tuned over a small range by phase shifting.

*[ The acoustic waves generated at the surface of the substrate are

affected by the presence of the fingers. The fingers cause the waves to be
reflected back and forth between the fingers and the input and output
transducers. Thig effect is caused by a discontinuity in the impedance of
the substrate (represented by each finger). The discontinuity causes the
waves to peak ind be reflected. These reflections can be reduced by using
the appropriate techniques listed in Table 11. The bandwidth of a SAW
device is determined by the number of finger pairs in the transducers (de-
lay lines) or the number of lines in the gratings (resonator). Adding to
the number of finger pairo reduces the bandwidth.

"Once the desired bandwidth is established, the next requirement is

usually to reduce the responses outside this bandwidth to the lowest values
possible (at least below some specified level). A narrow bandwidth is ob-
* tained by having a large number of finger pairs, but having numerous fingers
results in reflected waves. To compensate for this, the thinned electrode
transducer design variable is applied (Table 11). This involves eliminat-
ing groups of finger pairs until the transducer consists of multiple sets
of a few finger pairs separated by space, while still maintaining the same
finger width and epacing. The same frequency and bandwidth will result.
To prevent waves from being reflected across the open spaces between finger
sections dummy fingers are placed in the open sections.

44
- [NN

I I . ** * * .
!V

TABLE 11. DEIG V ARIBE

VFNUMBERS OF 149 FINGERS 13 FINGERS Number of fingers is related to bandwidth by the
FINGERS AND expression A1f/fc-1/n where n is the number of
TRANSDUCER qlllllllli finger pairs.
SSEPARATION 'Ii
Transducer separation determines delay.

I • to6 A

NUMBER OF Multiple fingers produce stronger harmonics.

FINGERS PER Three fingers per period provides stronger fun.
] PERIOD damental 2ndnd d 4th harmonics, plus (decreas.
(WAVELENGTH). ingly) seven additional harmonics. Four fingers
MAY BE TWO per period provides stronger fundamental. 3rd.
O
PER PERIOD 9th and l1th harmonics.

(AS SHOWN
HERE)
[2 WRii)A - PrniouX.
0

J THINNED .[Link])NS.
41 [Link] L( K. Either or both transducers can be thinned. Re.
TRANSDUCER '0 CTiONS SPAL ING -It moving groups of fingers while maintaining over-
(ALSO CALLED all transducer length cuts down on second-order
OPEN effects resulting from internal reflections.

Jopen
DUMMY iii iii. i l. Dummy fingers (not connected to either electrode)
FINGERS can be inserted to absorb waves reflected across
spaces between finger sections.

PORTS(FORllt !iit !r~i l!i~ !l!l

ONE OR TWO
ORESON ORS
One port resonator behaves exactly like a bulk
crystal resonator and simplifies circuit design.
ONAl
ONLY')
ii i i l Has high Qand low loss. port devices may
have variable Q and are easier to build to given

APODIZATION changi lithe oetip of the lingers ro opoite,

"eJ|ctroles in a deterrmined patle n resuits In
weighttn5{ the fqude
N nc esponset Ortilne fdie-
he
1ducet. NWrmally one of the transducers in a delay
lineIi
is apod. d. Note that the shonsened fingers
I'l These suppress multiple reflections across the
olrn spacioe and the associated [Link]
d kct%hi the tcspunse, curve.

4> 45

. a* .... * •..,, .': ..a*.-

l~t','-:-':*: '.. •* -" -"":'''• ,""'""'"- .-* •: ,
' ;.".- :.-'. *'-.'-','''_k ',. -. * A*-.Se
.-.*. *. *.''.4,
* '. ;.*'%*-.'[-.'*.-*..*
 Insertion loss is a major consideration in many SAW device applica-
tions. It is defined as the proportion of the input energy that does not
appear at the output. There are two main causes of insertion loss:

1 Waves traveling away from transducer

2 Coupling coefficient.

* The waves that are excited by the tranducer travel in both directions away
from the transducer. Tn a delay line, only those waves that travel toward
the output transducer are used; the other half are dissipated or absorbed.
Half of the waves, or a quarter of the acoustic energy, that reach the out-
put transducer will travel past it and be absorbed or dissipated. This
U translates into a minimum six decibel loss of the acoustic energy. Reson-
ators, however, are able to utilize both sets of waves due to the gratings
on both sides of the transducer. Delay lines typically exhibit a high in-
sertion loss, whereas resonators are associated with a low insertion loss.

The insertion loss which results from the electromechanical coupling

coefficient of the substrate material is a characteristic of the material
itself. There is no way to change it. All commonly used substrate materi-
als have low coupling coefficients, but some are much lower than others.
Table 12 lists the coupling coefficients of commonly used substrate mater-
4 ials for SAW devices along with their temperature coefficients (how much
the frequency of the device changes with each degree change in temperature).
There is clearly a trade-off to be made between increased coupling coefficient
and increased temperature stability depending on the device application.
As the table indicates, the coupling coefficient of lithium niobate is much
better than that of quartz, but its temperature coefficient is very poor
and that of quartz is nearly perfect.

SAW devices, in most cases, are used in the very low power level of
circuits. Therefore, even a 15 dB loss is translated into only a few milli-
watts or less in absolute terms. However, the loss is undesirable since

TABLE 12. COUPLING COEFFICIENTS OF COMMONLY USED SUBSTRATE

MATERIALS FOR SAW DEVICES

JTemperature
"* Coefficient
*•a ive Velocity Coupling per Degree
Meters per see Coefficient in Percent Centigrade
Lithium
Iliobate
A (YZ cut) 3488 4.82 94

Lithium
Tantalate 35
(YZ cut) 3230 0.66

Quartz
"" (ST cut) 3358 0.116 Negligible

46

9*
-';.,,,..,- •. •'.- * -••' •j't'-. . -' ',•,-
19S. 9 .-....- '. '. * , o.'**..,. '.- • t. .• . ..- ', '. ' .
*%
-o . . •
 the amplification needed to compensate for it may introduce instability,
phase distortion, or other types of noise in the signal. The coupling co-
efficient has to be considered in combination with the closely related
frequency stability.

The frequency stability of SAW devices has to be considered on three

different time scales, with each affected by different parameters:

1 Short term (less than a second)

2 Medium term (hours)

3 Long term (months).

The short term stability depends on the efficiency of the device, while
medium term stability is largely determined by the temperature coefficient
"of the substrate material. Long term stability is a problem when frequency
stability is required over periods of many months, as in the case of fre-
'•, quency sources. Experience indicates that with present technology the fre-
quency drift demonstrated by SAW devices is not as desirable as that shown
by crystal oscillators. The aging effect of SAW devices is at least one or
two parts per million per month while the best crystal oscillator achieves
a drift of about one part per million per year.

SAW devices are passive; they typically operate at a low power level
and are low heat generators. Due to these operating characteristics, de-
rating, in most cases, is inappropriate. The level I, II, and III derating
breakdown does not apply because of the operative nature of these devices
(passive) and their low population in systems. There has also been no in-
formation received from industry to support derating levels for SAW devices.

The frequency stability demonstrated by the SAW device is a design

requirement which can cause part degradation if it is not controlled. Life
tests that have been conducted on SAW filters suggest that the best fre-
quency stability exhibited by these devices is at low power, while main-
taining constant temperature range. The results of the tests with input
power of 13 dBs and 18 dBs and a center frequency of 500 megahertz are
illustrated in the plot of frequency change versus time of Figures 37 and
38. Figure 38 (18 dBs) shows that frequency stability is forfeited at in-
creased input power. The power ratio of the 18 dB samples is three times
that of the 13 dB samples. This situation creates an effect on aging which
is four times greater. It can be concluded that minimum aging and increas-
4 ed frequency stability occur at low input power. Therefore, input power is
the primary derating factor for SAW devices.

The temperature dependence of SAW devices is driven by the substrate

material. Each substrate material has an associated temperature coefficient
(see Table 12) which determines how the frequency of the device changes
with each degree change in temperature. The frequency stability is deter-
mined by the temperature coefficient of the substrate specified as a design
consideration. Since SAW devices are low heat generators, their environ-
ment determines the operating temperature. The devices surrounding the SAW

" 47
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49

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: :.:.: 4 * *. * *. * * ** - .. ** *S1.*

_ ' 1' .** * *>* 4

 device are a major concern because of their heat potential. With such an
environment, industry indicates that the SAW operating temperature is not
to exceed 125*C.

Industry has determined through work with SAW devices that they are
not particularly sensitive to shock and vibration. However, SAWs are some-
what sensitive to electro-static discharge. Design attention is required
--'I to minimize this stress.

Based on this discussion, the derating criteria for SAW devices out-
lined in Table 10, section 2.6, was selected.

"A4

4MI

.'-'o50

S., ¶ % % % - ` • . ° • • °- - - - -2 . -• ° . -` . . ,. o, . -. • o . ..- .
 4.0 FAILURE MODES/MECHANISMS

4.1 General

Failure modes are a primary concern of reliability when considering

semiconductors and their failure rate. The origin of failure modes can
occur at many different points. The failure mode can be a result of inher-
", ent design weaknesses (actual or potential), a manufacturing process, mat-
erials used, or human error.

Generally, failure modes are initially identified through accumulated

experience or device physics analysis. Some failure modes can be elimin-
ated or controlled, while others are inherent in a particular device type.
The modes which can be eliminated or controlled are related somewhat in the
quality levels discussed in section 3.1.

The controlled modes can be translated to concerns in the overall

Q semiconductor, the die fabrication process, and the assembly process.
"Figures 39 through 41 show the major reliability concern in each area,
respectively. The control method or constraint for the concern is also
shown. Some of the concerns can only be controlled at the semiconductor
manufacturer's facility, while others can be controlled at the contractor's
facility or an independent testing laboratory. Figure 40 shows an example
of a semiconductor manufacturer control using internal visual inspection.
Such inspection controls such modes as glassivation, metalization, and
bonding pads. Electrical performance in which the control can take the
form of burn-in, baselining, or rescreening is an example of contractor's
facility control modes.

4.2 Application Guidelines

Specific failure mode information is not readily available for the

components under investigation, due to their recent entry into the market.
The Martin Marietta kurvey (Appendix 3) revealed some failure mode data
with associated failure mechanisms.

"VLSI and VHSIC devices are relatively new technologies. The failure
mechanism list is tentative in nature, since much of what needs to be known
0 will not be discovered until development is further along. The VLSI and
VHSIC devices, along with hybrids, have typically exhibited failures in the
form of shorts, opens, leakage, and latch-up. According to sources at
Martin Marietta, the mechanisms associated with these failures are primar-
ily due to manufacturer's techniques and design applications. Both of
these mechanisms are controllable. Inadequate manufacturing techniques
"have resulted in insufficient substrate contacts, lack of guard bars, and
*• lack of protection at the input/output point. The designer should imple-
ment safeguards into his design and create a system that would be tolerant
to such failures. The application of the design should also be specifical-
ly stated so as no discrepancies exist.

Since these devices represent a new technology still in a development

phase, failure mode/mechanism data has not been completely established.
However, many of the possible areas of concern can be identified through

51

"-7 . -... '........ -..... ".*. -

 xw 2

E ,

c 0c

2 CL 0
z~~~ &Z4. 2

4z 0

1-4

00
4-i

* ~ -52
 CONTROL METHOD
CONCERN OR CONSTRAINT
INTERNAL CAVITY: %to~stw's Content Watrhal wale,.apo Contaerr

L0056 1"AtinCles i"1411"nhtV-11-i

Par!cil, Impact 40ose cetecr~on
Aa~ Grapht,-. X PAY' I.,I

P'al 'qJ Oal,ty OC Ifl5O.1'fl

POST (LAND) - Plalo. ouallty OC inspection

WeglAdhes~or OrejShear Tq~t,ng

C ýs~stoncyiunilormity internal Visua

Co,,qge
W~ttn5Radtogdott: fl I~RAY1
[Link]
'.widad
Ce, Orental'on Internal Vollusi and MeClnctan.C

Polenniallt L~oose Partincle$ internal Vriiua-

particle ra1NOACe

X-RAY]
[Link].-C
Penstince to Tempe~rature Stress Tomnperatull CrClil
trerrtta Shsoca
HirghTemperafture Storage

Peist1artee to Mechranical Stress Mlicnanteal Shock

constant Accelertitonl
vbtirtlon. Varablof Freauency

DIE ATTACH Rewrork Control andoAatIrlCtiOn

[Link],Oati CraireCler.3%.ic Elit,.trical Test-nq

GenrallOushlly and WorlftttflanshP Line Certifcation OnOMonitorng

Opelftor Train,"g

BONDING W IRES:-- ---- Sizeand Matteril Control and Fltflctlin

Cu~rret Density Controt and Aestilction

Rewomland Oserbonding Control and AleeftttlOft

Strength and Adhesion Bond Pull (Oesrjtiulot

100% NOn-Destrta~lte Bond Pull

Placemn
Height sdLos IInternal and Wilett
(X-RAY)
Radogemoflhc - Gold WitreOnly
Cleaac
UnitornttyJ
Nickined Other Damtage

Orea~pallon Colactil'llattC111 electrfca Test

SirriatalticCantalnslttaon Monoattaallalic Wn ft..almd

Pkelstafte to ThermaelStres Teinslitimrts, Ctrcle

Thermal shat

P4Patatance to MoChwual Sit~e" Consteril ACCOMPONO

fteneial Qualty and W 0iaeu~ UMiCOOfloatamm eaweMw"

oplaeta Truilnin

Figure 40. Reliability Concerns: The Die Fabrication Process

the extrapolation from what is known regarding existing technologies.

Other areas have been highlighted in the course of analysis over the last
few years. It is possible to focus upon several specific portions of the
manufacturing process to the extent that process changes might impact reli-
ability, some physical parameters (such as threshold voltage and surface
mobility) that affect various failure mechanisms, and such specific failure
mechanisms as radiation sensitivity and multiple layer interconnects.

53
 CONTROL METHOD
CONCERN OR CONSTRAINT

IILCIIICI FFFORUN(.

lnn~pniaiuSitIJI.,I.I

IN~DESIGNl. MTRILO PRCS

CH4ANGES RenselCaBnge
INoict

M-,n.n1C. IDili, UIaipgectio,

SU nRFAE OTA IATO [Link] PituInin"yTe...

ThiCknoss GeaflaastaIorThickness Measuriivemen

UnG.*CoINg Scanning Election Uicrocope

Litopi 'g e ionspection

Wangnig Intimnal Vis~al inspecionltf

bLing 0i Piniing

C."..]enil Current Gensily mL,.I

BONDING PADS
Ciajance

proS. Damae nltl Visu., Inspection

ReInduatGiassivali0nJ
scraIetch* end Voids5

OXIDE AND DIFFUSION FAULTS I.~Vsa Iseto

CORROSION AND CHEMICAL 0AMAOE Il~nlVliiiion,.

FOREIGN MATERIAL IniternalVinyln Inlspection

SCRBN DEFECTS [Link] Nose Geilacrion
CRACKS. CHIPS. SPLITSI

DIE UNDERCUTTING RAdiognaphiC IX RAVI

DIE THICKNESS Wales,ThircknessMaasii,ente.
Minimum Ore Thitckniasa

High T ampStor age(PostS eal)

SURFACEABSORPTION
DOLD-BACKINGTHICKNESS (3td-Bakihng ThickneesS
Mitavurnintents

THERMAL STABILITY TheimalStbIV~il UMe,ninuinenAIa

REWORKINDUCED FAULTS ReworkiRealiniclonis

[Link] AND L"ineCnrlicglvon

PROCESS CONTROL 00.141o, TrainingRegai,en,.nIs
TracteagrIN Reguirements
Inco'"ing MaternialCo
OC Inspection

Figure 41. Reliability Concerns: The Assembly Process

The main causes of failure of microelectronic partsa stedb

P.D.T. O'Connor in his paper "Microelectronic System Reliability Predic-
tion," are summarized in Table 12b with typical percentage contributions.
These percentage contributions can vary, based on technology, production
techniques, quality control, screening methods, circuit design, system mat-
urity, maintenance, and use. However, they do represent "typical"' percent-
age points. An additional failure mode not covered in the table is an out-
of-spec overload condition which refers to failures not due to part proper-
ties but due to system design.

54
 TABLE l2b. FAILURE MODES OF MICROELECTRONIC
DEVICES
Typical Failure
Failure Mode Percent

Bulk Silicon, Surface Related 50

Foreign Materials/Particles 5

"Bonds 25 L
Hermeticity 10 "

Other 10

As shown in Table 12b, the major causes of microelectronic part failure

(applicable also to LSI devices) are usually defects introduced during the
wafer fabrication process. Failures due to this type of defect can occur 4.
when cross-sectional areas are reduced to the extent that physical process-
es such as electromigration or localized overheating can change the part
characteristics within the operating lifetime. Normally, geometrics are
such that these processes would not affect electrical characteristics in
the typical lifetime of a good part. However, imperfections due to non-
uniformity of diffusion, oxidation or metalization, crystal flows, etc.,
can lead to reduced cross-sections in parts which otherwise pass initial
visual, electrical, and burn-in tests. Subsequent deterioration due
*. to these processes can then. result in failure. The probability of the
existence of failure-inducing imperfections is likely to be higher with
increasing complexity and packing density, other things being equal. How-
ever, this aspect tends to be offdet by improvements in fabrication
* technology.

The other two main internal failure modes shown in Table 12b, bond
failure and hermeticity, are package related and time dependent. Tempera-
ture is unlikely to be the prime failure factor in a purely mechanical pro-
cess, such as some bond failures, but is a factor intermetallic processes.
Temperature effects also affect the time to failure caused by a leaky
package. The relationship between temperature and time is unlikely to be
simple, since temperature cycling and the nature of impurities introduced
are likely to dominate.
Package related failure modes are not as highly correlated with chip
complexity as are failures due to chip imperfections. The rate of occur-
"rence depends upon quality control during part fabrication and test.
Microwave devices suffer from yet another set of failure modes. Ac-
cording to the article, "Reliability Life Tests on an Encapsulated Milli-
meter Wave DDR IMPATT Diode," the primary failure mode appearing in their
Saccelerated life test was a junction short. Such shorts are caused by gold
"in the ohmic metalization diffusing into the silicon layer through the
N platinum barrier. This diffusion creates a current path. According to
sources,a the diffusion is commonly referred to as migra-
tion. Marietta
Martin It is typically result of inadequate design application related to

55

N-h

.. 6

. " " .. '

 temperature strepses. Hermeticity problems in microwave devices have also
emerged due to design applications.

Microwave devices are another relatively new technology with limited

information available on typical failure modes. To gain insight into poc-
sible failure modes, it would be beneficial to examine data on diodes in
general.

diode will generally fail either open or SThe

short. The following
information 'taken from the Martin Marietta book, Reliability for the Engi-
neer (Book 7), is a summary of the percentage of the time that the general
purpose germanium, silicon, and surge limiting/logic diode will fail either
open or short. The short percent of failures for the germanium diodes is
65 percent, for the silicon diodes is 65 percent, and for the surge limit-
ing/logic diodes is 45 percent. The open percent of failures for the ger-
manium diodes is 35 percent, for the silicon diodes is 35 percent, and for
the surge limiting/logic diodes is 55 percent.

Table 13 shows the most common causes of PIN diode failures and design
features used to eliminate these failures, as reported by Unitrode in their
book PIN Diode Designer's Handbook and Catalog. This information can be
directly used by designers of microwave devices (diodes in general) to pos-
sibly prevent these failures from occurring.

Failure mode data was not available for memory devices. However, some
design considerations were pinpointed in a memory applications handbook for
memory subsystems. These designs will maximize RAM board yields during
manufacturing.

Some memory board designs are easy to manufacture. Others, while

functionally identical, have low manufacturing yields due to many bad chips.
The difference between the two is usually the amount of margin designed
into the system. Power supply and timing margins are both critical.

As margins go up to zero or negative, the amount cf soft errors

increases. Soft errors are those that occur intermittently. Soft errors
•'. usually occur during a memory cycle where some system parameter has gone
out of specification. The solution to soft errors is a careful system
design and board layout.

boardThere are three things the system designer can do to maximize RAM
board yield during manufacturing:

1 Design proper power supply decoupling

2 Design as much margin as possible in all control signal timing

3 Never allow spurious, shortened memory cycles to occur.

These suggestions are applicable to a design with tolerance for faults

"built in.

56
*'].
TABLE, 13. COMI-ON' DIODE FAILURES WITH DESIGN" FEATURES
TO ELIMINATE FAILURES

Diode Failures Design Features

Wb~liker o rlbbon-to-pout connection No whisker, ribbons, or posis necessary. Terminael

failure. fitlakers or ribbon-to-die bond pin# ate bondeld to th* die atf*PpArorlmotretV
failure. Bmokn whiskers or ribbon. 1000C.
Insufficient whisker pressure.
A uniform, true metallurgical bond lakes, place
Mechanical failure of the die bond, along both aldes of the dIe. A fused glass seal
extending beyond both sides of the die-to-pin
bond gives added strength.
Lead brazed directly to pin. Lead does notl eiiatnd
Into the gf&asstomnetal seal; hence, no glass edge
Lad fatigue. to cut Into the lead. Lead bonding dris not stress
glass seal, Statistical quslilty-controll sampling is
Lo performed to assure uniformity of braze.
Impurities In protective coaling, Glass Is one of the moat st able melertaift known.
movement and change In character A thick glass seal fused directly to the silicon
latic of coating (such as hardening surface eliminates the need for other protoctive
or cracking), pIn hoies In coating, coating.
welInNo
resltin
Incoplet weld Is used for hermetic seal. Glass sleetve is
incmplrete [Link] remelted and fused ground the silicon die Io
Imperect ealpermanently seal and passilvate the aurface.
Lack of hermaticily In plastic devices. Fused-In-glass construction.
All components are Inherently corrosion resistant
Corr oslon of diode components. Material content Is veriffied by certifications and
_____________________________ by regular Independent laboratory analses.
instablilty of paint used for All paint cured during bakeout at200C.
light shields._________________________
Mlemtch f
thrmalcoeficiet ofTerminal SCal are matched
pins, silicon and glass11
gI cefceto
expansion reutf thermal for temperature coefficietriof expansion. Material
[Link] hra and regular
content verified by corfluication-s
faliue ailuesIndependent laboratory analyses.
Melting of eutectic compounds Lowest melting combinations 01 elements is ?O0*t
aI temperatures that [Link] .bove maximrum tated temperatures.
diode ratings.
No copper, silver paste, or gold used indevice.
Entrapped flakes of copper oxide, In addition, there Is absolutely no void in which
siliver
paste and gold, plus glass particles may become entrapped. The motaliurga-
chips or other conductive or cal bond between die faces and both the terminal
non-conductive particles, pins and overall fused glass seal make Unirrode
diodes void free.
V41d splash residue contaminates No welding performed inside hermetic
Junction. glass seal.
ionc ad mleclarMigrations
Voltge-cilate are restricted by virtue of the glass
Voltge-activatIcldionic andtrmolecular adhering directly to the silicon Power-stress
migronactios incaluds. lcroir scroening eliminates the romslning ettremely
of cntac [Link] percentages of devices in which Such
______________________________ changes occur.

57
 5.0 TEMPERATURE MODELING AND VERIFICATION

5.1 Objective

The need has been established for a method of verifying the junction
temperature of a device to ensure that derating has been implemented.
Since the junction temperature of a device cannot be measured directly, a
point on the case where easy access for measurement can be obtained had to
be identified. The objective was to find a practical, reliable, and easy
to use method of establishing the derated junction temperature from the
thermally related case temperature (measurement point).

5.2 Approach

To accomplish the objective, analytical thermal models were developed

and verified that generate a practical method of computing or graphically
determining the derated temperatures. Two specific types of models were
developed and verified with test data for this purpose. The first model
was an internal thermal model approximating the thermal resistance from the
chip junction to the case bottom (6jC). This model was predominately
used for new designs as a ball park predictor, or quick look method of
deriving an initial thermal resistance (6jC). The second was an external
-- thermal model designed for specific package types to relate the measured
case temperature with the junction temperature. This model was used for
already existing devices that are housed in one of six package types. Both
of these models can be modified for the specific applications of the user.
The computer programs for the internal model, and the conduction calcula-
tions for the external model, are provided in appendices 5 and 6 respec-
"tively, so that modifications can be made to model specific designs and
assumptions.

Test measurements were performed on a 40-pin, side-brazed ceramic

package. Measurement data was acquired on the ceramic chip carrier package
for the purpose of verifying two of the external models. Since a high cor-
relation between the models and the measurement data was obtained, it was
assumed that the models for the other package types were accurate. All
models were based on the same assumptions and ground rules.

Upon verification, the external models were used to provide a graphic

representation of the relationship between the junction temperature and the
identified measurement point for each of the package types, based on speci-
fied assumptions. The implementation of derating was determined, In the
internal model, thermal resistance tables were generated for each level of
device coastruction. These tables were used in the computation of the
* thermal resistance from the chip junction to the case bottom ( 0jC)"
This established the ball park prediction of OjC for new designs.

As in the case of the external model, the thermal resistance tables

produced by the internal model were based on certain assumptions. Each of
these models (internal and external) will be addressed in the following
sections, along with their assumptions, specific applications, and results.

58

%%% .
 5.3 Internal Model

Discrete devices can be modeled using approximations for heat spread-

ing effects at each level of construction. These models are particularly
useful for devices of new design when a ball park prediction of ejC is
required. Computer programs that aodel the internal thermal characteris-
tics of these discrete devices were developed for square, rectangular, and
circular surfaces. These models are dependent on critical assumptions, and
are operable over specific parameters, in order for them to be useful to
the average device user who is not familiar with the internal construction
of the device. The assumptions and parameters incorporated in these pro-
grams are:

1 50-percent thermal dissipation area (100 percent for circular

surfaces)

2 100-percent attachment coverage

3 Specified material conductivity

4 Surface shape

5 Spreading angle at each level of construction (variable input)

6 Thickness variability as chip dimensions vary at chip level.

The impact of the other thermal parameters such as cooling, internal
radiation, and secondary flow paths are discussed in the external model
(Section 5.4) since the thermal resistance calculated by the internal model
is independent of these parameters.

"V heThe applicability of these programs is dependent upon the user knowing
q the material of each level of the device; the material conductivity (sec-
tins 5.4, Table 30); and the spreading angle (appendix 5.4). The programs
are written so that the computer will cue the user when specific inputs are
required. For example, at the chip level, the program asks for the chip
material, the material conductivity, and the desired spreading angle. At
"the attachment level, the program first provides the user with a list of
attachment materials and then asks for the choice to be entered. The
material conductivity and the spreading angle are then requested. The in-
ternal heat spreading angle has a significant impact on thermal resistance,
from the chip junction to the case bottom (9jG)• The internal model
employs the spreading angle in the computation of the thermal resistance at
each level of device construction by allowing the model user to specify the
angle desired. There are many variables, such as attachment voids, chip
size, dissipation area, material type, and thickness, all which affect the
heat spreading function. This creates difficulty in specifying one angle
th.t typically represents the heat spread. Based on analysis (Appendix
5.4), it was concluded that the correct spreading angle could not be deter-
mined. The spreading function is an important factor that needs considera-
tion when developing models. However, further investigation was not possi-
ble, due to program limitations. All the programs follow the same user-
friendly format.

59

*" .. , ,,.. • ... .. . .. ,. .. -:->V.... . .. .,, -.. ... f , k,

- .-
 The programs, which are presented in appendix 5, allow for the modifi-
cation of these terms and others so that more specific cases can be insti-
tuted. They are written in the BASIC programming language and are well
documented with comments and section headings so that modifications can be
"accomplished.

The programs that model the previously mentioned surface types con-
sider the heat flow at each level of construction beginning with the chip
(device) itself. The thermal dissipation area is accounted for at this
level, with the thermal resistance being computed for these dimensions.
The next level dimensions are calculated, based on the thickness of the
device and the desired spreading angle. The calculation is rerresented by
the following equation for the square and rectangular surfaces. The next
WV). level dimension calcula~ion for circular devices is discussed in the
respective section.

L2 L+2*T*TAN(A)

where

L2 new length
L present length
T = thickness of present level
"A= spreading angle.

Units are in mils.

It should be noted that if the spread exceeds the dimensions of that

level of construction, then the point at which the spread touches the edge
becomes the dimensions for the next level.

-. ... The programs for the other levels follow the same format, with the
variable values changing in order to account for the varying materials,
spreading, and dimensions. The attachment materials and the intermediate
materials have both been limited to the ones most widely used in industry.
However, this can be modified to incorporate any material used. The
1.1q'" attachment materials assumed are eutectics, silver, gold, and nonconduc-
tive epoxies. The [Link] materials assumed are a gold header, beryl-
lia, alumina, molytau, and nickeltab.

The result of the program's computation is a table comprised of ther-

mal resistance values for a variety of dimensions. By adding the thermal
resistance values for each level of construction, a thermal resistance
value from the junction to the case can be calculated. The resulting
tables for each device level of the three different surface types are pre-
" sented in their respective sections which immediately follow. The tables
have all been generated assuming a 45-degree spreading angle. For a more
detailed analysis of the spreading angle, see appendix 5.4.

5.3.1 Square Model

"LSI and VLSI devices are frequently square or nearly square. Since
the package features of these devices may also have a square format, such
as hermetic chip carriers, a square model is attractive. The programs
60
%: .
6 Is.
that model the square devices employ the following equation for the compu-
tation of the thermal resistance at each level of the device construction:

Rl - T/(K*W*(W+2*T*TAN(A)))

where

RI = thermal rpsistance (*C per watt)

T - thickness (mils)
W - wiath (mils)
K -imaterial conductivity (watts per inch *C)
A = spreading angle (degrees).

The value for K must be divided by 1000 in order to have agreement among
measurement units.

Calculations have been performed for typical materials in the primary

heat flow path using various spreading angles. As expected, the thermal
resistance (Ojc) increases as the spreading angle decreases, with the
greatest impact occurring at the outermost packaging level. An increased
area is inversely proportional to the calculated thermal resistance.
Similar comparisons can also be made to estimate the effects of chip hot
spots and voids in the chip attachment which concentrate the thermal flow.

A sample calculation shown in Table 14 illustrates the use of the

tables generated by the square model. This particular example has four
levels of construction and assumes a 45-degree spread. Using Tables 15
through 18, the values for the thermal resistance and the next level dimen-
sions can be obtained for all the levels of construction. The dimensions
used to enter the tables subsequent to the device level are calculated in
the previous level's table and carried over. Interpolation may be required.
The thermal resistance values for each level are then summed and multiplied
by the power dissipated to obtain the junction to case temperature change.
TABLE 14. SQUARE DEVICE SAMPLE CALCULATION
0uicv: Sviere $iULr•e, Meader: ft ,ial| CGoWd
atorial, silicon Coo lctivity: ?,54 Wttl per isc
Coo•Iduiity. 2.13 *Ott - d*4eg# [Link]$ro"
Per [Link]
coodtra, Tbiktwoozz 0.1 sit*

ittv-
Atrfti :
'hW ciiilyz
,
toto•tc
4.5
h
P
iio
ei. Ot• lgl: &|unift
ctivilt, 0.418 votle pe.r lZ ch

T%#_A N 0'MOtootq1•• UtMlt(o) T dt

a W.t COW$ 113. a 30.4

WO
I (to
4#.Wqee
watt)
tow

61

*.;~~~'..:.~~ . *.-* * '0I N'

 TABLE 15. SQUARE SURFACE DEVICE - 50% DISSIPATION

MATERIAL: SILICON
CONDUCTIVITY: 2.13 (W/IN.*C)
SPREADING ANGLE: 45 DEGREES

LENGTH * WIDTH THERMAL RESISTANCE Linc * Winc

2 X 2 148.51285 2.00 X 2.00

4 X 4 67.17533 4.00 X 4.00
6 X 6 40.88483 6.00 X 6.00
8 X 8 28.20787 8.00 X 8.00
10 X 10 23.02732 10.00 X 10.00
15 X 15 13.31180 15.00 X 15.00
20 X 20 8.81288 20.00 X 20.00
25 X 25 7.64834 25.00 X 25.00
30 X 30 5.87526 30.00 X 30.00
35 X 35 4.67073 35.00 X 35.00
40 X 40 3.81055 40.00 X 40.00
45 X 45 3.17263 45.00 X 45.00
50 X 50 3.04843 50.00 X 50.00
60 X 60 2.29236 60.00 X 60.00
70 X 70 1.79013 70.00 X 70.00
80 X 80 1.43842 80.00 X 80.00
90 X 90 1.18205 90.00 X 90.00
100 X 100 1.12024 100.00 X 100.00
110 X 110 0.95512 110.00 X 110.00
120 X 120 0.82130 120.00 X 120.00
130 X 130 0.71884 127.91 X 127.91
140 X 140 0.63253 134.98 X 134.98
150 X 150 0.5609$ 142.05 X 142.05
160 X 160 0.50098 149.12 X 149.12
170 X 17Q 0.45017 156.19 X 156.19
18c) X 180 0.40675 163.26 X 163.26
,190 x 190 0.36935 170.3 17X
0.33
S200 X 200 0.33689 177.40 X 177.40
250 X 250 0.22473 212.75 X 212.75
300 X 300 0.16059 248.10 X 248.10
350 X 350 0.12049 283.45 X 283.45
400 X 400 0.09373 a 13.16K 318.10
450 X 450 0.07500 354.15 X 354.15
v5O X 500 0.0613s 389.50 X 389. 50

td

62
2) TABLE 16. SQUARE SURFACE ATTACHMENT

MATERI:AL: EUTECTIC
CONDUCTIVITY" 4.5 (W/IN.*C)
SPREADING ANGLE: 45 (DEGREF':)

LENGTH * WIDTH THr-7%-,AL. RESISTANCE Linc * Winc

- - - - - - - - - - - - - - -

X 2 18.51852 2.00 X 2.00

4 X 4 5.55556 4.00 X 4.00
6 X 6 2.64551 6.00 X 6.00
8 X :8 1. 5432; 8.00 X 8.00
10 X 10 1.01010 10.00 X 10.00
.1.5 X 15 0.46297 15.00 X 15.00
20 x 20 0. 26455 20.00 X 20.00
25 X 25 0.17094 25.00 X 25.00
:'30 X 30 0.11948 30.00 X 30.00
S35 X 35) 0.0881 on35.00 X 35.00
40 X 4(0' 0,06775 40.00 X 40.00
45 X 45 0.05368 45.00 X 45.00
50 X 50 0.04357 50.00 X 50.00
60 X 60 0. 03036 60.00 X 60.00
70 X 70 0.02236 70.00 X 70.00
,0 K 30 O.01715 80.00 X 80. 00
-'.) X 90 0.01357 90.00 X 90.00
:00 X !OO 0.01100 100.00 X 100.00
"ItoIxO 0.00910 110.00 x 110.00
.120 X 1.20 0100765 120.00 X 120.00
'Ii tc0 X 130 0.00652 131.00 X 131.00
,40 x ;0 0. 00563 141.00 X 14J.00
x 150 0.00491 151.00 X 151.00
K .A,
1160 0.004 . 1 161.00 X 161.00
V * 70
,-.,,)X
x 170
t(-: 0.00'341 '
C,..003ý8•" 171.00
181.0O0 X 171.00
X 181.O00
%i:O4E..6 181.00 x 191.00

.x . .0, 0.0"276 201.00 ?01100

2
-SO , 0.,177 751 . 00 X 251.O0
0 x -rý-O
300 0.001 23 301.00 X 301.00
"0.X350 ,00090 3Vi1.00 X 351.00
N.j X 46(s 0.06q 401.00 Y 4l1.00
ti J, ., 0.00055 451.00 X 451.00
0' o 00044 501.00 X 501. O0

•'.4.'
1,'

4' 63

,1'
 TABLE 17. SQUARE SURFACE - INTERMEDIATE MATERIAL

MATERIAL: GOLD HEADER

CO-NDUC:TIVITY: 7.54 (W/IN.*C)
SPRE:DING ANGLE: 45 (DEGREES)

LEN(,TH * WIDTH THERMAL RESISTANCE Linc * Winc

2 X 2 5.52609 2.40 X 2.40

A X 4 1.50712 4.40 X 4.40
6 X 6 0.69077 6.40 X 6.40
- X 8 0.39472 8.40 X 8.40
10 X 10 0.25505 10.40 X 10.40
15 X 15 0.11483 15.40 X 15.40
20 X 20 0.06501 20.40 X 20.40
25 X 25 0.04177 25.40 X 25.40
30 X 30 0.02908 30.40 X 30.40
35 X 35 0.02141 35.40 X 35.40
40 X 40 0.01641 40.40 X 40.40
45 X 45 0.01298 45.40 X 45.40
50 X 50 0.01053 50.40 X 50.40
60 X 60 0.00732 60.40 X 60.40
70) X 70 0.00538 70.40 X 70.40
80 X 80 0.00412 80.40 X 80.40
90 X 90 0.00326 90.40 X 90.40
100 X 100 0.00264 100.40 X 100.40
110 X 110 0.00218 110.40 X 110.40
120 X 120 0.00184 120.40 X 120.40
130 X 130 0.00156 130.40 X 130.40
140 X 140 0.00135 140.40 X 140.40
150 X 150 0.00118 150.40 X 150.40
160 X 160 0.00103 160.40 X 160.40
170 X 170 0.00092 170.40 X 170.40
ISO X 180 0.00082 180.40 X 180.40
19 X 190 0.00073 190.40 X 190.40
-• x 200 0.00066 2,00.40 X 200.40
2150 x 2-50 0. 000 ,2 25,0.40 X 2150. 40
io0 X 300 0. 00029 300.40 X 300.40
50X 350 O. 00022 350.40 X 350.40
S400 X 400 0.00017 400.40 X 400.40
450 X 450 0.00013 450.40 X 450.40
500 x 500 0.00011 500.40 X 500.40

64
9.l
 TABLE 18. 40-PIN CERAMIC SIDE BRAZED PACKAGE

MATERIAL: ALUMINA
CONDUCTIVITY: .478 (W/IN.*C)
SPREADING ANGLE: 45 (DEGREES)
ATTACHMENT MATERIAL: EUTECTIC
INTERMEDIATE MATERIAL: GOLD HEADER

LENGTH * WIDIH THERMAL RESISTANCE Linc * Winc

2 X 2 513.14441 106.00 X 106.00

4 X 4 251.82081 108.00 X 108.00
6 X 6 164.82819 110.00 X 110.00
8 X 8 121.41362 112.00 X 112.00
10 X 10 94.91708 108.00 X 108.00
15 X 15 60.47814 113.00 X 113.00
20 X 20 42.96175 112.00 X 112.00
25 X 25 32.90063 117.00 X 117.00
30 X 30 26.29352 122.00 X 122.00
35 X 35 21.65001 127.00 X 127.00
40 X 40 17.71495 124.00 X 124.00
45 X 45 15.13628 129.00 X 129.00
50 X 50 13.11434 134.00 X 134.00
60 X 60 10.16969 144.00 X 144.00
70 X 70 8.15084 154.00 X 154.00
80 X 80 6.53766 160.00 X 160.00
90 X 90 5.46942 170.00 X 170.00
100 X 100 4.64901 180.00 X 180.00
110 X 110 4.00392 190.00 X 190.00
120 X 120 3.48675 200.00 X 200.00
130 X 130 3.06528 210.00 X 210.00
140 X 140 2.71695 220.00 X 220.00
150 X 150 2.42557 230.00 X 230.00
160 X 160 2.1/922 240.00 X 240.00
170 X 170 1.96900 250.00 X 250.00
180 180
% 1.78808 260.00 X 260.00
190 x 190 1.63123 270.00 X 270.00
200 X 200 1.49433 280.00 x 280.00
250 X 250 1.01433 330.00 X 330.00
300 X 300 0.73406 380.00 X 380.00
350 X 350 0.55603 430.00 X 430.00
400 X 400 0.43585 480.00 X 430.000
450 X 450 0.35087 530. 00 X 530.00
500 X 500 0.28856 580.00 x 5*0.)00

65
 5.3.2 Rectangular Model

The rectangular model is particularly applicable to chips which have

concentrated power dissipation, such as output drivers along one side in a
rectangular region, as well as chips with high aspect ratios. The follow-
ing equation is used to model the thermal resistance of devices of this
type:

R= 1 In 2 T TAN(A) +W
(L-W) (2 9 AN() .iK 2 T TAN(A) + L

where

R = thermal resistance (*C per watt)

L =length (mils)
W = width (mils)
K - material conductivity (watts per inch 'C)
T = thickness (mils)
A - spreading angle (degrees).

The value for K must be divided by 1000 in order to have agreement

among the units of measurement.

The rectangular model is very similar to the square model, except

square dimensions cannot be modeled by the rectangular programs. If square
dimensions were applied to the thermal resistance equation above, the result
would be division by zero. However, using the concept of iimits, dimen-
sions up to the perfect square can be modeled correctly by the rectangular
programs.

A sample calculation that employs Tables 19 through 22 is illustrated

-. in Table 23. The steps involved in this calculation are identical to those
in the square model. It should be noted that the shape or behavior of the
"* chip determines which model to use and w'hich tables to employ. Using val-
ues from both the square and rectangular tables interchangeably can result
"in erroneous answers.
TABLE 19. RECTANGULAR SURFACE DEVICE .- 50 DISSIPATION

MtATERIAL.: $ILICON
CONDUCTIVITY: 2. Lt (Wi/N.* C} ,
SPREADING ANGLE: 45 (DEGREES)

.ENi,4TH 'IDtH T
THERMAL RESISTANCE Lin ,U ln,:
- - - --- - - ------------ ----
9.3- 433,15 1 2. -O X 4, O,
">):6 75..1•" , 2.O-C
.... q ..' .o 5. 91 54. 4.0O0
0 X 7% O00
.00
S43. 046•14 4.O .
• I0Is
X ?' 21117 4i. 00 X [Link].)
X I3) 23.!85 1 4.00 X 1 00

66

-•'qk

,., •,. ". , . .* e,*-.* .. . .... .... t.... ,, . .,. :. ' p,•.-'.A .. .*'.,, *.*
," o ,,, .r -. .- ?• .,.. ,•.. ,.,•• . , %.-
in •
•° .. •
 TABLE 19. (CONTINUED)
6 X 8 33.90086 6.00 X 8.00
6 X 10 29.07790 6.00 X 10.00
6 X 12 25.51632 6.00 X 12.00
6 X 14 22.76464 6.00 X 14.00
6 X 16 20.56767 6.00 X 16.00
6 X 18 18.76930 6.00 X 18.00
8 X 10 24.25487 8.00 X 10.00
8 X 12 21.32400 8.00 X 12.00
8 X 14 19.05248 8.00 X 14.00
8 X 16 17.23435 8.00 X 16.00
8 X 18 15.74303 8.00 X 18.00
8 X 20 14.49566 8.00 X 20.00
8 X 22 13.43587 8.00 X 22.00
8 X 24 12.52351 8.00 X 24.00
10 X 15 17.45786 10.00 X 15.00
10 X 20 14.13854 10.00 X 20.00
10 X 25 11.91016 10.00 X 25.00
i0 X 30 10.30220 10.00 X 30.00
15 X 20 10.81927 15.00 X 20.00
15 X 25 9.13631 15.00 X 25.00
15 X 30 7.91702 15.00 X 30.00
15 X 35 6.99019 15.00 X 35.00
15 X 40 6.26062 15.00 X 40.00
15 X 45 5.67069 15.00 X 45.00
20 X 25 7.45344 20.00 X 25.00
20 X 30 6.46590 20.00 X 30.00
20 X 35 5.71385 20.00 X 35.00
20 X 40 5.12094 20.00 X 40.00
20 X 45 4.64097 20.00 X 45.00
20 X 50 4.24416 20.00 X 50.00
20 X b5 3.91045 20.00 X 54.89
20 X 60 3.62578 20.00 X 58.42
25 X 30 6.70063 25.00 X 30.00
25 X 35 5.96889 25.00 X 35.00
25 X 40 5.38526 25.00 X 40.00
25 X 45 4.90808 25.00 X 45.00
25 X 50 4.51019 25.00 X 50.00
25 55
, 4.17302 25.00 X 55.00
25 X 60 3.88349 25.00 X 60.00
25 Y 65 3.63204 25.00 X 65.00
25 X 70 3.41155 25.00 X 70.00
-5 X 75 3.21656 25.00 X 75.00
30 K 35 5.23/10 30.00 x 35.00
30
30 X 40 4.72759 30.00 X 40.00
x 45 4.31059 30.00 X 45.00
30 x 50 3.96260 30.00 X 50.00
30 x 55 3.66751 30.00 x 55.00
30 X 60 413.4139 30.00 X 60.00
310 X 65 3.19367 30.00 X 65.00
30 X 70 3.00041 30.00 X 70.00
30 X 75 2.82945 30.00 x 75.00

67

. M VS
 TABLE 19. (CONTINUED)
B30 X 80 2.67709 30.00 X 80.00
:30 X 85 2.54045 30.00 X 84.10
30 X 90 2.41719 30.00 X 87.63
35 X 40 4.21806 35.00 X 40.00
35 X 15 3.84734 35.00 X 45.00
35 X 50 3.53776 35.00 X 50.00
35 X 55 3.27510 35.00 X 55.00
35 X 60 3.04934 35.00 X 60.00
35 X 65 2.85310 35.00 X 65.00
,35 X /0 2.68088 35.00 X 70.00
35 X 75 2.52848 35.00 X 75.00
35 X 80 2.39264 35.00 X 80.00
. 35 X 85 2.27078 35.00 X 84.10
35 X 90 2.16083 35.00 X 87.6,ý
35 X 95 2.06110 35.00 X 91.17
35 X 100 1.97025 35.00 X 94.70
:35 X 105 1.88711 35.00 X 98.24
40 X 45 3.47660 40.00 X 45.00
40 X 50 3.19759 40.00 X 50.00
40 X 55 2.96080 40.00 X 55.00
40 X 60 2.75716 40.00 X 60.00
I0 X 65 2.58011 40.00 X 65.00
40 X 70 2.42468 40.00 X 70.00
40 X 75 2.28711 40.00 X 75.00
10 X 80 2.16446 40.00 X 80.00
40 X 85 2.05442 40.00 X 84.10
,0 X 90 1.95511 40.00 X 87.63
•0
It X 95 1.86502 40.00 X 91.17
.0 x 100 1.78293 40.00 X 94.70
X 105 1.70780 40.00 X 98.24
X 110 1.63879 40.00 X 101.77
4C,40 X 115 1.57516 40.00 X 105.31
'10 X 120 1.51631 40.00 X 108.84
45 x 50 2.91856 45.00 X 50.00
"4-i45 X 55 2.70289 45.00 X 55.00
45 X 60 2.51735 45.00 X 60.00
X 65
X5 2.35598 15.00 X 65.00
45 x 70 ".2130 45.00 X 70.00
x5
K75 2. 0$:7 45.00 X 75.00
X5 8' 1.97703
1 45.00 X 80.00
, 45 x S5 I.876,5 45.00 X $4.10
-. 5 "-,0 1.18605 45.00 X 87.63
At- 05 1.70387 45.00 X 91.17
1-5 X100 1.62896 45.00 X 94.70
K I05 1.56040 45.00 X S.2A
4,, K 10 1.497-11 45.00 X 101.77
"•s x i51.4V 3 45.00 x 105,31
45 1.38562 45.00 X 108.84
C ""A 45.00 X 112.3$
45
t 130 1.2894.1 45.00 X 115.91
t 45 x 1I5 1.24620 45.00 K 119.4.

68

'1* e ~ ' * ~ , . - . . * ~ %. * < . .

"' ,' " '-" ' " %' ' " ' * ' • ' . • * ' ' ° , ° , -" • ' . , ** • -• ' * .' *' C• "* ' C .' . ' .* ." " C " " ,, , ,, ,• *,*, , '*",-*'
 TABLE 19. (CONTINUED)
50 X 60 2.64284 50.00 X 60.00
50 X 70 2.33412 50.00 X 70.00
50 X 80 2.09091 50.00 X 80.00
50 X 90 1.89416 50.00 X 90.00
50 X 100 1.73158 50.00 X 100.00
50 X 110 1.59492 50.00 X 107.77
50 X 120 1.47840 50.00 X 114.84
50 X 130 1.37785 50.00 X 121.91
50 X 140 1.29018 50.00 X 128.98
50 X 150 1.21305 50.00 X 136.05
60 X 70 2.02544 60.00 X 70.00
60 X 80 1.81497 60.00 X 80.00
60 X 90 1.64460 60.00 X 90.00
60 X 100 1.50377 60.00 X 100.00
60 X 110 1.38534 60.00 X 107.77
60 X 120 1.28433 60.00 X 114.84
60 X 130 1.19714 60.00 X 121.91
60 X 140 1.12110 60.00 X 128.98
60 X 150 1.05418 60.00 X 136.05
60 X 160 0.99485 60.00 X 143.12
60 . 170 0.94186 60.00 X 150.1?
60 X iKX 0.89425 60.00 X 157.26
70 X 80 1.&)452 70.00 X 80.00
70 X 90 1.45419 70.00 X 90.00
70 X 100 1.32989 70.00 X 100.00
70 X 110 i.22532 70.00 X 107.77
70 X 120 1.13612 70.00 X 114.84
7v X 130 1.05909 70.00 X 121.91
70 X 140 0.99192 70.00 X 128.98
70 X 150 9:.3279 70.00 X 136.05
70 X 160 0.8803- 70.00 X 143.12
"4% X 170 0.83350 70.00 X 150.19
70 X 180 0.79141 70.00 K'7.2*
X
7,' X 190 0.75338 70.00 X 164.33
70 X 200 0.71885 70.00 X 171.40
70 X 210 0.68735 70.00 X 178.47
* 90
x 1.30388 80.00 X 90.00
K 100 1.19258 80.00 X lov.o0
80 X 110 1.09892 X 107.77
x0.00
80 x 120 1.01902 80.00 X 114.84
80 X 130 '..95001 80.00 X 121.91
so0 140 0.88981 80.00 X 128.98
80
80 x 0.368 80.00 X
:60 0.78982 80.-0 X 136.05
143.12
80 X 170 0.74783 X0.00 X 150.19
80 x 1S0 9.71010 80.00 X 157.26
80
S - 0.6760( 80.00 X 164.33
80 x 0.64504 80.00 X 171.40
80 x 210 0.61680 80.00 X 178.47
S0 X 220 0.59093 80.00 X 185.54
s0 x Ž30 0.56715 80.00 X 192.61
80 X 240 Q.54522 80.00 X 199.68

69
 TABLE 19. (CONTINUED)
90 X 100 1.08127 90.00 X 100.00
90 X 110 0.99645 90.00 X 107.77
90 X 120 0.92407 90,00 X 114.84
90 X 130 0.86155 90.00 X 121.91
90 X 140 0.80700 90.00 X 128.98
vI 90 X 150 0.75899 90.00 X 136.05
90 X 160 0.71638 90.00 X 143.12
90 X 170 0.6"7833 90.00 X 150.19
90 X 180 0.64412 90.00 X 157.26
90 X 190 0.[Link] 90.00 X 164.33
90 X 200 0.58515 90.00 X 171.40
90 X 210 0.55955 90.00 X 178.47
90 X 220 0.:53609 90.00 X 185.54
90 X 230 0.51453 90.00 X 192.61
90 X 240 0.49464 90.00 X 199.68
90 X 250 0.47624 90.00 X 206.75
90 X 260 0.45915 90.00 X 213.82
90 X 2i0 0.44325 90. 00 X 220.89
100 X 110 1.03435 100.00 <x 110.00
100 X 120 0.96082 100.00 X 120.00
100 X 130 0.89713 100.00 x 127.91
100 X 140 0.84142 100.00 X 134.98
100 X 150 0.79227 100.00 X 142.05
110 X 120 0.88729 110.00 X 120.00
110 X 130 0.82853 110.0,0 X 127.91
110 X 140 0.77711 liO.00 X 134.98
110 X 150 0.73176 110.00 X 142.05
110 X 160 0.69142 i10.00 X 149.12
120 X 130 0.76975 12.00 x 27.91
121 X 140 0.72202 120.00 X 134.98
120 X 160 0. 67990 120.00 X 142.05
120 X 160 0.64246 120.00 X 149.12
120 X 170 0.60895 120.00 X 156.19
'. 120 X 180 0.57877 120.00 X 163.26
130 X 140 0.67430 127.91 X I,.-.
X 150
S0.63498 1-7. 91 X 142.05
130 x 160 '0.60003 121.91 X 149.12
1,30 x 170 0.75685 127.91 x 156.19
1,34 180 0.54058 127.91 X 163.26
13 o X 190 0.51508 127.91 X 170, 3
414
x 150 K1204.96 C3.j
140 x 160 0.56290 134.,,
0 X1 12.
, 10
Q 1 /0 u.56317
5 134 .93
? 156.19
140 )k It 0.50715 134.9,0- x -3.
t
14') X 190 0. '1832 1344.98. X 170. 33
14' 0')0.Z 4614*03.~ 1/4
140 X 270 0.441462 ll.93 X 1,4. 4 7
•,"150 .I y
K 1*0 7,V5015 142.05 K 149.12
1', 0. 502:51 142.0'• K 156. 1"•
1150 x775 180 142.05 x 0 -3
1,0 K l O. 4551.3 142.05 K 170.3;3

( . • 70
 TABLE 19. (CONTINUED)
150 X 200 0.43465 142.05 X 177.40
150 X 210 0.41595 142.05 X 104.47
150
160, X 220
0(I0 0.39879
0.474,90 [Link] X 191.54
149.12 X 156•.19
160 X 180 0.45140 149.12 X 163.26
160 X 190 0.43013 149.12 X 170.33
160 X 200 0.41079 149.12 X 177.40
160 X 210 0.39311 149.12 X 184.47
160 X 220, 0.37690 149.12 X 191.54
160 X 230 0.36198 147,.12 X 198.61
160 X 240 0.34820 149.12 X 205.68
170 X 180 0.42794 156.19 X 163.21.
170 X 190 0.40777 156.19 X 170.33
170 X 200 0.38943 156.19 X 177.49
170 X 210 0.37267 156.19 X 184.47
170 X 220 0.35730 156.19 X 191.54
170 X 230 0.34316 156.19 X 18.61
170 X 240 0.33009 156.19 X 205.68
170 X 250 0.31799 156.19 X 212.75
180 X 190 0.38761 163.26 X 170.33
180 X 200 0.37017 163.26 X 177.40
180 X 210 0.35426 163.26 X 184.47
180 X 220 0.339L. 163.26 X 191.54
180 X 230 0.32621 163.26 X 198.61
180 X 210 0.31379 i&3.26 X 205. 6
1803 X 250 0.30229 163.26 X 212.75
180 X 260 0.29160 163.26 X 219."*2
180 X 270 0.28195 163.26 X 226.89
:90 X 200 0.35-79 170.33 X 177.4')
190 X 210 0.33758 170.33 X 184.47
190 x 220 0.32367 .170.33 X 1141.54
i' 0 X 230 0.31086 10.33 aX 198.61
190 x 240 0.29903 170.33 X 2,05.6
"190 X 250 0.28808 !N.33 A 212.75
i,9O x 260 0.27739 170.33 X 219.622
"1I710 X 2`70IL1.26841 170. 3131 : 2261.89
190 x 2*0 0.25955 17033 aX 233.96
""200 250 0.2751 I 177.40 X 212.75-
200 K 300 ,.2'325 17 7.40 X 24*.10
250 A 300 0. Ž1Ž.75
2.992 X 24:.I0
250 x 350 0.16454 212.75 X -8 1. 4'45
300 y 3'50 "4,.10 $
'4.:13910 23.4
•
30. 400.
x 0. 12.2481. 248. 10 X Ži•$.$O
300 y 45) 0. L0'47i 243. 10 X 354.15
350 X '100 0,,' 10628 28•3.4•5 K .318.Z('
4jO0.090 .33.45 X .Ž54. V5
Y50 M )00 0.0599 283. 45 x 3Ž9.50
46's) x 450 0.3 .S. 31.80 '554. 15
I
400 X .W;:' O.ons5 :I1.30 x 3&9.%'
400 A $50 0.06424 318.A0 X 4.A4,*5
00
Ak. 60o 0.0ft-7 0 Ž18.80 X 460.20P

71

""'
 40X C)TABLE 19. (CONTINUED)
.450 X 500 0. 078 :354. 15 X 39.. 50
"450 X 550 0.(C)6194 354.15 X 424. 85
450 X 6.00 0. 0569- .:354. 15 X 460. 20
50 X 650
. '). 005276 :54.15 X 495.55
5(0 X 550 0. 05604 *.389'). 50 X 424.85

TABLE 20. RECTANGULAR SURFACE ATTACHIENT - ABLEBOND 36-2 EPOXY

MATERIAL: EPOXY
[Link] CETIV -1Y. 5. 10000E--02 (W/IN.*C)
SfRE'AD I NG ,ANGLE: 45 (DEGREES)

[Link] * WID'TH THERMAL RESISTANC.E Lin:c Win'c

2 X 4 1987. 57'"227 2. 00 X 4.00

2 X 6 1440. ,5479 2.00 X e. 00
I6 893": 42 4. 00 X 6. 00
4 X 8 7C.'. "6.6 4. 00 X 8.. 00
4 X 10 582. :u2 74 4. 00 X 10. (00
4 X 12 496.89356 4. 00 X 12.. 00
6 X !516. 471 6.00 X 8.000
X 10 427. 33716 6. 00 X 1u.*100
6. X 12 . , 1,.1359 6. 00 X 12. 00
6 X 14 31:8. 0),,::8' 1 6. 0 X i 4. 00
6 X 16 2 8 2 . 041 0.8,: 6. 00 X 16. C,0
6,X 18 .. 08
3.9,5 6. 00 X 18. 00
I.:" X 1.0
(2:0270 8 00 X 1 0 .0
:, X 12 " 684:33
,. ,3 00• X 12. 00
8 X 14 251.88123 .00 X1.0
" 16 :• ,.2 .4:351 8. 00 X 16.00
X 1.,8 -'00. 77891 8:. 00 X 1. 00
8 X .C2 182. :30698 00C X 2C) 00
: X 166, 95457 8.*00 X -.' 0
2 SX 15:. 99201 . C4. X 00
1.0 X 15 19-. 2.113 10. 00 X 151 ,'0.
10 X - 1 1 12875, 1. OC X 2' 00fQ
10Q 25 .
122.91018 10 . 00 X 2.0':3
to X :3C) 0C". 5:3 20 1C). 00 X f0.
0
1 X 2C) 00
1..5 X 20 06 01372 15.00
15 X :25 86. 24472 1(5..0 X 2'2. 00J
". X 3 72. 667. 15.00 X 30.00
:-967)
.5 X 3 ,:, 16 4 15. (0 X .5 00
15 X 4) 5. .32501 15. C"0O X 40 00
5 X< 45 4'. 615. 0 X
`) X '. 47504 20. C)0 X .00
' X ... 6'2 Q ...8 71 20. (W0) X :=:]) .00
"':','[' '.'•
() X ,..,..":'
F-x 48 .4,., -:.,.''-
:1 2C).
000O0C..,."X =.
"..0 :-5 81C :35.C:(
X 1
10 42... 5.2 7 20. 0 X 40.C0
. :() X 45 t... 6
". 1 C): 20. 00 X 4,5. k0

72

-,,'"". .
 TABLE 20. (CONTINUED)
20 X 50 34.43162 20.00 X 50.00
20 X 55 31.40551 20.00 X 55.16
20 X 60 28.86845 20.00 X 62.23
2b X 30 45.60268 25.00 X 30.00
25 X 35 39.41858 25.00 X 35.00
25 X 40 34.71226 25.00 X 40.00
25 X 45 31.01099 25.00 X 45.00
25 X 50 28.02312 25.00 X 50.00
25 X 55 25.56090 25.00 X 55.00
25 X 60 23.49645 25.00 X 60.00
25 X 65 21.74045 25.00 X 65.00
25 X 70 20.22895 25.00 X 70.00
25 X 75 18.91378 25.00 X 75.00
30 X 35 33.23519 30.00 X 35.00
30 X 40 29.26775 30.00 X 40.00
30 X 45 26.14769 30.00 X 45.00
30 X 50 23. 62925 30. 00 X 50.00
30 X 55 21.55268 30.00 X 55.00
30 X 60 19.81197 30.00 X 60.00
30 X 65 18.33175 30.00 X 65.00
30 X 70 17. 05732 30.00 X 70.00
30 X 75 15.'4860 30.00 X 75.00
30 X 80 14.97512 30.00 X 80.00
30 X 85 14.11381 30.00 X 86.28
W X 90 13. 34618 30.00 X 93.35
35 X 40 25.30200 35.00 X 40.00
35 X 45 22.60357 35.00 X 45.00
35 X 50 20.42669 35.00 X 50.00
\ 35 X 55 18.63230 35.00 X 55.00
:35 X 60 17.12779 35.00 X 60.00
3f X 65 15.84805 35.00 X 65.00
35 X 70 14.74621 35.00 X 70.00
"25 X 75 13.78779 35.00 X 75.00
:35 X 8 12.94625 35.00 X 80.00
35 X 85 12.20177 35.00 X 86.28
35 X 90 11.53818 35.00 X 93.35
35 X 95 10.94301 35.00 X 99.00
:35 X 100 10.40616 35.00 X 104.00
35 X t05 9.91967 35.00 X 109.00
10 X i.5 I.5.90781 40.00 X 45.00
40 X 50 17.98995 40.00 X 50.00
A0 X 55 16.40941 40.00 X 55.00
40 X 60 15.08420 40.00 X 60.00
A0 X 65 13.95751 40.00 X 65.00
10 X 70 12.98720 40.00 X 70.00
40 X 75 12.14314 40.00 X 75.00
40 X 11. 40204 40.00 X 80.00
40 x 85 10.746,33 40. 00 X 86.28
40 X 90 10. 16190 40.00 X 93.35
GC.. X 95 9.63770 10. 00 X 99.00
40 X I Q0 9. 16496 40.00 X 104.00

73
 TABLE 20. (CONTINUED)
10 X 105 8.73656 40.00 X 109.00
40 X 110 8.34621 40.00 X 114.00
10 X 115 7.98937 40.00 X 119.00
40 X 120 7.66186 40.00 X 124.00
45 X 50 16.07307 45.00 X 50.00
45 X 55 14.66086 45.00 X 55.00
45 X 60 13.47674 45.00 X 60.00
45 X 65 12.47029 45.00 X 65.00
'15 X 70 11.60305 45.00 X 70.00
45 X 75 10.84917 45.00 X 75.00
45 X 80 10.18705 45.00 X 80.00
45 X 85 9.60119 45.00 X 86.28
45 X 90 9.07909 45.00 X 93.35
45 X 95 8.61078 45.00 X 99.00
45 X 100 8.18848 45.00 X 104.00
45 X 105 7.80569 45.00 X 109.00
45 X 110 7.45705 45.00 X 114.00
45 X 115 7.13822 45.00 X 119.00
45 X 120 6.84549 45.00 X 124.00
45 X 125 6.57590 45.00 X 129.00
45 X 130 6.32674 45.00 X 134.00
45 X 135 6.09574 45.00 X 139.00
50 X 60 12.17997 50.00 X 60.00
50 X 70 10.48584 50.00 X 70.00
50 X 80 9.20624 50.00 X $0.00
50 X 90 8.20500 50.00 X 90.00
50 X 100 7.140007 50.00 X 100.00
50 X 110 6.73903 50.00 X 113.15
50 X 120 6.18649 50.00 X 124.00
50 X 130 5.71766 50.00 X 134.00
50 X 140 5.31489 50.00 X 144.00
50 X 150 4.96515 50.00 X 154.00
60 X 70 8.79319 60.00 X 70.00
60 X 80 7.71982 60.00 X 80.00
60 X 90 6.88041 60.00 X 90.00
60 X 100 6.20536 60.00 X 100.00
60 X I10 5.65109 60.00 X 113.15
60 X 120 5.18769 60.00 X 124.00
60 X 130 4.79459 60.00 X 134.00
60 X 140 4.45689 6o.00 X 144.00
60 X 150 4.16356 60.00 X 154.00
60 X 160 3.90647 60.00 X 164.00
6C' X 170 3.67934 60.00 X 174.00
60 X 180 3.47712 60.00 X 184.00
70 X 80 6.64699 70.00 X 80.00
70 X 90 5. 92417 70.00 X 90.00
70 X 100 5. 34297 70.00 X 100.00
70 X 110 4.86575 70.00 X 113.15
70 X 120 4.46680 70.00 X 124.00
70 X 130 4.1283t 70.00 X 134.00
70 X 140 3.83744 70.00 X 144.00

74

-€.
-.V .-.. - ,< ,• ,.,-,,: • .•,< .. '. ' . . . -", ,"- ' ,.", ,-,. . •.,,",.., -. 7 ,, " , • • ,• ,.
 TABLE 20. (CONTINUED)
70 X 150 3.58487 70.00 X 154.00
70 X 160 3.36355 70.00 X 164.00
70 X 170 3.16802 70.00 X 174.00
70 X 180 2.99394 70.00 X 184.00
70 X 190 2.83796 70.00 X 194.00
70 X 200 2.69741 70.00 X 204.00
70 X 210 2.57014 70.00 X 214.00
80 X 90 5.20131 80.00 X 90.00
80 X 100 4.69,134 80.00 X 100.00
80 X 110 4.27195 80.00 X 113.15
80 X 120 :3.92183 80.00 X 124.00
80 X 130 3ý.62458 80.00 X 134.00
80 X 140 3.36919 80.00 X 144.00
80 X 150 3.14747 80.00 X 154.00
80 X 160 2.95316 80.00 X 164.00
"80 X 170 2.78150 80.00 X 174.00
80 X 180 2.62859 80.00 X 184.00
80 X 190 2.49172 80.00 X 194.00
"80 X 200 2. 36833 80.00 X 204.00
80 X 210 2.25656 80.00 X 214.00
80 X 220 2.15489 30.00 X 224.00
80 X 230 2.06196 80.00 X 234.00
80 X 240 1. 97680 80. 00 X 244.00
90 X 100 1.18093 90.00 X 100.00
90 X 110 3,80748 90.00 X 113.15
',90 X 120 3.49529 90.00 X 124.00
90 X 130 3.23061 90.00 X 134.00
91" X 140 3.00284 90. 00 X 144.00
90 x 150 2.80526 90.00 X 154.00
90 X 160 2.63206 90.00 X 164.00
90 x 1/0 2.47907 90.00 X 174.00
90 X 1M0 2.34274 90.00 X 184.00
90 X 190 2.22070 90.00 X 194.00
90 X 200 2.11075 90.00 X 204.00
90 X 210 2.01121 90.00 X 214.00
90 X 220 1.92062 90.00 X 224.00
90 X 230 1. 83780 90.00 X 234.00
90 X 240 1.76183 90.00 X 244.00
90 X 250 1 .69193 90. 00 X 254.00
"90 X 260 1.627378U 90.00 X 264.00
90 X 270 1.56753 90.00 X 274.00
100 X 110 1. 43444 100.00 X 110.00
t 0o X 120 3. 15268 100.00 X 120. 00
100 X 130 2.91371 100.00 X 172.96
*100 x 140 2.70845 100.00 X 144.o0
100 X 150 2. 53030 100. 00 X 154.00
1t10 X 120 2.87157 110.00 X 120.00
110 X 130 2.65361 110.0C0 X 132.96
110 X 140 2.46645 110.00 X 144.00
"110 X 150 2. 3043:4 110.00 X 154.00
110 X 160
{" 11 X 15 z. 16194
2. "" "5 110.00 X 164.00
 TABLE 20. (CONTINUED)
120 X 130 2.43644 120.00 X 132.96
120 X 140 2.26459 120.00 X 144.00
120 X 150 2.11551 120.00 X 154.00
* 120 X 160 1.98463 120.00 X 164.00
120 X 170 1.86930 120.00 X 174.00
* 120 X 180 1.76664 120.00 X 184.00
130X 140 2.09358 132.9 X144.00
130 X 150 1.95524 1:32.96 X 154.00
130 X 160 1.83437 132.96 X 164.00
130 X 170 1.72769 132.96 X 174.00
130 X 180 1.63276 132.96 X 184.00
130 X 190 1.54766 132.96 X 194.00
140 X 150 1.81716 144.00 X 154.00
140 X 160 1.70516 144.00 X 164.00
140 X 170 1.60592 144.00 X 174.00
140 X 180 1.51785 144.00 X 184.00
140 X 190 1.43858 144.00 X 194.00
140 X 200 1.36751 144.00 X 204.00
140 X 210 1.30291 144.00 X 214.00
150 X 160 1.59354 154.00 X 164.00
S150 X 170 1.50064 154.00 X 174.00
150 X 180 1.41796 154.00 X 184.00
150 X 190 1.34399 154.00 X 194.00
150 X 200 1.27742 154.00 X 204.00
150 X 210 1.21724 154.00 X 214.00
150 X 220 1.16231 154.00 X 224.00
160 X 170 1.40840 164.00 X 174.00
160 X 180 1.33052 164.00 X 184.00
160 X 190 1.26113 164.00 X 194.00
160 X 200 1.19865 164.00 X 204.00
160 X 210 1.14199 164.00 X 214.00
160 X 220 1.09056 164.00 X 224.00
160 X 230 1.04358 164.00 X 234.00
160 X 240 1.00040 164.00 X 244.00
170 X 180 1.25374 174.00 X 184.00
170 X 190 1.18778 174.00 X 194.00
* 170 X 200 1.12922 174.00 X 204.00
170 X 210 1.07579 174.00 X 214.O0
170 X 220 1.02718 174.00 X 224.00
X 230
30.170 0.98293 174.00 X 234.00
170 X 240 0.9A.2.30 174.00 X 244.00
170 X 250 0.90488 174.00 X 254.00
180 X 190 1 .1229 18q.00 X 194.00
180 X 200 1.06699 184.00 X 201.00
.180X 210 1.01666 184.00 X 214. 00
180 X 2:20 . ""7086 184'.
0(
180 X 230 0."92884 184.00 X .4.00
1 10 - 40 0.,9049 184.00 X 244.00
180 X 250 0. -,-,17 184.00 X 24 00
-. 180 X 260 0.782259 184.00 X 264.00
180 X 270 0.792'24 184.00 X 274. 00

76

S"
 TABLE 20. (CONTINUED)
190 X 200 1.01189 194.00 X 204.00
190 X 210 0.96381 194.00 X 214.00
190 X 220 0.92054 194.00 X 224.00
190 X 230 0.88057 194.00 X 234.00
190 X 240 0.84405 194.00 X 244.00
190 X 250 0.81071 194.00 X 254.00
190 X 260 0.77972 194.00 X 264.00
190 X 270 0.75099 194.00 X 274.00
190 X 280 0.72439 194.00 X 284.00
200 X 250 0.77052 204.00 X 254.00
200 X 300 0.64288 204.00 X 304.00
250 X 300 0.51533 254.00 X 304.00
250 X 350 0.44216 254.00 X 354.00
300 X 350 0.36912 304.00 X 354.00
300 X 400 0.32308 304.00 X 404.00
300 X 450 0.28730 304.00 X 454.00
350 X 400 0.27723 354.00 X 404.00
350 X 450 0.24652 354.00 X 454.00
350 X 500 0.22197 354.00 X 504.00
300 X 450 0.21591 404.00 X 454.00
400 X 500 0.19440 404.00 X 504.00
O00 X 550 0.17673 404.00 X 554.00
4 00 X 600 0.16208 404.00 X 604.00
450 X 500 0.17289 454.00 X 504.00
450 X 550 0.15722 454.00 X 554.00
450 X 600 0.14415 454.00 X 604.00
450 X 650 0.13309 454.00 X 654.00
500 X 550 0.14165 504.00 X 554.00

TABLE 21. RECTANGULAR SURFACE HEADER - GOLD PLATE

MATERIAL: GOLD
CONDUCTIVITY: 7.54 (W/IN.*C)
SPREADINO ANGLE! 45 (DEGREES)

ILENGTH * WIDTH THERMAL RESISTANCE Linc * Winc

2 X 4 2.88499 2.40 X 4.40

2 X 6 1.95265 2.40 X 6.40
i X 6 1.02028 4.40 X 6.40
4 X 8 0.77123 4.40 X 8.40
4 X 10 0.61992 4.40 X 10.40
4 X 12 0.51825 4.40 X 12.40
6 X 8 0.52217 6.40 X 8.40
6 X 10 0.41973 6.40 X 10.40
6 X 12 0.35089 6.40 X 12.40
6 X 14 0.30147 6.40 X 14.40
6 X 16 0.26423 6.40 X 16.40
6 X 18 0.23519 6.40 X 18.40

77

4i!I `••.•.` ?` . • . • 5 . .. ; . v• `%.%%c .`` . . .`.` . • •. .` .

 TABLE 21. (CONTINUED)
8 x 10 0.31732 8.40 X 10.40
8 X 12 0.26527 8.40 X 12.40
8 X 14 0.22789 8.40 X 14.40
8 X 16 0.19975 8.40 X 16.40
8 X 18 0.17780 8.40 X 18.40
S8 8 X 20 0.16019 8.40 X 20.40
X 22 0.14576 8.40 X 22.40
8 X 24 0.13371 8.40 X 24.40
10J X 15 0.17115 10.40 X 15.40
I'. 10 X 20 0.128/7 10.40 X 20.40
!•
10 X 25 0.10322 10.40 X 25.40
10 X 30 0.08613 10.40 X 30.40
15 X 20 0.08640 15.40 X 20.40
15 X 25 0.06926 15.40 X 25.40
15 X 30 0.05779 15.40 X 30.40
15 X 35 0.04958 15.40 X 35.40
15 X 40 0.04341 15.40 X 40.40
15 X 45 0.03861 15.40 X 45.40
20 X 25 0.05212 20.40 X 25.40
20 x 30 0.04348 20.40 X 30.40
20 X 35 0.03731 20.40 X 35.40
20 X 40 0.03267 20.40 X 40.40
,20 X 45 0.02905 20.40 X 45.40
.20 X 50 0.02616 20.40 X 50.40
20 X 55 0.02379 20.40 X 55.40
20 X 60 0.02182 20.40 X 60.40
25 X 30 0.03486 25.40 X 30.40
25 X3 0.02991 25.40 X 35.40
25 X 40 0.02618 25.40 X 40.40
25 X 45 0.02329 25.40 X 45.40
25 X 50 0.02097 25.40 X 50.4Q
25 X 5!, 0.01907 25.40 X 55.40
25 X -,,0 0.01749 25.40 X 60.40
25 X 65 0.01615 25.40 X 65.40
25 X 70 0.01500 25.40 X 70.40
25 X 75 0.01400 25.40 X 75.40
.30 X 35 0.02497 30.40 X 35.40
30 X 40 0.02185 30.40 X 40.40
30 X 45 0.01943 30.40 X 45.40
-30 X 50 0.01750 30.40 K 50.40
130 x 55 0.01592 30.40 X 55.40
""30 X 60 0.01459 30.40 X 60.40
.30 X 65 0.01347 30.40 X 65.40
30 X 70 Q.0t251 30.40 X 70.40
* 30 X 75 0.01168 30.40 X 75.40
30 X 80 0.01095 30.40 X 80.40
30 X 85 0.01031 30.40 X 85.40
30 x 90 0. 00974 30.40 X 90.40
X 40
K35 0.01875 35.40 X 40.40
35 X 45 0.01667 35.40 X 45.40
* 35 X 50 0.01501 35.40 X 50.40

78
 TABLE 21. (CONTINUED)
35
35 X
X 55
60 0.01365 35.40 55.40
0.01252 35.40 X
X 60.40
35 X 65 0.01156 35.40 X 65.40
35 X 70 0.01074 35.40 X 70.40
35 X 75 0.01002 35.40 X 75.40
35 X 80 0.00940 35.40
35 X 80.40
X 85 0.00885 35.40 X 85.40
35 X 90 0.00836 35.40
35 X 90.40
X 95 0.00792 35.40
35 X 95.40
X 100 0.00752 35.40 X 100.40
35 X 105 0.00716 35.40 X 105.40
40 X
X 'O
15
50 0.01460
0.01315 40.40 45.40
40 X 40.40 X 50.40
50 0.01195 40.40 X 55.40
40 X 60 0.01096 40.40 X 60.40
40 X 65 0.01012 40.40 X [Link]
40 X 70 0.00940 40.40 X 70.40
40 X 75 0.00878 40.40 X 75.40
40 X 80 0.00823 40.40 X 80.40
40 X 85 0.00775 40.40 X 85.40
40 X 90 0.00732 40.40 X 90.40
40 X 95 0.00693 40.40 X 95.40
40 X 100 0.00659 40.40
40 X X 100.40
105 0.00627 40.40 X 105.40
40 X 110 0.00599 40.40 X 110.40
40 X 115 0.00573 40.40 X 115.40
40 X 120 0.00549 40.40
45 X 50 0.01169 45.40 X 120.40
X 50.40
45 X 55 0.01064 45.40 X 55.40
15 X 60 0.00975 45.40 X 60.40
45 X 65 0.00900 45.40
45 X 65.40
X 70 0.00836 45.40 X 70.40
45 X 75 0.00780 45.40
. X 75.40
45 X 80 0.00732 45.40 X 80.40
45 X 81 0.00689 45.40 X 85.40
45 X 90 0.00651 45.40 X 90.40
45
45 X
X 95
too 0.00617
0.00586 45.40 X 100.40
95.40
45 X 105 0.00558 45.40
45 X 105.40
X 110 0.00533 45.40 X 110.40
45 X 115 0.00509 45.40 X 115.40
45 X 120 0.00488 45.40 X 120.40
45 X 125 0.00469 45.40 X 125.40
45 x 130 0.00451 45.40 X 130.40
45 X 135 0.00434 45.40 X 135.40
50 X 60 0.00879 50.40 X 60.40
50 X 70 0.00753 50.40 X 70.40
50 X 80 0.0065T 50.40 X 80.40
50 X 90 0.00586 50.40
50 X 90.40
X 100 0.00527 50.40
50 X 110 X 100.40
0.004/9 50.40 X 110.40

79
 TABLE 21. (CONTINUED)
50 X 120 0.00440 50.40 X 120.40
50 X 130 0.00406 50.40 X 130.40
50 X 140 0.00377 50.40 X 140.40
50 X 150 0.00352 50.40 X 150.40
60 X 70 0.00628 60.40 X 70.40
60 X 80 0. 00549 60.40 X 80.40
60 X 90 0.00489 60.40 X 90.40
60 X 100 0.00440 60,40 X 100.40
60 X 110 0.00400 60.40 X 110.40
60 X 120 0. 00367 60.40 X 120.40
60 X 130 0.00338 60.40 X 130.40
60 X 140 0.00314 60.40 X 140.40
60 X 150 0.00293 60.40 X 150.40
60 X 160 0. 00275 60.40 X 160.40
60 X 170) 0.00259 60.40 X 170.40
60 X "80 0.00245 60.40 X 180.40
70 X 80 0.00471 70.40 X 80.40
70 X 90 0.00419 70.40 X 90.40
70 X 100 0.00377 70.40 X 100.40
70 X 110 0.00343 70.40 X 110.40
70 X 120 0.00314 70.40 X 120.40
"-70 X 130 0.00290 70. 40 X :130.40
""70 X 140 0.00270 70.40 X 140.40
70 X 150 0.00252 70.40 X 150.40
70 X 160 0.00236 10.40 X 160.40
70 X 1/0 0.,00222 70.40 X 170.40
70 X 180 0.00210 70.40 X 180.40
70 X 190 0.00199 70. 40 X 190.40
70 X 200 0.00189 70.40 X 200.40
70 X 210 0.00180 70.40 X 210.40
80 X 90 0.00367 80.40 X 90.40
80 X lot) 0.00330 80.40 X 100.40
-0 X 110 0.00300 80.40 X 110.40
80 X 120) 0.00275 80.40 X 120.40
80 X 130 0.00250! 80.40 X 130.40
80 X 140 0.002a6 80.40 X 140.40
80 X 150 0.00220 80.40 X 150.40
S- X 160 0.00206 80.40 X 160.40
$0 X 170 0.00194 80.40 X 170.40
80 X 180 0.00184 80.40 X 180.40
80 X 100 0.00174 80.40 X 190.40
80 X 200 0.00165 80.40 X 200.40
80 X 210 0.00157 80.40 X 210.40
80 X 220 0.00150 SO. 40 X 220. 40
80 X 230 0.00144 80.40 X 2•0. 40
80 X 240 .001 ts 80.40 X 240.40
90 X 100 0.00294 F0. 40 X 100.40
g0 x lit) 0.00267 90.40 X 110.40
90c X 120 0. 00245 :50 40 X 120.40
90 X 1130 o. 00226 90.40 X 130. 40
90 X 140 0.00210 90.40 X 140.40

80
 TABLE 21. (CONTINUED)
90 X 150 0.00196 90.40 X 150.40
90 X 160 0.00184 90.40 X 160.40
90 X 170 0.00173 90.40 X 170.40
90 X 180 0.00163 90.40 X 180.40
90 X 190 0.00155 90.40 X 190.40
90 X 200 0.00147 90.40 X 200.40
90 X 210 0.00140 90.40 X 210.40
90 X 220 0.00134 90.40 X 220.40
90 X 230 0.00128 90.40 X 230.40
90 X 240 0.00122 90.40 X 240.40
90 X 250 0.00118 90.40 X 250.40
90 X 260 0.00113 90.40 X 260.40
90 X 270 0.00109 90.40 X 270.40
100 X 110 0.00240 100.40 X 110.40
100 X 120 0.00221 100.40 X 120.40
100 X 130 0.00204 100.40 X 130.40
100 X 140 0.00189 100.40 X 140.40
100 X 150 0.00176 100.40 X 150.40
110 X 120 0.00200 110.40 X 120.40
110 X 130 0.00185 110.40 X 130.40
110 X 140 0.00172 110.40 X 140.40
110 X 150 0.00160 110.40 X 150.40
110 X 160 0.00150 110.40 X 160.40
120 X 130 0.00170 120.40 X 130.40
120 X 140 0.00158 120.i0 X 140.40
120 X 150 0.00147 120.40 X 150.40
120 X 160 0.00138 120.40 X 160.40
120 X 170 0.00130 120.40 X 170.40
120 X 180 0.00123 120.40 X 180.40
130 X 10 0.00146 130.40 X 140.40
130 X 150 0.00136 130.40 X 150.40
130 X 160 0.00127 130.40 X 160,40
130 X 170 0.00120 130.40 X 170.40
130 X 180 0.00113 130.40 X 18(1.40
130 X 190 0.00107 130.40 X 190.40
IQ0 X 150 0.00127 140.40 X 150.40
140 x 160 0.00118 140.40 X 160.40
140 X 170 e.00111 110.40 X 170.40
140 X 180 0.00105 140.40 X 180.40
140 X 190 0.00100 140.40 X 190.40
140 X 200 0.00095 140.40 X 200.40
140 X 210 0.00090- 140.40 X 210.40
150 X 160 0.00110 150.40 X 160.40
150 X 170 0.00104 150.40 X 170.40
, 150 X 180 0.00098
- 150.40 X 180.40
150 X 10 0.00093 150.40 X 190.40
150 X 200 .000D8 150.40 X 200.40
150 X 210 0.00084 150.40 X 210.40
150 X 220 0.00080 150.40 X 220.40
160 X 170 0.00098 160.40 X 170.40
160 x 180 0.00092 160.40 X 180.40

81
 TABLE 21. (CONTINUED)
160 X 190 0.00087 160.40 X 190.40
160 X 200 0.00083 160.40 X 200.40
160 X 210 0.00079 160.40 X 210.40
160 X 220 0.00075 160.40 X 220.40
160 X 230 0.00072 160.40 X 230.40
160 X 240 0.00069 160.40 X 240.40
170 X 180 0.00087 170.40 X 180.40
170 X 190 0.00082 170.40 X 190.40
170 X 200 0.00078 170.40 X 200.40
170 X 210 0.00074 170.40 X 210.40
170 X 220 0.00071 170.40 X 220.40
170 X 230 0.00068 170.40 X 230.40
170 X 240 0.00065 170.40 X 240.40
170 X 250 0.00062 170.40 X 250.40
180 X 190 0.00078 180.40 X 190.40
180 X 200 0.00074 180.40 X 200.40
180 X 210 0.00070 180.40 X 210.40
180 X 220 0.00067 180.40 X 220.40
180 X 230 0.00064 180.40 X 2.2.
180 X 240 0.00061 180.40 X 240.40
180 X 250 0.00059 180.40 X 250.40
180 X 260 0.00057 180.40 X 260.40
180 X 270 0.00055 180.40 X 270.40
190 X 200 0.00070 190.40 X 200.40
190 X 210 0.00067 190.40 X 210.40
190 X 220 0.00064 190.40 X 220.40
190 X 230 0.00061 190.40 X 230.40
190 X 240 0.00058 190.40 X 240.40
190 X 250 0.00056 190.40 X 250.40
190 X 260 0.00054 190.40 X 260.40
190 X 260 0.00050 190.40 X 260.40
190 X 270 0.00052 190.40 X 270.40

200 X 250 0. O0053 200.40 X 250.40

200 X 300 0.00044 200.40 X 300.40
250 X 300 0.00035 250.40 X 300.40
250 X 3t0 0.00030 250.40 X 350.40
300 X 350 0.0002b 300.40 X 350.40
300 X 400 0.00022 300.40 X 400.40
300 X 450 0.00020 300.40 X 450.40
350 X 400 0.00019 350.40 X 400.40
350 X 450 0.00017 350.40 X 450.40
350 x 500 0.00015 350.40 X 500.40
i00 X 450 0.00015 400.40 X 450.40
401) X 500 0.00013 400.40 X 500.40
400 K 550 0.00012 400.40 X 560.40
400 X 600 0.00011 400.40 X 600.40
450 X 500 0.00012 450.40 X 500.40
450 X 550 0.00011 450.40 X 550.40
450 X 600 0. 000iO 450.40 X 600.40
450 x 650 0.00009 450.40 X 650.40
500 X 550 0.00010 500.40 X 550.40

82
4F4

SQ
 TABLE 22. RECTANGULAR - 40 PIN CERAIUC SIDE BRAZED PACKAGE

MATERIAL: ALUMINA
CONDUCTIVITY: .478 (W/IN.*C)
SPREADING ANGLE: 45 (DEGREES)
ATTACHMENT MATERIAL: NON-CONDUCTIVE EPOXY
INTERMEDIATE MATERIAL: GOLD HEADER

LENGTH * WIDTH THERMAL RESISTANCE Linc * Winc

2 X 4 352.71793 106.00 X 108.00
2 X 6 277.60/06 106.00 X 110.00
S4 X 6 202.46662 108.00 X 110.00
I X 8 171.75175 108.00 X 112.00
I X 10 150.31781 108.00 X 114.00
^ X 12 131.30350 108.00 X 116.00
6 X 8 141.03760 110.00 X 112.00
6. X 10 124.2'4382 110. 00 X 114.00
6 X 12 111.58256 110.00 X 116.00
6 X 14 101.60744 110.00 X 118.00
6A X 16 93.49555 110.00 X 120.00
6 X 18 86.73919 110.00 X 122.00
8 X 10 107.45017 112.00 X 114.00
X 12 96.85520 112.00 X 116.00
X 14 88.46430 112.00 X 118.00
8 X 16 81.61023 112.00 X 120.00
8 X 18 75.87959 112.00 X 122.00
X 20 70.9969 112.00 X 124.00
X 2- 66.78260 112.00 X 126.00
SX 14 63.09367 112.00 x 128.00
10 X 15 75.84531 114.00 X 119.00
1') X 201 63.70966 114.00 X 124.00
S0 K 25 55.27736 114.00 X 129.00
10 K 30 •9.00475 114.00 X 134.00
15 x 20 51.12657 [Link] X 118.00
tS 25 44.56381 11.00 X 123.00
115 x 30 39.64470 I13.00 X 128.00
5 .3• 35.7916"4 113.00 X 133.00
X 4( 32.67627 113.00 x 138.00
!5 X 45 30.016I0 113.00 X 143.00
X 2K -2:t v.00090 118.00 X 123.00
20 X 30 33.90,371 118.00 X 128.00
2 K 35 30.68004 118.00 X 133.00
"20) x 40 -8. 06371 118.00 x 138.00
S20 x 45 25. s99' 118.00 X 143.00
20 x1 50 24.05033 118.00 X 140.00
"T
10" x 2. 47 003 111.00 153. 00
-0 K 60 21.0957e 118.00 X 158.00
25 x 30 29.80668 123.00 x 128.00
•5
2, :35 27.01967 123.00 X 133.00
U 25 X ') 2.75137 123.00 X 138.00

83
) TABLE 22. (CONTINUED)
25 X 45 22.86230 123.00 X 143.00
25 X 50 21.26022 123.00 X 148.00
25 X 55 19.88157 123.00 X 153.00
25 X 60 18.68075 123.00 X 158.00
25 X 65 17.62410 123.00 X 163.00
2t, X 70 16.68619 123.00 X 168.00
.25 X 75 15.84737 12:3.00 X 173.00
30 X 35, 23.84629 122.00 X 127.00
30 X 40 21.85158 122.00 X 132.00
30 X 15 20.18866 122.00 X 137.00
30 X 50 18.77723 122.00 X 142.00
30 X 55" 17.56167 122.00 X 147.00
30 X 60 16.50237 122.00 X 152.00
30 X 45 15.56980 122.00 Y 157.00
30 X 70 14.74172 122.00 X 162.00
30 X 75 14.00089 122.00 X 167.00
30 X 80 13.33380 122.00 X 172.00
30 X 85 12.72966 122.00 X 177.00
30 X 90 12.17968 122.00 X 182.00
35 X 40 19.85714 127.00 X 132.00
:35 X 45 18.35989 127.00 X 137.00
"35 X 50 17.08759 127.00 X 142.00
"35 X 55 15.99057 127.00 X 147.00
"35 X 60 15.03362 127.00 X 152.00
35 X 65 14.19039 127.00 X 157.00
35 X 70 13.44105 127.00 X 162.00
35 X 75 12.77024 127.00 X 167.00
35 X 80 12.16578 127.00 X 172.00
35 X 85 11.61802 127.00 X 177.00
35 X 90 11.11909 127.00 X 182.00
35 x q5 10.66261 127.00 X 187.00
35 X 100 10.24324 127.00 X 192.00
35 x 105 9.85647 127.00 X 197.00
40 X 45 16.8S6292 132.00 X 137.00
40 x 50 15.70282 1
0 55 14.70178 132.00 X 147.00
4•0 60 13.82777 132.00 X 152.00
AQ0 x 65 13.05707 132.00 X 157.00
40 X 70 12,371/4 132.00 x 162.00
A' X 75 11.75785 142.00 X 167.00
.40, X 80 11.20437 132.00 X 172.00
40 X 85 10.70258 132.00 X 177.00
40 X 90 10.24530 132.00 X 182.00
40 X 95 9.82679 132.00 X 187.00
40 X IW0 9.44208 132.00 X 192.00
40 X 105 9.08721 132.00 X 197.00
40 X I10 8.75875 132.00 X 202.00
40 X 115 S.45377 132.00 X 207.00
40 A 120 8.16982 132.00 X 212.00
.45 X 50 14.54283 137.00 X 142.00
"45 x 55 13.62134 137.00 X 147.00

84
 TABLE 22. (CONTINUED)
45 X 60 12;81612 137.00 X 152.00
45 X 65 12.10567 137.00 X 157.00
45 X 70 11.47355 137.00 X 162.00
45 X 75 10.90704 137.00 X 167.00
45 X 80 10.39601 137.00 X 172.00
45 X 85 9.93257 137.00 X 177.00
45 X 90 9.51003 137.00 X 182.00
45 X 95 9.12316 137.00 X 187.00
45 X 100 8.76747 137.00 X 192.00
45 X 105 8. 43926 137.00 X 197.00
45 X 110 8.13535 137.00 X 202.00
45 X 115 7.85315 137.00
45 X 120 X 207.00
7.59029 137.00 X 212.00
45 X 125 7.34487 137.01 X 217.00
45 X 130 7.11514 137.00 X 222.00
45 X 135 6.89963 137.00 X 227.00
50 X 60 11.95280 142.00 X 152.00
50 X 70 10.70626 142.00 X 162.00
50 X 80 9.70491 142.00 X 172.00
50 x 90 8.88094 142.00 X 182. 00
50 X 100 8.18993 142.00 X 192.00
50 X 110 7.60141 142.00 X 202.0t0
50 x 120 7. 09369 142.00 X 212.00
50 x 130 6.65093 142.00 2.00>
50 X 140 6.26115 112.00 x -%200
50 10 .91530 142..00 X 4:42. 00
60 X 70 9. 10169 1414.00 x 154. Q
160 x 80 8. 54422 144 00 X 1•4.00
90 7::,t918
.60 .144.00
X 14.
100 .60
.4454 144.00 18.10
4
",60 K 10 6.44543 14.0 19 .00
60 X 120 6.01186 1414.00 X 204. tX)
60 X 130 5.63401 144. 00 X 214.00
60 X 140 5.30159 144.00 X 2.24. 00
60 x 150 kt.00678 144.00 X 234.00
60 X 160 4.74346 II.00 X 244. O
60 X 1?0 4.50679 144.00 254.00k
60 K 180 4. 2286 144.00 X 26. 00
70 X 80 7.38682 154.00 X 164.0(,
70 X 90 6.75794 154. 00 X 174..Ost
70 X 100 6.13(66 15
70 x 13
70 A I110
to 5.
'53951A39.%9 15". 00
O
X 'Aý4. v,:)
0,O
70 X 1,30 154.0 Ko 204. On.
X
5 . 05608 154. 00 x 2 !1. ,x?
70 x 110 . 7587Ž 15." +".0
7%- K 150 4. 494- 3 .t X 3,4>o,
70 160 ".25'£2
2 154.00 X I,44.O,.
70 X 17) 41*•47 %t C54. 00 X 254
70 x 10 557 3.00
0.-
70 2Ž64.00
1906 15".00 X --74. Ov
70 .* 200 3. t322U i54. 00 X

85
 TABLE 22. (CONTINUED)
70 X 210 3.37706 154.00 X 294.00
80 X 90 6.12909 164.00 X 174.00
80 X 100 5.65244 164.00 X 184.00
80 X 110 5.24625 164.00 X 194.00
80 X 120 4.89571 164.00 X 204.00
80 X 130 4.58995 164.00 X 214.00
80 X 140 4.320/2 164.00 X 224.00
"80. X 150 4.08180 164.00 X 234.00
80 X 160 3.86827 164.00 X 244.00
80 X 1.70 3.67626 164.00 X 254.00
80 X 180 3.50260 164.00 X 264.00
80 X !90 3.34477 164.00 X 274.00
80 X 200 3.20070 164.00 X 284.00
80 X 210 3.06862 164.00 X 294. O0
80 X 220 X.94710 164.00 X 304.00
* 80 X 230 2.83492 164.00 X 314.00
80 X 240 2. 73102 164.00 X 324. 00
90 X 100 5.17581 174.00 X 184.00
x 110 4.80434 174.00 X 194.00
90 X 120 4.48458 174.00 X 204.00
90 X 130 4.20513 174.00 X 214.00
;%:o90 X 140 3.95904 174. C X 224.00
90 X 150 7405: 174.00 X 234.00
90 X 160 3.54531 174.00 X 244.00
90 X 170 3.36965 179.00 X 254.00
90 X 180 3.21076 174.00 X 264.00
90 X 190 3..06634 174.00 X 274.00
0 X 200 2 93448 174.00 X 2,48. 00
90) X 210 2.81358 174.00 X 294.00
90 X 220 X. 7023A 174.00 X 304.00
t. 90 X 230
x....-. 2.59962 174.00
4o•- 174.00 X 314. 00
J :324..00
90
0.41
0 X 240
.250: 2. 50417
2.1,1I0 174.00
174.0O0 X 324.00
X 3::-4.00
9) X 260 2.33378 174.00 X344.00
9.X 20 2..25692 174.00 X
354.00
100 x 110 4. 4339 : 184.00 X194.00
100 X 120 4.13904 184. 00 X
204.00
100 X 130 -3. 88161 184.00 X
214.00
100 X 14.0 3. 65490 184.00. X
224. 00
100 X 150 3 45356 1 84.*00 X
234. :0
i10 X 120 3./736213 190. 00 X
200. 00
11.0C X 130:, 50270_ Pi0. 00 210. 0
X
110 x , .0 3. 2P70Q4 190. 00 X
220. 00
.1.1) X ', 0 3 1 ..1455 190 00 X
"30. " .,o
110 X 160 .9'5145 190. C0 X
:240.00
I.X 130. 2 6.9 11 20(). 00 X7 10.
1.00
120 X 1401.0 3. 077 6 200.00 X :220. 00
1.- X 15() :2. ' •0 :4 20)0 0%) X 2 .0 QQC)
1..X 160 75!24 200. 00 X 240 ,00
I "("" X 1 C) : 1 ,.200. 00 X 2!50. 00
"120 X 180" 00. 0C X 260. O0

86
 TABLE 22. (CONTINUED)
130 X 140 2.88578 210.00 X 220.00
130 X 150 2.72646 210.00 X 230.00
130 X 160 2.58399 210.00 X 240.00
130 X 170 2.45583 210.00 X 250.00
1230 X 180 2.33994 210.00 X 260.00
130 X 190 2.23439 210.00 X 270.00
140 X 150 2.56716 220.00 X 2310.00
140 X 160 2.43307 220.00 X 240.00
140 X 170 2.31253 220.00 X 250.00
140 X 180 2. 20348 220.00 X 260 .00
140 X 190 2.10436 220.00 X 2,70.00O
140 X 200 2.18 22.0 X 280, cn:
140 X 210 0(
JL.93085 220.00 X *,0.0
150) X 160 2. 29905 230. 00 X240. 00
15Sc X 1.70 2.18527 230.*00 X 250. 00
150 x 1SO 2.*08226 230.00 X 260.00
150 X 190 1 .98867 230.00 X 270.00
150 X 200 1 . 9031.9 230. 00 X 280. 00
A150 X 210 1. 82482 230.00 X 290. 00
150 X( 220 1. 75269 2;30.00 X 300.00

.160 X 200 1.970"2:0 o

240 .0 X 260. 00)
Il--O X 210 1.72997 240.*00 X 290. oo0
160 X 220 1.*66162 240.00 X 300.00
160 X 230 1 .59352 240.*00 X 3 10.*00
160o X 240 1 .54006 240.0c:0 X 320 .00
010 X I "R0 1 .87639 250.00 X 260. 00
170 X 190 1 .7921 1 250. 00 X 270.O
00
170 X 0 0 .7151 25000 X 280.00o
170 X 200 1:.64460 250 00 X 290. 00
1.70 X 220 1 . 5*7969- 5.0 30 )
1 70 X 230 1 . 51970 250. 00 X 310. 00
1-/0 X 240 I.A6416 250. 00 X 320.*Oo
1 70 X 250 1 .41254 250. 00 X 3:30 .0o
180 X 190 1 .70793 260. 00 X 270. 00
180 x20 1.*63-157 260.*00 X 280. 00
180 X 210 1.56737 260.00 X 2190
18 2X .50551 260.*00 x 300. 00
1.S0 x 230 1 .A44838 260.*00 X 3,10. 00(.
V24 180 1.*39545 260. 00 X .320. 00
c'O X 250 1.342 ~ .. 00
26i0 X 330,C. 00
180 x 260 1.* 30049 260 *00 X 00o
180 X 270) 1.*257/1. 26.-0 *00) X :;3S0. 00)
I "PQ X 200 1 . 36 [Link] 270. 00 X 280. 0
190 X 2 10 1. 49~713: 270.00 X 2'o.o).00
1'"0 X2 :,,.'.(.)s~o ..
4 80,270:.(00 2<30
.-O) c)(:
10 X< 230
h
1.*33: () 00
270 X 310o. 00
190 2241 :32 270. 00 X< 320. 00
290 ..50
X. 1.286:0'-- 2,7 0. 00 X< a:Q . 0

87
 TABLE 22. (CONTINUED)
190 X 260 1.24230 270.O0 X 340.00
190 X 270 1.20146 270.00 X 350.00
190 X 280 1.16322 270.00 X 360.90
200 X 250 1.23098 280.00 X 330.00
200 X 300 1 .04690 280.00 X 380.00
250 X 300 0.86284 330.00 X 380.00
250 X 350 0. 75084 330.00 X 430.00
300 X 350 0. 603886 380. 00 X 430.00
300 X 400 0. 56556 380.00 X 480.00
3'0O X 450 0.50739 380.00 X 530.00
350 X 400 0. 49228 430.00 X 480.00
350 X 450 0.44167 430.00 X 530.00
350 X 500 0.40051 430.00 X 580. 00
400 X 450 0.39107 480.00 X 530.00
400 X 500 0.35463 480.00 X 580.00
400 X 550 0.32441 480.00 X 630.00
400 X 600 0.29895 480.00 X 680.00
450 X 500 0.31819 530.00 X 580.00
450 X 550 0.29109 530.00 X 630.00
450 X 600 0."2 -350. 0.0 X 680. 00
450 X 650 0. 24874 530. 00 X 730.00
500 X 550 0.26399 580.00 X 630.00

TABLE 23. RECTANGULAR DEVICE AMPLE CALCULATION

Given:

Device: Material: Silicon (2.13 watts per inch-degrees centigrade 50 percent dissipation
Dimension: 120 x 140
Thickness: 18 Mils

Epoxy Type: Ablebond 36-2 (0.051 watts per inch-degrees centigrade)

Thickness: 2 Mils

Header Type: Gold Plate (7.54 watts per inch - degrees centigrade)
Thickness: 0.2 Mils

Package Type: Ceramic (0.478 watt per inch - degrees centigrade)

1,> Thickness: 40 Mils

PD: 1 Watt
Thermal Resistance
Dimension (degrees centigrade
Level Material (inches) (per watt) Next Level DIM

Device Silicon 120 x 140 0.72202 120.00 x 134.98

Epoxy Ablebond 120 x 134.98 2.35068 120.00 . '38.56

Header Gold 120 x 138.56 0.00160 120.40 x 138.96

Package Ceramic 120.4 x 138,96 3.10490

6.179
Aj
AJC P'D* e c
= I * 6,179 -Th,rmal resistance values are interpolated
= 6.179C

88

~n2W
% '*WN .t¶
5.3.3 Circular Model

Specific constructions, such as mesa devices, that are required to

dissipate high power, are readily evaluated by a circular model. Actual
temperature gradients could be more accurately described by a hemispherical
model, but the added complexity is not warranted, due to the thin sections
involved up to the point of the heat sink. The circular model can be
represented by the following equation:

1
R1 1 R-1
K -wr TAN(A) R + T • TAN(A)

where

R1 = thermal resistance (degrees centigrade per watt)

K = material conductivity (watts per inch - degrees centigrade)
A = spreading angle (degrees)
R = radius (mils)
T = thickness (mils).

The value for K must be divided by 1000 in order to have agreement

among measurement units.

Table 24 illustrates the use of the circular model tables. These

tables are generated by the model programs for each level of construction.
Tables 25 through 29 are of the same format as the ones that represent the
square and rectangular surfaces. However, the diameter and radius are used
in place of the length and width. When entering these data tables, it
should be noted that the diameter is used as the entering dimension for the
first level of construction. All subsequent levels use the radius.
Next level dimension computation for circular devices is based on the
thickness of that particular level of construction and the radius of the
dissipation area. The equation which represents this computation follows: I
R2 - R+T*TAN(A)

where

SR2 - new radius (mils)

R - present radius (mils)
T - present thickness (mils)
A - spreading angle (degrees).

The heat dissipated is assumed to be over 100 percent of the area, since
circular devices have junctions over the entire surface.

89

' '.' V,
 60

14.

> ~00w

4) A

$4.
60 be P'

04) 0 I

041 -A CA
0. 40
o~' 0)04.'
F4* 00 - 0t%

4JF4
m~ J:"w :l

140
Q-4C P4gg'00a.v4H
I'U9 41 0 4 S-oU
PI -. 4 C3 cl
to A *.0 0 4 -0 4 C

-@4 W U .. .. 4 .'

-i-A
.'.4 -4 -4 P4
-4 is U
P.. A.' . w.

0)
>~1 Q 0)
0 * 0*4 1.4 1- 4 4

90

00* %h
1, *.
 TABLE 25. CIRCULAR SURFACE DEVICE

MATERIAL: SILICON
CONDUCTIVITY: 2.13 (W/IN.*C)
SPREADING ANGLE: 45 (DEGREES)

DIAMETER THERMAL RESISTANCE RADIUS(inc)

"1 35.1627 0.57

2 17.5813 1.13
3 11.7209 1.70
4 8.7907 2.27
5 7.0325 2.83
6 5.8604 3.40
7 5.0232 3.97
4.53 S
-9 3.9070 5.10
10 3.5163 5.67
12 2.9302 6.80
14 2.5116 7.93
16 2.1977 9.07
18 1.9535 10.20
20 1.7581 11.33
22 1.5983 12.47
24 1,4651 13.60
26 1.3524 14.73
28 1.2558 15.87
30 1.1721 17.00
32 1.0988 18.13
3q 1.0342 19.27
36 0.9767 20.40
38 0.9253 21.53
40 0.8791 22.67
•42 0.8372 23.80
44 0.799' 24.93
46 0.1644 26.07
A18 0.7326. 27.20
50 0.7033 28.33
%- %

91

... . . . . . . . . *. •. *...........
. .,'.. ... ~ * ,,•-. .. .. .' ., - '.".- .e *. .', .-. .. .,-I-o•
• ,.,•-%
",•. . °-.*--
•'-'-'o'-' .',• .'. ."-o o." ", o. •." _ . o,°
. °*e • .. •" •_ °.• -• . b" . •"•°*
. • " •°" to"•"•* " •-'•'-°.•" •'•'•-. . -.-..
• %'* . .."*-%*." -*-a-.o •
 TABLE 26. CIRCULAR SURFACE METALLIZATION - PLATINUM

MAIERIAL: PLATINUM
CONDUCTIVITY: 1.8 (W/IN.*C)
SPREADING ANGLE: 45 (DEGREES)

RAD I US THERMAL RES I STANCE RAD I US ( i nrc)

1 1.4035 1.01

2 0.3523 2.01
3 0.1568 3.01
4 0.0882 4.01
5 0. 0565 5.01
6- 010393 6.01
7 0.0288 7.01
.3 O,.0221 8. Ol
9 0.0171 9.01
10 0.0141 10.01
12 0.0098 12.01
14 0.0072 14.01
16 0.0055 16.01
18 0.0044 18.01
"20 0.0035 20.01
22 0.0029 22.01
24 0.0025 24.01
26 0.0021 26.01
28 0.0018 28.01
30 0.0016 30.01
32 0.0014 32.01
3'1 0.0012 34.01
36 0.0011 36.01
as 0. 0010 38.0Ol
1.0 0. 0009 40.01
42 0.0008 42.01
44 0.0007 44.01
46 0.0007 [Link]
-48 0.0006 48.01
50 0.0006 50.01

92

".J,. SIN
AN
 TABLE 27. CIRCULAR SURFACE METALLIZATION - TITANIUM

MATERIAL: TITANIUM
CONDUCTIVITY: .45 (W/IN..*C)
SPREADING ANGLE" 45 (DEGREES)

RADIUS THERMAL RESISl ANCE RADIUS(in c)

1 63.7199 1.10
2 16.6813 2.10
3 7.5323 3.10
4 4.2711 4.10
5 2.7467 5.10
6 1.9137 6.10
7 1.4092 7.10
8 1.0808 8.10
9 0.8551 9.10
10 0.6934 10.10
12 0.4823 12.10
140.3548 14.10
16 0.2719 16.10
is 0.2150 18.10
20 0.1742 20.10
22 0.1440 22.10
24 0.1211 24.10
26 0.1032 26.10
28 0.0890 28.10
30 0.0775 30.10
"32 0.0682 32.10
"34 0.0604 34.10
36 0.0539 36.10
38 0.0484 38.10
10 0.0437 40.10
42 0.0396 42.10
44. 0. 0361 44.10
rc 46 0.0330 46.10
,nl 48 0.0303 48.10
"50 0.0280 50.10

-93

?.4

"4- 4 -
 TABLE 28. CIRCULAR SURFACE - GOLD PLATE

MATERIAL: GOLD
CO'NDUCTIVITY: 7.54 (W/IN. *:)
SPREADING ANGLE: 45 (DEGREES)

RAD I US THERMAL RESISTANCE RADIUS( irnc)

------------------- ------------------ -----------
1 3. 0909 1.08
2 0.8021 2.08
3 0.3611 3.08
, 0.2044 4.08
5 0.1313 5.08
6 0.0914 6.08
7 0.06,73 7.08
8 0.0516 8.08
9 0.0408 9.08
10 0.0331 .i 1 08
12 0.023( 12.08
14 0.0169 14.08
16 0.0130 16.08
18 0.0102 18.08
20 0.0083 20.08
22 0.0069 22.08
24 0.0058 24.08
. 26 0.0049 26.0-11
, 28 0.0042 28.08
30 0.0037 30.08
32 0.0032 32.08
34 ).0029 34.08
36 0. 002V 36.08
* 38 0.0023 38.08
,0 0.0021 40.08
42 0.0019 42.08
44 0.0017 44.08
46 0.0016 46.08
48 0.,0ItO 48.08
V 50 0.0013 50.08

-94

A%'2

N' ;,':•, ,,;•

°,# ' .*:'
, • • '-C. , - '.. ' ." ¢ ,o • .. ' ',g ,, ,•. ,' • . " " .• ." .,." ;. ". '., .:o• •" . , ; ', *) ,,91* L.
 TABLE 29. CIRCULAR SURFACE HEAT SINK - COPPER

MATERIALS COPPER
CONDUCTIVITY: 10 (W/IN.*C)
SPREADING ANGLE: 45 (DEGREES)
HEAT SINK THICKNESS: 2.5 (MIL IN.)

RADI US THERMAL RESISTANCE RADIUS (INC)

1 22.7364 3.50
2 8.8419 4.50
3 4.8229 5.50
4 3.0607 6.50
5 2. 1221 7.50
6 1.5603 8.50
7 1.1967 9.50
8 0.9474 10.50
9 0.7689 11.50
10 0.6366 12.50
12 O,.4573 14.50
14 0.3-4,45 16.50
16 0.2688 18.50
18 0.2157 20.50
20 0. 1768 22.50
22 0. 1476 24.50
24 0.1251 26.50
26 0.1074 28.50
28 0.0932 30.50
30 0.0816 32, 50
32 0.0721 34.50
34 0.0641 36.50
36 0.0574 38.50
38 0.0517 40.50
40 0.0468 42.50
42 0.0426 44.50
44 0.0389 46.50
A6 0.0357 48.50
"48 0.0328 50.50
't. 50' 0.0303 52.50

95
 5.3.4 Hybrid Model

Thermal considerations for hybrid microcircuits have become more

important with the advent of high power devices and the increased density
of devices on a hybrid substrate. The hybrid model is the concept that
lead to the derivation of the square, rectangular, and circular models.
The hybrid model provides a rapid and relatively simple approach to predict
the maximum temperatures reached in various devices on the hybrid sub-
strate. This model considers the effect of the heat transfer between all
device/device and resistor/device combinations, with modifications to allow
for both chip resistort and devices on heat spreaders. The model program
will not be presented, but the following commentary on the hybrid model
provides sufficient information for its derivation and implementation.
The hybrid circuit usually consists of a metal casing or package,
which consists of a header and cover. The substrate is attached to the
header, and the hybzid circuitry is fabricated on the upper surface of the
substrate. The circuitry can consist of thick and thin film resistors,
capacitors, inductors, conduction paths, and assorted semiconductor devices.

Most semiconductor devices on the substrate have a defined heat gener-

ating region. This rerion is normally considered to be about 50 percent of
the devices' total uppe. surface area. Resistors also have a heat generat-
ing region, but this region is a function of the way they are trimmed
(i.e., L shaped, laser or abrasive trimning). Various trimmings are shown
in Figure 42. Heat flows through the device or resistor, and substrate and
header, to the external header surface. When there is more than one heat
dissipaLing device or resistor on the substrate, there is often a thermal
coupling developed between them. When this coupling occurs, the junction
temperature of a device rises to a higher temperature than that produced by
the device itself. Figure 43 shows a basic thermal resistance model for a
device

where

Tj a junctical temperature of the device

O-, = thermal resistance from the device to the center of the sub-
strate
TS - midsubstrate temperature under the device
STCp - the portion of the substrate temperature due to other
devices and resistors
-CS - the midsubstrate to header thernel resistance
TC - the header lower surface temperature (ambiem..

The temperature source TCp is given by

'4 N
:.,T( li ] OlJPJ()
L

Jl
Ji

96
 where

Oij = the coupling thermal resiscan:e from device j to device or

resistor i
N - total number of heat dissipating elements on a substrate
'P - the power dissipation of device j.

4.

T11T CHIP
till RESITOR
• .. ~NEWTON "

KW•AT GENERATING
REGION

sn"MaDEVICE

Figure 42. Hlybrid Mtdel Heat [Link] Regions

QTi

Figure 43. Device

9-97
I7
 The heat generating temperature, Tji, of device i is given as

T =Tepli+ Pi(Odi+ e ) + Tc. (2)

J Sci

Two assumptions must be made to be able to derive a closed form

solution of the temperature distribution. The first assumption is that
rectangular-shaped heat dissipation can be modeled as a circular device
with the same base area. The second assumption is that the substrate
itself is circular, with a radius Ro that is equal to the distance from
the center of the device to the nearest substrate edge. Figure 44
illustrates both assumptions.
SThe radius of the assumed circular device is
..Thegiven, by

r Aibi (3)

where ai and bi are the rectangular dimensions. This assumption is valid

unless ai exceeds bi more than three times. It should be noted that
the assumption of a circular substrate with an area less than that of the
rectangular substrate will give a conservative answer.

"Using the circular models, the temperature distribution is given by

the following ordinary differential equations:

d 2dT 1 dT 2 T =0 (4)
dr r drX

S(5)

S (• + 'E+ %

where

S substrate thickness
K• = substrate conductivity
E = epoxy (under substrate) thickness

KE = epoxy (under substrate) thermal conductivity

H = header thickness
K = header thermal conductivity.

*• The equation applies for ro < r < Ro, with boundary conditions

T Ts at r = r0

dT 0 at r > RO.
dr
- ...- 9

•i.€,98
'A':

- - ', ".",,'
.. ,... . • .".,.". . . . .' ",;.".ft * •, ,• • • ,.,*",": : -*''.i' •Y -
 DEVIC i
-5-
- N

.__•,tSUBSTR,-' E /y

J'• MUTUAL HEATING AREA

'-Figure 44. Single/Multiple Device(s)

i• The solution of equation 4 is

T = ello (Xr) + C2Ko (Xr). (6)

/0
-- ,• Evaluating CI and C2 by applying the 6oundry conditions gives

1I(XRo0)1Io(X F) + I I(XR o)K o(Xr)

K-
T = - x TS (7)

--•where Io) Ii) Ko, and KI are modified Bessels of the 0th and first
... order. Thus, the midsubstrate temperature is given by equation 7 for
;7r < r < R and by T for 0 < r < r.
o-
0. 0 0
:,•jThe heat power for P is given by

P =KSX
K- Trdrdý (8)
• •mO r=o

/99

-.
Z-
 %;

iS When integrated, the temperature T, (for ro < r < Ro) is arrived at in

terms of the power dissipation P of the device.

"A(K1 (XR)1Io (Xr) + I I(XR0)KA (Xr))

r 1 r 1
K(XR
1 )2 -1 I 1 (XR )-2 K (Xro) + K,(Xro)
2 2
?\Jwhere1

-- :A!"27K A Sk rr
•%•s 0

esc is calculited by setting r = ro in equation 9. This is

calculated the same way for all devices and resistors on the substrate.

6d is calculated by adding the device thermal resistance to the

thermal resistance through half the substrates.
-v" S V G (10)
0
.d dr 2K ab K ab K ab
s v g
where

adr device thermal resistance

V = device epoxy thickness
KV = conductivity
G = conductor thickness
- K = conductor conductivity.

The device thermal resistance is calculated by a simple and conserva-

tive spreading resistance model. If rectangular heat dissipation region:

61 2 in a d+2t (11)
dr Kd(c-d) d c+2t

where

St = thickness of device
c,d = rectangular dimensions of heat generation region
K = device thermal conductivity.
d

If c = d (square)
6"• 2T (12)
0 dr (KdC 2 )(1 + 21)

If circular dissipation area, r =

'-,.'=(13) t
_ •
Odr Kdr(r+t)

100
v,•.,
t',

' . ' .
 Trimmed [Link] experience rather high surface temperatures. The
majority of this temperature is dissipated across the length of the cut and
the remaining wi4th of the resistor.

- W _ _- __ W

I I L I

_ i ii ii ii
LASER nR ABRASIVE L SHAPE

if the resistor is a chip resistor, (typically a resistor printed on a

small rectangular substrate material), the dissipation area should be
cal-ula,.ed. Then the chip can be treated as a device for all other
purposes. The thermal resistence to midsubstrate now would be
0 d fchip + substrate+ epoxy conductor (14)

If printed directly on the substrate, chip = epoxy = 0.

' •To account for a he't spreader, the heat generating region of the
device is projected to the top .Tf the ipreader using the appropriate
spreading resistance model. Figure 45 shows this principle.

The spreader is then treated as a device with the projected heat

generating region. Its thermal resistance to midk~ubstrate is

0d -e=
= dr
+0
spreader
+ 1/2 q
-,ibstrate
+06
epoxy
+06(5
conductor. (15)

If the chip is not eutectically b-nded to the spreader, an additional

epoxy must be added.

5.4 External Model

Analytical external thermal models have been designed, for the six sel-
* ected packages (side-brazed dip, cerami.. chip carrier, cerdip, flatpack,
hybrid, axial stud). The models were designed to relate the case temper-
ature measurement (selected measurement point) with the junction tempera-
ture for verification. These models are represented as nodal thermal equa-
tions, with each model consieei•ing the measurement point, the type of cool-
ing, end the exte:-nal environments.

101
 "# H

CNEW C

lo DNEW

bEVICE

SPREADER

D - D+2H
NEW 2
CNEW- C+ H

-EVICE , 450

2 IH
: HI
/- I
" "H 8 H
• -•i1 •"• . ...... - DN EW . . . . .. - *

EPOXY IF NOT EUTECTIC

jK•, [Link] ,,EA, ER

Figure 45.

The major consideration in model design is the identification of a

measurement point that is accessible and thermally related to the junction
temperature. The measurement point location has been defined as the geo-
metric center of the device for all packages where the center is an acces-
sible point.

102

P64
.4....,K ,%KA
'4 *

~~~
J.K.4.* ~ 1. 4')** K4'
% %*
.4 K4. AWN. ~ --
 The selection of the geometric top center was based on several major
considerations. The center of the top may not be the peak temperature
point of the device top, but access to the top is generally the most con-
venient and very easily definable. From an engineering standpoint, the
conductivity of the lid is extremely high compared to the rest of the pack-
age. The thermal drop across the lid is small in relation to the total
thermal resistance from junction to the measurement point (lid center).

The geometric top center of the device is not an accessible measure-

ment point for microwave devices because they are predominately stud mount-
ed inside a cavity. This positioning presents many complications in measu-
ring microwave devices directly. However, before the device is mounted
into an operating system, a thermocouple can be attached to the ceramic
ring near the bottom of the heat source. There is a much better conduction
path through the bottom than through the top. For these reasons, the bot-
tom has been selected as the measurement point for axial studded packages.

There are three predominant types of cooling to be considered for the

external model. They are 1) conduction, 2) convection, and 3) radiation.
Each cooling method is addressed in the following paragraphs.

Conduction

The basic approach to conduction heat transfer is the use of the

standard heat transfer equation

Qk 'k AT
where

Qk heat flow rate; degrees centigrade per watt

Ok =L -conductive thermal resistance
length of flow path
K f material thermal conductivity
A heat flow area
AT temperature difference.

The values for thermal conductivity (k to be used are shown in Table 30.
These values are shown at a particular temperature, since thermal
conductivity varies with~ temperature.
Convection
The basic approach to convection heat transfer is the use of the
* standard heat transfer equation

V ~ QhnOh (TS TF)

103

• ,-'.•:.'.,"
" •- •- /"•. "-•"-'-,•"•-
,. . i ":•";"•:•."• '"", "'. ,-'' -'-",--:'.' ,-;••:,'X ':•''',-'•'.N, '
4

where

Qh - heat flow rate; degrees centigrade per watt

Oh - I convection thermal resistance

9h = heat transfer coefficient

TS = surface temperature
TF = temperature of surrounding fluid, such as ambient air
L = length of flow path
A = heat flow area.

The heat transfer coefficients (0h) to be used are shown in Table 31.

TABLE 30. THERMAL CONDUCTIVITY OF TYPICAL

MATERIALS

Materials Thermal Conductivity

(watts per inch -
degrees centigrade)

Air 0.00066
Alumina (96 percent) 0.478
Amu(90 percent) 0.339
•.•,Aluminum 5.52
Beryllia 4.1
Copper 9.66
Diamond 9.0
Epoxy (conductive) 0.051
(non-conductive)
Ablefilm-550-1 0.0079
Ablebond-450 0.0091
Eutectic (gold-silicon) 4.5
Fiberglass 0.00122
Galium Arsenide
Glass (CV-111) 0.025
(7583) 0.029
G (KC-l) 0.034
Go ld 7.54
Gold (Glass Dieattach) 0.255
Kovar 0.419
Molybdenum 3.7084
Molytab 3.9
* Plastic (polystrene) 0.00381
Plastic foam 0.0043 - 0.0035
Platinum 1.77
4 Silicon 2.13
Silver 10.61
Stainless Steel 0.4318
"Steel 1.2192
Tin 0.44604
Titanium 0.45
Water 0.0153

•.. 104

44
- %"-"
 TABLE 31. CONVECTION HEAT TRANSFER COEFFICIENT

Cooling'Technique Heat Transfer Coefficient eh

(watts per square inch-
degrees-centigrade)

Free Convection (Horizontal Surface) 0.00181 -0.00368

High altitudes [21,336 meters (70,007 feet)] 0.00181
Sea level 0.00368
Forced air (20 CFH) 0.0109 - 0.0181

Forced convection
Air over plain fins 0.0219 - 0.10967
Air over interrupted fins 3 to 5 times higher than
plain fins

Liquid Cooling

Dielectric liquid 0.36774 - 1.4645

Water 1.8064 - 36.774

Radiation

Radiation heat transfer is the most complex method to be investigated.

The same basic approach is used with the standard heat transfer equation

R of Fs A(T T4)

where

QR - heat flow rate; degrees centigrade per watt

o - Stefan-Boltzmann constant (air - 0.37 pounds of force-feet
cubed per pounds of mass-square inches-degrees Rankin)
fR relative emissivity between the surface and the surroundings
approximately equal to the product of both emissivities
F - view factor between the part and the surroundings
ES
A - radiating area
ST - absolute temperature of radiating surface
.TS - absolute temperature of surroundings.

The view factor is the measure of how well the emitter sees the absorber.
It is a value between 0 and 1. Typical values are given in Table 32. The
emissivity also varies between 0 and 1. A perfect black body has an emis-
sivity equal to 1, while a perfectly shiny body has an emissivity of 0.
The emissivity of typical metals and non-metallic materials is given in
"Table 33.

105

ab
 TABLE 32. VIEW FACTORS FOR VARIOUS CONFIGURATIONS

Configuration View Factor

Infinite parallel planes 1.0

Body completely enclosed by another body; 1.0

internal, body cannot see any part of itself

- Two squares in perpendicular planes with a common side 0.20

Two equal, parallel squares separated by distance 0.19

equal to side

Two equal, parallel circular disks separated by 0.18

distance equal to diameter

TABLE 33. EMISSIVITY OF TYPICAL SURFACES

Surface Emissivity

Silver 0.02
Aluminum (buffed) 0.03
, Aluminum foil (dull) 0.03
Gold (plated) 0.03
' Gold (vacuum deposited) 0.03
Aluminum foil (shiny) 0.04
Aluminum (polished) 0.05
* . Stainless steel (polished) 0.05
0.08
0Chrome
Tantalum 0.08
"Beryllium (polished) 0.09
Beryllium (milled) 0.11
Rene 41 0.11
Nickel 0.18
"Titanium 0.20
Aluminum (sandblasted) 0.40
White silicone paint (gloss) 0.75
Black silicone paint (flat) 0.81
* Black vinyl phenolic (dull) 0.84
Lamp black 0.95
Magnesia 0.95
Grey silicon paint 0.96
Silicon 0.64
* Alumina (A' 20 3 ) 0.30

•', •" 106

1 .. ;
t;.e
 Ik
External Environments

The considerations for external environments are sh'wn in Figure 46.

The package represented in Figure 46 is the cofired side-brazed package,
D5, for which measurements have been made. The package measured data is
discussed in appendix 7. The external environments have already beer
addressee in the type of cooling discussion. The environments are [Link]-
tion, convection, and radiation. For the external area, cooling must be 4
applied and considered with forced air, still air (free air), heat sinks,
insulators, pins, and printed circuit boards.

RADIATION { G I Nt

LID (KOVAR)

BOND
TIN
(LEAD), AIR

P
ti

SEAL
\J
KOVAR A
(DRY NITROGEN)

RING BRA- E . f
CONVECTION
.6
/
~AND
RADIATION
/

GOLD PLATE

WIR

CON~TIOI TERMEOIATE MGOLD PLATE)

O
NTNvEcTION

"LIf
GAP OR HEAT SINK CONDCTION
IT -IARDN
OAROAI
lOUATION

(PACKAGE END VIEWI

IC
-NOT TO SCAI.-

Figure 46.

107

.%
• "..... . . , • ."•. ","• "" '.'•
" 'J" , ' •"• .";"•",•i.J•";v..•€ €..'.•.'. .... '.. .•.q.•'.'.?,•'.'(
 5.4.1 Nodal Programs

Nodal programs that model all six of the specified package types have
been developed. Their purpose was to establish a relationship between the
junction temperature and the measurement point. These programs solve a
network analysis in a way similar to that of the SINDA computer program.
The nodal programs also are based on the same modeling techniques as the
SINDA computer program. The techniques used to model these packages
involved separating them into integral parts and then establishing the
applicable dimensions and nodes.

The external model is nodal, which solved a network analysis. The

number of nodal regions in the packages are divided in a range from nine to
sixteen. Four of the nodes were designated as boundary or source condi-
N tions, while one was designated as the selected measurement point. The
number of nodes were kept to a minimum in order to keep the costs of the
analysis within the program constraints.
Several inputs were required to use the model. The inputs were
referred to as the boundary or source conditions. The specific boundaries
required were the ambient air, radiation sink, circuit board, and junction
temperatures. Supplying all these condition in degrees centigrade resulted
in the nodal model predicting the temperntures of the other nodal regions.

The nodal model can also be used to predict the junction temperature
by supplying the first three boundary conditions (ambient air, radiation
sink, and ofcircuit
applied) board temperatures),
the junction temperature in and the source (amount of power
watts.

Table 34 illustrates the inputs (boundaries and source) required for

the nodal model conditions. Using the model in these two formats results
in output data that is highly comparable. This comparability will be discussed
in the next section, external model correlation.

The materials used in the packaging were considered in the modeling

process, since the flow of heat depends on the conductivity of these mater-
ials. Taking these factors (node location dimensions, and material conduc-
tivity) into consideration, conduction calculations were developed and the 0,
nodal programs implemented. The nodal programs will not be provided, how-
ever. The conduction calculations, package diagrams, and node descriptions
" presented in appendix 6 can directly be used in the derivation of nodal
programs.
The side-brazed model was exercised considerably to assess the impact L
of the boundary conditions on the tempe•-t-..re of the
various nodes of
interest. As indicated by Figures 47 c,:. 48, the ambient air and the radi-
"ation sink do not appear to have a sigaif'Ocant impact on the temperatures
of the other nodes when the board temptrvt-ure was kept constant.
Maintaining the board temperature constant created, in effect, an ultimate
heat sink. There is a temperature delta of only 2 to S'C as the variable
temperature changes from 25 to 130C for all except board temperature. The
main temperature driver was found to be the circuit board, based on the

." " -108

W.I
 TABLE 34. EXTERNAL MODEL INPUTS -

Boundaries (Temperature) Source

(Power)
Model Conditions Ambient Air Radiation Sink Board Junction Junction

Predicted Junction
Predicted Measurement x X X X
Point

Measured Junction
Predicted Measurement x X X X
Point

701

I \..'•

'DESb601 x .---

-U0
-0 --- "
WoA'ON S14K - 25 C
30A0D A%)o
AMBENCON TTMPARA*I e HOe C
~50 Legend
A NODE 4 t
2x NODE 5

j20
40K- 7 7 77 > 0
40 60 so 1C 20 U
AMBIENT AIR TEMPERATURE - degrees C
Figure 47. Ambient Air Impact on Package Hodes .4

109 NODE

evidence presented in Figure 49. As the temperature of the board

increases, the node temperatures increase linearly with an approximate
temperature delta of 42% as the board temperature varies from 25 to
* 1300C.
<'.y,
109

-. 4
 a,70-

S601

AR 25 C Legend
BOARD AND AMBIkl A R 25 C
SJUNCTION4 tEWFEI•tURE" 110 C %.NODE 4 "k
S50 J x NODE 5 •.
- NODE 9

__.....- ....... -- CNODE

E NODElO
1 ;

S20 40 60 80 100 '20 140

RADIATION SINK TEMPERATURE - degrees C
Figure 48. Badiation Sink Temperature on Package Nodes

'20-1

9/ Legend
-I NODE 4

AMtIENT AI AJCION ~qiPRAUN

AN •ADIATI&ON
- 10SINK
CC 2$ NODE'~

.•"20 40 60 so0 toG I'Ct U0

"A A 10 -
figur.*e a..a49. fiur4.* B~r Teprtr b*c on ackge...e

~. **~***~* ~ CIto

~ C2~*"7 -
 The primary objective in developing the external models was to relate
the measurement point temperature back to the junction temperature, in a
format that allows a quick and easy verification that derating has occurred,
This has been accomplished through a graphic representation of the -'

relationship between the junction temperature and the measurement point

temperature for each of the six package types. These package curves,
discussed in section 5.4.3, Package Derating Curves, are applicable only
under certain conditions. These conditions are defined in appendix 6 under
the respective package types. The limiting conditions of appendix 6 for
the packages are: package size, pin quantity, materials, and dimensions.
These conditions, if not acceptable for a specific set of requirements, may
be modified by making changes to the conduction calculations (appendix 6).
PIPS
, 5.4.2 External Model Correlation
.Correlation of the external model was necessary to substantiate study
results. Test measurements were performed on a group of seven 40-pin side-
brazed ceramic packages, with power transistors connected as the actrve
chips. There were temperature measurement points on the package: lid
* (center), center lead, and end lead. The base resistor of each sample was
adjusted so that all packages were dissipating about the same power. The
main supply collection voltage was then adjusted to vary the power of all
the test packages. Both free air and circuit board environments were
measured at varying power levels. The results, conditions, test set-ups,
etc. of the correlation tests are in appendix 7.1.

In addition to the measurements made on the size-brazed package, data

extracted from the Martin Marietta Ceramic Chip Carrier Test Report was
used for verifying the ceramic chip carrier external model. The test was
conducted with two 48-pad carriers at four power levels. The test module
description, procedures, measurements, layout, and thermocouple location
*.: are shown for the Ceramic Chip Carrier Test in Appendix 7.2. Modal
programs were developed to model the conditions set forth in both the
side-brazed and ceramic chip carrier data so a direct correlation could be
made.

The correlation of the side-brazed package nodal model, with the

"[Link] measured data for the junction, lid, and center lead temperatures,
is illustrated in Figure 50. The predicted and measured temperatures in
this figure represet average values. Each computer iteration involved
specifying an ambient air and radiation sink temperature of 25*C, the
measured board teaperature, and the measured power level. It was observed
that the prediced temperatures were higher in all cases, indicating that
the modei represents warse case results. The largest temperature differ-
ences observed between the predicted and measured values for the junction,
lid, and center lead were 3.62, 4.25, and 5.34'C, respectively. The
""odels* prediction of the lid temperature was better than that for zhe
center lead by approximately VC. Bsed on these observations, it was
Mc;C• did Gais zte mwdv'., [Link] of the values for the junction, lid,
and ceuter lead correlated with the measured results at equivalent power
dismipation levels.

6 To show the effect of power on the measureinwnt point in both the side
.razed-package model and the actual measurements, Figures 51 and 52 were

-. .. 5 -. 44i
. . . . . . '. * . .
 plotted, using both the lid and center lead as possible requirement points.
In these curves, both the predicted and measured temperatures represent
average values. The model tracks closely with the measured values. Once
again, the predicted values were higher %'in most cases) than the measured
values, resulting in a worst case prediction. The largest variation
between the predicted and measured values occurred while using the lid as
the measurement pcint (Figure 51). The variation occurred at 2 watts, and
was 2.19°C. The resulting slope of the predicted line is 5.52 degrees,
per watt, indicating that the power does have an impact on the lid as a
measurement point.

* •Figure 52 employs the center lead as the measurement point, resulting

in data comparable to t' .t in Figure 51. The predicted temperature tracked
closely with the measured temperature, with the largest delta (2.47C)
occurring at 2 watts. The power also impacts the center lead as a measure-
ment point, as indicated by the slope of the predicted line (7.36 degrees).

Several conclusions can be made, based on data in Figures 51 and 52.

First of all, the power does have an effect on the measurement point in
both the model and the measurement data. This conclusion is illustrated by
the positively increasing slopes in the f'gures. Secondly, the power
impact is much less on the lid than on the center lead. This conclusion is
based on the comparison of the two slope values for the lid and center
lead. The slopi± for the lid is the smallest of the two. The model predic-
tion tracks more closely with the measured results using the lid, as
opposed to the center lead, as the measurement point.

140-
40 PIN SIDE BRAZED
DIP PACKAGE
V. 120
"1AMBIENT AIR= 25 C
RADIATPON SINK 25C•
100-

7'-'
go-

% I
CL a~~ 4slT193gE

0 40
1 2 'S4
POWER -watts

Figure 50. External Model Correlation with Board Measurement Test

( easurenent Point)

112

1:-,.¢ ..
*• , .. " " ." ......... ......
•hX,:•:•,-.,•..:•',,'
' " " "• " "'" "'" ... "• .... ." '" " " " .. '... "" " ' " "
 ~25-
ZI

E
,-,, M 15- I
I-

45
1
Power 3- watts

Figure 51. Junction minus Lid Temperature versus Power

.4.1

0
.4

1 2
0,

*-7.
r,.'-:-,versus Power - Heasured and Predicted
S~40 Pin Side Brazed Package
;• it llli ,I, • ," tilt, ,.i, ' at ,•a"' *i • i " • . .tl t. __) , "i l i l " I !il" ••Ia,• i ,-•

-- N
 Since the above dissertation concluded that the power has an impact on
the measurement point, the two methods of using the model were investigated
as to their impact on the resulting derating curves. Figures 53 and 54
show the effect of using the model with four boundaries or three bounda-
ries. Four boundaries involved supplying the ambient air, radiation sink,
circuit board and junction temperatures. Three boundaries involved supply-
ing the ambient air, radiation sink, and circuit board temperatures, along
with the power supplied in watts.

The legend in the two figures identifies measured and predicted tem-
peratures. That is, the four boundry conditions were inputted to the model
for the measured juntion temperature curve, and three boundry conditions
were inputted to the model for the predicted curve. For the predicted
curve the power was also inputted and the model computes the junction
temperature. Figure 53 plots the lid versus junction temperature, and
illustrates an excellent correlation between the two model variations, with
the predicted values representing worst case results.

Figure 54 plots the center lead versus junction temperature, and

illustrates a larger distinction between the two model variations. How-
ever, the model does track closely with the measured temperatures. It was
concluded that by inputting the power directly to the model, there is
minimal impact on the resulting derating curves. It was also decided that
r 4!the model can be used in both capacities, regardless of power, for the
determination of junction temperature derating.

The ceramic chip carrier nodal model was designed based on a 48-pad
carrier. In order to correlate the model results with the ceramic chip
carrier test report, the data on the 48-pad carrier was extracted from the
report and summarized in Table 35. As indicated in the table, two chips
were subjected to four power levels, ranging from 0.27 watt to 1.1 watts.
Measurements were taken at three locations (base, solder pads, and lid) and
theta values computed.

According to the carrier test report, the ambient air and radiation
were 80"C. The board temperature was assumed to be the solder pad tempera-
ture. This data, along with the power, was used as input into the ceramic
chip carrier model.

The results were then compared to the test data illustrated in Table
36. The predicted lid temperature (on the average) was within one-half
degree centigrade of the measured temperature. The predicted junction
temperature (on the average) was within two degrees centigrade of the
measured temperature. Based on these results, it was concluded that an
excellent correlation between the model and the test data exists for the
ceram-. chip carrier.

114
 100-

80s40 0
A ~I
60

., Junction Temperature - degrees C

:9;: Figure 53. Predicted Junction and Lid Comparison to Measured
•:"Junction and Predicted Lid Temperature
i," 40 Pin Side Brazed Package
"100-
0
E
A-! 50-

40-
, 0
40 68 0 100 120 140
Junction Temperature - degrees C
Figure 54. Junction and Center Leid
Pedicted Temperatsure
JunComparison and Predicted Lidte
Lead T
Temperature - 40 Pin Side aturer
Brazed Package

:• 40 Pin
0115Si~de

N o A N
 V)- 00-m

(a 'e .. a%0-a 4

A4

-~ 0000 00 0

0) 0

3a% mv E4)
00 n0 Nr rO% Ca
E-4- 1- '--

1-o IfS. 00 0%t

%C'

00O
4. .

C4 C4

E-4 0 C q)1
E-4-

4'00

00 unC%% mt

1-4 -

0'0
aa

434

C. 0 C'C- %D C44

v. 43T
43 0% LM q-O' wM
00 0; 'ON NVý

~ V

U)- "'

''.4.1-4 0 0016

q -~-4 -- C%
-4 ~ ~ ~ ~ ~ ~ ~ ~ ~ X 0
Ni1_____________________
'1
TABLE 36. CERAMIC CHIP CARRIER TEST DATA VERSUS MODEL

Temperature
(Degrees Centigrade)
Sample Power Solder Package Package
$
Number (watts) Pads. Lid Has"

Test 1 0.27 94.31 89.90 92.6 -

DAtat 2 0.27 94.00 90.10 89.10 92.4
1 0.54 103.68 95.80 .00.10 92.9
2 0.54 103 .27 96.00 93 .30 100 .40
, 0.8 114.27 102.60 10 8.10 98.,40
2 0.8 113.59 102.90 98.60 108.60
I ;.1 127.17 117.70 119.60 i06.30
2 1.1 126.26 112.20 107.00 119.90

Nodel I 0.27 92.94 89.90 90.08 92.45

Output 2 0.27 93.14 90.10 90.28 92.65
I 0.54 101.89 95.80 96.18 100.90
2 0.54 102.09 96.00 96.38 101.10
1 0.8 111.62 102.60 103.17 110.16
2 0.8 111.92 102.90 103.47 110.46
I 1.1 124.10 117.70 112.,48 112.09
2 1 1. 124.60 112.20 112.98 112.59

*Sjlder pad t..mperutureg used as an inpuit into the model

o Individual [Link] data points were input into the 0- mode.d
-Ambient air and radiation sink * 80 degrees [Link]
S" power. pad temperature-
NMeasured solder
- Neasured

"5.4.3 Package Deratin, Curves '.,

The derating curves developed for the six package types (side-brazed,
ceramic chip carrier, cerdip, flatpack, hybrid and axial stud) are the end
result of the external nudal models. They show the relationship between
the junction temperature aad the selected measurement point. The curves
are to be used in verifying junction temperature derating for existing
devices, based on the temperature of the measurement point. For new tech-
nology devices that will be housed in the same package types, curves were
generated to show the relationship between the base temperature and the
measurement point temperature. It should be noted, however, that the pack-
ages have been modeled assuming specific chip sizes. These chip sizes are
discussed in respective sections in appendix 6. Any other curves generated
will vary, based on the size of the chip. Additional limiting assumptions
"of appendix 6 for the packages, are: single package size, pin quantity,
materials, one cooling environment, and single heat output.

'5 Three curves were generated for each package type based on board temp-
eratures of 25, 55, and 85"C. A tolerance band was created for these cur-
"¾ yes by changing the ambient air and radiation sink from 25 to 85"C. This
was done to account for the model's boundary conditions. The desired temp-
5, eratures should fall within the tolerance band, permitting the verification
*• of derating. Interpolation can be performed due to the linear relationship
in the band.

The accuracy of two of the models (side-brazed and ceramic chip car-
rier) was proven by the correlation of the model output with measured test
data. The assumptions, rationale, and design used in developing these two
models were used in the development of the other models. Therefore the
"same accuracy is expected, but cannot be verified, due to the lack of test
,as

1 . . . -'
4,

*A'. 1m61 .% *. m * *~* %

 data for these package types. The exception to the accuracy expectations
4" will be the hybrid model. The large quantity of variales and the
complexities in hybrid design would render the unverified hybrid model a
best estimate.

[Link] Side-Brazed Package

The derating curves generated for the side-brazed package can be used
if the ambient air, radiation sink, board, and lid temperatures are known.
To obtain the board temperature, a measurement must be taken on the bottom
side of the board directly under the device. Figure 55 can be used to
determine the related junction temperature, and establish whether derating
has been implemented. The curves are applicable only when used in conjunc-
'. tion with the specifications and assumptions described in appendix 6.1,
Side-Brazed Package. The assumptions are based on the package being a 40
pin side brazed package with specific package, attachment, and chip
(device) dimensions. The nodal conduction equations are written for these
specific dimensions and materials. The assumptions can be changed to apply
to certain specifications by modifying the conduction calculations (alAo in
appendix 6.1).

Figure 56 should be used for new technology devices to establish the

proper relationship between the base and lid temperatures. The curves in
Figure 56 represent a typical 40-pin package with all internal leads con-
nected.
120

100 --~~0100
0,1- .

• "U .v**'.'*- .,',-""

CL

::•.8
E 4W 9 AMIISI ANo A
to "M@K I ,o t
UAWMOw
SINK COMMW Legen
AT 25 KEom 4 - M004ae rdw C011nSAY F"e
33 'Q95C PCREAS(S.D TWPOWATU3ZI0E0WBOARD a 2C
egn
40 - SOARO - U C

; 0' 80' 90 100 !10 i20 130

Junction Temperature - degrees C
Figure 55. Junction Versus Lid Temperature - Predicted
40 Pin Sized Braxed Package

oftý f".1110
...
-,

.%I
 120-

moo~oo ... o.•, /

E
;"
Go-

•,• ~~40 "I..

S70 40.. 100o
so Temperature
SBase '10
- degrees_4o
C '13

Figure 56. Lid versus Base Temperature - Predicted

Brazed Package
Pin SideN"W40

•[Link] Ceramic Chip CarrierU &

The derating curves for the ceramic chip carrier are shCw in Figures
and 58. The junction versus lid temperature curves (Figure 57) are to
,•F57
be used for existing devices. The base versus lid temperature curves (Fig-
ure 58) are to be used for nev technology devices, or where this relation-
S~ship needs to be established. The assumptions and specifications made when •
developing this model are presented in appendix 6.2, Ceramic Chip Carrier,
7and andbe Tdified according to need. The nodal conduction equations are
based on specific material and package and device dimensions. It should be(Fig-
noted that the solder pad temperature is substituted for the board temperlat-
ture in this model. This assumption was made based on the fact that there
n devareno leads going through the board, and that the thermal gradients (if
-*" any) through the board are ignored.

,[Link] Cerdip Package

41
od aFigures 59 and 60 represent the dersting curves for the cerdip pack-
The
turage. ausmpe
model.T his tion as used in modeling this package are

•!: ~in appendix 6.3. Applicability of the curves in Figures 59 and 60 are.:
along with The enodal
thermlhe air,
ambientpqua-
ardependent board,asrougptions,
sink, these
radiation upon andrid temperatures. conduction

tions are based on specific materials and package and device dimensions.
The board temperature measurement location is specified as being on the
bottom side of the board directly under the device.

119

%;I
 100

~80

so
S• 60.
S• ~ ~~~~of&&#
I Io# at i o bt;o
@ewIe l 140
o 46 #"o Iet#$to a I Ia O O •

HOM AI1
AAit~d NE & ATI~ON
3,NK CONSTAr
,n AT 25 0 GRm' C ll
E 40 M ri .OwOruz

20 70i0 soi 9 100 110 120 130

Junction Tempera3ture - degrees C
Figure 57. Junction Versus Lid Temperature
- Predicted
Ceramic Chip Carrier Package

a'.,
100

sao

4,A,-
.
20 a

E 4

*eend

I%
60 , so
BasTempOrcturS 100-der 110 sC'2o
so
40
Figure 58. Lid versus Base Temperature
Ceramic Chip Carrier package -Predicted

,. ",*se"emeraur
-4 degee C.
"q120 *~ur
58 L d qvesu Base Tep -tr . Predicted.
ra [Link] 4 -Ch *arie t
., . .'.
a * 'a.~* ,*.
"
120 """ *. '
Aj,

A 120-

00

go-

*0 .. C**. 9

- ~E
10 oo
MMAM&MAM RMUMLegend
HCONSTANAT 25 KOMC
SIN NOM -25 C
TDMaTUR
NONI M34AOA aSC
40-..................I...,. ... USU mm

Junction Temperature - degrees C

Figure 59. Junction versus Lid Temperature - Predicted
Cerdip, Package

'207

0) 4

9D *D 000 wo .%..too

9."b

E *60-Lgn
~~~R
"U sow U IS&RMAI0

70 so g0 100 110 120 130

Base Temperture - degmaes C
Figure 60. Lid versus Base Temperature -Predicted

*Cerdip Package

121

% -. *****
 [Link] Flatpack Package

The derating curves for the flatpack package are presented in Figures
61 and 62. The flatpack modeling techniques (assumptions and specifications)
are addressed in full detail in appendix 6.4. The same conditions hold for
using these curves. The correct assumptions must be identified, and the
ambient air, radiation sink, board, and lid temperatures must be known.
The nodal conduction equations are based on specific package and material
type and dimensions. The measurement location for the board temperature is
specified as being on the bottom side of the board, directly under the
device.

[Link] Hybrid Package

The derating curves for the hybrid package are specified in Figures 63
through 68. In Figures 63 and 67, the derating tolerance bands for the
different board temperatures overlap one another. Therefore, the band for
each board was plotted separately in Figures 64 through 66, and Figures 68
through 70.
The hybrid package presents a special group of problems. Once the
hybrid is sealed, there is no way to tell what is inside. Therefore, it is
* necessary to know what elements make up the hybrid device prior to sealing.
Because of the quantity and variety of elements composing a hybrid, the
modeling of this package involved averaging the area as one siugle heat
source. The information required in the other package types (ambient air,
*_ radiation sink, board, and lid temperatures) is also required for the
1201
MM~ AUM3E AMRRAPAI
/ SN7 aONSNT A IM l

too
100

* *.... .

-- 80-

l•AA. -"1I.'="'' ,.::#

E

*'-"i.:' -_..,.,: "' t

70 so go 100 110 M s
Junction Temnpeature degrees C
Figure 61. Junction versus Lid Temperature -Predicted

.,.

:! -.
Flatpack
. .* . .

70*'~*
4:,
Package
. . . .. . 4 . . . . . ,'

gO.0
..

.0
,a •** .~ . ,.

122 .0 12 1*30
4,. .4

.~ 1

.• .• r,.,-IN .° . . o . • . ',., - .• t ' ' *o•• ' ,,.% %:. % , %... %,. ,. , ,• * * , . * - ?
 ip~

Sgo -

70 80 90 100 110 120 130

Base Temperature - degrees C
Figure 62. Lid versus Base Temperature - Predicted
Flatpack Package

S~140

£ioo-

xz0• 5 .. ''s.I.. moms••"

-- ••70 slo go 100 Ito 120 1M

-. ,,;,Junrflon To -- cdre - dogmae C
i•".Figure 63. JunctiLon versus Lid Temperat~ure - Predict~ed
Package S

" 123

I.
IA

120-

.100-
V

1o-

404

Junction Temperature - degrees C

Figure 64. Junction versus Lid Temperature - Predicted
V. Hybrid Package

120-

SO-
V -lop49

, A.,

-MENI

70 s' i 0 1
Jurmfln T~nwvftr - clgr*s.

Figure~~~~%.
65 ucinvru*i eprtr rdce
Hybrid Packag

,12
V
E4 1400

(47

IW AM/MM M t ¾N

70 so1000 11 3

20-

1101

Juntso Temperature - degrees C

Figure 66. JuLiod versus Lid Temperature- Predicted
Hybrid Package

1120

V~-
, Aw
 120-

C..o.".. ..

100

•.'7

100

MMOAW0
AMUT.
,wuI' WR&£AWM1O
Am

3'TOW0MPA 7W Doiw=[Link]

70 so 90 100 11 120 130

Bose Temperature - degrees C
Figure 68. Lid versus Base Temperature - Predicted
Hybrid Package

120-

* 100"

I.'.'.,.:..-8,'
"!0 to- 4 .. •.**...
* ,.."..*'....I,

*,,*".*, ,'" "" ~ii 1 d~~

,s
I"M" A" MO RADI•lO

30 1,WA WU

"70 80 90 100 110 120 130

Base Temperature - degrees C
Figure 69. Lid versus Base Temperature - Predicted
Hybrid Package

126

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. . .. . . . . . . . . . . . . . . . . 2
 140-

I 120"

o,.o.....

-'•• ~ ~~100' ,.:.'.-"

S•,•.~~',5.':. ".-

i ;-- NOMK A~I AM & RAMitON

..........................................
A
Legen

70 . 90 100 11o0 120 130

Base Temperature - degrees C
Figure 70. Lid versus Base Temperature - Predicted
Hybrid Package
hybrid. The board measurement location is the same. The basic assumptions
made in the modeling process are in appendix 6.5. Since hybrid packages
are very complex and are usually custom designed, a detail internal thermal
analysis should be required to be perforwed by the vendor.

[Link] Axia'. Stud Package

The axial stud package is a special case, since the devices are gener-
ally not accessible for measurement. In most cases, these devices are
mounted inside a cavity or heatsink. This creates a difficulty in making
measurements. The derating curves for the axial stud package type were
generated, based on certain assumptions and specifications which are
presented ir appendix 6.6. The actual curves for axial stud package models
are in Figures 71 and 72. The board temperature is replaced by the heat-
sink temperature in these figures, with the measurement location being
•
.adjacent to the ceramic ring. The measurement point identified for the
purpose of relating back to the junction temperature is a point on the
"ceramic ring near the bottom of the device. This point is only measurable
* before the device is mounted into an operating system.

5.5 Measurement Equipment

The accuracy of the measured device temperatures is directly dependent

* upon the device or method used to obtain the measurement. There are numer-
ous measurement devices available. The simplest method is the use of
thermocouples. If a thermocouple is used for measurement, the best accur-
acy one could expect wuLd be in the 1 to 2"C range, due to the limitations

127

a24-
 100

W4W

E NO1T AND=I AM kRADI~MON

70 so go 1o 11 120 130
* Junction Temperature - degrees C
Figure 71. Junction versus Ceramnic Ring Temperature -Predicted

Axial Stud Package

100-

go-

* & .0-

4 qn

40'-
 of the thermocouple itself. The cost involved in using thermocouples is
associated with the recorder. The recorder allows for approximately six to
twenty simultaneous thermocouple readings, and costs about $2000.

A second simple, but less versatile, method is the use of temperature

labels. The label method can only be used where there is sufficient space
to apply the label. The sizes generally available range from three-
sixteenths of an inch to approximately five-sixteenths inch in diameter
spots and rectangular labels approximately 3/4 by 114 of an inch. The
rectangular labels could be applied to a variety of dual-in-line packages,
and the spots to TO-5, TO-91, TO-99, TO-100, TO-3, and TO-66 packages. The
labels adhere to the surface of the object to monitor its temperature. As
each heat sensitive spot is exposed to temperature, the dot changes temper-
ature in approximately one second, with a plus or minus one percent accur-
acy. The temperatures available are generally in 10C increments. The dot
can can only be used once.

A more modern and sophisticated method is the use of infrared (IR)

temperature probes. These devices can be found in a wide range, from hand-
held, portable, self-contained to fixed-mounted instruments, with a broad
family of indicators and controllers. The instruments available can result
in much more accurate and repeatable temperature measurements. Table 37
shows the specifications available for such instruments. The cost of these
instruments, depending on the specification requirements, ranges from
approximately $350 to more than $2000. The IR technique is not the least
expensive way of measurement. Instead, it is an order of magnitude greater
"than other methods. The IR technique also allows for only one measurement
at a time. Testing problems emerge with using the IR temperature probes,
when access to the printed circuit board is not permitted in the system
configuration. In this case, the IR method would not be recommended, and
thermocouples would have to be used.
TABLE 37. INFRARED TEMPERATURE PROBES SPECIFICATIONS AVAITABLE

*.• Specification Range (Typical) -

Accuracy + 0.5 percent of reading or scale

Repeatability + l'C or I1F; + 0.5 percent

Temperature ranges -30°C to 1100C

(selection) -30°F to 2000*F

Power requirements ac or dc

, Display analog or digital

Target spot size Factory set and/or varies with

operation distance
Operations distance 2 centimeters to infinity

129

"., A 4
 6.0 COST VERSUS RELIABILITY

The cost of reliability is a very complex and controversial subject.

The complexity is due to several factors which interact and drive both the
cost and reliability. The concroversy is a result of the reliability fund-
ing level versus contract reliability analysis and component requirements
on a particular program.

The first factor to be considered is component temperature. As the

temperature of a component, specifically'microelectronic devices, increases,
*-2 the failure rate also increases. Figure 73 shows a curve' plotting junction
"temperature versus failure rate multiplier. This curve is based on a rel-
atively simple class B digital low power Schottky TTL quad 2-input nand
-A gate (generic 54LS00). This simple, yet common, gate was selected so other
impacting parameters can be assessed against the same device. The failure
rates used to derive the multipliers are shown in Table 38. The computer
program that derived the failure rates did so in accordance with MIL-HDBK-
217D. To derive the multipliers, the quality level B line was followed
across the temperature range from 15 to 120*C. Since a class B component
was used to produce the curve, a check was made to see if the multipliers
hold true for any quality level. The largest error found was approximately
0.05 percent at 120*C for a class S component.

4--.

-- w.
/

I4-

-LJ

L&..

0 20 40 60 80 100 120
TEMPERATURE - DEGREES C
Figure 73. Temperature Impact on Failure Rate

"130

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 The next factor to be considered is the relation of component quality
level and its impact on the failure rate. Figure 74 graphically shows this
relationship. The same digital low power Schottky TTL quad 2-input nand
gate was used to derive the multipliers. Again, the failure rates are
shown in Table 38. Table 39 is a copy of MIL-HDBK-217D quality factors for
microelectronic devices. The table gives the description of each quality
level addressed.

40

ix

w ?0

Li Figure 74. Quality Level Impact

c, on Failure Rate

0
D C1 C B2 B1 S
OUAUTY LEVEL

TABLE 39. n 0 , QUALITY FACTORS

"Qlual ty I•ieStr ipt i on TI

- /Irured in hell accordance with Class S requirements.

CIL-1-11510, 0.5
.1 I'rncured in f'tll .acordance with MIL-M-38510, Class B requirements. 1.0
1-i i'r~te'rli-r' Iill hill 4ccorrtancr with MIL-M-311510, Class B requirements 2.0
S,',pt that devirce is not IkterI nn Qualified Products List (OPL).
the devict! shall be tested to all the electrical requirements (para-
mroters. conditions and limits) of tho applicahbe MIL--38510 slash
..h..nt. No walver% Aire allowed except current and valid qeneric
dita" may be su)bstituted for Groups C and D.
0-I Procured to all the screening requirements of MIL-STD-883, Method 5004, 3.0
Class B and in accordance with with electrical requirements of IL-M-
38510, VESC drawings, or vendor/contractor electrical parameters. the
device shall be tested to all the quality conformance requirements of
MIL-STO-P.133, Method 5005. Class B. No waivers 'are allowed except current
and valid generic data"' may be substituted for Grops C and 0. This
rateiory applies to ODSC drawingJs and cnntractor prepared specification
contrnl drawings (SCI)'s) containing the above R-i screening and
quality ronformance reep•irements.

l-? I'recur'd to venyjor's "lq'ivalent of the screeninq requirements of MIL- 6.5

oID-neii, Pr-thnd .r5l"4. Cla%.a8, and in accordance with the vendor's
[Link],•l parwi'tstr% windvendor's equivalent quality conformance require-
",onts of 'ML.-.SO-0,13., Wthnd 5005. Class B. Applie. to contractor
propa'red SCD's containing the [Link] R-2 scre•ning and quality

r;
Pi',.ired it, fli ,accrnlnor•i with M1i-M-18510, Class . rrivllremints. 8. f
r,-I r'nro•r,,Id i, -rrer-inq rqeilrement, of MIL-S'f)-8P.3. Method 5004, Class C 13.0
la•rII¶,rl,,[Link] ,oisireveent% of Method 5005, Class C. Cenr'e* data
,ly he sdI)stituttd for Grops, C1.0I
1 - I-er-etically ,,al" part with no .creeninq beyond the manufacturer's 17.5
regular quility as-surance practices; parts encapsulated with organic
' itrterial.'
n-I frx,..mry,.i. (nr ron-,,iI Standla-r) part. encapsulated or sealed with 3s.0
L')rgoAnc manterials (e.g., epoxy. silicone or phenolic).

133
 Finally, the cost of the same device is assessed against the quality
levels previously discussed. The cost data against the subject device was
provided by the Martin Marietta component engineering group. This data was
based on an average cost from two large semiconductor manufacturers for the
specific quality level. IThe average cost was then converted to a multiplier
using the Dl quality level as a base (1.0). A Dl quality level is a com-
mercial or non-military standard component. Figure 75 shows the quality
level impact on component cost by plotting the cost multiplier against the
"quality level. The points on the figure marked by a triangle (A) indicate
actual data points obtained. The curve is then plotted across all the
quality levels.

20

15-

E5
D 10
Figure 75. Quality Level Impact
on Cost

S0 1
D1 D CI C B2 B1 BO B S
QUALITY LEVEL

Additional cost factors which impact reliability are contained in the

design process. The design process, in relation to derating criteria,
encompasses the type of cooling necessary and addition of heat sinks to
%J reduce the component temperature. The degree of reliability in design then
is part of the quantity and quality of analysis. Both are from the design
and reliability group. The driver becomes the requirement imposed by the
product specification, or the importance and visibility of reliability by
the contractor. An example of in-depth analysis of the microelectronics
may include investigation of all parameters that vary with temperature.
Figure 76 shows the variation of silicon conductivity with temperature.
This figure, coupled with the failure rate multiplier figures previously
discussed, could be used to determine the method of cooling and necessity
of heat sinks. A less thorough analysis may be the accomplishment of a
reliability prediction using average temperatures and stress levels.

The specification driver is defined through the imposition of MIL-STD-

"785B or MIL-STD-1543, notice 2. Through the imposing of specific tasks or
paragraphs of the military standards, a minimum level of reliability is
established. According to data collected in RADC-TR-83-13, "Missile and
Space Systems Reliability vs Cost Trade-off Study," the average cost in

C134

.- - '
 man-months per year, varies slightly across program phase. The reliability
program cost can be estimated as a percent of engineering l4ibor per year
for the three major program phases. The FSED program phase averages 4.3
percent of total engineering labor for the reliability program. The pro-
duction and validation program phases average 4.4 and 5.0 percent respectively.

S~Figure
76. Silicon Thermal Conductivity
S~versus Temperature
I
•

The major cost drivers, according tc RADC-TR-83-13, within the reli-

ability program related to MIL-STD-785B, are:
I Parts program 28.3 percent

2 FPACAS/FRB 100 e 11.3 percent•. 30 •0.4

TEPEATRE-"EGEE
3 Engineering support 14.0 percent
1'.........%.&.........A

,•4 FMECA 4.7 percent .

,5 Testing 6.0 percent

! 6 Analysis 8.7 percent ,.

S135
 SThese average cost driver percentages are based on the average across

FSED, production, and validation phases of a program. At this point, none

of the referenced funding levels for reliability include engineering sup-
port from engineering to reliability, or any engineering performed analyses.

In order to reduce program costs, part quality level reduction is

often considered. The reduction of part quality level, from mil to com-
mercial, has impacts on failure rate and cost. The failure rate impact has
been shown previously in figure 74 and related cost impact in figure 75.
Derating cannot be used to compensate for using parts of a lower quality
level. The derating levels specified (I, II or !II) are not based on part
ON quality. The levels are based on mission criticality assuming the proper
quality part has been selected. Component derating can in no way account
for or make up for poor quality.

The subject of cost versus reliability can be summarized as a complex

relationship. It is not solely controlled by the contractor or customer,
design engineer, or reliability engineer. The basic tools are available to
"produce a good reliable piece of hardware. Without the proper time span
and funding, however, something less is often accepted. Depending upon the
program phase, the commitment assumes different emphasis, i.e., analytical,
test, etc. But each phase commitment is reduced to two basic constraining
factors, cost and schedule. In spite of the restrictive cost and schedule
and schedule constraints, the reliability function must be introduced at
the early phase of the program. Continuity must be maintained. The relia-
bility tasks, as a minimum for each program phase, are specified in MIL-STD-
785B appendix A, Table A-I. These tasks should be strictly adhered to.

4.

-'4

- .-,13

'4S..4• ,. .•, . .% .'. .• : . . . .-. .. , ; . . , •,', ,., . ,.• . . .:• , . •, , • • • : . .•. . . .. . . .•

J t
 7.0 MI1LITARY STANDARD FRAMEWORK

The final specific task identified in the program approach was to

develop a military standard framework. The framework is intended to be
used for the creation of the standard for the derating of electronics and
electromechanical devices for Air Force application. Figure 76A shows the
outline for the military standard.

Figure 76A

OUTLINE OF MILITARY STANDARD

1.0 SCOPE

1.1 Purpose

1.2 Application of Standard

L.2.1 Content of Standard

1.2.2 Tailoring

2.0 REFERENCE DOCUMENTS

2.1 General

3.0 DEFINITIONS

4.0 GENERAL REQUIREMENTS

4.1 Equipment Deratiag Levels

4.2 Equipment Environments

5.0 DETAILED REQUIREMENTS

I" 5.1 Microcircuits

5.3 Diodes
5.4 Resistors

5.5 Capacitors

5.6 Surface Acoustical Wave Devices

6.0 APPENDICES

(Examples of Parts Derating)

137

".7
 8.0 CONCLUSIONS AND RECOMMENDATIONS

8.1 Conclusion

The primary objective of the Reliability Derating Procedures program

was to develop the framework for the creation of a military standard. This
standard is to be for the derating of electronic and electromechanical
devices for Air Force application. This was accomplished through the in-
vestigation of specific areas, such as the relationship of case tempera-
tures to junction temperatures, the development of derating standards for
selected advance technology devices, the creation of thermal models, the
derating thermal model verification through data collection and testing,
and the relationship of reliability to cost. Based on this investigation,
several conclusions were drawn which led to the accomplishment of the pro-
gram's overall objectives. These conclusions are:

1 Standardized derating criteria is greatly desired by industry,

sivce industry does not have such criteria available at the present
time.

2 The development of derating standards for the advanced technology

devices did not produce any astonishing results.

3 The internal mcdel is particularly useful when a ball park predic-

tion of the thermal resistance from the chip junction to the case
bottom (ejC) is desired for devices of new design.

4 The heat spreading angle involved in the internal model calculation

has a significant impact on the Ojc. However, correlation
of [Link] could not be ascertained, due to program limitations.

5 There are many variables involved in thermal modeling. The number

of variables necessitates the modeling of specific package types,
as opposed to general ones.

6 The external model is applicable only to specific package types or

configurations.

"7 Both models (internal and external) can be easily modified to

change variable conditions to meet particular needs.

8 Two external models were verified through test data, resulting in

an accuracy of approximately 4"C.

9 The remaining external models were developed with the same assump-
* tions and ground rules as the two that demonstrated such a high
correlation with test measurements. It can be expected that these
remaining models are accurate (except hybrid external model).

10 The hybrid package presents a special group of problems. Since

"hy}arid packages are very complex and are usually custoa designed, a
* detailed internal thermal analysis should be required to be
performed by the vendor.

138

Q..
SAV..
I , .'%ý4l,% .4 % ¶** '
 11 The methodology for verifying junction temperaLure derating
requires the identification of a case measurement point. The point
chosen for all pnckages, except the axial study package, is the
geometric top center of the lid. The axial stud measurement point
is on the ceramic ring close to the heat source.

12 The lid category was investigated as a possible measurement point.

It was determined that the lid temperature tracks more closely with
the junction temperature.

' 13 In terms of reliability versus cost, it was determined that the

reliability function must be introduced at the early phases of a
program. Also, continuity must be maintained, in spite of the
restrictive cost and scheduling constraints.

8.2 Recommendations

"All the objectives set forth for this program were achieved. However,
during the course of the program, areas deserving further investigation
were identified. Those areas could not be investigated in this study due
to program limitations. Instead, a series of recommendations have been
developed for possible implementation into future work in this subject
area:
.N"

"I Additional package types or configurations should be modeled in

"order to extend the data verification base.
2 Additional data from test measurements should be obtained to
further validate the models presented in this study. Any
additional models required should be created.

3 Additional investigation of the heat spreading angle is warranted,

due to its impact on the resulting thermal resistance.

4 In an effort to ascertain industry acceptance and possibly create

the surfacing of additional data, the Air Force should disseminate
the results of this study to all those concerned.

.* •.39
I' N

-
 APPENDIX 1.0

BIBLIOGRAPHY

This bibliography is a listing of the references used in the derating study.

The listing is alphabetical, generally by author and with the company affiliation

referenced parenthetically.

Advanced Electron Device Technology Status Report, Office of the Under Secretary
of-"- Tense for Res~arch' and Engineering, Advisory Group on Electron Devices
Report Number 186. Washington, D.C., December 1981.

Amoss, John W. "Transient - Thermal Behavior of Pulsed High Power IMPATT and
TRAPATT Diodes" Report. Georgia Institute of Technology, June, 1979.

Arsenault, JOE., and Roberts, J.A. Reliability and Maintainability of Electronic

"Systems, Computer Science Pre3s, 1980.
Ayyagari, M.S., Heaton, J.L., and Hansen, N. "Reliability of High-Power Pulsed
IMPATT Diodes" Report, Microwave Associates, Inc., Burlington, MA, November, 1981.

Baxter, G.K. "A Recommendation of Thermal Measurement Techniques for IC Chips

and Packages, Proceedings International Reliability Physics Symposium,
April, 1977, pp.--U4•2T1.

Bobek, Raymond C. "Product Evaluation Report on the Zilog Z8010 fMMU" Report,
Integrated Circuit Engineering Corp., Scottsdale, AZ, April 1982.

Bowma, L.S. Failure Mechanism Study of GaAs Technology, RADC-TR-81-180 (Hughes

Aircraft, Fullerton, CA).

Braun, Cedric R. "Rad-Hardening Faces the VLSI Challenge, Defense Electronics,

March, 1962, pp. 110-116.

Brummett, S.L., [Link]. Reliability Parts Derating Guidelines, RADC-TR-82-177,

(Boeing Aerospace, Seattle, WA).

Chang, Hsu, Editor. Magnetic Bubble Technology: Integrated-Circuit Magnetics

4.. for Digital Storage and Processing. IELL Press, New York, NY IV9b (IM-
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Chudobiak, W.J., [Link]. "Effect of Jun-tion Temperature on the Output Power

of a Silicon IMPATT Diode" IEEE Proceedings, Vol. 60, March 9182, pp. 340-341
(Commun. Research Center; Ottawa-,Untaro).J

Crook, Dwight L. "Method of Determining Screens for Time iDependent Dielectric

Breakdown." Annual Proceedings - 17th Reliability Physics Symposium, April
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"141

-. 4.
 "English, A.T. and Melliar-Smith, C.M. "Reliability and Failure Mechanisms of
Electronic Materials," Annual Review of Materials Science, Vol. 8, pp. 459-495
(1978).

"Folberth, O.G. "Interdependence of Geometrical, Thermal, and Electrical Limita-

tions for VLSI Logic." IEE Journal - Solid State Circuits, Vol. SC-16,
"February, 1981, pp. 51-53. (IBM; Boeblingen, W. Germany).
Gallace, Larry J. "Reliability of Plastic-Packaged CMOS Devices.': Solid State
Technology, Vol. 23, September, 1980, pp. 102-108. (RCA; Sommerville, NJ).

Gerhardstein, A.C. "Magnetic Bubble Error Correction Study" Report. Texas

Instruments, Dallas, TX, January, 1980.

:G. Graham, E.B. and Gwyn, C.W. Microwave Transistors, Prentice-Hall, Inc., 1980.

Grovender, S.L. "QUIP System Approach." IEEE Proceedings - 31st Electron

Components Conference, May, 1981, pp. 31-35. (Minn Min & Manut. Co.; ýt. Paul, MN)

Hartley, Robert. "Product Evaluation Report on the INTEL 8086, 8088, and the
8288" Report. Integrated Circuit Engineering Corp., Scottsdale, AZ,
November, 1981.

Hartley, Robert. "Product Evaluation Report on the Harris HMI-6100 12-BIT

Microprocessor" Report. Integrated Circuit Engineering Corp., Scottsdale,
AZ, November, 1981.

Horak, Joseph B. and Mindock, Ralph M. "Temperature Effects Upon Partially and
Fully Depleted Silicon Photodectectors." Proceedings - Electro-Optical
Systems Design Conference, May, 1971, pp. 357-.57Z (Texas Instruments, Dallas, TX).

Ito, C.R., [Link]. "240 GHz IMPATT Diode Development" Report. Hughes Aircraft
Company, Torrance, CA, June, 1979.
Kennedy, R.D. "Surface Acoustic Wave Devices." Quest, 1976, p. 2. (TRW Defense
and Space, Redondo Beach, CA).

Kim, S. Ul. "Instability and Failure Mechanisms of Small Area, Nitride-Defined

Schottky Barrier Diodes, in LSI Applications." Annual Proceedings - 17th
x•. Reliability Physics Symposium, April, 1979, pp. 226-233. (IBM; Essex
junction, VT1.
Laermer, Lother and Schenk, Robert. "Large Scale Integrated Circuit (LSI) Module
and Higher Level Packaging Study for MDC Program" Report. Singer Company,
Little Falls, NY, December, 1971.
Lash, K.B. Reliability Evaluation of Schottky - Device Microcircuits, RADC-TR-80-5,
(Hughes ArT-iaTt , rT1ron, CA},

Macksey, H.M. Reliability Evaluation of GaAs Power PETs, RADC-TR-80-124. (Texas

Instruments,M f,-7"7T .
Mains, R.K. and Haddad, G-1. "Capabilities and Potential of Millimeter Wave
IMPATT Devices" Report. MichigaA University Electron Physics Lab, November, 1982.
Malik, Sushi] K. "Role of Reliability and Accelerated Testing in VHSIC
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Vol. %.HMT-5, MSrc-k , pp. .oughkeepsie, WNV.

"142

Air *V.ý-4.? _ ___

 Mann, J.E., [Link]. "LSI MMOS Random Access Memory Reliability Characterization
Study" Report. Rockwell International, Anaheim, CA, June, 1982.
Masse, D., [Link]. "EHF GaAs Double-Drift IMPATT Diodes" Report. Raytheon
Company, Waltham, MA, December, 1979.
MIL-HDBK-251, "Reliability/Design: Thermal Applications," 1978.
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* Morrison, G.N., [Link]. RADC Thermal Guide for Reliability Engineers, RADC-TR-
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(National Bureau of Standards).
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Prince, John L., [Link]. "Performance of Digital Integrated Circuit Technologies

at Very High Temperatures. IEEE Transactions - Components Hybrids Manu-
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Design." IEEE Transactions on Reliability, Vol. R-32, April, 1983, pp. 106-110.

Ramamurthy, V., [Link]. "Temperature Rise in Microwave P-I-N Diodes: A Computer

Aided Analysis." Solid State Electronics, Vol. 24, May, 1981, pp. 445-453.
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143

l".
m.* [Link]*
11• Rosenberg, Robert L. "Thermal Shearing Effects on the Temperature Stability of
SAW Devices," IEEE Transactions - Sonics Ultrason, Vol. SU-27, May, 1980,
pp. 130-133 (BFeTTiCabT omde1, NJ).

"Rossiter, Thomas J. "Dynamic Thermal Properties of IMPATT Diodes," IEEE Pro-

ceedings - 11th Annual Int. Reliability Physics Symposium, April, T5,
'".4 pp. 2/5-29'. (RADC; Griffis AFB, NY).

Schelling, Arthur W. and Striny, Kurt M. "Reliability Evaluation of Aluminum-

Metallized MOS Dynamic RAMS in Plastic Packages in High Humidity and Temperature
Environments," IEEE Proceedings - 31st Electron Components Conference, May,
1981, pp. 238-244 (Bell Lab, Allenton, PA).

"Smith, Alan B. Bubble - Domain Memory Devices, Artech House, Dedham, MA, 1974,
(Sperry Research Center, Sudbury, MA).

Staecker, Peter "K-A-Band IMPATT Diode Reliability," 19th Int. Electron

Devices Meeting - Technical Digest, December, 1973, pp. 493-496 (Ava-iable
Trom IEEE) tMIll, Lexing~n, flAiT
k Takayama, Yoichira, "Effect of Temperature on Device Admittance of GaAs and Si
IMPATT Diodes," 20th Int. Electron Devices Meeting, December, 1974, pp. 130-
133, (Nippon Electric Company; Kawasaki, Japan) (Available from IEEE).

Van Diest, H.G. "The Reliability of Failure Rates," Microelectronics and

Reliability, Vol. 12, Pergamon Press, 1973.
Williams, W.D. "Bubble Memory Device Characterization Study" Report, Rockwell
International, Anaheim, CA, February, 1980.

Williams, D.F.. Cho, F.Y., and Sanchez, J.J., et~al. "Temoerature Stable SAW
Devices Using Doubly Rotated Cuts of Quartz," IEEE Proceedings - Ultra-
sonics Symposium, Vol. 1, November, 1980, pp. 4Z9-433 (Motorola, Inc.)

MOS Memory Data Book. Houston, Texas: Texas Instruments, Inc., 1982.

RF and Microwave Diodes. Hewlett Packard Applications Seminar, 1973.

Solid State Products. Burlinoton, MA: Microwave Associates, Inc.,

Seminar II,1974.

PIN Node Designer's Handbook and Catalog. Unitrode Corporation, 1979.

Diode and Transistor Designer's Catalog.. Hewlett Packard Electronic
Components, 1982.

Memory Applications Hlandbook. Santa Clara, CA: National Semiconductor

Co-r-poration, 1979.

* Reliability Handbook Volume I. Santa Clara, CA: National Semiconductor

Corporat ion, 1981.
Reliability for the Engineer Book 7. Orlando, FL: Martin Marietta Corpor-
". 'ation, 1965.
A Microwave Semiconductors. Alpha Industries, Inc.

144

N .. 11

~ %
 APPENDIX 2.0
POTENTIAL DATA SOURCES

Advanced Micro Devices Inc., Sunnyvale, CA

Aerojet Electrosystems, Azusa, CA
*Aerospace Corporation, Los Angeles, CA
Aertech Industries, Sunnyvale, CA
*Airesearch, Torrance, CA
AM General Corp., Detroit, MI
AMBAC Industries, Ft. Washington, PA
*AMEX Systems, Hawthorne, CA
N American Microsystems, Santa Clara, CA
Anderson Labs, Inc., Bloomfield, CT
Applied Devices, Kissimmee, FL
Applied Physics Lab, Laurel, MD
ARINC Research Corp., Annapolis, MD
Arma Division (AMBAC), Garden City, NY
Automation Industries (Vitro), Silver Springs, MD
*Ball Aerospace, Boulder, CO
Bechtel Power, Ann Arbor, MI
Bechtel Power, Norwalk, CA
Beckman Instruments, Fullerton, CA
Bell Aerospace, Buffalo, NY
Bell Helicopter, Ft. Worth, TX
Bendix-Oceanics, Sylmar, CA
Bendix-Guidance, Mishawaka, IN
*Bendix-Communications, Baltimore, MD
Bendix-Aerospace, Towson, MD
*Bendix-Guidance, Teterboro, NJ
Boeing-Aerospace, Seattle, WA
Bulova Watch, Valley Stream, NY
Bunker-Ramo, Thousand Oakes, CA
*Burroughs, Paoli, PA

S
-- NOTE: Asterisk (*) denotes useful responses.

145

. . •. ........
Jr~i~i=• .... •• •• e 4.7•4 . '1IN_.. ...... . . • ..- ••...• •..-.. . ••. .. ,; •+••;.•
 *Chandler Evans, W. Hartford, CT
Charles Stark Draper Lab, Cambridge, MA
Cincinnati Electronics, Cincinnati, OH
Comsat Labs, Clarksburg, MD
CONRAC Corp., Duarte, CA
Crystal Technology, Inc., Palo Alto, CA
*CUBIC Corp., San Diego, CA
Dalmo-Victor, Belmont, CA
*Douglas Aircraft, Long Beach, CA
Dynalectron-Aerospace, Ft. Worth, TX
EM & M - Sesco, Chatsworth, CA
*E-Systems, St. Petersburg, FL
*E-Systems, Monteck Division, Salt Lake City, UT
*E-Systems, Falls Church, VA
Eaton Corp., Long Island, NY
EDO Corp., College Point, NY
Efratom Systems, Irvine, CA
Electrodynamics (Talley), Rolling Meadows, IL
*Electrospace Systems, Richardson, TX
*Emerson Electric, St. Louis, MO
"Fairchild Republic, Farmingdale, NY
Fairchild, Space & Electronics, Germantown, MD
Fairchild Stratos, Manhattan Beach, CA
Fairchild Test Systems, Latham, NY
Fairchild-Weston, Syossett, NY
*FMC-Northern Ordnance, Minneapolis. 14
*• FMC-Ordnance, San Jose, CA
Ford-Aeronutronic, Newport Beach, CA
*Ford Aerospace, Palo Alto, CA
General Dynamics - Pomona, Pomona, CA
*General Dynamics - Convair, San Diego, CA
General Dynamics - Electronics, San Diego, CA

NOTE: Asterisk (*) denotes useful resoonses.

146
 General Dynamics - Land Systems, Warren, MI

General Dynamics, Ft. Worth, TX

General Electric, Daytona Beach, FL
S*General Electric, Pittsfield, MA
General Electric', Schenectady, NY
General Electric, Syracuse, NY
General Electric, Utica, NY
*General Electric, Philadelphia, PA
General Electric, Burlington, VT
General Instrument, Hicksville, NY
*Goodyear Aerospace, Akron, OH
Goodyear Aerospace, Litchfield Park, AZ
*Gould Inc., El Monte, CA
Gould Inc., Glen Burnie, MD
Gould, Inc., Cleveland, OH
. *Grumman Aerospace, Bethpage, NY
GTE Systems, Mountain View, CA
*Hamilton 57D, Windsor Locks, CT
Harris Corp., Melbourne, FL
Harris Corp., Rochester, NY
*Harris Corp., Syosset, NY
*Hartman Systems, Huntington Station, NY
Hazeltine Corp., Braintree, MA
%. *Hazeltine Corp., Greenlawn, NY
"Hewlett Packard, Palo Alto, CA
Hewlett Packard, Loveland, CO
Hi-Rel Labs, Monrovia, CA
*L-'oneywell Inc., West Covina, CA
"Honeywell Inc., Clearwater, FL
*Honeywell Inc., Tampa, FL
*Honeywell Inc., Lexington, MA
Honeywell Inc., Bloomington, MN

responses.
4i NOTE: Asterisk (*) denotes useful

147

,-...*............
 *Honeywell Inc., Hopkins, MN
*Honeywell Inc., St. Louis Park, MN
.Honeywel Inc., Seattle, WA
SHughes Aircraft, El Segundo, CA
*Hyghes Aircraft, Fullerton, CA
Hughes Aircraft,.Los Angeles, CA
Hughes Aircraft, Torrance, CA
Hughes Helicopters, Culver City, CA
. IBM Corp., Gaithersburg, MD
IBM Corp., Poughkeepsie, NY
IBM Corp., Owego, NY
IBM Corp.., Hopewell Junction, NY
IBM Federal Systems Division, Owego Tioga County, NY
*Ingalls Shipbuilding, Pascagoula, MS
Integrated Circuit Engineering, Scottsdale, AZ
International Engineering, San Francisco, CA
International Laser Systems, Orlando, FL
*Interstate Electronics, Anaheim, CA
Intel Corp., Chandler, AZ
Intel Corp., Santa Clara, CA
ITT Avionics, Clifton, NJ
ITT Aerospace, Ft. Wayne, IN
ITT Electro-Optical, Roanoke, VA
ITT Federal Electric, Paramus, NJ.
"*ITT Gilfillan, Van Nuys. CA
Joy Manufacturing, New Philadelphia, OH
*Kaiser Electronics, San Jose, CA
"Kaman Sciences Corp., Colorado Springs, CO

Keltec Florida, Ft. Walton Beach, FL

Ketrco Inc., Warminster, PA
*'yocera International Inc., San Diego, CA
Lawrence Livermore Lab, Livermore, CA

NOTE: Asterisk (*) denotes useful responses.

148

N"
@' ý*14- .A94 .!•-* 0*i~.*.
1U+8 ~ ~ ~ i ~. 0~
C

:' S .3 .C .
 Lear Siegler, Grand Rapids, MI
Litton Data Systems, Van Nuys, CA
Litton Systems Inc., Woodland Hills, CA
*Lockheed - California, Burbank, CA
Lockheed Electronics, Plainfield, NJ
Lockheed - Georgia, Marietta, GA
Lockheed Missile Systems, Sunnyvale, CA
*LSI Products, LaJolla, CA
Loral Electronic Systems, Yonkers, NY
*Magnavox Government & Industrial, Ft. Wayne, IN
*Magnavox, Torrance, CA
*Magnavox, Mahwah, NJ
*Martin Marietta, Denver, CO
*Martin Marietta, Orlando, FL
Mc'Lonnell Douglas, Huntington Beach, CA
*.: *McDonnell Douglas, St. Louis, MO
Memorex, Santa Clara, CA
*Microsonics, Weymouth, MA
Microwave Associates, Burlington, MA
Motorola, Shaumburg, IL
*Motorola, Scottsdale, AZ
Motorola, Ft. Worth, TX
National Waterlift, Kalamazoo, MI
Norden Systems, Norwalk, CA
Northrup Corp., Anaheim, CA
Northrup Corp., Hawthorne, CA
*Northrop Corp., Newbury Park, CA
Northrop Corp., Rolling Meadows, IL
Novatronics Inc., Pompano Beach, CA
Perkin-Elmer, Ponona, CA
Plessey Dynamics, Hillside, NJ
*Plessey Optoelectronics, Irvine, CA

NOTE: Asterisk (*) denotes useful responses.

149

v -a
 QED Systems, Virginia Beach, VA
*Exxon Office Systems, Lionville, PA
*RCA, Princeton, NY
*RCA, Burlington, MA
RCA Solid State Tech Center, Somerville, NJ
RCA, Camden, NJ
*RCA, Moorestown, NJ
Raytheon, Portsmouth, RI
*Raytheon, Goleta, CA
*Raytheon, Bedford, MA
Raytheon, Northborough, MA
Raytheon, Sudbury, MA
Raytheon, W. Andover, MA
Raytheon, Wayland, MA
*Reflectone, Tampa, FL
REL Inc., Boynton Beach, FL
Reliance Electric, Cleveland, OH
*RMI Inc., National City, CA
Rockwell International, Thousand Oaks, CA
Rockwell, Anaheim, CA
Rockwell, Downey, CA
*Rockwell, Los Angeles, CA
*[Link], Cedar Rapids, LA
*Rockwell, Columbus, OH
*Rockwell..Collins, Richardson, TX
*Rosemount Inc., Eden Prairie, MN
Sanders Associates, Nashua, NH
*Sandia Laboratories, Albuquerque, NM
*Sawtek Inc., Orlando, FL
Vs- *Science Applications, Palo Alto, CA
*Sedco Systems, Melville, NY
Semcor Inc., Moorestown, NY

NOTE: Asterisk ()denotes useful responses.

'V. 150

Wr4ýA &
 *Signetics, Sacramento, CA
Siemens-Allis Inc., Atlanta, GA
*Sierra Research Corp., Buffalo, NY
*Singer-Kearfott, Wayne, NJ
*Singer-Librascope, Glendale, CA
*Singer-Kearfott, Littlefalls, NJ
Smith Industries, Clearwater, FL
*Sperry-Flight Systems, Phoenix, AZ
*Sperry Gyroscope, Clearwater, FL
*Sperry Marine, Charlottesville, VA
Sperry Systems, Benicia, CA
Sperry Systems, Great Neck, NY
*Sperry Univac, St. Paul, MN
SPIRE Corp., Bedford, MA
SRI International, Menlo Park, CA
V• *Stromberg Carlson, Longwood, FL
Sunstrand, Rockford, IL
Sylvania Systems, Needham Heights, MA
Syscom Corp., Sunnyvale, CA
Tektronix, Beaverton, OR
Teledyne-Brown, Huntsville, AL
Teledyne Electronics, Newbury Park, CA
Teledyne MEC, Palo Alto, CA
Teledyne-Ryan, San Diego, CA
Teledyne Systems, Northridge, CA
Texas Instruments, Austin, TX
Texas Instruments, Dallas, TX
*Tracor Inc., Austin, TX

*TRW Defense & Space, Redondo Beach, CA

TRW Electronics, Colorado Springs, CO
TRW Equipment, Cleveland, OH
TRW LSI Prcducts, LaJolla, CA

NOTE: Asterisk (*) denotes useful responses.

151
•%'I

94 . I - *
L •.*-, o-j-.
•,*-*• •°. -•--.• o-• • .- •-•*, J '- ,•"P--,'. 1d 7• • v . • • • . . , . K
 TRW Semiconductors, Lawndale, CA
Tylan Corp., Torrance, CA
*Unidynamics/Phoenix, Phoenix, AZ
Unidynamics/St. Louis, St. Louis, MO
United Technologies, Windsor Locks, CT
United Technologies, Melville, NY
*Varian, Palo Alto, CA
*VLSI Technology Inc., San Jose, CA
Vought Corp., Dallas, TX
Weitek, Santa Clara, CA
Westinghouse Electric, Sunnyvale, CA
-*Westinghouse Electric, Baltimore, MD
*Westinghouse Electric, Hunt Valley, MD

Westinghouse Electric, Buffalo, NY

Westinghouse Electric, Pittsburgh, PA
Weston Controls, Archibald, PA
Xerox-Electro Optical, Pasadena, CA
*Zilog Inc., Cambell, CA

4i'

NOTE: Asterisk (*) denotes useful responses.

4*15
" -" 152
 APPENDIX 3.0
LITERATURE SEARCH AND DATA SURVEY

Martin Marietta wag required to complete an in-depth, computer assisted

literature search, coupled with telephvne calls and personal visits to
potentially key data sources. The object was to obtain, review and analyze
equipment and system manufacturer(s) derating policies, company internal
part derating documentation not released for general publication, periodi-
cal articles, technical reports, military specifications, and vendor docu-
mentation. This data has been published on integrated circuits, semicon-
ductors and advanced technology devices (i.e., VLSI, VHSIC, memory). How-
ever, there was little to be found in these particular areas of interest.

The computerized search and library reviews were then supported by a

letter survey, a telephone survey, and visits to the most promising data
sources to find more information on the vital subjects. The response to
these activities exceeded historical experience on similar data surveys
(see Table 40). However, it'was more an expression of mutual interest than
a contribution of useful information. The information received as a result
of these efforts has been analyzed and is discussed in the Published Guide-
lines Analysis of this appendix. Because of the limited information
received from industry on derating guidelines and failure mode data for
advanced technology devices, an internal letter survey was used. The
responses to this survey are summarized in the Martin Marietta Survey por-
tions of this appendix.

TABLE 40. HISTORICAL VERSUS ACTUAL RESULTS OF DATA SURVEYS

Time Span (Weeks) Response (Percent)* Yield (Percent)

Type of Survey Historical Actual Historical Actual Historical Actual
,
Letter 12 10 5 - 50 55 2 - 10 35

Telephone 1 1 100 100 20 65

' Literature 2 - 12 12 NA NA 25 25

Visits 8 2 100 100 75 7?2

"*Results are based upon experience observed over seven years on siX reliability data
survey programs :onducted at Martin Marietta Orlando Aerospace. The normal response
range in letter surveye is 5 to 50 percent.

Literature Search

The literature search was implemented by the Martin Marietta Orlando

Aerospace Technical Information Center (TIC). The Center has access to
virtually all technical information published during the past ten years.
It maintains on-line computer access to more than 100 data bases. In addi-
tion to our own files, special emphasis was directed to the files of the

153

. -.
 Defense Technical Information Center (DTIC). Because of the relative new-
2• ness of application of the devices of interest, the search was generally
limited to material published in the four years ending December 1982. More
recent publications were tracked on a day-to-day basis.

The electronic devices researched as key words are listed in column 1

of Table 40. Additional key words used are listed in Table 41. The com-
puterized search yielded 1037 abstracts, which were reviewed. Only 151
abstracts appeared to be relevant. After review, only 35 of the titles had
sufficient merit to be retained. These are included in the bibliography L
(Appendix 1).

TABLE 41. KEY WORDS

DEVICES OTHER KEY WORDS

Hybrid Derating
Transistor Reliability Derating
Capacitors Thermal Tests
Resistor Chips Thermal Testing
Integrated Circuits Thermal Resistance
LSI/Custom LSI Junction Temperature
A. VHSIC Junction Temperature Measurement
"VLSI Case Temperature
Microprocessors Case Temperature Measurement
Memory Temperature
Bipolar Thermal
MOS Application Notes
Bubble Application Guidelines
"Microwave Failure Modes
Silicon Detectors Failure Mechanisms
Germanium Detectors
Silicon Schottky Detectors
Silicon Mixers
Germanium Mixers
IMPATT Diodes
GUNN Diodes
Varactor Diodes
PIN Diodes
Step Recovery Diodes
"Tur•el Diodes
Transi stor
GaAs FET
,::SAW _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Letter Survey

A letter and two-part questionnaire was mailed to 257 addresses at 240

corporate locations, with a ret-rn date of 30 May 1983. The mailing list
was ciaapiled from the Electronic Industries Association JC-13 technical
co(mwittee rosters, the Government-Industry Data Exchange Program (GIDEP)

154

.~......
.
.*
.- A
 roster, and prospective respondents known by the Rome Air Development
Center (RADC) or Martin Marietta to have a vested interest in the subject.
The addresses are listed in appendix 2.

There were 90 returns. Eighty-four, or 93 percent of the returns

V+ provided useful information. The response to five general survey questions
is summarized here.

1 Does your company/division use standard electronics component

derating? 71 Yes 19 No

_:.2 Are the component derating guidelines documented? 68 Yes 22 No

3 Does your company/division have standard application guidelines and

tolerance factors? 55 Yes 35 No
Documented? 53 Yes 37 No

4 During forthcoming inspection, subsystem, and/or system level test-

ing, are failed parts subject to analysis to determine failure
modes and/or mechanisms? 30 Yes 14 No 46 Sometimes

5 Has your company/division performed any thermal tests to verify

derating parameters? 44 Yes 46 No
The second page of the survey questionnaire asked the question:

"Have you conducted, within the past 5 years, any testing

(life, screening, demonstrations, etc.) which measured any
of the following parameters on the following devices
(please check appropriate boxes)."

The number of addressees who responded to this question is summarized

in Table 42.

An analysis of the results of the literature search and the letter

survey lead to the following conclusions:

1 Of the 10 companies most common in the literature who were queried,

only seven responded. Only four of these seven reported conducting
"testing which measure case or junction temperatures.
2 Only one respondent, Sandic National Laboratories, reported an
accumulation of relevant failure rate data.

3 There is very little temperature measurement data awatlable, and

.* most of it resides in five companies. The companies are:

Sperry - Clearwater, Florida

Magnavox - Ft. Wayne, Indiana
Stromberg Carlson - Longwood, Florida
"Sierra Research - Buffalo, New York
Hughes Aircraft - Fullerton, California

155

AZ

.. .. .... .
....... ........ .**~* ........- ,..+....-..
............
.*, * -..... ' "..%.: ." i.'.'.'..'t''-z.-;."

•"u%•..•.,•%..•.-•• " -'-+-'-" " -• •+ "•'+S.* , i + -- ,,,.-. •.. .o .. ...... . .. .

 TABLE 42. TEST MEASUREMENT RESPONSE
TEMPERATE1 .
DEVICE JUNCTION CASE FAILURE RATE
Hybrid 8 18
Transistors
Capacitors
Resistor Chips

Integrated Circuits
LSI/Custom LSI 6 13
VHSIC 1 3
VLSI 4 8
Microprocessors 6 12

. ' Memory
Bipolar 6 12
MOS,
3ubble 41 121 1

Microwave
Silicon Detectors 2 3
Germanium Detectors I I
Silicon Schottky Detectors 1 3
Silicon Mixers 1 3
Germanium Mixers I I
IMPATT Diodes 2 2
, GUNNS DioJes 12 1
Varactor Diodes 2 4 1
PIN Diodes 1 5 1
Step Recovery Oiodes 1 3
Tunnel Diodes I 1
Transistor 3 4
GaAs FET 4 6

SAW 1,Z

jTelthone Survey

A telephone survey was used is a follov-up to the letter survey for

the purposo of obtainia• useful date or information by mail. There were a
",tal of $,2 telephotue calls. The calle led to the receipt of 33 copies of
corporate deratin guidelines, sad the bisis for %even personal visits.
"Lssdata was avsilable after contacting the most promising respondents.
The. telephone survey was terminated after 50 percent of the sources had
been contacted.

156

-'a.-',. .

*ic.5 ... ,,. .. * * *

 On-Site Visits

With proper prepacation and response, on-site visits are the best
source of data. Such visits provided clearer communication and less bias,
since fewer misunderstandings in terminology, meanings, or questions can
occur. The on-site visit offers the respondent an opportunity to clarify
points of doubt, since he has ready access to his organization's data base.
Last, but not least, the personal visit tends to assure the respondent's
cooperation and his company's approval for the release of data.

Seven visits were made because of a dearth of promised data and prac-
tical judgements with respect to fiscal limitations on travel. The results
of these trips to Motorola (6/20), Hughes Aircraft (6/21), AIRESEARCH
(6/22), Douglas Aircraft (6/21), TRW (6/22), Sierra Research (8/24), and
SAWTEC (9/20) were documented in trip reports and sent to RADC by Martin
Marietta letters. Four of these sources provided information that was
useful in completing Task 3 of the study contract, an assessment of case
temperature derating and measurement.

Due to conflicts in data availability and usefulness, the planned and

tentatively scheduled trips to additional respondents were cancelled. This
was a topic of discussion with RADC, and was documented in the appropriate
monthly status reports and the first interim review.

The literature search and data survey provided some very interesting
results. The results obtained did not further the progress of the program,
but highlighted the point that most everyone contacted was interested. In
general, the respondents had little useful information, but wanted some
form of consistent or standardized guidance in the field of derating and
junction temperatures. Each individual visited or contacted by telephone
had their own opinion of how it should be handled, but each was open to a
standard requirement in the form of a military specification.

Published Guidelines Analysis

Industry derating guidelines and information were obtained primarily

as a result of telephone calls following up the response to the survey let-
ter. Final document sources are listed in Table 43. This is an updated
version of the document source listing provided to RADC by the Martin
Marietta Ot-lando Aerospace Interim Report OR 17328 or 15 August 1983.

A total of thirty-three doc~tments were received. Of these, thirty-two

had useful derating criteria for semiconductors and integrated circuits.
Very few companies had published guidelines for the more advanced tech-
nology devices (i.e., LSI, VLSI, VHSIC, etc.) These guidelines weze
"included iu the analysis when they were available. The data collected from
the deratitg standards of these companies was analyzed by first grouping
the data by part type. Within the part typc, the analysis fonused on the
.. parameters derated and the amount of derating applied, The derating cri-
teria received from about 90 percent of the respondents was not based on
derating levels or operating environments. Therefore, these two elements
were not evaluated in the analysis.

"157

'''4
 TABLE 43. INDUSTRY DERATING GUIDELINES

Bendix-Guidance, Teterboro, New Jersey

Cubic Defense Systems, San Diego, California
Delco Electronics, Goleta, California
Douglas Aircraft, Long Beach, California
E Systems, Falls Church, Virginia
Electrospace Systems, Richardson, Texas
Exxon Corporation, Lionville, Pennsylvania
Ford Aerospace, Palo Alto, California
General Electric Company, Schenectady, New York
Goodyear Aerospace, Akron, Ohio
Gould Incorporated, Glen Burnie, Maryland
Hamilton Standard, Windsor Locks, Connecticut
Harris Corporation, Melbourne, Florida
Hartman Systems, Huntington Station, New York
Honeywell, St. Louis Park, Minnesota
Honeywell, Hopkins, Minnesota
Hughes Aircraft, Fullerton, California
Interstate Electronics, Anaheim, California
Kaiser Electronics, San Jose, California
Lockheed Aircraft, Burbank, California
Lockheed Missile, Sunnyvale, California
Martin Marietta Aerospace, Baltimore, Maryland
Martin Marietta Aerospace, Orlando, Florida
Northrop Corporation, Newbury Park, California
Raytheon Corporation, Bedford, Massachusetts
Raytheon Corporation, Goleta, California
Sierra Research Corporation, Buffalo, New York
Signetics Corporation, Sacramento, California
Sperry Marine, Charlottesville, Virginia
Sperry Flight Systems, Phoenix, Arizona
Texas Instruments, Dallas, Texas
TRW Corporation, Redondo Beach, California
VLSI Technology Corporation, San Jose, California

Tables 44 through 46 represent the tabulated results of the analysis

on derating standards for diodes, integrated circuits, and transistors,
respectively. On the left hand side of each table are the part types which
are derated, along with the number of sources that referenced that part
type enclosed in parentheses. The stress parameters are across the top of
"the tables. These parameters are derated by the majority of the respond-
ents. The value enclosed in parentheses for these parameters indicates
the percentage of respondents who derated that parameter for the specific
part type. The range of values to which the part is derated, and the per-
centage of respondents who derate to that value, is presented in descending
percentage order. This derating information can be reduced further for the
purpose of comparing the industry derating standards and those listed in
the "Reliability Part Derating Guidelines Report" (RADC-TR-82-177).

158

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 TABLE 46. SURVEY GUIDELINE SUMMARY
TRANSISTORS

TYPE JUNCTION TEMP VOLTAGE CURRENT POWER

(83%) (83%) (70%) (67%)

0*
GENERAL PURPOSE' 110 C-32% .75-52% .75-52% .50-65%
(30)
125 0 C-28% .80-1i6% .50-24% >.50-15%
<100°C-20% .70-16% .70-9.5% .30-15%
1000 C-16% <.70-16% .80-9.5V .40- 5%
>125 0 C- 4% .90-5% Power Transistor
.30-87%
.75-13%
(33%) (89%) (70%) (44%)
FIELD EFFECT 110°C-67% .75-38% .75-50% .65-25%
TRANSISTOR 125 0 C-33% .60-25% .65-25% .50-25%
(9)
.70-13% .50-25% .30-25%
.80-12% .20-25%
.50-12%

(100%) (100%) (50%) (100%)

Ga As FET lj0°C .75 .90 .50
(2) 125 0 C .70 .65

The survey results were condensed to show a single derating value for
each part type and stress parameter. The highest percentage of respondents
derating by a specific intensity established this single value. Tables 47
through 49 present these values, along with the applicable RADC report

derating standards (Levels I, I1, and III, respectively) in a tabular

format to facilitate a direct comparison.

Further review and analysis of the derating source documentation

"received has lead to the following conclusions:

I There is a body of general guidelines on transistors, diodes,

resistors, and capacitors that is comparable with the Level I/Il
"guidelines identified by RADC. These guidelines are referenced in
Tables 47 through 49.

2 There were some published guidelines for ICs, but none of them
addressed VHSIC or VLSI devices.

3 Derating for hybrid microcircuits was scarcely mentioned. As Table

n45indicates, only four companies address it in their guidelines,
and then only to derate junction temperature.
161

* 44
 < <

I U.

LLLi

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00

co 0

~fl0C'tC~ c16Q
_ _ __
IN_

~uJ _%
 "" K

L.j

i- ____,

-;Cz gjg
- ,
(-)

iw ,. ....

-o- ; --

• .. i p..
-. -1.1 -

riO

................... . ..
co
I-

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(

L0 J
61-o-

cc
zz
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-
-

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_ _ _ _ _ _ _

-j
-

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164
U
 4 Derating for memory devices was not mentioned. There was no derat-
ing information for bubble memories in particular.

5 Only silicon devices get any attention of any of the microwave

devices listed in the contract statement of work. No one seems to
use germanium devices, and they are not selected or recommended for
new design. Stress parameters for tunnel germanium diodes were
mentioned by only one respondant, with germanium devices in general
not being addressed by other sources. Martin Marietta followed the
format for derating established by the one respondent.

6 SAW devices were recognized only by the device manufacturers.

These devices are relatively new technology and little information
is available. However, derating information was received from a
device manufacturer.
7 Application guidelines in terms of mission criticality or the

MIL-HDBK-217D environments were virtually non-existent in the

industrial data.
8 Present derating criteria, i.e. RADC-TR-82-177, appears to be more
complete and inclusive than what is used by the industry in general.

9 Structured collection of field data and design analyses performed

on existing programs would substantiate or revise present derating
criteria.

Martin Marietta Survey

A survey of Martin Marietta electronics experts was conducted to sup-

plement the information received from industry. The objective was to
obtain failure mode data and derating guidelines for the specific advanced
"technology devices this contract addresses (i.e., VLSI, VHSIC, etc.).
There was a total of eleven letters and questionnaires mailed, with four
responses. Authors of the outstanding surveys were identified and con-
tacted by telephone.

The surveys that were returned did not reveal any additional facts.
They confirmed or reinforced what has been previously published on failure
modes and derating for ICs, hybrids, and memory devices. As one respondent
indicated, specific information on microwave devices was limited, due to
the fact that data needed for the creation of derating standards does not
"exist for these devices. The survey questions and results are sumarized
in Figures 77 and 78.

165

..
 Reliability Derating Procedures
Survey

Please complete the followinq questionnaire by recording the respornse to

the following questions in the chart on the next page. Feel free to make any
additional comments/remarks that you consider pertinent or helpful to this task.

1. What would, in your opinion, be the major parameters

for derating?

2. What derating value would you suggest for these parameters? L

3. What is the predominant failure mode?

4. This failure mode is the result of:

a. Manufacturing techniques

"b. Device physics

c. Design application
.F
Figure 77. Martin Marietta survey.

V,

'.2.
7-

166

qPp
 VL LlJ

0 .F~ U FLIi

LJJj

ILL,0- -
U- 10 U ~I ,-C:

UU
*ci FU
~I ~ 4A

L~1 M_ __ _ 41

vi
z
1S. _ _ _ _ _ _ _ __ ~ _ _ _ _ _ _ __ _ _ _ _ _ _ _ _ go__

CM,'

cr--
LI-

F 167
%L,~. ~
}

APPENDIX 4.0

DATA GROUPING

Data grouping is a significant step in the case temperature derating

and measurement task. It consists of two forms, the device grouping versus
packaging, and measured or collected temperature data grouping. The device
grouping versus packaging types is shown in Table 50.

TABLE 50. DATA GROUPING

•. Metal Cerauic Cerdip/
"Device Group Studs Cans Chip Carriers Flatpack Hybrid

Transistors X X
Diodes X X
Integrated circuits X X X
Microwave X X X
Hybrid X X

"The device grouping plan versus the package type encompasses the most
widely used military devices. Plastic encapsulated package types were not
addressed or considered, since chey are not approved for miltary equipment.
The axial package was not addressed or considered for two basic reasons.
First, there is limited future usage of axial packages, according to device
manufacture general data. Second, axial packages do not appear to be a
particular area ;..1 temperature problems, according to survey respondents
queried.

The second data grouping considered was the measured or collected

data. The data received has been grouped by package type. The generally
considered package types are listed against the case outline letter
designations shown in Table 51. Thia listing was extracted from Appendix C
of MIL-M-38510E.

.4"

41
*.

,168

- 168

a•

* :-,: .-
. . - - . - - . .. . . . , . .. . ..-. -*. , .. ,
S. ....
... ... .. . .* 4.
 TABLE 51. CASE OUTLINE LETTER DESIGNATIONS
Appendix C
Letter 1/ Designation f. Description 2/

A F-1 14-lead FP (1/4" x 1/4")

B F-3 14-lead FP (3/16" x 1/4")
C D-1 14-lead DIP (1/4" x 3/4")
D F-2 14-lead FP (1/4" x 3/8")
E D-L 16-lead DIP (1/4" x 7/8")
F F-5 16-lead FP (1/4" x 3/8")
G A-i 8-lead can
H F-4 10-lead FP (1/4" x 1/4")
I A-2 10-lead can
D-3
D 24-lead DIP (1/2" x 1-1/4")
K F-6 24-lead FP (3/8" x 5/8")
M A-3 12-lead can
P D-4 8-lead DIP (1/4" x 3/8")
Q D-E 40-lead DIP (9/16" x 2-1/,16")
R 0-8 20-lead DIP (1/4" x 1-1/16")
S F-9 20-lead FP (1/4" x 1/2")
V D-6 18-lead ,".P (1/4" x 16/16")
W D-7 22-lead UIP (3/8" x 1-1/8")
F-8 24-lead FP (1/4" x 3/8")
C-I 16-terminal SQ, CCP (.300" x .300")
C-2 20-terminal SQ, CCP (.350" x .350")
C-3 24-terminal SQ, CCP (.400" x .400")
C-4 28-terminal SQ, CCP (.450" x .450")
C-5 44-terminal SQ, CCP (.650" x .650")
C-6 52-terminal SQ, CCP (.750" x .750")
C-7 68-terminal SQ, CCP (.950" x .950")
C-8 84-terminal SQ, CCP (1.150" x 1.150")
C-9 IF-terminal RECT, CCP (.285" x .350")
C-10 : terminal RECT, CCP (.285" x .425")
C-1I :'d-terminal RECT, CCP (.350" x .550")
C-12 32-terminal RECT, 'CP (.450" x .550")

*i .. ... .-..

169
[Pt.
. APPENDIX 5. INTERNAL MODEL

APPENDIX 5.1. Square Surface Program

This appendix contains the computer program for the square surface device.
* i• This program is referenced in section 5.3.1.

"SQUARE SURFACE DEVICE - 50% DISSIPATION

000059OPF.N "LP:" FOR WRITE AS FILE #1
00010 REM ASSUMPTIONS AND VARIABLE NAMES
00011 REM UNITS FOR LENGTH, WIDTH, & THICKNESS ARE IN MIL INCHES
06012 REM DISSIPATION AREA IS 50%
00014 REM SPREADING ANGLE VARIES PER EXTERNAL ENVIRONMENTS
00020 REM L=Lensth W=Width T=Thickness K-Thermal Conductivity
00021 REM A=SPreadins Ansle(radians) S=Spreadins Anule(deirees)
00022 REM Ll(W1)=Adjusted lenoth(width) for dissipation area
00023 REM L2(W2)=Lensth(width) for next level
00024 REM R1,R2=Thermal Resistance I-Increment
00025 REM SUBROUTINE VARIABLES: W-Width of field D-# decimal disits
00026 REM Q$=formatted output JFO-tab settinis
00039 REM INPUTS
00040 L-W=T=O
* 00050 INPUT "ENTER THE MATERIAL TYPE "IF$
00060 INPUT "ENTER THE [Link] CONDUCTIVITY IN W/INCH*CENTIORADE "IK
00061 INPUI "ENTER THE .•READING ANGLE IN DEGREES ";S
00069 REM TABLE TITLES
00070 PRINT #1, TAB(21.';"SQUARE SURFACE DEVICE-501 DISSIPATION"
00075 PRINT #1, .
00076 PRINT #1, "
* 00077 PRINT #1, "
00080 PRINT *1, 1AB(2e)1"MATERIAL: 1;F$
00081 FRINT #1, TAB(28)t"CONDUCrIVITY: "iKI4(W/IN.*C)"
00082 PRINT #1, TAB(28);"SPREADINO ANGLE' "tSI1"DEGREES"
00083 PRINT 41, ""
00085 PRINT *1.
00090 PRINT #1. TAB(12)t" LENGTH * WIDTH THERMAL RESISTANCE "I
0009•2 PRINT #1, Linc * Winc"
00095 PRINi #1, TAB(12)1" -,------------------us
000&6 PRINrr 1. " - ..................
00099 REM INCREMENTING
00100 L=2
"00105 W-2
00110 IF L<IO THEN I=2
00120 IF (L<50) AND (L>=10) THEN I-5
0()121 IF (L<200) AND (L>050) THEN 1-10
00122 IF (LZ•O01) AND (L>'200) rHEN 1-50
0012!-, REM THICKNESS VARIATION
001", 0 IP (L<14) OR (WN:10) THEN T=6
00140 IF (L-:25) AND (L'-10) THEN T-8
00150 IF (L'50) AND (L,,-225) THEN To12
-0(015 1 IF (L ;CK)) )ND (L:>-*50) THEN T-I5
00 152 IF L::-m100 THEN T',18
* 00160 REM 50% DISSIPATION
4)(1016 1 L I . 7Q:7*L
")0162 4 WjI'.70T*W
0..1161 Rn M THERMAL RESISTANCE
",.) 6 16,) An?. 141"150 1-
/ 15y .
"''' 1770 R I=T/(I' 4N1 1 1'I+Ze T oTAN (A) )
00171 R1 R1.I00
00101 REM NEY1 [Link]. DIMENSIONS (SPREnDINO.
•001•2 L2' 1-2• *rrANA7

"- ~170
it'
'itI

6' .' , . . . • . . .. .. .. . . . . . ., . . . , ,. , . . . . -. . ., ,
. - ...,,. ,. .. .. . . ,. .. % .. .. . . . . - ,, . ,. %, J. . . , , j • • . . • •. ; .,•- ,-,, .
 SQUARE SURFACE DEVICE - 50% DISSIPATION (CONTINUED)
00194 IF L2>L THEN L2.L
00200 GOSUB 800
00?05 IF L=500 THEN 420
00370 L=L+I
00380 W=L
00390 GOTO 110
00420 CLOSE #1
00440 END
004Y0 REM SUBROUTINES
00500 REM OUTPUT
00800 W=5: D=O
00810 V=L: GOSUB 1000: PRINT #1, TAB(14);Q$;TAB(20) ;"X"; TAB (22);Q$I
00820 W=13: D=5: V-R2: GOSUB 1000: PRINT #1, TAB(J);Q$;
00830 W=7:D=2:V=L2tGOSUB 1000:PRINT #1, 1'AB(F);Q$;TAB(62);"X";TAB(O);Q$
00840 RETURN
00900 REM TABLE FORMAT
01000 IF D=O THEN 1050
01003 Q=INT(V÷.5/(I0OD))
01005 C=LEN(STR$(Q))
01010 OOSUB 4000
01011 Q$=LEFTSfSTR$(Q),C-1)+". '
"01015 Q=INT((V-Q)*(1OD)+.5)
01020 P$=STR$(Q)
01030 M=LFN(P$)
01033 M1=M-1
01035 Q-Q=.+RIGHT$("00000000"+RIGHT$(P$,M1)•D+I)
01040 RETURN
01050 U=INT(V+.5)
"01060 Q$=RIGHT$(S$+STR$(Q),W)
01070 RETURN
01080 REM TAB SETTINGS FOR TABLE
04000 X=C-2
04010 IF H=: 4050
:HEN
04015 IF x=; THEN 4056
04020 IF X=3 THEN 4060
04025 IF X=4 THEN 4065
04030 IF X=5 THEN 4070
04050 4=37: F=55: 0=65: RETURN
04055 F=54: 0-641 RETURN
1=3•.
04060 J=35t F=53: 0=63: RETURN
04065 J=34: F=53: 0=63: RETURN
04070 Jv33t F=53: 0=63: RErURN

SQUARE SURFACE ATTA_,'!.?I"

100005 OPEN "LPt" FOR WRITE A1S FILE #1
00010 REM ASSUMPTIONS AND VARIABLE NAMES
""0011 REM UNITS FOR LENGTHWIDTH,& THICKNESS ARE MIL INCHES
00012 REM 100%. COVERAOE
Q00013 REM SPREADING ANGLE VARIES PER EXTERNAL ENVIRONMENTS
"00020 REM LmLensth W-'Wdth T-Thickness K-Thermal Conductivity
. 0(021 REM =-Spreadins Anple(radians) $=Spreadine Anvle(derpees)
0002-2 REM L2(W2)sLen~th(width) for next level I-Increment
00023 REM RI.R2- Thcrmal Resistance
"00621 REM SJBROUTINE VARISBLESsW-Width of field On# decimal divits
- V5 REM O$formatted output .,F,O-tab settinvs Z(L3)-device leneth
000"A REM r2-devlce thickness
0030 REM INPUTS

171

I,
 SQUARE SURFACE ATTACHMENT (CONTINUED)
00040 L=W=T=O
00045 S$=" i
00046 PRINT "ATTACHMENT MATERIAL CH3ICE3S EUTECTIC, SILVER EPOXY, "
', 00047 PRINT "COLD EPOXY, NON-CONDUCTIVE EPOXY, CONDUCTIVE EPOXY, "
00048 PRINT "AND NONE"
0(0050 INPFrT "ENTER THE MATERIAL TYPE: ";F$
00060 INPUT "ENTER THE THERMAL CONDUCTIVITY IN W/INCH*CENTIORADEs ";K
00061 INPUT "ENTER THE SPREADING ANGLE IN DEGREES: "IS
00069 REM TABLE TITLES
00070 F-PIT #1, TAB(26);"SQUARE SURFACE ATTACHMENT"
00075 PRINT #1,
00076 PRINT #I,
00077 FRINT #1,
00080 PRINT #1, TAB(26)i"MATERIA[: "IF$
00081 PRINT #1, TAB(26);"CONDUCTIV]IY: "lK;"(W/IN.*C)"
,0082 PRINT #1, TAB (26); "SSPREAD INO ANGLE: "IS*t"(DEOREFS)"
00083 PRINT #1, "..
00085 PRINT #I, " "
00090 PRINT ti. AEAB(12)8" LENGTH * WIDTH THERMAL RESISTANCE ";
'7 '.'2 PRINT #I, " [Link] * Winc"
.095 PRINT #1, TAB(12)"----------------------------------- "
0,C:)(O'?6 PRINT #1 - ".....
.u098 REM INCREMENTING
00100 L=2
100105 W=2
00106 Z=2
00110 IF L<10 THEN 1=2
00120 IF (L<50) AN'. (L-=10) THEN 1=5
00123 IF (L<2,.C' AND (L>-=50) THEN I=10
OOL2.. I .LK500)
'- AND (L'.-200) THEN Il50
"00"T, OOTO 400
00160 REM THERMAL RESISTANCE
Q:01)5 A=3. 1415927/180*"
(K,1 7 0 P1-T/(K*-J*(W+2*T*TAN(A:))
00171 R2=RI*1000
00191 REM NEXf LEVEL DIMENSIQNS(SPREADING)
"00192 L2=L+2*T*TAN(A)
""0195 OSUB 2000
00196 Z=Z+I
00197 f30JUB ::P"
•:. 002,)5 lt L.>=500
00Y3t" L~'L+ I THEN 700

t.)) *:teo WTI-

00400 REM ATTACHMENT THICKNFS-ES
00401 IF F4-"EUTFCTIC" THEN T-.5
"00410 IF F*-""[Link] EPOXY" THEN T-.5
00420 IF F$-"GOLD EPOXY" THEN T-.5
"00430 IF F*w"NON-CONDUCTIVE EPOXY" THEN T,2
00440 IF F$="CONDIICTIVE EPOXY" THEN To1
00450 IF F$""NONE" THEN T,-0
00460 ,OTO 160
00700 CLOSE #1
00720 END
00(/50 REM SUBROUTINES
"00760 REM OUTPUT
00*00 W*5: D"O
00.10 VuL: OOSUB 1000: PRINT #I. TAB(14)1Q$ITAB(20);"X"tTAB(22):O*$
00820 W-13t D-5: V-R21 COSUB 1000: PRINT #i, TAB(J)iQS:
T
00930 W=7:Du2tV--L2:OOSUB 1000PRINT #1, TAB(F);Q$;TAB(62):"X" TAB(O)IQ$
".q_ 00S40 RETURN
10900 REM TABLE FORMAT

172
,6,

* ~e . '
 SQUARE SURFACE ATTACHMENT (CONTINUED)
01000 IF D=6 THEN 1050
01003 Q=INT(V+.5/(10D))
01005 C=LEN(STR$(Q))
01010 GOSUB 4000
01011 Q$=LEFr$(STR$(Q),C-1)+"."
01015 Q=INT((V-Q)*(10'D)+.5)
01020 P$-STW$(Q)
01030. M=LEN(P$)
01033 MI=M-1
01035 Q$=Q$+RIGHT$("00000000"+RIGHT$(P$sM1),D+I)
01040 RETURN
01050 Q=INT(V+.5)
01060 Q$=RIGHT$(S$+STR$(Q),W)
01070 RETURN
01090 REM DEVICE THICKNESS
02000 A=3.1415927/180*S
02010 IF Z<1O THEN T2=6
02020 IF (Z<25) AND (Z>=10) THEN r2=8
02030 IF (Zk50) AND (Z>=25) THEN T2=12
02040 IF (Z<100) AND (Z>=50) THEN T2=15
02050 IF Z>=100 THEN T2=18
02070 ZI=Z*.707: Z2=ZI+2*T2*rAN(A)
02080 IF Z2>Z THEN Z2=Z
02085 Z3-Z-Z2
02087 IF Z3=0 THEN 2095
02088 L3=(Z-2*T2*TAN(A))/.707
02089 Z4=Z: Z=L3: GOSUB 5000: L4=(Z4-2*T3*TAN(A))/.707
02090 IF L2>L4 THEN L2=L4
02092 ZrZ4
02091 RETURN
02095 L2=Z: RETURN
02098 REM TAB SETTINGS FOR TABLE
04000 X=C-2
04010 IF X=1 THEN 4050
04015 IF X=2 THEN 1055
04020 IF X=3 THEN 4060
04025 IF X"4 rHEN 4065
04030 IF Xý5 THEN 4070
04050 J=3/: F=55: 0-65: RETURN
04055 J=36: F=54: 0=64: RETURN
04060 J=35t F=53: 0=63: RETURN
04065 J=34: F=53: 0=63t RETURN
04070 J-33: F-53t 0=63: RETURN
05000 IF Z<10 THEN T3=.
05010 IF (Z<25) AND (Z>=IO) THEN T3=8
05020 IF (Z<50) AND (Z>=25) THEN T3=12
05030 IF (Z<iO0) AND (Z>=50) THEN T3-15
05040 IF Z>=100 THEN T3=18
05050 RETURN

173
 '.v

4
•SQUARE SURFACE - INTERMEDIATE MATERIAL

00005 OPEN "LPS" FOR WRITE AS FILE #1

00010 REM ASSUMPTIONS AND VARIABLE NAMES
00011 REM UNITS FOR LENGTH, WIDTH, & THICKNESS ARE IN MIL INCHES
00012 REM 100% COVERAGE
00013 REM SPREADING ANGLE VARIES PER EXTERNAL ENVIRONMENTS
00020 REM L=Lensth W=Width T=Thickness K-Thermal Conductivity
00021 REM A=Spreadins Ansle(radians) S=Srreadins Anvle(desrees)
00022 REM L2(W2)=Length(width) for next level I-Increment
00023 REM RlR2=Thermal Resistance
. 00024 REM SUBROUTINE VARIABLES: W=width of field D=# decimal disits
, 00025 REM Q$=formatted output J,FO=tab settings
00030 REM INPUTS
00040 L=W=T=O
00041 PRINT "INTERMEDIATE MATERIAL CHOICES: GOLD HEADER, BERYLLIA, "
00042 PRINT "ALUMINA, MOLYTAB, NICKELTAB, AND NONE"
00050 INPUT "ENTER THE MATERIAL TYPE: ";F$
00060 INPUT "ENTER THE THERMAL CONDUCTIVITY IN W/INCH*CENTIGRADE: "1K
00061 INPUT "ENTER THE SPREADING ANGLE IN DEGREES: "IS
00069 REM TABLE TITLES
00070 PRINT #1, TAB(23); "SQUARE SURFACE-INTERMEDIATE MATERIAL"
00071 PRINT #1, "
00072 PRINT #1, "
00075 PRINT #1, "
9 00080 PRINT #I, TAB(27);"MATERIAL: ";F$
00081 PRINT #1, TAB(27);"CONDUCTIVITY: ";K;"(W/IN.*C)"
00082 PRINT #1, TAB(27);"SPREADING ANGLE: "1;S;"(DEGREES)"
"00085 PRINT #1,
"00086 PRINT #1,
00090 PRINT #1, TAB(12)," LENGTH * WIDTH THERMAL RESISTANCE "I
"00092 PRINT #1, " Line * Winc"
00095 PRINT #1, TAB(12)" --------------------------------- "Ott
00096 PRINT #1, ".......
00099 REM INCREMENTINO
00100 L=2
00105 W=2
00110 IF L<10 THEN 1=2
00120 IF (L<50) AND (L>=10) THEN I=5
00121 IF (L<200) AND (L>=50) THEN 1=10
3:00125 IF (L<500) AND (L>=200) THEN I=50
"00130 007O 400
00165 REM THERMAL RESISTANCE
00168 A=4.1415927/180*S
00170 R1=T/(K*W*(W+2*T*TAN(A)))
00172 R2-RI*1000
00191 REM NEXT LEVEL DIMENSIONS(SPREADING)
00192 L2-L+2*T*TAN(A)
00193 W2=W+2*T*TAN (A)

00205 IF L=500 THEN 420

00370 L--L+I
00380 4=L
00390 GOTO 110
00400 REM THICKNESSES
. 00401 IF F$O"GOLE' HEADER" THEN T=.2
(00402 IF F$="BERYLLIA" THEN T=0
"" 00403 IF F$="ALLUMINA" THEN T=O
"00404 IF FS="M0LY1AB" THEN T=0
O,0,45 IF F$="NICKELTAB" tHEN T-0
00406 IF F$'-"NONE" THEN T=O
00407 GOTO 165

174
1..:-,:
 SQUARE SURFACE - INTERMEDIATE MATERIAL (CONTINUED)
00420 CLOSE #1
00440 END
00699 REM SUBROUTINES
00700 REM OUTPUT
00800 N=5t D=O
00810 V=L: GOSUB 1000: PRINT #1, TAB(14);Q$tTAB(20);"X";TAB(22);Q$;
00820 W=13: D=5: V=R2: GOSUB 1000: PRINT #1, TAB(J);Q$;
00830 W=7tD=2fV=L2SGOSUB IO00:PRINT #1, TAB(F)tQ$ITAB(62)s"X"ilAB(O)%Q$
00840 RETURN
00850 REM TABLE FORMAT
01000 IF D-0 THEN 1050
01003 Q=INT(V*.5/(IO^D))
01005 C=LEN(STR$(G))
01010 GOSUB 4000
01011 Q$=LEFT$(STR$(Q),C-1)+"."#
01015 Q=INT((V-Q)*(IO^D)+.5)
01020 P$=STR$(Q)
01030 M=LEN(P$)
01033 MI=M-1
01035 0$=Q$+RIGHT$("OOOOOOOO"+RIGHT$(P$*M1)sD+I)
01040 RETURN
01050 Q=INT(V+.5)
4d 01060 Q$=RIOHT$(S$+STR$(Q),W)
01070 RETURNk
03999 REM TAB SETIINGS FOR TABLE
04000 X=C-2
01010 IF X=1 THEN 4050
04013 IF X=2 THEN 4055
04020 IF X=3 THEN 4060
04025 IF X=4 THEN 4065
04030 IF X=5 THEN 4070
04050 J=37t F=55: Om65: RETURN
04055 J=36: F-541 0=64: RETURN
04060 J=35: F=53: 0=63: RETURN
04065 J=34: F=53: 0=63: RETURN
040/0 J=33: F-53: 0=63: RETURN

40 PIN CERAMIC SIDE BRAZED PACKAGE

00005 OPEN "LP:"' FOR WRITE AS FILE #1

00010 REM ASSUMPTIONS AND VARIABLE NAMES
00011 REM UNITS FOR LENGTH, WIDTH. & THICKNESS ARE IN MIL INCHES
00012 REM 100% COVERAGE
00013 REM SPREADING ANGLE VARIES PER EXTERNAL ENVIRONMENTS
00020 RiM L=Lensth W-Width T-Thickness K-Thermal Conductivity
0002! REM A=Spreadinv Ansle(radians) S$preadinq Ansle(deore*s)
00022 REM L2(j2)-lonsthtwidth) for next level I=Incrtment
00023 REM RI.R2-Thermal Resistance
00024 REM T1.T2,T4=Thickness for attachment, headerand rackase respectively
00025 REM SUBROUTINE VARIABLES! W=width of field D=# decimal digits
00026 REM 0$=-formatted output J.F.O=tab settines Z(L)-ddevice lenuth
000217 REM r-dovice thickness
00030 REM INPUTS
00040 L=W=T4-0
00050 INPUT "ENTER THE MATERIAL TYPE? "!F$
00059 INPUT "ENTER THE THERMAL CONDUCTIVITY IN W/INCH*CENTIORADE: "1K

175
 40 PIN CERAMIC SIDE BRAZED PACKAGE (CONTINUED)
00060 INPUT "ENTER THE SPREADING ANGLE IN DEGREES: "';S
00061 PRINT "..
00062 PRINT "ATTACHMENT MATERIAL CHOICES: EUTECTIC, SILVER "s
00063 PRINT "EPOXY, GOLD EPOXY,"
00064 PRINT "NON-CONDUCTIVE EPOXY, CONDUCTIVE EPOXY, AND NONE"
00065 INPUT "ENTER THE ATTACHMENT MATERIAL "tAS
00066 PRINT
00067 PRINT "INTERMEDIATE MATERIAL CHOICES: GOLD HEADER,BERYLLIA,ALUMINAu
00068 PRINT "MOLYTAB,NICKLETAB AND NONE"
00070 INPUT "ENTER THE INTERMEDIATE MATERIAL "`H$
000/3 REM TABLE TITLES
"" 00074 PRINT #1, TAB(21)*;"40-PIN CERAMIC SIDE BRAZED PACKAGE"
00075 PRINT #1, "
00076 PRINI #1, "
000/7 PRINT #1,
00080 PRINT #1, TAB(28),"MATERIAL: "IF$
00081 PRINT #1, TAB(28):"CONDUCTIVITY: ";K;"(W/IN.*C)1"
00082 PRINT #1, TAB(28);"SPREADING ANGLE: ";S;" (DEGREES)"
00083 PRINT #1, TA• (28)9"ATTACHMENT MATERIAL: ",,AS
"00084 PRINT fil. TAB(28);"INTERMEDIATE MATERIAL: ";H$
00085 PRINT #1, " "
00087 PRINT t.1," "
00090 PRINT #1. TAB(12);" LENGTH * WIDTH THERMAL RESISTANCE ";
00092 PRINT #1, " Linc * Wine"
00095 PRINT #1, TAB(12)" -....-
00096 PRINT #1, " ....
00098 REM INCREMENTING
00099 Z=2
00100 L-2
00105 W=2
00110 IF L<1O IHEN I=2
00120 IF (L<50) AND (L>=10) THEN I=5
, 00121 IF (L<200) AND (L>=50) THEN 1=10
00122 IF (L<500) AND (L>=200) THEN I=50
00125 REM THICKNESS VARIATION
00129 OOTO 402
001,0 IF (LI<10) OR (WI<10) THEN T4=52
00140 IF (L1<25) AND (L1>=10) tHEN r4-49
00150 IF (LI<50) AND (LI>=25) THEN T4=46
00151 IF (LI<100) AND (L1>-50) THEN T4-42
00152 IF LI>=100 THEN T'i-40
00167 REM THERMAL RESISTANCE 16
0016a A-3.1415927/180-.
00170 RI=Ti/(K*W*(W+2*T4*TAN(A)))
00171 R2=RI*1000
00191 REM NEXT LEVEL DIMENSIONS(SPREADINO)
00192 L2'-L+2*T4*TAN( A)
00193 W2=W+2*T4*TAN(A)
00199 GOSUs 800
00205 IF L=500 THEN 429
00370 LL+I
00380 W-L
00390 GOTO 110
00400 REM THICKNESS OF PREVIOUS LEVELS
00402 IF H$="GOLD HEADER" THEN T2-.2
00403 IF HS&'BERYLLIA" THEN T2-O
00404 IF H$="ALUHINA" THEN T2-0
00405 IF H$="MOLYTAIt" THEN T2=0
00406 IF H$-,"NICKLETAB" THEN T2-0
00407 IF H$-"NONE" THEN T2-0
00408 IF A$,%"EUTECTIC" THEN TI-.5
00409 IF A$="SILVER EPOXY" THEN T1=.5
00410 IF ASU"GOLD EPOXY" THEN TI1.5

176

S * * . . . * .*.* .%

I'm
 40 PIN CERAMIC SIDE BRAZED PACKAGE (CONTINUED)
00411 IF A$="NON-CONDUCTIVE EPOXY" THEN T.1-2
00412 IF A$*"CONDUCrIVE EPOXY" THEN T1=I
00413 IF A$="NONE" THEN TI10
00415 GOSUS 2000
00416 Z=Z+I
00417 GOTO 130
00429 CLOSE #1
00440 END
00500 REM SUBROUTINES
00550 REM OUTPUT
00800 W=5t D=O
00810 V=L: OOSUB 1000: PRINT #1, TAB(14)tQ$;TAB(20)1,"XIIITAB(22);Q$s •

00820 W=13: D-5:V=R2: GOSUB 1000: PRINT #1, TAB(J)QS..

00830 W-7:D=2:V=L2:OOSUB 1000:PRINT #1, TAB(F)1Q$;TAB(62);"X"lTAB(O)fQ$
00840 RETURN
00900 REM TABLE FORMAT
01000 IF 0=0 THEN 1050
0100? Q=INT(V+.5/(IO^D))
01005 C=LEN(STR$(Q))
01010 GOSUB 4000
01011 Q$=LEFT$(STR$(Q),C-I)+"."
01015 Q=INT((V-Q)*(IO^D)+.5)
01020 P$=STR$(Q)
01030 M=LEN(P$)
01033 MI=M-1
01035 0$=Q$+RIGHt$("000O0000"+RIGHI$(P$,MI),D+I)
01040 RETURN
01050 QmINT(V+.5)
01060 Q$=RIGHT$(S$+STR$(Q),W)
.01070 RETURN
01999 REM DEVICE THICKNESS
02000 A=3.1415927/180*St IF Z<10 THEN T=6
02005 IF (Z<25) AND (Z>=IO) THEN T-8
02010 IF (Z<50) AND (Z>-25) THEN T=12
02015 IF (Z<100) AND (Z>=50) THEN T-15
02020 IF Z>=100 THEN T-18
02025 ZI1l*.707: Z2=ZI+2*T*TPA(A): IF Z2>Z THEN 2095
02030 LI=(Z-(2*(T*+T2+T)*TAN(A)))/.707: RETURN
02095 Ll=(Z-(2*(T1+12)*TAN(A)))/.707: RETURN
020'98 REM TAB SETTINGS FOR TABLES
04000 X-C-2
04010 IF X-1 THEN 4050
04015 IF X-2 THEN 4055
04020 IF X_3 tHEN 4060
04025 IF X-4 THEN 4065
04030 IF X_5 THEN 4070
04050 J-371 FaSS: 0-65t RETURN
04055 J-361 F-54t U-641 RETURN
04060 J-351 F-53t 0-63: RETURN
04065 J-341 F*53: 0-631 RETURN
04070 J-33t Fm53: 0-631 RETURN

4*4
"177

"' - . "*, *, •" . . ", . - * -..,.. ".**

" .. *.*..*...
A..' . .'*1**.-
* •., -'*.* * .. * ... .•" .C"
-,,. * ....- ... , -. • .,- " *,,,- . •-* . ..... . ., A- :. -.
 APPENDIX 5.2. Rectangular Surface Programs

This appendix contains the computer program for the square surface device.
This program is referenced in section 5.3.2.

RECTANGULAR SURFACE DEVICE - 50% DISSIPATION

00005 OPEN "LP:" FOR WRITE AS FILE #1
00010 REM ASSUMPTIONS AND VARIABLE NAMES
06011 REM UNIYS FOR LENGTH, WIDTH,& THICKNESS ARE IN MIL INCHES
00012 REM SPREADING ANGLE VPRIES PER EXTERNAL ENVIRONMENTS
00013 REM DISSIPATION AREA IS 50%
00020 REM L=Lensth W-Width TwThicknass K-Thermal Conductivity
00021 REM A=Spreeding Ansle(radians) S-Spreadini Anule(dewrees)
00022 REM Ll(W1)-Adjusted lensth(width) for dissipation area
00023 REM L2(W2)=Lensth(width) for next level I-Increment
00021 REM R1,R2,R3,R4=Thermal Resistance
00025 REM SUBROUTINE VARIABLES: WS-Width of field D-* of decimal disits
00026 REM V=Function Q$-formatted output JFO-tab settinvs
00039 REM INPUTS
00040 L-W=T=O
00050 INPUT "ENTER THE MATERIAL TYPE "IF$
00060 INPUT "ENTER THE THERMAL CONDUCTIVITY IN W/INCH*CENTIORADEE "sK
00061 INPUT "ENTER THE SPREADING ANGLE IN DEGREES "IS
00069 REM TABLE TITLES
00070 PRINT #1, TAB(18);"OECTANOULAR SURFACE DEVICE-50% DISSIPATION"
00071 PRINT #1,
00072 PRINT #1"
000/5 PRINT 1,"
00080 PRINT 41. TAB(28)1"MATERIAL: ";F$
00081 PRINT f1, TAB(28)1"CONDUCTIVITYt ";Kw"(W/[Link])"
00082 PRINT #I* TAB(28)t"SPREADING ANGLE, "ISI"(DECREES)"
00085 PRINT #1, "
00087 PRINT #It .
00090 PRINT *l, TAB(12)1" LENGTH * WIDTH THERMAL RESISTANCE "t
00092 PRINT #1. " Linc * Winc"
00095 PRINT 01, TAB(12)" ----------------
0009c PRINT #It - -"
0('099 REM INCREMENTING
00100 L-2
00105 W-2
00110 IF L<10 THEN 1w2
00120 IF (L<50) AND (L>-I0) THEN 1-5
00121 IF (L<200) ANt (L>-50) THEN 1=10
00123 IF (L<1500) AND (1>-200) THEN I-50
00129 REM THICKNESS VARIATION
00130 IF (L<10) OR (W<10) THEN Ts6
00140 IF (L<25) AND (L>-10) THEN T-s
00150 IF (1.<50) AND (L0-25) THEN T-I2
00151 IF (L<100) AND (L>=50) THEN T-15
00152 IF L>0100 THEN T-I1
00159 W-W+I
00 160 REM 50% DISSIPATION
00161 Ltw.707#L
00162 W1-.70701
0016$ REM THERMAL RESISTANCE
00169 A-3.1415927/180-$
00170 RI-1/(2*K*TAN(A)*(L1-WI))
00130 R2c(LI/NI).((2*r*TAN(l)+*WI)/(2-T*TAN(A).Ll))
00190 R3rLOG(R2)
00191 R4-R1.R3*100o
00193 REM NEXT LEVEL DIMENSIONS(SPREADINO)

178
 RECTANGULAR SURFACE DEVICE - 50% DISSIPATION (CONTINUED)
00194 L2=LI+2*T*TAN(A)
00195 W2=WI+2*T*TAN(A)
00196 IF L2>L THEN L2=L
00197 IF W2>W THEN W2-W
00198 GOSUB 800
00199 REM TABLE INCREJIENTINO
00205 IF L-500 THEN 420
09206 IF L>100 THEN 400
00330 IF (L<100) AND (W+I>L*3) THEN 370
00340 OOTO 110
00370 L-L+I
00380 W-L
00390 GOTO 110
00400 IF (L>=100) AND (W+I>L*1.5) THEN 370
00410 GOTO 110
00420 CLOSE #1
00440 END
00500 REM SUBROUTINES
00600 REM OI PUT
n0000 W5=5: D=0
00810 VYLt GOSUB 1000t PRINT *I, TAB(14);Q$WTAB(20)t"X"t
00815 V=Wt GOSUB 1vO0 PRINT 01, TAB(22);Q0$
00820 W5=13: D=51 V=R4: GOSUB 10004 PRINT *1, TAB(J);Q$!
00830 W5-7: O=2t V-L2: GOSUB 10001 PRINT #1, TAB(F)IQ$1 TAB(62)1 "XXl
00835 V=rJ2t OOSUb 10002 PRINT #1. TAB(O)!Q$
00840 RETURN
00900 REM TABLE FORMAT
01000 IF D-0 THEN 1050
01003 0-INT(V÷.5/(IO^D))
01005 C=LEN(SrR$(O))
01010 OOSUB 4000
01011 Q$=LEFT$(STR$(Q).C-I)÷"."
01015 0=INT((V-Q)*(10'D)÷.5)
01020 PS'sTrR$(0)
01030 MI=LEN(P$)-1
01035 0$=O$÷R1OHt$(t00000000 RIOi4T$(P*.Ml),D÷I)
01040 RETURN
01050 0-INT(V÷.5)
01060 Q$-RIOHT$(S$+SrR$(Q). .5)
01070 RETURN
010W0 REM TAB SETTINGS FOR TABLES
04000 XmC-2
04010 IF X-1 THEN 4050
(#401AS IF Xc2 THEN 4055
04020 IF X-3 THEN 4040
04025 IF Xw4 THEN 4065
04030 IF X-5 THEN 4070
0W050 J-37t F-55t :05t RETURN
04055 J-36t F-541 0=641 RETLRN
04060 im3't Fm53t 0&-3t RETURN
04065 tr34: F-53, 0-634 RETURN
04070 J-33: F-53t 0-634 RETURN

17 749
 RECTANGULAR SURFACE ATTACHHENT
00005 OPEN "LP:" FOR WRITE AS FILE #1
00010 REM ASSUMPTIONS AND VARIABLE NAMES
00011 REM UNITS FOR LENGTH, WIDTH, AND THICKNESS ARE IN MIL INCHES
00012 REM 100% COVERAGE
00013 REM SPREADING ANGLE VARIES WITH EXTERNAL ENVIRONMENTS
00020 REM L=Lenoth W=Width T=Thickness K=Thermal Conductivity
00021 REM A=Sprcadins Ansle(radians) S=Spreadins Ansle(desrees)
00022 REM L2(W2)-Lensth(width) for next level I-Increment
00023 REM R1,R2,R3,R4=lhermal Resistance
00024 REM SUBROUTINE VARIABLES:W5=Width of field D=# of decimal disits
00025 REM V=function Q$=formatted output F,J,O-tab settinss
00026 REM Z=device lensth T2=device thickness
00039 REM INPUT
,00040 L=W=T=O S.
00045 S$%--
00046 PRINT"ATTACHMENT MATERIAL CHOICESt EUTECTIC, SILVER EPOXY,
00047 PRINT"GOLD EPOXY, NON-CONDUCTIVE EPOXY. CONDUCTIVE EPOXY, j
00048 PRINT"AND NONE"
00050 INPUT"ENTER THE MATERIAL TYPE "IF$
00060 INPUT"ENTER THE THERtKAL CONDUCTIVITY IN W/INCH*CENTIORADE "iK
00065 INPUT"ENTER THE SPREADING ANGLE IN DEGREES "IS
00069 REM TABLE TITLES
00070 PRINT#1, TAB(24)t"[Link] SURFACE ATTACHMENT"
00075 PRINT#1, " "
00076 PRINT#I, * "
00077 PRINT41.
00080 PRINT#1. TAB(28)1"MATERIAL: "IF$
00081 PRINT#1, 1AB(28)I"CONDUCTIVITYI "IKI"(W/IN.*C)"
' 00082 PRINT*1, TAS(28);"SPREADING ANGLE: "iSt"(DEOREES)u
00085 PRINT*I. "
00087 PRINT#1, ""
"00090 PRINT#I. TAB(12):" LENGTH * WIDTH THERMAL RESISTANCE "I
00092 PRINT *I. " Linc * Winc"
00095 PRINT #1, TAB(12) - --------------- -------- "
"00096 PRINT #It ------ "
00099 REM I NCREMENT ING
00100 L-2
"00105 W-2
"0X0106 Z-2: Yw2
-00110 IF L-10 THEN 1-2
k00120 IF (L<50) AND (L>=I0) THEN 1-5
00121 IF (L<200) AND (L>m50) THEN 1-10
0=.
0123
I IF (L<500) AND (L0-200) THEN -,50
00130 0OT0 500
00160 wW.I
00160-REM I HERJAL RES ISTANCE
'0161 A-3.1415927/1*0*S
J ~ ýX 1-Y)! RmI-1(1*VoTAN(A)*(L-W}))
00•10 R2-(L/W).({2eT*TAN(A).4&)I(2ertTAN(A).L))
-I ,1o0 RS, LL00 (R2)
* -00 '1 REMI.3IO. t%
00l•2 REM NEXt LEVEL DIIENSIONS(SPREADINO)
-- 193 L2uL.•2T*TAN(A) i%
% (1010!~ WeU2wN*2T1ANCA)
""Ib.~ 0OUB ,i00'
6'•¶
(.-) 19t- IF Z-10to 1HEN I
I->'7 IF AND
.D t.,I:"Z3) THEN 201
t00141-S QnOTA 202
1,V
i,(qO IF (Zu1(K0) &*ND (Y.I'-z.1.5) THEN 201
-W)_.00 0OrO 202

180
6-=•
 RECTANGULAR SURFACE ATTACHMENT (CONTINUED)

00201 Z-Z+I1 Y"Z

00202 GOSUB 800
00204 REM TABLE INCREMENTING
00205 IF L=500 THEN 700
00206 IF L>=100 THEN 400
00330 IF (L<1O0) AND (W+I>L*3) THEN 370
00340 GOTO 110
00370 L=L+I
00380 W-L
00390 ooro 1to
00400 IF (L>100) AND (W+I>L*1.5) THEN 370
00410 GOTO 110
00490 REM ATTACHMENT THICKNESSES
00500 IF F$="EUTECTIC" THEN T-.5
"00510 IF F$="SILVER EPOXY" THEN T-.5
"00520 IF F$="GOLD EPOXY" THEN T-.5
00530 IF F$="NON-CONDUCTIVE EPOXY" THEN T-2
00540 IF F$="CONDUCTIVE EPOXY" THEN T-1
00550 IF F$="NONE" THEN 7-0
00560 GOTO 160
00700 CLOSE #1
00720 END
00740 REM SUBROUTINES
00750 REM OUTPUT
00800 W5-z5s -0=
00810 V=L: OOSUB 1000! PRINT 01, TAB(14)1Q$lTAB(20)l*X"l
-00815 V-413 GOSUB 1000t PRINT #It TAB(22)1Q0$
00820 W5=131 DmSt V=R4t GOSUJ5 10001 PRINT *1, TAB(J)IQ0$
001330 W5-7: D-24 V-La: GOSUB 1000t PRINT *1, TAB(F)IQSITA(462)I "X~l
00835 V=W2: GOSUJi 1000: PRINT #1. TAD(0)1Q$
S"00840 RETURN
00900 REM TABLE FORMAT
01000 IF D=0 THEN 1050
01003 QOINT(V4.5/( 10D))
01005 C-LEN(STRS(Q))
01010 GOSUB 4000
"01011 OG-LEFT$(STRV4Q).C-l )*". '•
S0 O"INT( (V-O0*10•D)..5)
!020PI,=TRI01015
01020 PS-STRIOG)
01030 MI-LEN(PF)-1
0103'5 O$-,*R7C4T$( "00000000".RIOHTSCPS.N ) .1+I
01040 RETURN
01050 0WINT(V..S)
01060 0$"RI HT$ ($S÷S.T$ (Q).b5)
01070 RFTURN
k ," 01090 REM 1,EVICE THICKNESS
02000 An3. 1415927/1804S
02010 IF Z<10 THEN T2w6
.'- 02020 IF (Z<25) AND (Z>-u10) THEN T2.S
02030 IF fZV50) ANDr (Z>w25) THEN T2-12
02040 IF (Q<100) AND (ZVoSO) THEN T2-15
•" '0205-1, Ii THLN
* 0055YuRY*I
S02060 i1-Z*.7071 YI•Y*.707t Z2-Zl*2*12eTAN(A)t Y2-YVI2*T2*TAN(A)
020615 IF Z2ýt THEN Z,'l
026•6 IF v2rr THEN Y2,Y
0,2O060 Z3'Z-121 Y3-Y-Y2
02070 IF Z3-0 THEN 20,.
02072 Ll-(l-2*T..TAlNfIA))/.707
0207A Z4-2t ZwL3t GOSU8 30001 L4r(Z4-2eT3*TAN(A))/.707

1*. 181

I9.-'
 RECTANGULAR SURFACE ATTACH4ENT (CONTINUED)
02076 IF LZ>L4 THEN L2-L1
02078 Z=Z4
02080 IF Y3=0 THEN 2096
02082 W3=(Y-2*T2*TAN(A) ) /.707
02084 IF W2>W3 THEN W2-W3
* 02086 RETURN
02095 L2=Z: GOTO 2080
02096 W2=Y: RETURN
"-" 03000 IF Z<10 THEN T3=6
0:ýC010 IF (Z<25) AND (Z>=10) THEN T3=8
0:3020 IF (Z<50) AND (Z>=25) THEN T3=12
03030 IF (Z<100) AND (Z>=50) THEN T3=15
03040 IF Z>=100 THEN T3=18
03050 RETURN
03999 REM TAb SETTINGS FOR TABLE
04000 X=C-2
04010 IF X=1 THEN 4050
04015 IF X=2 THEN 4055
04020 IF X=3 THEN 4060
04025 IF X=4 THEN 4065
"040:'30 IF X=5 THEN 4070
"04050 J=37: F=55: 0=65: RETURN
"04055 J=36: F=54: 0=64: RETURN
0-060 J=35: F=53: 0=6.: RETURN
04065 J=34: F=53t 0=63t RETURN
04070 J=33: F=53: 0=63: RETURN

RECTANGULAR SURFACE - INTERMEDIATE MATERIAL

00005 OPEN "LP: " FOR WRITE AS FILE 0I
00010 REM ASSUMPTIONS AND VARIABLE NAMES
00011
tX REM UNITS FOR LENOTH, WIDTH, AND THICKNESS ARE IN MIL INCHES
00012 REM SPREADING ANGLE VARIES PER EXTERNAL ENVIRNMENT
S00013 REM 100% COVEklGE
""" 00020 REM L-Lensth W-Width T-Thickness K-Thermal Conductivity
00021 REM A-S•Preadinv Ansle(radians) SuSpreadins Ansle(delfees)
00022 REM L2(W2)- Lenoth(width) for next level I-Incre•mnt
00023 REM R1.R2.R3.R4.,ThermaI Resistance
Q00024 REM SUBROUTINE VARIABLE~sW*UWidth of field D-0 of decimal digits
0002"5 REM Vefunction O$uformatted output .[Link] settines
00Q10 REM INPkITS
-- v tXXI 10 LwWmT"0
.O%45 PRINT "INTERMEDIATE MATERIAL CHOICESt GO-LD HEADER. BERYLLIA,
00046 PRINT "ALUIMINA. MOLYtAB. NIMCIELTAB, AND NONE,
kP0050 INPUT "ENTkR THE MPITERIAL TYPE ";F$
0,'0<60 INPUT "ENTER THE THERMAL [Link] IN WiINCH*CENTIGRADE 01K
00065 INPUT "ENTER THF SPREADING ANGLE IN DEGREES "tS
0X069 REM TABLE rITLES
O{KXO PRINT II, TAB I9)1."RECTANGULAR SURFACE-INTERMEDIATE MATERIAL"
00072 PRINT a1t * -

('K-
"73 PRINT *I. " '

00075 PRINT 6I1. "

t'00IO PR4::T 41. TABC2Sý)tMATERI-t. "tF$
•00081 PRINT $I. TAB9(2)1"CkW4D*CTIVITYt "tKt'CU/IN.0C)"
,'06O2 PRINT *it TAB(2e):1"SIPREA1DING AN4LEl "ISt"(DEGREES)"
.-00,•0.5 PRINT al. "
S008'*.? PRINT 0i1 . -

0009rO PRINT ml. TAB'12)." LTiHH * b•IDTH THERMAL RESISTANCE 's

O00'g2 PRINT li. Ltne 4 Wince
0(0095 PRINT I1. TAB(12);" --

182
*I*
 RECTANGULAR SURFACE - INTERMEDIATE MATERIAL (CONTINUED)
00096 PRINT #1, " -- "
00099 REM INCREMENTING
00100 L=2
00105 W=Z
00110 IF L<1O THEN I-2
00120 IF (L<50) AND (L>=10) THEN I--5
00121 IF (L<200) AND (L>=50) THEN I=10
00123 IF (t•<500) AND (L>=200) THEN I=50
00130 OOTO 411
00160 J=W+I
00161 REM THERMAL RESISTANCE
00162 A=3. 1415927/180*S
00170 RI=I/(2*K*TAN(A)*(L-W))
00180 R2=(L/W)*((2*T*TAN(A)+W)/(2*T*TAN(A)+L))
00190 R3;-LO ( R2)
001,91 R4=R I*R3* 1000
00192 REM NEXT LEVEL DIMENSIONS(SPREADING)
00193 L2=L+2*T*TAN(A)
00194 W2=W+2*T*TAN(A)
W
019..'5 GOSUB 800
00204 REM TABLE INCREMENTING
00205 IF L=500 THEN 420
00206 IF L>=100 THEN 400
00330 TF (L<100) AND (W+I>L*J) IHEN 370
00340 6OTO 110
00370 L-L+I
00380 W=L
00390 OOTO 110
00400 IF (L>=100) AND (W•I>L*1.5) THEN 370
00409 GOTO 110
00410 REM THICKNESSES
00411 IF F$="OOLD HEADER" THEN T=.2
00412 IF FS-"BERYLLIA" THEN T=0
00413 IF FW="ALUMINA" THEN TO
0-0414 IF F$="M0LYTAW" WHEN T-O
00415 IF F$,"NICKELTAB" THEN T=O
00A.16 IF FS="NONE" THEN T-0
00417 (,OTO 160
"00420 CLOSE 01
00440 END
00500 REM SUBROUTINES
00550 REM OUTPUT
00800 W5-5! DO
,0810 VmLt OOSUB 1000t PRINT 01, TAB(I4)iQ*tTAB(20)UX"s
00$15 V=WI oC.SU8 1000: PRINt I1, TAB(22)iQ$!
00820 W5&13: Dm5t VwR4 OGOSUb 1000t PRINT N1. TAB(J)tQSt
"08•30
(1,5,71 0-21 V-=L24 GOSUB 10(101 PRINT *1I TAB(F)lQ0ITAB(62)s*X M ,
'(4035
V-wit OSUB 1O000 PRINT 01. TAB(O)SO$
"0-10-4• RETURN
• (Ký10, REM TABLE FORMAT
"1)
1000 IF L•0 THEN 1050

01005 C•LEN(STRI(Q))
01 ( 10 000'!U 4000
. 01011 O0-LEFT*{STR4tO},C-l)*"."
',,.,,01015 O=INT{(V-O).(1O'D)..5)
"'0102(1
F'STR$ 0)
01030 MI-LEN(P$ -1
.. ~
'•.• ~ ( I10 ý'ý
5. 05"05•,R IHT ( "00000•" •R l04T$ (P$, I) ,D÷I )
-o01040 RETURN
101,50 oft N1 (V1,5+
•010%0 0$RIGHT$(S$SSTl%10 . W5)
.,- lOWO RETURN

183

:: . .. --..
'•* * * ~~ * ' ; t.~..*.
 RECTANGULAR SURFACE - INTERMEDIATE MATERIAL (CONTINUED)

03999 REM TAB SETTINGS FOR TABLES

04000 X=C-2
04010 IF X=1 THFN 4050
04015 IF X-2 THEN 4055
04020 IF X=3 THEN 4060
04025 IF X=4 THEN 4065
04030 IF X=5 THEN 4070
04050 J=37: F=55: 0=65: RETURN
04055 J=36: F=54: 0=64: REIURN
04060 J-35: F=53: 0=63: RETURN
04065 J=34: F=53: 0=63: RETURN
04070 J=33: F=53: 0=63: RETURN

RECTANGULAR - 40 PIN CERAMIC SIDE BRAZED PACKAGE

00005 OPEN "LP:" FOR WRITE AS PIL.E #11

00010 REM ASSUMPI IONS AND VARIABLE NAMES
00011 REM UNITS FOR LENGTH, WIDTH, AND rHICKNESSS ARE IN MI". INCHES
00012 REM SPREADING ANGLE VARIES PER EXTERNAL ENVIRONMENT
00020 REM L-Lensth W=Width T=Thickness K=Thermal Conductivity
00021 REM A=Spreadins A,,ile(radians) S=Spreadins Anule(desrees)
00022 REM L2(W2)=L-nuth(width) f.r next level I-Increment
00023 REM R1,R2,R3,R4'Ther-mal Resistance
00024 REM TI,T2,T4=Thickness for attachmentheade*.and Packaie respectively
00025 PEM SUBROUTINE VARIABLEStW5= Width of fit'd D-# of decimal digits
00026 REM V-function 0$=formatted output Z(L1)=device lenith
00027 REM T=device thickness
00030 REM INPUTS
00040 L=W-T==0
00045 INPUT "ENTER THE MATERIAL TYPE ";F$
00050 INPUT "ENTER THE THERMAL CONDUCTIVITY IN W/INCH*CENTI0RADE "tK
00055 INPUI "ENTER THE SPREADING ANGLE IN DEUREE$ "IS
00060 PRINT " '
00061 PRINT "•.TIAZHMENT MATERIAL CHOICESt EUTECTIC, . SILVER
0004.2 'rINT "EPOXY, GOLD EPOXY, NON-CONDUCTIVE EPOXY,
0C1063 PRINT "CONDUCTIVE EPOXY, AND NONE"
00064 INPUT "ENTER THE ATTACHMENT MATERIAL, "tA$
O000! P-R INT .
00066 PRINT "INTERMEDIATE MATERIAL CHOICES: GOLD HEADER. BERYLLIA*
00067 PRINT "ALUMINA, MOLYTAB. NICKELTAB, AND NONEu
00068 INPUT "ENTER THE INTERMEDIATE MATERIAL: ";IH
0C.00.q REM TABLE TITLCS
00070 PRINT #1. TAB(16)1"RECTANOULAR-40 PIN CERAMIC SIDE BRAZED PACKAGE"
00071 PRINT 91. " "
(0)072 PRINT 41. " "
000/5 PRINT 411.
t'•O,-, PRINT VS. '•B(•_0)S'MARTERIALS "tr*
00081 PRINT Si1. TAB28)tU"CONDUCTIVITY2 "tKt"(W/IN.*C)"
000e2 PRINT 411. TAB(28)I "SPREADING ANGLE: "tSt"(DEGREES)"
('0003 PRINT 01. TAB(23)t"ATTACHMENT MATERIALt "SAS
000k84 PRINT *It TAB(29)t"INTERMEDIATE MATERIAL: "tH$
k00085 PRINT 01I. "
00007 PRINT 1,.
(0090 PRINT ti. TAB(12)t" LENGTH * WIDTH THERMAL RESISTANC "
0'0002 PRINT io1," [Link] WinC"
K10O95 PRINT 41. TAB(12)t" -----------------------------------
0<O PRINT U-, " ----------
C,0OS¢ REM INLREMENTING
0010'
K) L"2
00105 W"2

"9"9 184
'I.
 RECTANGULAR - 40 PIN CERAMIC SIDE BRAZED PACKAGE (CONTINUED)

00106 Z=2
00110 IF L<10 THEN 1=2
00120 IF (L<50) AND (L>10) THEN 1=5
00121 IF (L<200) AND (L>=50) THEN I=10
00123 IF (L<500) AND (L>.200) THEN I=50
00125 REM THICKNESS VARIATION
001-9 GOTO 411
00130 IF ILI<10) OR (WI<10) THEN T4=52
00140 i! '1.1'25) AND (LI>=10) THEN T4=49
OW.0 f.ftL1<50) AND (L1>=25) THEN T4=46
00151 IF" (LI<lC.-) AND (L1>=50) THEN T4=42
S0C152 IF L,>=100 THEN T4=40
"00160 W=÷+I
00162 REM THERMAL RESISTANCE
00,165 P 3.1415927/180*-
061?0 R1=1/(2*K*fAN(A)*(L-W))
"00180 R2=CL/W)*((2*T4*TAN (A)-+W)/(2*T4*TAN(A)+L))
00190 H3=LO3 (R2)
00191 FR4='I*R3*1000
00192 REM NEXI LEVEL DIMENSIONS(SPREADING)
00193 L2=L+2*T4*TAN (A)
00194 |42=W+2*T4*TAN (A)
00199 GOSUB 800
00200 REM TABLE INCREMENTING
00205 IF L=500 THEN 435
00206 IF L>=100 THEN 400
00330 IF (L<100) ANO (W+I>L*3) THEN 370
00340 GOTO 110
00370 L=L+I
00380 W=L
00385 Z=Z+I
"00390 GOTO 110
00400 IF (L>-100) AND (W4IX.*1.5) THEN 370
00410 GOTO 110
00411 REM THICKNESS OF PREVIOUS LEVELS
00412 IF H="'GOLD HEADER" THEN T2-.2
00413 IF H$•"BERYLLIA" THEN T2-O
00414 IF H$="ALUMINA' THEN T2=O
00415 IF H$="MOLYTAB" THEN T2-O
001416 IF H-We"NICKELTAB" THEN T2-0
00417 IF H$-"NONE" THEN T2-0
00420 IF A$w"EUTECrTIC" THEN Tl-.5
L 00421 IF A$-"SILVER EPOXY" THEN TIW.5
00422 IF A-"GOLD EPOXY" THEN TI-.5
00423 IF A,,NON-CONDUCTIVE EPOXY" THEN Tim2
00424 IF A$-"CONDUCTIVE EPOXY" THEN TI-1
00425 IF At$"NQNE* THEN TI-O
00430 OOSUB 2000
00433 GOTO 130
00435 CLOSE 01
00440 END
005.00 REM SUBROUTINES
0X0550 REM OUTPUT

0. 0010 V-iLt WSL'B 1000t PRINT l1. TAB(14)tk-jtTAB(2O)t"X"l

S00815 V-W: WOSU8 1000: PRINT 1, TAB(g2)tO$t
00820 W5-13: .P-5 V-R4t GOUL 1000t PRINT 01. TAB(J)OQst
No9-. : 0 55-7:t D22t VL2: GOSUB 1000: PRINT I1. TAB(F)Q0$TAB•62)1"X'l
l01*8135 Vr'W2t COWSUI'• IWO: PRINT #I. TAB(O)sOS
00$1.
40 RETLRN
A0'000 REM TABLE FORMAT
OI,>vv IF 0-0 THEN 1050

185

.* %,*
 RECTANGULAR - 40 PIN CERAMIC SIDE BRAZED PACKAGE (CONTINUED)
01003 Q0INT(V+.5/(10D))
01005 C=LEN(STR$(Q))
01010 G0SUB 4000
01011 0$=LEFT$(STR$(Q),C-1)+"."'
01015 Q=INT((V-0)*(IO^D)+.5)
01020 P$=STR$(Q)
01030 MI=LEN(P$)-1
01035 Q$=Q$+RIcHT$("0000000"+RIGHT$(P$,M1),D+I)
01040 RETURN
01050 Q=INT(V+.5)
01060 Q$mRIGHT$(S$+STR$(Q),W5)
01070 RETURN
01999 REM DEVICE THICKNESS
02000 A=3.1415927/180*S: IF Z<10 THEN T-6
02005 IF (Z<25) AND (Z>10) THEN T-8
02010 IF (Z<50) AND (Z>=25) THEN T=12
02015 IF (Z<100) AND (Z>=50) THEN T-15
02020 IF Z>=100 THEN T-18
02025 ZI=Z*.707: Z2=ZI+2*T*TAN(A): IF Z2>Z THEN 2095
02030 LI=(Z-(2*(TI+T2+T)*TAN(A)))/.707i RETURN
02095 LI=2-2*T2*TAN(A)z RETURN
02098 REM TAB SETTINGS FOR TABLES
04000 XýC-2
04010 IF X=I THEN 4050
04015 IF X=2 THEN 4055
04020 IF X=3 THEN 4060
04025 IF X=A THEN 4065
04030 IF X=5 THEN 4070
04050 J=37: F=55: 0=65: HElURN
04055 J=36t F=54: 0=64: RETURN
04060 J=35: F=53t 0=63: RETURN
04065 J=34: F=53: 0-63: RETURN
04070 J-33% F-53t 0-63t RETURN

0.•

"a186
%•0 % ° • % . * • , , . " ,• , . -°. , , . .* . - • o . . . . . . . -. .
 APPENDIX 5.3. Circular Surface Programs
This appendix contains the computer program for the circular surface

device. This program is referenced in section 5.3.3.

CIRCULAR SURFACE DEVICE

00005 OPEN "LP:" FOR WRITE AS FILE #1

00010 REM ASSUMPTIONS AND VARIABLE NAMES
00011 REM UNITS FOR DIAMETER, THICKNESS, AND RADIUS ARE IN MIL INCHES
00012 REM DISSIPATION AREA IS: 100%
00013 REM SPREADING ANGLE VARIES PER EXTERNAL ENVIRONMENT
00020 REM D=DIAMETER T-THICKNESS K-THERMAL CONDUCTIVITY
00021 REM A=SPREADING ANGLE(RADIANS) S= SPREADING ANGLE(DEGREES)
00022 REM I=INCREMENTS R=RADIUS R2,R3=THERMAL RESISTANCE
00023 REM R4=NEXT LEVEL DIMENSIONS DUE TO SPREADING
00024 REM SUBROUTINE VARIABLES: W=WIDTH OF FIELD D-* DECIMAL DIGITS
00025 REM Q4C=FORMATTED OUTPUT JF,O=TAB SETTINGS
00030 REM INPUTS
00040 D=T=O
00050 INPUT "ENTER THE MATERIAL TYPE: "IF$
00060
6 INPUT "ENTER THE THERMAL CONDUCTIVITY IN W/INCH*CENTIGRADEI "sK
00065 INPUT "ENTER THE SPREADING ANGLE IN DEGREES: "IS
00066 REM TABLE TITLES
00070 PRINT #1, TAB(28);'"CIRCULAR SURFACE DEVICE"
00075 PRINT #1, .".
00076 PRINT #1, " "
00077 PRINT #1. " "
00080 PRINT #1. TAB(26);"MATERIAL: "IF$
00081 PRINT *1. TAB(26)1":ONDUCTIVITYS "1Kt"(W/IN.*C)"
00082 PRINT #1, TAB(26)I"SPRFADIN0 ANGLE: "1S;"(DEGREES)"
00083 PRINT #1, "
CKHtR-5 PRINT #1 ".
00090 PRINT #1, TAB(i4)1" DIAMETER THERMAL RESISTANCE RADIUS(inc)
00095 PRINT #I, riB(14);"-- -----------------
00099 REM INCREMENTING
00.100 D01
00110 IF 0<10 THEN 1=1
00120 IF (D<5O) AND (D>I10) THEN 1I-2
00125 REM THICKNESS
00130 T=D/15
0X0 155 REM 1HERMAL RESISTANCE
00156 A=3. I •15927/160.$
"~~1 00160 R-D/2
00170 R2v( 1 /( .([Link](A))).(1/R-I/([Link](A)))
00172 R3-R20 I0k00
00175 REM NEXT LEVEL DIMFNSIONS(SPREADING)
""
,.31•0 R4uR.T*(AN(A)
00190 IF R4>D THEN R4wD
"&N00200
C0$UB 50: REM PRINT *I1TAB(I);DtTAB(32)tR3;TAB(51);R4
""02')2 REM TABLE FORMAT
-Ž•05 IF D0-50 THEN 25
00210 D-D*t
00(2.0 C"YI0 110
"<K1225 CLOSE 01
,r.,"E•END
""H5(150 REM S*JUROUT INES
005.50 REM OUTPUT
W-4*
K180 Ck3'(0
0.08 10 V-D: [Link] 10(Kit PRINt *I. TABCIS)tOIt
00820 W-11t: D-4: VR3t C'0SUB 1t00, PRINT 01. TAB(J.POI0
W-s: D3,2: VR4: 0OASUB 1000t PRINT I1. TAB(Fe)10$
)K*3.0

187

6%
. ... *... .. .-. • - -.- -... .. .. . -. ~. ...- .. .. . . ... - . ".•.*.. * "
 CI4CULAR SURFACE DEVICE (CONTINUED)
00840 RETURN
00900 REM TABLE FORMAT
01000 IF D3=O THEN 1050
01003 0=INT(V+.5/(10^D3))
01005 C-LEN(STR$(Q))
01010 GOSUB 4000
01011 Q$=LEFT$(STR$(Q),C-1)+".#'
01015 Q=INT((V-Q)*(10^D3)+.5)
01020 P$=STR$(Q)
01030 MI=LEN(P$)-,1
01035 O$=Q$+RIGHT$("00000000"+RIGHT$(P$,M1) .D3+1)
01040 RETURN
01050 Q=INT(V+.5)
01060 Q$=RIGHT$(S$+STR$(Q).W)
01070 RETURN
01080 REM TAB SETTINGS FOR TABLE
04000 X=C-2
04010 IF X=I THEN 4050
04015 lF X=2 THEN 4055
" 04020 IF X=3 THEN 4060
0402:5 IF X=4 THEN 4065
04050 J=34: F=53: RETURN
04055 J=33: F=52: RETURN
04060 J=32: F=51: RETURN
04065 J=31: F=50: RETURN

CIRCULAR SURFACE METALLIZATION - PLJTINUM

00005 OPEN "LP9" FOR WRITE AS FILE #1

00010 REM ASSUMPTIONS AND VARIABLE NAMES
00011 REM UNITS FOR RADIUS AND THICKNESS ARE IN MIL INCHES
00012 REM 100% COVERAGE
00013 REM SPREADING ANGLE VARIES WITH THE EXTERNAL ENVIRONMENT
00020 REM R-RADIUS T-THICKNESS K.*THERMAL CONDUCTIVITY
00021 REM A=SPREADING ANGLE(RADIANS) S-SPREADING ANGLE(DEGREES)
00022 REM ImINCREMENTS R2.R3-THERMAL RESISTANCE
00023 REM R4-RADIUS FOR NEXT LEVEL
00024 REM SUBROUTINE VARIA4LESt W=WIDTH OF FIELD DuO DECIMAL DIGITS
00025 REM O,-FORMATTED OUTPUT JF,.-TAB SETTINGS
00035 REM INPUTS
S000O R"T-O
00050 INPUT "ENTER THE MATERIAL TYPEt "tFt
00060 INPUT "ENTER THE THERMAL CONDLUCTIVITrY 'N W/INCH*CZN47GRADES•1 'K
(00065 INPUT "ENTER THE SPREADING ANGLE IN DEtAEESt "t.
0(067 REM TABLE T:TLES
%000070 PRINT 01 TAIV(0)t"[Link] SURFACE METALLIZATION-PLATINUMW
0'071 PRINT #1.,
0XK072 PRINT 01.,
0'0075 PRINT 01,
00080 PRINT 31. TAB(26)t"MATERIALt "tF$
00081 PRINT t1. TAB(26)stC"ONDUCTIVITYS "lKt"(W/IN..C)"
000.*2 PRINT 01. TA{(20)t"SPREADINi ANOLE9 "tSl"(DEGREES)"
00X'3)#
PRINT 01. "
000*5 PRINT 01. "
00040 PRINT Pl. TAV(14)%"
% RAIILS THERMAL RESISTANCE RADIUS(in¢c)
oo000S PRINT *I. TAB(14)- -------- ------------------
00.9" REM INCREMENT INO

00110 IF R,"I0 THEN 1-1

00120 IF (R<50) AND (A)1O) THEN 1-2
001Ž25 REM THICKNESS

188
 CIRCULAR SURFACE METALLIZATION - PLATINUM (CONTINUED)

00130 T-.008
00135 REM THERMAL RESISTANCE
00165 A=3.1415927/180*S
00170 R2=(I/(K*3.1415927*TAN(A)))*(1/R-1/(R+T*TAN(A)))
00175 R3=R2*1000
00177 REM NEXT LEVEL DIMENSIONS(SPREADING)
00180 R4=R+T*TAN(A)
00199 REM OUTPUT
00200 GOSUB $00
00202 REM TABLE FORMAT
00205 IF R=50 THEN 225
00210 R=R+I
00220 GOTO 110
00225 CLOSE 01
00230 END
00500 REM SUBROUTINES
00550 REM OUTPUT
00800 W-4: D=0
00810 V=Rt GO5SUB 1000: PRINT #1, TAB(18)1i$;
00920 W=1i: D=4: V=R3: GOSUB 1000: PRINT #1, TAB(J)10S$
00830 W=6: D=2: VR4: OOSUB 1000* PRINT *lI TAB(F);Q$
00840 RETURN
00900 REM TABLE FORMAT
01000 IF D-0 THEN 1050
01003 Q=INT(V+.5/(IO^D))
01005 C=LEN(STR$(Q))
01010 GOSUB 4000
01011 Q$=LEFT*(STR$(Q).C-1)+"."
01015 Q=INT((V-Q)*(IOD)+.5)
01020 P$=STR$(Q)
01030 MI=LEN(P$)-1
01035 Q#=Q$+RIGHT9("OOOOOOOO"+RIOHT$([Link]),D+I)
01040 RETURN
' "01050 Q=INT(V+.5)
01060 Q$-RIGHTS(S$+STR4(Q),W)
0!070 RETURN
01080 RE" TAB SETTINGS FOR TABLE
04W00 XVC-2
04010 IF X-1 THEN 4050
04015 IF X*2 THEN 4055
04020 IF X-3 THEN 4060
04035 IF X-4 THEN 4065
04050 j-34s F-53i RETURN
04055 .J33: F-52t RETURN
04060 dJ32 Fv51: RETURN
04065 .Jo31 F-504 RETURN

/•;• 189

4.
 CIRCULAR SURFACE METALLIZATION - TITANIUM

00005 OPEN "LP:" FOR WRITE AS FILE #1

00010 REM ASSUMPTIONS AND VARIABLE NAMES
00011 REM UNITS FOR RADIUS AND THICKNESS ARE IN MIL INCHES
00012 REM 100.% COVERAGE
00013 REM SPREADING ANGLE VARIES PER EXTERNAL ENVIRONMENT
00020 REM R=RADIUS T=THICKNESS K=THERMAL CONDUCTIVITY
00021 REM A=SPREADING ANGLE(RADIANS) S-SPREADING ANGLE(DEGREES)
00022 REM I=INCREMENTS R2,R3=THERMAL RESISTANCE
00023 REM R4=RADIUS FOR NEXT LEVEL
00024 REM SUBROUTINE VARIABLES: W=WIDTH OF FIELD D=# DECIMAL DIGITS
00025 REM Q$=FORMATTED OUTPUT J,F,O=TAB SETTINGS
00035 REM INPUTS
00010 R=T=O
00050 INPUT "ENTER THE MATERIAL TYPE: ";F$
00060 INPUT "ENTER THE THERMAL CONDUCTIVITY IN W/INCH*CENTIGRADE: "tK
00065 INPUT "ENTER THE SPREADING ANGLE: "IS
00067 REM TABLE TITLES
00070 PRINT fl, TP.B(20)t"CIRCULAR SURFACE METALLIZATION-TITANIUM"
*v0071 PRINT #1, "
00072 PRINT *I, ""
00075 PRINT #I, "
00080 PRINT #1 TAB(28)r;MATERIAL: "tF$
*00081 PRINT #1, TAB(28);"CONDUCTIVITY: ";Ki "(W/IN.*C)"l
00082 PRINT #1, TAB(28 );"SPREADING ANGLE: ";S;'"(DEGREES,"" _

00083 PRINT #1, " "

00085 PRINT #I. " "
"10090 PRINT el, TAB(14)*" RADIUS THERMAL RESISTANCE RADIUS(inc) "'
00095 PRINT #1, TAB(14):" -
00099 REM INCREMENTING
00100 R=t
"00110 IF R110 THEN 1=1
-:00120 IF (RK'50) AND (R>10) THEN 1=2
0 l125 REM THICKNESS
i':00: 13 T=..
,,t'' 1,35 REM THERMAL RESISTANCE
* *:)o1•5 A=3.I415927/1$0*S
VC,17C- RI=(I/k(.*'•.1415927*TAN(A)))*(l/R-l/(R+T*TAN(A)))

S"NEXT LEVEL DIMENSIONS(SPREADINhiG

"" I')20f)
1o0' REM
C,Ob$OOB
OUTPUT
"-)4"
0020Q2
REM TABLE TITLES
')(Il IF R-50 THEN 21.'5
':'02IO R~xR+ I
00221) GOTO I 10.
"00Z2ý- CLOSE 0I
6I051x", REM SU0LIUT I NES
"-0055f) REM OUTPUT

et(s$ I ) V-tRt %.A u'('('PRINT 81. TAP(I8):OW:,4*

¢•N) Wnil Vv4t V'.-W, CtOSUP''O PRINT St. TABc .J)t0O
t."
S,'.'•.?.40r SWmt: tl4t
RE [Link]- V--4t CtO$U;sU IOQ'Z'Z PRINT 01. TAB(FIt06

1v,000 REM TABLE FORMAT

': (s(i IF tHEN
fr': .

-'1'.';5 COLEN'.STRV• O)'

190

-,. -, *.*4.' *- v *. - *.. ,- '. .• .- -..- " ". .. * ";.. *'..:,*

. U -*•% -,Ti-, .,F:•"-" .'-, **.
".*2'.. . *'." .L.. .' ' -. .".
lil.*.*. * .. , • .. • . iI .. . . .U . UI - *I * , - .% • - i I
 ilk

[Link] SURFACE METALLIZATION- TITANIUM (CONTINUED)

0101 1 Q$-LEFT$ (STR* ( Q),C- 1) +". " '

01015 Q-INT((V-Q)*(I0AD)+.5)
01920 P$=STR$(Q)
01030 MI=LEN(P$)-I
01035 0$=Q$+RIGHT$("00000000"÷RIGHT$(P$,M1 ),D+I)
01040 RETURN
01050 Q=INT(V+.5)
01060 Q$=RIGHT$(S$+STR$(Q),W) .
01070 RETURN
01080 REM TAB SETTINGS FOR TABLES
04000 X=C-2
04010 IF X=l THEN 4050
04015 IF X=2 THEN 4055
04020 IF X=3 THEN 4060
04025 IF X=4 THEN 4065
04050 J=34: F=53: RETURN
04055 J=33t F=52: RETURN
04060 J=32: F=51: RETURN
04065 J-311 F=502 RETURN

CIRCULAR SURFACE - GOLD PLATE r

00005 OPEN "LP:" FOR WRITE AS FILE #1
*=00010 REM ASSUMPTIONS AND VARIABLE NAMES
00011 REM UNITS FOR RADIUS AND THICKNESS ARE IN NIL INCHES
00012 REM 100% COVERAGE
* 00013 REM SPREADING ANGLE VARIES WITH THE EXTERNAL ENVIRONMENT
00020 REM R-RADIUS T-THICKNESS KITHERMAL CONDLCTIVITY
00021 REM A-SPREADINO ANGLE(RADIANS) S-SPREADING ANOLE(UDOREIS)
00022 REM I-INCREMENTS R2.R3.'THERMAL RESISTANCE
00023 qEM R4-RADIUS FOR NEXT LEVEL
00024 REM SUBROUTINE VARIABLES$ W-WIDTH OF FIELD DI DECIMAL DIOITS
00025 REM GQ$,FORMATTED OUTPUT JFO-TAB SETTINGS
00030 REM INPUTS
"00040 R-T-0
00050 INPUT "ENTER THE MATERIAL TYPE: "IF$
00060 INPUT "ENTER THE THERMAL CONDUCTIVITY IN W/INCH*CENTIGRADE1 lK
00065 INPUT "ENTER THE SPREADING ANGLE IN DEGREES1 "1S
00069 REM TABLE TITLES
(0070 PRINT *1, TAI'(26)t"CIRCULAR S,.[Link] PLATE"
000 71 PRINT #it " "
00072 PRINT *I,. "
"W0075 PRINT 01, " "
10*080 PRINT I1, TAB(28)t"KATERIALt "tF$
00081 PRINT *It TAB(28)I"CONDUCTIVITVS "tKI"(W/IN.*C)"t
0008Z PRINT i*1l TAB(28)%OSPREADING ANGLES "ItS"((DEGREES)"
0,083 PRINT I1. " "
0008,5 PRIN1 01. "
f00090 PRINT S1: TAB(14)1" RADIUS - THERMAL RESISTANCE RADIUS(inc)
"00095 PRINT *to. TAB(14)t" ------ .... .. .
00099 REM INCREMENTING

00110 IF R<10 THEN 1-1

00120 IF (R<50) AND (R>-10) THEN 1*2
0015( REM THICKNESS
00130 To. 0 19
00 160. REM THERMAL RESISTANCE
00 ,165 Aw3. 1415927/ieOtS
:'• 00170 R2"( ll(Ke3. 1415927eTAN(A) ) )(IIR-I/(R*TITANA) ) )

"191
 CIRCULAR SURFACE - GOLD PLATE (CONTINUED)
00175 R3=R2*1000
00177 REM NEXT LEVEL DIMENSIONS(SPREADING)
00180 R4=R+T*TAN (A)
00190 REM OUTPUT
00200 GOSUB 800
00203 REM TABLE FORMAT
00205 IF R=50 THEN 225
00210 R=R+I
00220 GOTO 110
00225 CLOSE #1
00230 END
00500 REM SUBROUTINES
00550 REM OUTPUT
00800 W41: D=0
00810 V-R: GOSUB 1000: PRINT 01, TAF'(1)tQ$l
00820 W=11: D=4: V=R3" -.OSUB 10001 PRINT *1, TAB(J)IQ$4
00830 W=6: D=*: V=R4t OOSB 1000t PRINT *1, TAB(F)1Q#
00840 RETURN
(0900 REM TABLE FORMAT
01000 IF D=0 tHEN 105v
01003 O=INT(V+.5/(0^D)O)
01005 C-LEN(STR.(Q))
01010 GOSUB 4000
01011 Q$-LEFTt(STR$(Q),C-1}÷"."
Q-INT( (V-Q)*(10-D)+.5)
)1015
01020 PI-STR$(Q)
01030 MI=LEN(P$)-1
01035 0$=O$÷RIOH1$( M "000 ."+kIGHT$(P$,Mi).D.1)
01040 RETURN
01050 0QINT(Vt.5)
" 01060 O$=RII OHT4S
t'ý+STR$(O)) W)
01070 RETURN
01080 REM TAB SETTINGS FOR TABLE
04000 X-C-2
00,010 IF X-1 THEN 4050
04015 IF X=2 THEN 4055
04020 IF Xw3 THEN 4060
04025 IF Xw4 THEN 4065
04050 ,j3l4t F-53t RFTURN
04055 Ji33t Fw52 REiTULRN
04060 .- 32t F'u51t RETURN
0404 J-31t FuSOl RETURN

£92
 CIRCULAR SURFACE HEAT SINK - COPPER

00005 OPEN "LPI" FOR WRITE AS FILE 01

00010 REM ASSUMPTIONS AND VARIABLE NAMES
00011 RtM UNITS FOR RADIUS AND THICKNESS ARE IN NIL INCHES
00012 REM 100% COVERAGE
00013 REM SPREADING ANGLE VARIES PER EXTERNAL ENVIRONMENT
"00020 REM R-RADIUS TwTHICKNESS K-THERMAL CONDUCTIVITY
00021 REM A=SPftEADING ANGLE(RADIANS) S-SPREADING ANGLE(DEGREES)
"00023 REM I-'INCREMENTS R2,R3-THERMAL RESISTANCE
00024 REM R4=RADIUS FOR NEXT LEVEL
00025 RqM SUBROUTINE VARIABLES: W-WIDTH OF FIELD D=# DECIMAL DIGITS
00026 REM Q$-FORMATTED OUTPUT JF,O-TAB SETTINOS
00030 REM INPUTS
00040 D=T-0
('0050 INPUT "ENTER THE MATERIAL TYPE "SF$
00060 INPUT "ENrER THE THERMAL CONDUCTIVITY IN W/INCH*CENTIGRADE "0K
00065 INPUl "ENIER THE SPREADING ANGLE IN DEGREES "IS
00066 INPUT "ENTER THE H-AT SINK THY, KNESS IN MIL INCHES"IT
00069 REM TABLE TITLES
00070 PRINT 11, TAB(23)t"CIRCULAR SURFACE HEAT SINK-COPPER"
00075 PRINT #1,
00076 PRINT 01.
0007T PRINT 01,
00080 PRINT *1. TAB(28)t"MArERIAL: iF$
00081 PRINT *1, TAB(28t'CONDUCTIVITY: "lKt"(W/[Link])"
00082 PRINT *1. rAB428)"SPREADING ANGLEt ";St"iDEOREES)"
00083 PRINT *I. TAB(28)t"HEAT SINW THICKNEgSt "ItTI(MIL IN.)"
000•8 PRINT 01, " "
00089 PRINT #1. " "
00090 PRINT 11. TAB(14);" RADIUS THERMAL RESISTANCE RADIUS(INC)
00095 PRINT 0I. TA8(14):*' -------------
00099 REM INCREMENY ING
0100 R-,1
(10110 IF R10 THEP I=!
00120 IF (R<50) AND (R>,10) THEN 1-2
401 3•0 REM THERMAL RESISTANCE
00135 A",3. 115"t27; I$01 S
(*+170 R2=w( 1(1<o3. 14159275TtTP,(A) ) )*titR-I/{FR*,T*TAN(A)) )
*t >075 R.3-fR2.I004)
;,7717 REM NEXT LEVEL DIMENSIONS(SPREADING)
0018)0 R4-R'[Link](A)
0012. REM OUTPUT
IHWZ,r 00$LPIE'
80
tK,'C'?" TABLE FORP4UT
";•205 IF Re50 THEN Ž25

00CI,2Ž5 CLO••E ti

RE'5•,•F+M rT
tVFI NE
0.~0RFM

0o810tl Vt-lR (-i.;KIS 10#u0t: PRINT ft. TABIt 'i

p.82'oZt-It: D-4t V-RI2 ,09.19 10'00t PRINT 4I. TAbiJ)SO04
* 45w, W!--: [t- VkR4: (40SA. 1<(':,i PRINT *I. TAIif:04

"0AREMS TABL~E F09MAf

es I-WWI IF P-40 ThE•N 105e

!93
. . ..

I•-." , *-,.* .. t . .*V *+ . V" *+ *

.oVo* *.- - .* ." .++ -+• " ° `• • "- . V -
 CIRCULAR SURFACE HEAT SINK- COPPER (CONTINUED)

01011 Q$mLEFTY(STR$(Q),C-I)h"."
S01015
Q-,]NT( OV-Q)*(10"'D)÷.5)
01020 P$-STR4(0)
01030 MI-LEN(P$)-1
01035 0. 0$,',RIOHT$("00000000"+&RIGHT$(P*,M1 ),DI)
01040 RETURN
01050 OMINI(V+.5)
01060 Q$SI6HT4(S$+STR$(Q),oW)
01070 RETURN
(0100REM TAB SETTINGS FOR TABLES
04000 X=C-2
, 04010 IF X=l THEN 4050
04015 IF X-2 THEN 4055
04020 IF X=3 THEN 4060
04025 IF X=4 tHEN 4065
04050 J-34t F=53: RET uRN
04055 J=33t F=52: RETURN
04060 J=32: F=51: RETUHN
04065 J=31: F=;O: IRETURN

V: ,

'i 194
 APPENDIX 5.4

Spreading Angle Analysis

The internal heat spreading angle has a significant impact on thermal

resistance, from the chip junction to the case bottom (OjC). The
internal model employs the spreading angle in the computation of the ther-
mal resistance at each level of device construction by allowing the model
user to specify the angle desired. There are many variables, such as
attachment voids, chip size, dissipation area, material type and thickness,
all which affect the heat spreading function. This creates difficulty in
specifying one angle that typically represents the heat spread.

An analysis based on the comparison of the internal model, the exter-

nal node, and the measurement data was conducted. The purpose of the
analysis was to determine the spreading angle for a specific chip. The
device modeled for this analysis was the one involved in the circuit board
test with an ambient air of 25*C and a lower level of 1 watt. Several
iterations of the internal model were made to determine the predicted ther-
".. mal resistance, from junction to case, for a range of spreading angles
x% range of 0 to 89.9 degrees. The results are represented in Figure 78. As
expected, an inverse relationship exists between the spreading angle and
ejC. As the spreading angle increases, ejC decreases. These predicted
values were then compared to the measured ejC values recorded for the
seven devices mounted on the circuit board (ambient air = 25°C and power =
"•_• • 1 watt). This comparison is summarized in Table 52. The table shows evi-
- dence that the measured QjC values fall above the values in the pre-
dicted range. Using the side-brazed external nodal model, the predicted
- jC value for the specified measurement conditions is 0.31 degrees
centigrade per watt. This value falls within the internal model predic-
tion. However, it does not compare with the measured values.

Based on this analysis, it was concluded that the correct spreading

angle could not be determined. The spreading function is an important
* factor that needs consideration when developing models. However, further
invee-tigation was not possible, due to program limitations.

-7".5
 1'4ERMA-. RESISTANC:.
junctl-or -to- case
degrees C./ watt

L&J

-j

I~l Spreading Angle versus Thermal Resistance

•Ii 40 Pin Side Brazed Dip Package

TABLE SZ. INTERNAL MODEL PREDICTION VERSUS

pJCIRCUIT BOARD MESRMN ATA
i •Predicted Oj(; for Spreading Measured 6jr of Seven

',• AnglIe Var iat ions Dev ice s

SSpreading
Angle Predicted
AjC (degrees 0 idegrees centigrade per watt)
C Measured

4P Sez0 3.25 9.33

8 [Link] 8.82
"-"12.5 2.81 10.58
• 22 2.52 9.50
. •40 2.00 11.87
"':45 1.85 7.25
• 67 1.1I0 6.32
"(dg89e9 8 0.002
2.96 pJc 196 Average 9.10

12A2.1105
W 225295
40 .0 1.8
45 1.5 7.2
 APPENDIX 6. EXTERNAL MODEL
Appendix 6.1. Side-Brazed Package

The figures in this appendix are intended to supplement the text in section
[Link].

SIDE BRAZED PACKAGE NODAL DESCRIPTION

NODE ~JrO
( 1 NIENT AIR
CONDITIONSI 2 RADIATION SINK
•x)Ai~T) 3 CIRCUIT BOARD

4 PACKAGE EDGE AREA (NOT INCLUDING #5)

5 AREA OF PACKAGE EQUIVALENT TO NO UINDER LID AREA
6 CENTER OF PACKt'E OMNTER
7 AL CERJ"IIC L•NDER 01AR RING (EDGE)
wrpiur
8 10VAR RING (EDGE)
PRIM'•Y 9 EM OF LID
PO INT OF
[Link], eNT 10 CENTER OF LID
11 INTERNAL AIR
INPUT 12 JUNCTION TEIERAIURE
13 BOTTOM OF DIE CAVITY
14 BOTTOM OF PACKAGE CENTER
POINT OF 15 "INTERLEAD
16 ENDEAD

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PROJECT PAGE TEMP. PE U.
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 Appendix 6.2. Ceramic Cip Carrier

The figures in this appendix are referred to in section [Link]. They also
supplement the work described in that section.

.- .

N,

%Z-

- 7*. -.. S 5.V

209
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 CERAMIC CHIP CARRIER NODAL DESCRIPTION

1 Ni IENT AIR
BOUNMRY 2 RADIATION SINK
CCONIDITIONS
(INF.T) 3 SOLMER PADS
4 BASECENTER
oum5 BASE
"6 PACK4G EDXE
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POINT OF 8
EASRE8 LDCNE
LIDC R
:1
.INPUT 9 JLtCTrION

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PROJECT PAGE TEMP. PERM
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PROJECT PAGE TEMP. PERM.
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MODEL _ ORLANDO DIVISION REPORT

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,.4'.

i-1.
N

Appendix 6.3. CQrdip Package

The figures in this appendix are referred to in section [Link]. They also
supplement the work described in that section.

Mý
i

IN

217

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.
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-- ~~ L~~ --,tF. •
 CERDIP NODAL DESCRIPTION

I MIIT AIR
2RADIATIONk SIM(
CONDITIONS 3 CIRCUIT BMARD
(iNeur) 4 CAVITY BO1'M

5 BASE CENTER (ER CAVITY)

6 BASE BOTTOM (UNDE CAVITY)
7RAOF PACKAGE BASE EWUIVALENT TO CAVITY
WomU 8 PACKAGE BASE EIM~
9 PACKAGE LID ODW
POINT OF 10 WAOF PAM LIDEUIVALENT TO CAVITY
ME•URBe4T' 11 LID OER
12 GLASS SEAL EDGES (PIN LMiS AVG, IN)
13 EQUIVA[BfT TO NODE 10, BUT GASS SEAL
PORTION (PIN LEADS AVG. IN)
INKI 14 JUNTI'IN

%*

219

S'b........ . .. . .
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PROJECT PAGE TEP LE

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PROJECT PAGE TEMP. PERK
All"'
65 MARTIN MARIETTA AEROSPACE
MODEL ORLANDO DIVISION REPORT
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• PROJECT PAGEITEP
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JMODEL ORLANDO DIVISION REPORT

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 Appendix 6.4. Flatpack Package

The figures in this appendix are referred to in section [Link]. They also
supplement the work described in that section.

-.1

222

2;:

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4.4.
•.•' . . . . .. . .. . .. " . . " - ." - . ."-,"=
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 FLATPACK NODAL DESCRIPTION

HUE

( 1 ABIENT AIR
• WONTRY
(CMITIONS 2 RADIATION SINK
"(rNPUT) 3 CIRCUIT BOARW
4 PACKAGE BASE CENER
SOljrPn, 5 PACKAGE BASE EDGE
6 KOVAR RING
POINT OF 7 LID DGE
8 LIE CENTER
INPtI 9 JUNCTION

229

'K. *.
 Form D-3061 April 1978
PROJECT PAGE TEMP. PERKt
M/c~*a~du~esMARTIN MARI [Link]/
MODEL ORLANJIDO DIVISION REPORT

evil #sZ'

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 Form D3M61 April 1970
PROJECT PAGE TEMP. PERk.
Mj44,0,C4&-4W•of eje MARTIN MARIETTA-AEROSPACE 71
MODEL ,4A./, ORLANDO DIVISION REPORT

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 Form 0-3061 April 1978
PROJECT PAGE TEMP. ER
1_/eo*'c1AYz/'.s MARTIN MARIETTA AEROSPACE
MODEL ORLANDO DIVISION REPORT

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PROJECT PAGE TEMP. PERM.
A4o• l , MARTIN MARIETTA AEROSPACE
MODEL
FU rpA e" ORLANDO DIVISION REPORT

sL-j
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 Appendix 6.5. Hybrid Package

The figures in this appendix are referred to in section [Link]. They also
supplement the work described in that section.

.:
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 HYBRID NODAL DESCRIPTION

NODE

i WMIENT AIR
oiOUwN 2 RADIATION SIw
(INWtN)
CWIITIOWS
3 CIRCUIT BOARD

OtSIT 4 BASE MIDDLE

5 N-CONWICrIV E 3XY (MIMI[E)
INPJ 6 TOP OF CHIP CWRRIER B"aRD (CMf'EJO
7 BASENER
8 UDEDGE
LR 9 UD (CNIER

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A4 MARTIN MARI ETTA AEROSPACEI
MOELORLANDO DIVISION REPORT

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 Form 0-3061 AwII 1970
PROJECT PAGE rTEMP. PERK
$4 MS*@ f~l404tC5MARTIN MARI ETTA-AEROSPACE 2
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PROJECT PAGE I TEMP. I PERM.
gme~o!/.'crR•o/i $ MARTIN MARIETTA AEROSPACE I
MODEL ORLANDO DIVISION REPORT

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 Appendix 6.6. Axial Stud Package

The figures in this appendix are referred to in section [Link]. They also
supplement the work described in that section.

,. V

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24
 AXIAL STUD PACKAGE NODAL DESCRIPTION

I MIBIT AIR
BUNDRY 2 RAIATION SINK
CONDITIONS
(INPUT) 3 HEAT SINK
4 COPPER STUD
BOTTIOM CENT CERAMIC
S5 RING
MEASURE 6 BWHO EDGE CERAMIC RING
OUTPUT 7 CEPWIC RING SIDE
8 TOP EDGE OF CEROMIC RING
9 TOP CU" CERA(MIC RING
10 10/AR SUI)
11 SOLWER
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 Form 0-3061 April 1975

PROJECT PAGE TEMP. PERI.

M
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MODEL ORA'NDO DIVISION REPORT

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p

APPENDIX 7.0

?4EASUUMEHENT TESTS

7.1 Temperature Measurement Tests

"o Open Air TeLt

"o Printed Wiring Board Mounting

7.2 Hermetic Chip Carrier Thermal Test

4..44
I,'

1.

NýS

250

.~ ~ . ...... ~ .,
 APPENDIX 7.1

TEMPERATURE MEASUREMENT TESTS

Test Objectives

The basic objective of this task was to generate actual thermal gradi-
ent data for a standard package. This data can be used to verify thermal
models for the generation of derating curves.

Test objectives were to:

1 Develop capabilities to measure junction and test point temperatures

2 Control and determine package power output for the test package

3 Calculate junction to test point resistance

4 Determine the best measurement point to externally establish junc-

tion temperature derating.

Test Result Summary

It appears that the best measuring points for determining the junction
temperature are the lid and the center lead of the package. Both had a
high correlation factor with the junction to power.

Test Hardware and Procedure

A standard 40-lead side-brazed package was chosen as the test package

because of its popularity in the industry. The package had an NPN 2NC5337
transistor mounted in the die cavity for power dissipation. A transistor
was used instead of a resistor because the junction temperature of the
transistor is directly proportional to the reverse bias resistance of the
base-emitter junctions. Attached to the package on the lid, center lead,
and end lead of the package were three mil chromel - constantan thermo-
couples, used to measure the gradient across the package when power is
applied to the transistor. The small thermocouples were chosen because of
the small amouut of heat they would draw off. The packages were configured
in two fashions: one was unmounted (open air), while the other was mounted
to a printed wiring board (PWB). For more information, see the section on
test configuration conditions and power levels.

Power Dissipation Measurement

*Q To generate heat, the transistors were dc biased, using a load and

base resistor, as shown in Figure 79. The power dissipated was calculated
in watts by measuring the voltage drop across the collector-emitter of the
*: package, multiplied by the voltage drop across the load resistor, and
divided by the load resistor's resistance. The base resistor was adjusted
so that all the packages were dissipating about the same power. The main
supply cullection voltage was then adjusted to vary the power of all the
test packages.
251
 Collector Voltage

Bias VE

<El
oa d
load

- ----

2.1
* 2"
, ~1.-
* 1.6-
.6
1.7"

• ~1."
1.5-

.':-,-1.3-
': "-';1.2.

1.1

00.
.$- [ u•zhz P - FmuUDZSSIPAXo1

0.,- / - 13m VOl.T , -. ,WI •.

0.4. 2. 2 3 to.1
I I fl i3CI

..
-~'.4" T

VOLTS

-. :~Figure 79. Power Dissipation Circuit

Junction Temperature Measurements

The relationship of the voltage drop across the emitter-base junc-

*0 tions, when biased by a ronstant power supply and temperature, is shown in
Figure 80. The relationship mentioned is linear over the test temperature
(25 to 130 degrees C.). Therefore, the package's voltage drop was expressed
, by the linear equation y - Mx + B, where y equals junction temperature, x
equals voltage drop, and M and B are constants. The constants were found
by measuring the voltage drop at knowu temperatures and fitting the data in
the equation by the least squares method described in the section on cali-
bration.

252

-t.

U% , .. • ' ., --..-
[•,w ,.• .,-,-
',...' , ..
.'o'..' .',;.. ,, •... .- ,,-', ; '. •." . . ., ,.'..-.,.'. . .- -, w• '..,. .•- Z•- •,A.o,
i
~,

880 Temp Evaluation

Data Ldg1ur Interfaoe
Millivolts
588
485
478
~ Tram%

13
A• 448
425
418
395 TrOM7
14

358
335
3211
•: ~305 "
-%.

+" "i•-•!275 *pII*,Ippj ppIuIppIpI I ppIIIIIIImIIIpIIIIIIpIIImahII pmspIppnpIIIImIIIIII~III l

25 38 35 40 45 58 55 60 65 78 75 8 85 90 95 106
TONP. DWCanurd&
.-.. V
i:.•:iFigur e 80. Traimsistor CZliba•ion Curve (Typical)

The package's junction temperature was determined by switching the

power dissipation circuit off and by switching the reverse bias circuit
into place. The final circuit that was used is shown in Figure 81. The
relay was activated, isolating the emitter and base junctions. Then the
voltage drop across the reversed biased emitter-base junctions was
measured. The total off-time of the powering circuit was about 30 milli-
seconds. This short off-time did not alloy the junction to cool off sig-
* nificantly. The Fluke datalogger then converted this voltage to the junc-
tion temperature.

Thermal Resistance Calculation

To determine the thermal resistance from the device junction to the

test points, it was necessary to measure the power dissipation, junction
temperature, and test points with the Fluke 2240C datalogger. The junction

253

S.. . . .=:.:,.:%
 temperature was determined by the technique mentioned earlier and was
recorded by the datalogger. The power was determined by measuring the
various voltages and using the equation previously mentioned in the power
dissipation section, The Hewlett-Packard 9836 computer was used to calcu-
late and record the wattage. The test point temperatures were measured by
the thermocouples and the datalogger, and recorded by the computer. The
accuracy of the datalogger is as follows.

Worst case resolution 0.1 degree

NBS conformity 0.11 degree
System accuracy 0.7 degree

The temperature delta was then calculated by taking the difference of the
two test points, (the lid and the package junction), and dividing it by the
power dissipated. This gives an answer in degrees centigrade per watt (*C/W).

BASE
CURRENT CURRENT
METER METER

I..-..'VARIABLE
RESISTOR Q-BIAS

RELAY CONTROL POWER

t'C BOARD CONTROL BOARD SUPPLY

IZ RESISTOR

K(-I/18

REL.AY_________

COIL - -

V1

CONSTANT VOLTAGE BUFFR DATA

CURRENT METERlG
SOURCE
VOLTAGE DROP ACROSS
COLLECTOR BASE JUNCTION

Figure 81. System Block Diagram

254

0
.- *-.w- . . 4

.' *...* ~ *% %

'-"''. •"•
' •, ••
'4" "•
'••-" •.° ; • •, ."-" • ", "• "- ;"•'•, .- " "-"•".*. "•%,'•,, - " . ," ••."•" $"*"" "',"
 Cal ibrat ion

The junctions were all calibrated by measuring the voltage drop of the
reverse biased E - B junction with respect to temperature. This was done
at 15 steps over the temperature range of -10 to 130 degrees Centigrade.
This data was fitted to a curve, as shown in Figure 82, to produce a linear
equation for each transistor. Figure 83 also shows the amount of error
typically encountered by this method over the temperature range. This was
done prior to each test to increase the accuracy.

1.30E+2 -
1.20E+2 -4.,'
.leOE+2 "
[Link]+2 "-.
, Z E+ 1'"•"
9~~~.
• B~~.008E+1I""'

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• [Link]+ I.

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[Link]+l -"
•02 E+-
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-I .BOE+l r +.

* '4 W W W W w W W W w
to 0) m w g q w c tM

u CU CU M~ en W V V In In to
- RegresIon Fit #40 in V - -- X99 Confidence
S"npeo-3.96÷L+02

-• Figure 82. Transistor Calibration Test 2/1/84

Test Configuration, Conditions, and Power Settig

Two different test configurations were chosen. The first was an open
-" air test where the package was not mounted. The second was a VIB test,
which consisted of mounting the packages to a polyimide PWB.

-Open Air Test

The packages in this test were not mounted. The test points measured
were the lid., center lead, end lead, junction, &ad the case under the pack-
age. This test was chosen to give data to the thermal model on the, effects
of radiation and air convection. The test uo. performed £tiside a tempera-
ture oven to prevent any air currents from coming in contact with the pack-
ages. The ambient chamber air vas 25 degrees centigrade. The wattage was

255

'S,+)% •'+.' .•+..%

.• +.- +""." +... " " " .'. . ." ". +++* " ' • •
+•' *.,•++'. . .. '• V . .• .• '.+ '. • '+, ,' "+,' " ,%' " ' " " ." "." ". %% " ILI.+
. ; .•+.•'-",%
,•VLYNOMIAL REGRESSION ON DATA SET:

Tr'ansistor CalzibatQ-r. Test 3/4/04

-- where: Dependent variable = (5)Lid #41

Independent variable = (39)#41 jr, V

STANDARD COEFF. OF
VARIABLE N MEAN VARIANCE DEVIATION VARIATION
#41 in V 15 .40314 .0 13 4 .C1't5C3 28.73265
15 58.99333 2j35.V89924 46.21579 78.34070
Lid #41

CORRELATION = -. 99986

SELECTED DEGREE OF REGRESSION = 1

R-SQUARED = .99972
STANDARD ERROR OF ESTIMATE = .800607086159

ANALYSIS OF VARIANCE TABLE

DF SUM OF SQUARES MEAN SOUARE F-VALUE

SOURCE

TOTAL 14 29902.5W933
1 29894.25670 _9894.25670 46638.96
REGRESSION 46638.96
X^I 1 29894.Ž5670 29894.25670
13 . 332• .4097
RESIDUAL

REGRESSION COEFFICIENTS STANDARD ERROR

STD. FORMAT E-FORA7 PCO. COEFFICIENT T-VALUE
VARIABLE

219.81857 .Z19818574050E+01 .77286 284.42

"CONSTANT'
-. 39:1)3 9598E+02 1.434724 '15.96
X.,I -398.qD149

90 % CONFIDENCE INTERVPL
COEFXCIENT LOWER LIMIT UPPER LIMIT

'CONSTANT' 8.
219.Rt657 2 44957 281..1875
-398.93149 -409.20362 -39. 65936
X" 1

TABLE OF RESIDUALS

STANDARDIZED
OBS# OFSEP'I)E Y PREDIDTED Y RESIDUAL RESIDUAL SGNIF.
1 -:2.50000 -11.32233 -1.17767 -1.47097
a -1.00000 -. 31182 -. 681s8 -. 85957
3 5.50000 6.03119 -. 53119 -. 66340
4 15.80000 1S.84490 -. 04490 -. 0609
5 27.10000 26.61605 .48395 .60447
6 34.60000 33.95639 .64361 .80390
7 45.70000 44.92701 .77299 .9"551
8 65.20000 64.35497 .84503 1.05548
9 7..30000 72.01446 .78954 .98118
10 81.3@001 80.55159 .74841 .93480
11 9;.000 91.64180 .35511 .44730
12 -c.3C'? 100. 13913 .16087 .20094
A3 01-,.1:000 109.75338 -. 15338 -. t9157
14 ti.r!.o0 118.72933 -. 62933 -. 78607
15 30. 40000 131.973e6 -1.57386 -1.96583

Durbi n-Wetson Stati st c: .268989720107

Figure 83. Transistor Calibration Test

256
 adjusted so that the junction temperature did not exceed the maximum oper-
ating temperature of around 135 degrees centigrade. The desired power was
around 2 watts.

Printed Wiring Board Test

In this test, all seven packages were mounted to a single piece of

0.047-inch standard double-sided polyimide fiberglass, with 1 ounce copper
on the underside (Figure 84). The 1 ounce copper underside simulates the
thermal spreading effect of circuitry.'normally found in actual hardware.
The leads that are connected to the transistors were isolated from the cop-
per ground plane. The PWB was not mounted to a heat sink. The test was
performed in a thermal oven that was turned off. This test was performed
at three different power levels: 1, 2, and 4 watts at 25 degrees centi-
grade ambient conditions, and at 55 and 85 degrees centigrade ambient con-
ditions. A 2 watt power level was employed.

1 40 lead side Brazed

package

r 'N, PWB
.047 Polyimide
102 Ccpper Side
Figure 84. PWB Configuration

,jM,
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 APPENDIX 7.2

Hermetic Chip Carrier Thermal Test

Test Module Description:

Four multilayer polyimide fiberglass printed wiring board assemblies

were fabricated and assembled. Each circuit board contained four
metallization layers as illustrated in Figure 2.0. The following HCC
components were installed on each circuit board assembly; 5-64 terminal,
2-48 terminal, 2-40 terminal, 3-32 terminal and 10-24 terminal size
devices. All carriers, with the exception of nine 24 terminal carriers
contained power transistors. To accommodate the various size HCC chip
cavities two different dies were used, a 2NC5337 transistor and a 2N6274
transistor were eutectically mounted to the HCC cavities. Figure 4
illustrates the component and thermocouple locations for each printed
wiring board.

The printed wiring board assemblies were bonded to two different

support plate materials. One each A and B circuit board assemblies were
bonded to an .090 thick aluminum support plate using RTV-88 silicon
adhesive (.010 max thickness). The remaining A&B boards were hard bonded
"to a .030 thick Cu clad Invar support plate using ablefilm 506 (.006
thickness). The Cu clad thickness on each side of the invar was .0048 inch
or 16% of the total thickness.

4.2 Thermal Resistance & Temperature Measurement Procedures:

NPN power chip transistors were installed in each carrier to simulate

actual device die and provide a mens for directly measuring the junction
temperature. In addition to the transistors, small diameter (3-mil)
Chromel - Constantan thermocouples were added to measure the base
temperature, solder joint temperature and lid temperature for various HCC's
as shown in Figure 4.

4.2.1 Power Dissipation Measurements

The power dissipated was determined by measuring the voltage drop

across the emitter-collector (VEC) of the transistor and multiplying
* the voltage by the current (IC).

P = VEC x Ip.

where:

P = power dissipation of device, in watts

VEC= voltae drop across emitter - collector, in volts
Ic = collector current, current in amps

The power dissipated by the transistor (0 to 2 watts max.) was adjusted by

a change in the base voltage and current resulting from varying the
resistance.

..- `.291

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 Junction Temperature Measurements

All power transistors were calibrated to determine the individual

forward bias of the base-emitter voltage versus temperature
characteristics. The relationship of the voltage drop across the
emitter-base and temperature is linear over the test temperature range.
"Therefore, the transistor's forward voltage drop can be expressed by the
"equation y = Mx + b, where y equals temperature, x = voltage drop, and M
and b are constants. The constants can be found by measuring the voltage
drop at known temperatures and fitting the data in the equation by using
the least squares method. Using this equation the temperature of the
transistor junction can be determined by measuring the forward voltage drop
across the emitter base.

Thermal Resistance Calculation

To determine the thermal resistance from the device junction to case,

it was necessary to measure the power dissipation, junction temperature,
and case temperature. The junction temperature and case temperature were
measured using a Fluke 2240C data logger. The voltage drop across the
emitter and base of the transistor is then measured. Using the transistor
calibration curve relationship, the data logger converts the measured
voltage to temperature. Knowing the device junction temperature, case
temperature and power dissipation, the thermal resistance (Oj-c) was
calr'ulated using the following relationship:

-jc T"j - Tc
"Gjc Pwr

where:

•j-c = junction to case thermal resistance (°C/w)

Tj = junction temperature ('C)
Tc - HCC case temperature at the solder joint (*C)
Pwr - device power dissipation (w)
Calibration and Pre-Test Configuration

Both module assemblies were installed in P pair of ATLIS cold wall

plates with sufficient air baffles to minimize temperature chamber air cur-
rent effects on the component temperature measuremencs. The temperature
chamber was initially set at 90C where the transistors were adjusted such
that they were dissipating zero power. The voltage drop acroas the emitter
base was then measured. Several temperature step increases were made in
increments of IOC until 130C was reached. For each temperature the
* boards were allowed to stabilize before the voltage drop across the emitter
base was recorded. These measurements with the temperature reading were
then curve fitted to each transistor using the least squares method. The
calibration test was performed on the test modules in these test configura-
tions to minimize errors generated by test set up variations.

" .292

.. Z
 k• '" "-, •L . ' •'•N" • '• ,•, , - •, " - . - - *

Test Configuration Cqnditions & Power Setting Test Levels

To obtain the test data under typical operating conditions the modules
were installed in a chamber set to 80"C. Each transistor was initially aet
to dissiphte 1/4 watt. After chamber stabilization the function and
thermocouple measuremeaits were recorded. Power levels were re-adjusted to
1/2, 3/4 and 1 watt. After stabilization, junction and thermocouple
readings, were again recorded for all power level settings.

Junction to Case' Thermal Resistance

The junction to case thermal resistance values obtained from the test
.3,, results are summarized in Table I for various size HCCs. Case temperature
measurements for 9j-c were taken from the HCC solder joint locations.
Test results indicate that the junction to case thermal resistance remains
fairly constant for the various power levels tested. ej-c values for
the copper clad invac module compared well with the 4lumintw supported
module.

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