FIELD EFFECT TRANSISTOR (FET)

They are three terminal unipolar solid state devices in which current is controlled by
an electric field just as it was the case with vacuum tubes. Below is the classification
of FETs.

FET

JFET MOSFET
(IGFET)

P-channel N-channel

Depletion type Enhancement type

N-channel P-channel N-channel P-channel

Junction field effect transistor (JFET)

JFETs can be divided into two categories, depending upon their structure:
 N-Channel JFET
 P-Channel JFET
D (drain)
D (drain)
N-type P-type
channel channel
P-type P-type N-type
N-type

G (gate) G (gate)

S (source) S (source)

The basic construction of both P-channel and N-channel are shown.

N-channel JFET
It consists of N-type semiconductor bar with two P-type heavily doped regions
diffused on opposite sides of its middle part. The P-type regions form two PN
junctions. The space between the junctions, the N-type region, is called a channel.
Both the P-type regions are connected internally and a single wire is taken out as a
terminal called gate (G). Also electrical connections are made at both ends of the N-
type semiconductor and the terminals are known as source (S) and drain (D). Source
is the terminal through which electrons enter the semiconductor bar and drain is the
terminal through which the electrons leave the semiconductor bar.
When voltage is applied across the source and the drain, a current flows through the
channel and it consists of one type of carrier only i.e. electrons. Hence the JFET is a
unipolar device unlike bipolar junction transistor (BJT) which is a bipolar device
where current consists the flow of electrons and holes.
P-channel JFET
It is similar in construction to N-channel JFET, except that it consists of a P-channel
and N-type junctions. The charge carriers for P-channel are holes.
Symbols

D D

G G

S S

N-channel P-channel

Formation of depletion region in JFET

D
D
N-type Depletion
channel regions
P-type P-type
G
G

-
𝑉𝐺𝐺
+

S S
Let’s consider the N-channel JFET in the diagram. The p-type gate and the n-type
channel form the PN-junctions. In JFET operation, the PN-junctions are always
reverse biased as shown in the diagram.
When a PN junction is reverse biased, a depletion layer is created on both sides of
the junction. If the two regions are equally doped, it extends equally in both sides.
However if one region is heavily doped, it extends more in the lightly doped region.
For the N-channel JFET shown, because the p-type region is heavily doped, the
depletion layer extends more in the N-channel as shown. When there is no applied
voltage between the drain and the source, the depletion layer is symmetrical around
the junction. As the depletion layer has no carriers, the effective width of the channel
is reduced. If the reverse voltage is increased further, the effective width of the
channel is further reduced.
Reverse bias across the gate and the source junction may also be obtained by
applying a voltage across drain and source terminals as shown in the diagram.
D
𝐼𝐷 D
Depletion 𝐼𝐷
𝑟𝑎 regions

+ G +
G 𝑉𝐷𝐷 𝑉𝐷𝐷
- -

𝑟𝑏

S
S

The channel resistance between the drain and the source is represented by two
resistances 𝑟𝑎 𝑎𝑛𝑑 𝑟𝑏 which are variable as their magnitude depends on drain to
source voltage (𝑉𝐷𝑆 ) and gate to source voltage (𝑉𝐺𝑆 ).
When the voltage 𝑉𝐷𝐷 is connected, with the gate open, electrons flow from source
to drain. This constitutes the drain current (𝐼𝐷 ). The drain current causes voltage drop
across resistance 𝑟𝑏 , whose effect is to reverse bias the gate to source junction. Thus
even if the gate is grounded, the gate to source junction is reverse biased by the drain
to source voltage. This creates depletion region within the channel as shown.
The depletion layer is not symmetrical around the gate to source junction. It extends
deeper near the drain and less near the source terminal. This is because the voltage
drop is higher across 𝑟𝑎 as compared to 𝑟𝑏 .
Operation of JFET
When drain to source voltage (𝑉𝐷𝑆 ) is applied across the drain and the source from
battery 𝑉𝐷𝐷 , electrons flow from the source to the drain through the narrow channel
existing between the depletion regions. This constitutes the drain current 𝐼𝐷 . The
value of the drain current is maximum when no voltage is applied between the gate
and the source. This maximum current is designated as 𝐼𝐷𝑆𝑆 .
When the gate to source voltage (𝑉𝐺𝑆 ), is applied by battery 𝑉𝐺𝐺 , and increased above
zero, the reverse bias voltage across the gate source junction is increased. As a result,
the depletion regions are widened. This reduces the effective width of the channel
and therefore controls the flow of the drain current through the channel. If the gate
to source voltage is increased further, a stage is reached at which the two depletion
regions touch each other. At this gate to source voltage, the channel is completely
blocked or pinched off and drain current is reduced to zero.
The gate to source voltage at which the drain current is zero is called pinch off
voltage. It is designated by 𝑉𝑃 or 𝑉𝐺𝑆(𝑜𝑓𝑓) . The value of pinch off voltage is negative
for N channel JFET and it depends on the doping of P and N regions and the width
of the original channel structure.
D
D
𝐼𝐷

G + G +
𝑉𝐷𝐷 𝑉𝐷𝐷
- -
- -
𝑉𝐺𝐺 𝐼𝐷 𝑉𝐺𝐺
+ +
S
S

Characteristics of JFET
There are two characteristics associated with JFET:
 V-I or drain characteristics
 Transfer characteristics
The following circuit can be used to take measurements for plotting the
characteristics:
 D
A

G
VDS V
+
R2 VDD
S
R1 V VGS
VGG
+

Drain characteristics
These are curves which give relationship between drain current (𝐼𝐷 ) and drain to
source voltage (𝑉𝐷𝑆 ) for different values of gate to source voltage (𝑉𝐺𝑆 ).
For a given value of 𝑉𝐺𝑆 , the voltage 𝑉𝐷𝑆 is increased in small suitable steps and the
values of current 𝐼𝐷 tabulated. The values tabulated are used to plot the
characteristics shown.

𝐼𝐷 (mA)

𝐼𝐷𝑆𝑆 VGS= 0 V

-1V

-2V

-3V

-4V

𝑉𝐷𝑆 (𝑉)
1 2 3 4

The characteristics have different regions namely:

 Ohmic region
 Pinch off region
 Breakdown region
 𝐼𝐷 (mA)

D
Ohmic
Pinch off or saturation region
region Breakdown
region
B
A VGS= 0 V C

𝑉𝐷𝑆 (𝑉)
0

Ohmic region
In this region the drain current increases linearly with increase in drain to source
voltage following Ohm’s law. This is because the N-type semiconductor bar acts
like a simple resistor.
Curve AB
In this region the drain current increase at the reverse square law rate with the
increase of the drain to source voltage. In this region, increase in drain to source
voltage increases drain current which in turn increases the reverse bias voltage across
the gate source junction. Hence the depletion region grows in size reducing the
effective width of the channel. At point B, the channel width is reduced the minimum
value known as pinch off and the corresponding drain to source voltage is known as
pinch off voltage (𝑉𝑃 ).
Pinch off region
It is also known as saturation or constant current region. The drain current remains
constant at maximum value (𝐼𝐷𝑆𝑆 ). Drain current at pinch off region depends on drain
to source voltage and is given by:
𝑉𝐺𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )
𝑉𝑃
This relationship is known as Schockly’s equation. When JFET is used as an
amplifier, it operates in the pinch off region.
Breakdown region
This is represented by curve CD, where the current increases rapidly as the drain to
source voltage is increased. This is a result of breakdown of gate to source junction
due to the avalanche effect. Drain to source voltage at point C is called breakdown
voltage.
Transfer characteristics
They are also called transconductance curves. They give relationship between drain
current (𝐼𝐷 ) and gate to source voltage (𝑉𝐺𝑆 ) at a constant drain to source voltage
(𝑉𝐷𝑆 ).
𝐼𝐷 (mA)

𝐼𝐷𝑆𝑆

𝑉𝐺𝑆 (𝑉) +
0
- 𝑉𝑃

The upper end of the curve is shown by the value of drain current (𝐼𝐷𝑆𝑆 ), while the
lower end is indicated by voltage equal to 𝑉𝑝 . The curve is a parabola and may be
expressed by the equation:
𝑉𝐺𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )
𝑉𝑃
JFET parameters
These are parameters that can be used to describe the behavior of a JFET. Among
the important parameters are the following:
DC drain resistance
It is the ratio of 𝑉𝐷𝑆 𝑡𝑜 𝐼𝐷 and is also called the ohmic or static resistance of the
channel.
 𝑉𝐷𝑆
𝑅𝐷𝑆 =
𝐼𝐷
AC drain resistance
It is the ac resistance between the drain and the source terminals when the JFET is
operating in the pinch off region. It is also called dynamic drain resistance. It is given
by the ratio of small change in drain to source voltage to the corresponding change
in drain current, for a constant gate to source voltage.
∆𝑉𝐷𝑆
𝑟𝑑 =
∆𝐼𝐷
Transconductance
It is given by the ratio of small change in drain current to the corresponding change
in gate to source voltage, for a constant drain to source voltage. It is also called
forward transconductance or forward transmittance.
∆𝐼𝐷
𝑔𝑚 =
∆𝑉𝐺𝑆
Amplification factor
It is given by the ratio of small change in drain to source voltage to the corresponding
change in gate to source voltage, for a constant drain current.
∆𝑉𝐷𝑆
𝜇=
∆𝑉𝐺𝑆
The amplification factor may be expressed in terms of transconductance and ac drain
resistance:
∆𝑉𝐷𝑆 ∆𝑉𝐷𝑆 ∆𝐼𝐷
𝜇= = × = 𝑟𝑑 × 𝑔𝑚
∆𝑉𝐺𝑆 ∆𝐼𝐷 ∆𝑉𝐺𝑆
Input resistance
The gate source junction is used as the input. This junction is always reverse biased
and therefore the current flowing is the reverse biased current which is very small.
Hence the input resistance is very high which is an advantage compared to a BJT
whose input junction is forward biased.
 𝑉𝐺𝑆
𝑅𝑖 =
𝐼𝐺𝑆𝑆
𝑉𝐺𝑆 is the gate to source voltage
𝐼𝐺𝑆𝑆 is the gate reverse current which is in order of nano-amperes.
Mathematical expression for transconductance
We have:
𝑉𝐺𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )
𝑉𝑃
Differentiating both sides w.r.t. 𝑉𝐺𝑆 we get:
𝑑𝐼𝐷 𝑉𝐺𝑆 1
= 2𝐼𝐷𝑆𝑆 (1 − ) × (0 − )
𝑑𝑉𝐺𝑆 𝑉𝑃 𝑉𝑃
2𝐼𝐷𝑆𝑆 𝑉𝐺𝑆
𝑔𝑚 = − (1 − )
𝑉𝑃 𝑉𝑃
Substituting 𝑉𝐺𝑆 = 0 we get:
2𝐼𝐷𝑆𝑆
𝑔𝑚 = − = 𝑔𝑚𝑜
𝑉𝑃
This is the maximum value of transconductance. Hence we have:
𝑉𝐺𝑆
𝑔𝑚 = 𝑔𝑚𝑜 (1 − )
𝑉𝑃
Comparisons between FET and BJT
FET BJT
1 It is a unipolar device. Current is due to either It is a bipolar device. Current is due to both electrons
electrons or holes and holes
2 It is a voltage controlled device. It is a current controlled device.
3 It has very high input resistance. Has low input resistance compared to FET
4 Has negative temperature coefficient at high current Has positive temperature coefficient at high
levels and this prevents thermal breakdown. temperatures and it can lead to thermal breakdown.
5 It does not suffer from minority carrier storage Suffers from minority carrier storage effects and
effects and hence have high switching speeds and therefore has lower switching speeds and cut off
cut-off frequencies. frequencies as compared to FETs.
6 Less noisy than BJT Comparatively noisier compared to FET
7 It is much simpler to fabricate and occupies less Comparatively difficult to fabricate on IC and
space in IC as compared to BJT. occupies more space compared to FET
MOSFETs
It stands for Metal-Oxide-Semiconductor-Field-Effect-Transistor. It also has gate,
source and drain. Unlike in JFET, the gate is insulated from the channel and hence
it is also called Insulated-Gate-Field-Effect-Transistor (IGFET). There are two types
of MOSFETs namely:
 Depletion type (or DE) MOSFET
 Enhancement type MOSFET
Depletion type MOSFET
D Drain

G S
N P Substrate
Gate

𝑆𝑖𝑂2 𝑙𝑎𝑦𝑒𝑟

S Source

The diagram is of an N-channel MOSFET. It has a conducting bar of N-type, an

insulated gate on the left and P-region on the right. Free electrons can flow from
source to drain through the channel. P-region reduces the conducting path to a
narrow channel and is called substrate (or body). Thin layer of silicon dioxide is
deposited on the left of the channel and insulates the gate from the channel. Due to
this insulation, negligible gate current flows even when the gate voltage is positive.
In MOSFET, PN-junction which exists in JFET has been eliminated.
Working of a depletion MOSFET
Depletion MOSFET can be operated in the following two modes:
 Depletion mode when the gate voltage is negative.
 Enhancement mode when the gate voltage is positive.
In depletion mode, the negative voltage applied to the gate induces positive charges
in the channel. This way free electrons are repelled away from the channel and hence
depleted of the electrons. The drain current is thus reduced. As the negative voltage
increases, the drain current is further reduced and at sufficient negative voltage
called 𝑉𝐺𝑆(𝑜𝑓𝑓) the channel is totally depleted off the charge carriers and the drain
current reduces to zero. Because negative gate voltage depletes the channel of free
electrons, negative gate operation is known as depletion mode.
In enhancement mode, the positive voltage applied to the gate increases the number
of electrons in the channel. The greater the positive gate voltage, the greater is the
number of free electrons in the channel and this enhances the conductivity of the
channel. From this action, positive gate operation is called enhancement mode.
Because depletion type MOSFET conducts even when gate to source voltage is zero,
it is also known as normally ON MOSFET.
D D

N N
ѳ +
⊕ + G
G
⊕ 𝑉𝐷𝐷 ѳ 𝑉𝐷𝐷
P ѳ P
⊕ -
- - + ѳ
⊕
𝑉𝐺𝐺 𝑉𝐺𝐺
+ -
S S

Enhancement mode
Depletion mode

Drain characteristics of depletion type MOSFET

The curves are plotted for both positive and negative gate voltage hence showing the
enhancement and depletion mode of operation. They resemble those of a JFET
except that a JFET does not operate with positive gate voltage.

𝐼𝐷 (𝑚𝐴)
𝑉𝐺𝑆 = +2V
Enhancement
mode
𝑉𝐺𝑆 = +1V

𝑉𝐺𝑆 = 0

𝑉𝐺𝑆 = −1V
Depletion
𝑉𝐺𝑆 = −2V mode
𝑉𝐺𝑆(𝑜𝑓𝑓)

𝑉𝐷𝑆 (𝑉)
Transfer characteristic of depletion type MOSFET
The curves are shown for positive and negative gate voltages. It resembles that of a
JFET but extends for positive values of gate to source voltage. The drain current
when the gate to source voltage is zero is given by 𝐼𝐷𝑆𝑆 . Drain current at all points
is given by:
2
𝑉𝐺𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )
𝑉𝐺𝑆(𝑜𝑓𝑓)

𝐼𝐷 (mA)

Depletion Enhancement
mode mode

𝐼𝐷𝑆𝑆

𝑉𝐺𝑆 (𝑉) +
- 0
𝑉𝑃

Circuit symbol for depletion type MOSFET

D
D

G G

S S
N-channel P-channel
Enhancement type MOSFET
Enhancement type operates in enhancement mode only. It has no physical channel
as shown in the diagram. The P-type substrate extends to the silicon dioxide layer.
The N-channel enhancement type MOSFET is always operated with positive gate to
source voltage. When 𝑉𝐺𝑆 = 0, no current flows when voltage is connected across
the drain and source due to the presence of the P-type region. Enhancement type
MOSFET is therefore known as normally OFF MOSFET.
D D

N N

G G + -
P P 𝑉𝐷𝐷
+ -

N 𝑉𝐺𝐺 N

S
S

When positive voltage is applied at the gate, negative charge is induced in the P-type
substrate adjacent to the silicon dioxide layer. The negative charge are obtained by
attracting electrons from the source. If the gate is made positive enough, it attracts
many electrons and forms a thin layer of electrons stretching from source to drain.
This layer is called N-type inversion layer.
Minimum gate to source voltage at which inversion layer is produced is known as
threshold voltage (𝑉𝐺𝑆(𝑡ℎ) ). When gate to source voltage is greater than this threshold
value significant value of current flows.
Drain characteristic for enhancement type MOSFET
The drain characteristics for N-channel enhancement type MOSFET are shown in
the diagram. When the gate to source voltage is less than the threshold value, there
is no drain current. In practice a very low and negligible current flows due to the
thermally generated electrons in the P-type substrate. Drain current increases with
increase in gate to source voltage due to resultant widening of the inversion layer
which allows more electrons to pass through. At a certain value of drain to source
voltage, the drain current reaches its saturation.
 𝑉𝐺𝑆 = 6 𝑉
𝐼𝐷 (µ𝐴)

𝑉𝐺𝑆 = 5 𝑉

𝑉𝐺𝑆 = 4 𝑉

𝑉𝐺𝑆 = 𝑉𝐺𝑆(𝑡ℎ) = 3 𝑉
Cut-off region

0 𝑉𝐷𝑆 (𝑉)

Transfer characteristic for Enhancement-type MOSFET

There is no drain current when 𝑉𝐺𝑆 = 0. When the voltage is increased
beyond 𝑉𝐺𝑆(𝑡ℎ) , the drain current increases rapidly. The drain current at any point is
given by:
𝐼𝐷 = 𝐾[𝑉𝐺𝑆 − 𝑉𝐺𝑆(𝑡ℎ) ]2
K is a constant whose value depend on the type of MOSFET. It can be determined
by taking a specified value of drain current known as 𝐼𝐷(𝑂𝑁) from the data sheet at
the given value of 𝑉𝐺𝑆 and substituting these values in the equation.
𝐼𝐷 (µA)

𝑉𝐺𝑆(𝑡ℎ)
𝑉𝐺𝑆 (𝑉)
0
-
Circuit symbol for enhancement type MOSFET

D
D

G
G

S
N-channel S
P-channel

Advantages of N-channel MOSFETs over P-channel MOSFETs

For fabrication of MOS circuits and systems, N-channel MOSFETs are more
common than P-channel MOSFETs. P-channel MOSFETs find their use only in
complementary metal-oxide-semiconductor (CMOS) integrated circuits. The main
advantage of N-channel over P-channel is the fact that charge carriers in N-channel
are electrons while for P-channel they are holes. Electrons have high mobility
compared to holes approximately three times. Current in semiconductors is directly
proportional to carrier mobility and therefore for the same dimensions, current in N-
channel is almost three times that of P-channel.
Hence the ON resistance of N-channel is almost one-third that of P-channel. To
achieve the same value of current and ON resistance, P-channel MOSFET requires
three times the area of an equivalent N-channel MOSFET. Therefore electronic
circuits using N-channel are much smaller in size than those of P-channel and this
results in higher packing density.
Handling precautions of MOSFET
MOSFETs get easily damaged when they are mishandled due to static electricity
which raptures the silicon dioxide layer between the gate and the channel. This static
electricity may result from sliding against a plastic bag or when a person is handling
MOSFET touches the gate lead against some ground object.
To protect MOSFET from damage, it is kept with it terminals shorted by a ring or
they can be kept in a conducting foam. They should never be inserted or removed
from a circuit when the power is ON.
Nowadays, some of the MOSFETs have a built in protection against static electricity
and high voltages by using a pair of zener diodes connected back to back between
gate and source as shown in the diagram. The zener diodes are designed such that if
the voltage exceeds for instance +10 V (or -10 V) one of them conduct and the other
breakdown, providing a path for excessive charge from gate to source. However the
minor disadvantage of this mode of protection is that it reduces the input resistance
of the MOSFET.