ESP32-WROVER-E &

ESP32-WROVER-IE
Datasheet Version 2.0

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About This Document
This document provides the specifications for the ESP32-WROVER-E and ESP32-WROVER-IE modules.

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1 Module Overview

1 Module Overview
Note:

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1.1 Features

CPU and On-Chip Memory • SD card, UART, SPI, SDIO, I2C, LED PWM, Motor
PWM, I2S, IR, pulse counter, GPIO, capacitive
• ESP32-D0WD-V3 or ESP32-D0WDR2-V3 touch sensor, ADC, DAC, TWAI® (compatible
embedded, Xtensa dual-core 32-bit LX6 with ISO 11898-1, i.e. CAN Specification 2.0)
microprocessor, up to 240 MHz

• 448 KB ROM Integrated Components on Module

• 520 KB SRAM • 40 MHz crystal oscillator

• 16 KB SRAM in RTC • 4/8/16 MB SPI flash

Wi-Fi • ESP32-D0WDR2-V3 also provides 2 MB PSRAM

• 802.11b/g/n Antenna Options

• Bit rate: 802.11n up to 150 Mbps • ESP32-WROVER-E: On-board PCB antenna

• A-MPDU and A-MSDU aggregation • ESP32-WROVER-IE: external antenna via a
• 0.4 µs guard interval support connector

• Center frequency range of operating channel:

Operating Conditions
2412 ~ 2484 MHz
• Operating voltage/Power supply: 3.0 ~ 3.6 V
Bluetooth®
• Operating ambient temperature: –40 ~ 85 °C
• Bluetooth V4.2 BR/EDR and Bluetooth LE
specification Certification

• Class-1, class-2 and class-3 transmitter • Bluetooth certification: BQB

• AFH • RF certification: See certificates for
• CVSD and SBC ESP32-WROVER-E and ESP32-WROVER-IE

• Green certification: REACH/RoHS

Peripherals

• Up to 24 GPIOs Test

– 5 strapping GPIOs • HTOL/HTSL/uHAST/TCT/ESD

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1 Module Overview

1.2 Series Comparison

ESP32-WROVER-E and ESP32-WROVER-IE are two powerful, generic Wi-Fi + Bluetooth + Bluetooth LE MCU
modules that target a wide variety of applications, ranging from low-power sensor networks to the most
demanding tasks, such as voice encoding, music streaming and MP3 decoding.

ESP32-WROVER-E comes with a PCB antenna, and ESP32-WROVER-IE with a connector for an external
antenna. The information in this datasheet is applicable to both modules.

The Series Comparison for the two modules is as follows:

Table 1: ESP32-WROVER-E Series Comparison1

Ambient Temp.2 Size3

Ordering Code Flash5 PSRAM
(°C) (mm)
ESP32-WROVER-E-N4R8 4 MB (Quad SPI) 8 MB (Quad SPI) –40 ~ 85
ESP32-WROVER-E-N8R8 8 MB (Quad SPI) 8 MB (Quad SPI) –40 ~ 85
ESP32-WROVER-E-N16R8 16 MB (Quad SPI) 8 MB (Quad SPI) –40 ~ 85
18.0 x 31.4 x 3.3
ESP32-WROVER-E-N4R2 4 MB (Quad SPI) 2 MB (Quad SPI)4 –40 ~ 85
ESP32-WROVER-E-N8R2 8 MB (Quad SPI) 2 MB (Quad SPI)4 –40 ~ 85
ESP32-WROVER-E-N16R2 16 MB (Quad SPI) 2 MB (Quad SPI)4 –40 ~ 85
1 This table shares the same notes presented in the table 2 below.

Table 2: ESP32-WROVER-IE Series Comparison

Ambient Temp.2 Size3

Ordering Code Flash5 PSRAM
(°C) (mm)
ESP32-WROVER-IE-N4R8 4 MB (Quad SPI) 8 MB (Quad SPI) –40 ~ 85
ESP32-WROVER-IE-N8R8 8 MB (Quad SPI) 8 MB (Quad SPI) –40 ~ 85
ESP32-WROVER-IE-N16R8 16 MB (Quad SPI) 8 MB (Quad SPI) –40 ~ 85
18.0 x 31.4 x 3.3
ESP32-WROVER-IE-N4R2 4 MB (Quad SPI) 2 MB (Quad SPI)4 –40 ~ 85
ESP32-WROVER-IE-N8R2 8 MB (Quad SPI) 2 MB (Quad SPI)4 –40 ~ 85
ESP32-WROVER-IE-N16R2 16 MB (Quad SPI) 2 MB (Quad SPI)4 –40 ~ 85
2 Ambient temperature specifies the recommended temperature range of the environment immediately out-
side the Espressif module.
3 For details, refer to Section 10.1 Module Dimensions.
4 This module uses PSRAM integrated in the chip’s package.
5 The integrated flash supports:
- More than 100,000 program/erase cycles
- More than 20 years data retention time

At the core of the module is the ESP32-D0WD-V3 chip or ESP32-D0WDR2-V3 chip*. ESP32-D0WD-V3 chip
and ESP32-D0WDR2-V3 chip* are designed to be scalable and adaptive. There are two CPU cores that can
be individually controlled, and the CPU clock frequency is adjustable from 80 MHz to 240 MHz. The chip also
has a low-power coprocessor that can be used instead of the CPU to save power while performing tasks that
do not require much computing power, such as monitoring of peripherals.

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1 Module Overview

Note:

• For details on the part numbers of the ESP32 family of chips, please refer to the document ESP32 Datasheet.

• For chip revision identification, ESP-IDF release that supports a specific chip revision, and other information on
chip revisions, please refer to ESP32 Series SoC Errata > Section Chip Revision Identification.

1.3 Applications
• Smart Home • Audio Devices

• Industrial Automation • Generic Low-power IoT Sensor Hubs

• Health Care • Generic Low-power IoT Data Loggers

• Consumer Electronics • Cameras for Video Streaming

• Smart Agriculture • Speech Recognition

• POS Machines • Image Recognition

• Service Robot • SDIO Wi-Fi + Bluetooth Networking Card

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Contents

Contents

1 Module Overview 1
1.1 Features 1
1.2 Series Comparison 2
1.3 Applications 3

2 Block Diagram 8

3 Pin Definitions 10
3.1 Pin Layout 10
3.2 Pin Description 11

4 Boot Configurations 13
4.1 Chip Boot Mode Control 14
4.2 Internal LDO (VDD_SDIO) Voltage Control 15
4.3 U0TXD Printing Control 16
4.4 Timing Control of SDIO Slave 16
4.5 JTAG Signal Source Control 16

5 Peripherals 17
5.1 Peripheral Overview 17
5.2 Digital Peripherals 17
5.2.1 General Purpose Input / Output Interface (GPIO) 17
5.2.2 Serial Peripheral Interface (SPI) 17
5.2.3 Universal Asynchronous Receiver Transmitter (UART) 18
5.2.4 I2C Interface 18
5.2.5 I2S Interface 19
5.2.6 Remote Control Peripheral 19
5.2.7 Pulse Counter Controller (PCNT) 20
5.2.8 LED PWM Controller 20
5.2.9 Motor Control PWM 21
5.2.10 SD/SDIO/MMC Host Controller 22
5.2.11 SDIO/SPI Slave Controller 22
5.2.12 TWAI® Controller 23
5.2.13 Ethernet MAC Interface 24
5.3 Analog Peripherals 24
5.3.1 Analog-to-Digital Converter (ADC) 24
5.3.2 Digital-to-Analog Converter (DAC) 25
5.3.3 Touch Sensor 26

6 Electrical Characteristics 27
6.1 Absolute Maximum Ratings 27
6.2 Recommended Operating Conditions 27
6.3 DC Characteristics (3.3 V, 25 °C) 27

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Contents

6.4 Current Consumption in Active Mode 28

7 RF Characteristics 29
7.1 Wi-Fi Radio 29
7.1.1 Wi-Fi RF Transmitter (TX) Characteristics 29
7.1.2 Wi-Fi RF Receiver (RX) Characteristics 30
7.2 Bluetooth Radio 31
7.2.1 Receiver – Basic Data Rate 31
7.2.2 Transmitter – Basic Data Rate 33
7.2.3 Receiver – Enhanced Data Rate 33
7.2.4 Transmitter – Enhanced Data Rate 34
7.3 Bluetooth LE Radio 34
7.3.1 Receiver 34
7.3.2 Transmitter 35

8 Module Schematics 36

9 Peripheral Schematics 38

10 Physical Dimensions 39
10.1 Module Dimensions 39
10.2 Dimensions of External Antenna Connector 41

11 PCB Layout Recommendations 42

11.1 PCB Land Pattern 42
11.2 Module Placement for PCB Design 43

12 Product Handling 44
12.1 Storage Conditions 44
12.2 Electrostatic Discharge (ESD) 44
12.3 Reflow Profile 44
12.4 Ultrasonic Vibration 45

13 Related Documentation and Resources 46

Revision History 47

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List of Tables

List of Tables
1 ESP32-WROVER-E Series Comparison1 2
2 ESP32-WROVER-IE Series Comparison 2
3 Pin Definitions 11
4 Default Configuration of Strapping Pins 13
5 Description of Timing Parameters for the Strapping Pins 14
6 Chip Boot Mode Control 14
7 U0TXD Printing Control 16
8 Timing Control of SDIO Slave 16
9 ADC Characteristics 25
10 ADC Calibration Results 25
11 Capacitive-Sensing GPIOs Available on ESP32 26
12 Absolute Maximum Ratings 27
13 Recommended Operating Conditions 27
14 DC Characteristics (3.3 V, 25 °C) 27
15 Current Consumption for Wi-Fi (2.4 GHz) in Active Mode 28
16 Wi-Fi RF Characteristics 29
17 TX Power with Spectral Mask and EVM Meeting 802.11 Standards 29
18 TX EVM Test1 29
19 RX Sensitivity 30
20 Maximum RX Level 31
21 RX Adjacent Channel Rejection 31
22 Bluetooth LE RF Characteristics 31
23 Receiver Characteristics – Basic Data Rate 31
24 Transmitter Characteristics – Basic Data Rate 33
25 Receiver Characteristics – Enhanced Data Rate 33
26 Transmitter Characteristics – Enhanced Data Rate 34
27 Receiver Characteristics – Bluetooth LE 34
28 Transmitter Characteristics – Bluetooth LE 35

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List of Figures

List of Figures
1 ESP32-WROVER-E Block Diagram (with ESP32-D0WD-V3 embedded) 8
2 ESP32-WROVER-E Block Diagram (with ESP32-D0WDR2-V3 embedded) 8
3 ESP32-WROVER-IE Block Diagram (with ESP32-D0WD-V3 embedded) 9
4 ESP32-WROVER-IE Block Diagram (with ESP32-D0WDR2-V3 embedded) 9
5 Pin Layout (Top View) 10
6 Visualization of Timing Parameters for the Strapping Pins 14
7 Chip Boot Flow 15
8 Schematics of ESP32-WROVER-E 36
9 Schematics of ESP32-WROVER-IE 37
10 Peripheral Schematics 38
11 ESP32-WROVER-E Physical Dimensions 39
12 ESP32-WROVER-IE Physical Dimensions 40
13 Dimensions of External Antenna Connector 41
14 Recommended PCB Land Pattern 42
15 Reflow Profile 44

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 SPIHD SIO3

Q
2 Block Diagram

2 Block Diagram
40 MHz ESP32-WROVER-IE
nna 3V3 Crystal Antenna
40 MHz ESP32-WROVER-E
3V3 Crystal Antenna
RF Matching
ESP32-D0WDR2-V3
EN RF Matching
GPIOs
ESP32-D0WD-V3
QSPI PSRAM
EN GPIOs

VDD_SDIO
SPICLK

SPIWP
SPIDO
SPIHD
SPICS

SPIDI

QSPI PSRAM
QSPI FLASH

VDD_SDIO VDD_SDIO
SPICS0 SPICS1
FLASH_CLK QSPI FLASHPSRAM_CLK
SPIDI SIO0
SPIDO SIO1
SPIWP SIO2
SPIHD SIO3

Figure 1: ESP32-WROVER-E Block Diagram (with ESP32-D0WD-V3 embedded)

40 MHz ESP32-WROVER-E
3V3 Crystal Antenna

RF Matching
ESP32-D0WDR2-V3
EN GPIOs
QSPI PSRAM
VDD_SDIO
SPICLK

SPIWP
SPIDO
SPIHD
SPICS

SPIDI

QSPI FLASH

Figure 2: ESP32-WROVER-E Block Diagram (with ESP32-D0WDR2-V3 embedded)

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 2 Block Diagram

40 MHz ESP32-WROVER-IE
3V3 Crystal Antenna 3V3

RF Matching
ESP32-D0WD-V3
EN GPIOs

QSPI PSRAM
QSPI FLASH
VDD_SDIO VDD_SDIO
SPICS0 SPICS1
FLASH_CLK PSRAM_CLK
SPIDI SIO0
SPIDO SIO1
SPIWP SIO2
SPIHD SIO3

Figure 3: ESP32-WROVER-IE Block Diagram (with ESP32-D0WD-V3 embedded)

40 MHz ESP32-WROVER-IE
ntenna 3V3 Crystal ESP32-WROVER-E Antenna
40 MHz
3V3 Crystal Antenna 3V3

RF Matching
ESP32-D0WDR2-V3 RF Matching
EN GPIOs
ESP32-D0WD-V3
QSPI PSRAM
EN GPIOs
VDD_SDIO
SPICLK

SPIWP
SPIDO
SPIHD
SPICS

SPIDI

QSPI PSRAM
QSPI FLASH

VDD_SDIO VDD_SDIO
SPICS0 SPICS1
FLASH_CLK PSRAM_CLK
SPIDI QSPI FLASH SIO0
SPIDO SIO1
SPIWP SIO2
SPIHD SIO3

Figure 4: ESP32-WROVER-IE Block Diagram (with ESP32-D0WDR2-V3 embedded)

40 MHz ESP32-WROVER-E
3V3 Crystal Antenna

RF Matching
ESP32-D0WDR2-V3
EN GPIOs
QSPI PSRAM
VDD_SDIO
SPICLK

SPIWP
SPIDO
SPIHD
SPICS

SPIDI

QSPI FLASH

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3 Pin Definitions

3 Pin Definitions

3.1 Pin Layout

The pin diagram below shows the approximate location of pins on the module. For the actual diagram drawn to
scale, please refer to Figure 10.1 Module Dimensions.

Keepout Zone
A

1 GND GND 38

2 3V3 IO23 37

3 EN IO22 36

4 SENSOR_VP TXD0 35

5 SENSOR_VN GND GND GND RXD0 34

6 IO34 Pin 39 IO21 33

GND GND
GND

7 IO35 NC 32
GND GND GND

8 IO32 IO19 31

9 IO33 IO18 30

10 IO25 IO5 29

11 IO26 NC 28

12 IO27 NC 27

13 IO14 IO4 26

14 IO12 IO0 25

15 GND IO2 24

16 IO13 IO15 23

17 NC NC 22

18 NC NC 21

19 NC NC 20

Figure 5: Pin Layout (Top View)

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3 Pin Definitions

Note A:

• The zone marked with dotted lines is the antenna keepout zone. The pin layout of ESP32-WROVER-IE is the
same as that of ESP32-WROVER-E, except that ESP32-WROVER-IE has no keepout zone.

• To learn more about the keepout zone for module’s antenna on the base board, please refer to
ESP32 Hardware Design Guidelines > Section Positioning a Module on a Base Board.

3.2 Pin Description

The module has 38 pins. See pin definitions in Table 3 Pin Description.

For peripheral pin configurations, please refer to Section 5.2 Digital Peripherals.

Table 3: Pin Definitions

Name No. Type1 Function

GND 1 P Ground
3V3 2 P Power supply
EN 3 I Module-enable signal. Active high.
SENSOR_VP 4 I GPIO36, ADC1_CH0, RTC_GPIO0
SENSOR_VN 5 I GPIO39, ADC1_CH3, RTC_GPIO3
IO34 6 I GPIO34, ADC1_CH6, RTC_GPIO4
IO35 7 I GPIO35, ADC1_CH7, RTC_GPIO5
GPIO32, XTAL_32K_P (32.768 kHz crystal oscillator input), ADC1_CH4,
IO32 8 I/O
TOUCH9, RTC_GPIO9
GPIO33, XTAL_32K_N (32.768 kHz crystal oscillator output),
IO33 9 I/O
ADC1_CH5, TOUCH8, RTC_GPIO8
IO25 10 I/O GPIO25, DAC_1, ADC2_CH8, RTC_GPIO6, EMAC_RXD0
IO26 11 I/O GPIO26, DAC_2, ADC2_CH9, RTC_GPIO7, EMAC_RXD1
IO27 12 I/O GPIO27, ADC2_CH7, TOUCH7, RTC_GPIO17, EMAC_RX_DV
GPIO14, ADC2_CH6, TOUCH6, RTC_GPIO16, MTMS, HSPICLK,
IO14 13 I/O
HS2_CLK, SD_CLK, EMAC_TXD2
GPIO12, ADC2_CH5, TOUCH5, RTC_GPIO15, MTDI, HSPIQ, HS2_DATA2,
IO12 14 I/O
SD_DATA2, EMAC_TXD3
GND 15 P Ground
GPIO13, ADC2_CH4, TOUCH4, RTC_GPIO14, MTCK, HSPID, HS2_DATA3,
IO13 16 I/O
SD_DATA3, EMAC_RX_ER
NC 17 - See note 2
NC 18 - See note 2
NC 19 - See note 2
NC 20 - See note 2
NC 21 - See note 2
NC 22 - See note 2
GPIO15, ADC2_CH3, TOUCH3, MTDO, HSPICS0, RTC_GPIO13,
IO15 23 I/O
HS2_CMD, SD_CMD, EMAC_RXD3
Cont’d on next page

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3 Pin Definitions

Table 3 – cont’d from previous page

Name No. Type1 Function
GPIO2, ADC2_CH2, TOUCH2, RTC_GPIO12, HSPIWP, HS2_DATA0,
IO2 24 I/O
SD_DATA0
IO0 25 I/O GPIO0, ADC2_CH1, TOUCH1, RTC_GPIO11, CLK_OUT1, EMAC_TX_CLK
GPIO4, ADC2_CH0, TOUCH0, RTC_GPIO10, HSPIHD, HS2_DATA1,
IO4 26 I/O
SD_DATA1, EMAC_TX_ER
NC 27 - -
NC 28 - -
IO5 29 I/O GPIO5, VSPICS0, HS1_DATA6, EMAC_RX_CLK
IO18 30 I/O GPIO18, VSPICLK, HS1_DATA7
IO19 31 I/O GPIO19, VSPIQ, U0CTS, EMAC_TXD0
NC 32 - -
IO21 33 I/O GPIO21, VSPIHD, EMAC_TX_EN
RXD0 34 I/O GPIO3, U0RXD, CLK_OUT2
TXD0 35 I/O GPIO1, U0TXD, CLK_OUT3, EMAC_RXD2
IO22 36 I/O GPIO22, VSPIWP, U0RTS, EMAC_TXD1
IO23 37 I/O GPIO23, VSPID, HS1_STROBE
GND 38 P Ground
1 P: power supply; I: input; O: output.
2 Pins GPIO6 to GPIO11 on the ESP32-D0WD-V3/ESP32-D0WDR2-V3 chip are connected to the SPI flash
integrated on the module and are not led out.

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4 Boot Configurations

4 Boot Configurations
Note:
The content below is excerpted from ESP32 Series Datasheet > Section Boot Configurations. For the strapping pin
mapping between the chip and modules, please refer to Chapter 8 Module Schematics.

The chip allows for configuring the following boot parameters through strapping pins and eFuse bits at
power-up or a hardware reset, without microcontroller interaction.

• Chip boot mode

– Strapping pin: GPIO0 and GPIO2

• Internal LDO (VDD_SDIO) Voltage

– Strapping pin: MTDI

– eFuse bit: EFUSE_SDIO_FORCE and EFUSE_SDIO_TIEH

• U0TXD printing

– Strapping pin: MTDO

• Timing of SDIO Slave

– Strapping pin: MTDO and GPIO5

• JTAG signal source

– Strapping pin: MTCK, MTMS, MTDI and MTDO

– eFuse bit: EFUSE_DISABLE_JTAG

The default values of all the above eFuse bits are 0, which means that they are not burnt. Given that eFuse is
one-time programmable, once an eFuse bit is programmed to 1, it can never be reverted to 0. For how to
program eFuse bits, please refer to ESP32 Technical Reference Manual > Chapter eFuse Controller.

The default values of the strapping pins, namely the logic levels, are determined by pins’ internal weak
pull-up/pull-down resistors at reset if the pins are not connected to any circuit, or connected to an external
high-impedance circuit.

Table 4: Default Configuration of Strapping Pins

Strapping Pin Default Configuration Bit Value

GPIO0 Pull-up 1
GPIO2 Pull-down 0
MTDI Pull-down 0
MTDO Pull-up 1
GPIO5 Pull-up 1

To change the bit values, the strapping pins should be connected to external pull-down/pull-up resistances. If
the ESP32 is used as a device by a host MCU, the strapping pin voltage levels can also be controlled by the
host MCU.

All strapping pins have latches. At system reset, the latches sample the bit values of their respective strapping
pins and store them until the chip is powered down or shut down. The states of latches cannot be changed in

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4 Boot Configurations

any other way. It makes the strapping pin values available during the entire chip operation, and the pins are
freed up to be used as regular IO pins after reset.

The timing of signals connected to the strapping pins should adhere to the setup time and hold time
specifications in Table 5 and Figure 6.

Table 5: Description of Timing Parameters for the Strapping Pins

Parameter Description Min (ms)

Setup time is the time reserved for the power rails to stabilize be-
tSU 0
fore the CHIP_PU pin is pulled high to activate the chip.
Hold time is the time reserved for the chip to read the strapping
tH pin values after CHIP_PU is already high and before these pins 1
start operating as regular IO pins.

tSU tH

VIL_nRST
CHIP_PU

VIH

Strapping pin

Figure 6: Visualization of Timing Parameters for the Strapping Pins

4.1 Chip Boot Mode Control

GPIO0 and GPIO2 control the boot mode after the reset is released. See Table 6 Chip Boot Mode
Control.

Table 6: Chip Boot Mode Control

Boot Mode GPIO0 GPIO2

SPI Boot Mode 1 Any value
Joint Download Boot Mode 2 0 0
1 Bold marks the default value and configuration.
2 Joint Download Boot mode supports the following
download methods:
• SDIO Download Boot
• UART Download Boot

In Joint Download Boot mode, the detailed boot flow of the chip is put below 7.

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4 Boot Configurations

Figure 7: Chip Boot Flow

uart_download_dis controls boot mode behaviors:

It permanently disables Download Boot mode when uart_download_dis is set to 1 (valid only for ESP32 ECO
V3).

4.2 Internal LDO (VDD_SDIO) Voltage Control

MTDI is used to select the VDD_SDIO power supply voltage at reset:

• MTDI = 0 (by default), VDD_SDIO pin is powered directly from VDD3P3_RTC. Typically this voltage is 3.3
V. For more information, see ESP32 Series Datasheet > Section Power Scheme.

• MTDI = 1, VDD_SDIO pin is powered from internal 1.8 V LDO.

This functionality can be overridden by setting EFUSE_SDIO_FORCE to 1, in which case the EFUSE_SDIO_TIEH
determines the VDD_SDIO voltage:

• EFUSE_SDIO_TIEH = 0, VDD_SDIO connects to 1.8 V LDO.

• EFUSE_SPI_TIEH = 1, VDD_SDIO connects to VDD3P3_RTC.

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4 Boot Configurations

4.3 U0TXD Printing Control

During booting, the strapping pin MTDO can be used to control the U0TXD Printing, as Table 7 shows.

Table 7: U0TXD Printing Control

U0TXD Printing Control MTDO

Enabled 1 1
Disabled 0
1 Bold marks the default value and
configuration.

4.4 Timing Control of SDIO Slave

The strapping pin MTDO and GPIO5 can be used to control the timing of SDIO slave, see Table 8 Timing
Control of SDIO Slave.

Table 8: Timing Control of SDIO Slave

Edge behavior MTDO GPIO5

Falling edge sampling, falling edge output 0 0
Falling edge sampling, rising edge output 0 1
Rising edge sampling, falling edge output 1 0
Rising edge sampling, rising edge output 1 1
1 Bold marks the default value and configuration.

4.5 JTAG Signal Source Control

The strapping pin MTCK, MTMS, MTDI and MTDO can be used to control the source of JTAG signals during
the early boot process.

If EFUSE_DISABLE_JTAG is set to 1, the source of JTAG signals can be disabled.

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5 Peripherals

5 Peripherals

5.1 Peripheral Overview

ESP32-D0WD-V3 chip and ESP32-D0WDR2-V3 chip integrate a rich set of peripherals including SPI, I2S,
UART, I2C, pulse count controller, TWAI® , ADC, DAC, touch sensor, etc.

To learn more about on-chip components, please refer to ESP32 Series Datasheet > Section Functional
Description.

Note:

• The content below is sourced from ESP32 Series Datasheet > Section Functional Description. Some information
may not be applicable to ESP32-WROVER-E and ESP32-WROVER-IE as not all the IO signals are exposed on the
module.

• To learn more about peripheral signals, please refer to ESP32 Technical Reference Manual > Section Peripheral
Signal List.

5.2 Digital Peripherals

5.2.1 General Purpose Input / Output Interface (GPIO)
ESP32 has 34 GPIO pins which can be assigned various functions by programming the appropriate registers.
There are several kinds of GPIOs: digital-only, analog-enabled, capacitive-touch-enabled, etc. Analog-enabled
GPIOs and Capacitive-touch-enabled GPIOs can be configured as digital GPIOs.

Most of the digital GPIOs can be configured as internal pull-up or pull-down, or set to high impedance. When
configured as an input, the input value can be read through the register. The input can also be set to
edge-trigger or level-trigger to generate CPU interrupts. Most of the digital IO pins are bi-directional,
non-inverting and tristate, including input and output buffers with tristate control. These pins can be
multiplexed with other functions, such as the SDIO, UART, SPI, etc. (More details can be found in
ESP32 Series Datasheet > Appendix, Table IO_MUX. ) For low-power operations, the GPIOs can be set to
hold their states.

For details, see ESP32 Series Datasheet > Section Peripheral Pin Configurations, ESP32 Series Datasheet >
Appendix A – ESP32 Pin Lists and ESP32 Technical Reference Manual > Chapter IO_MUX and GPIO Matrix.

5.2.2 Serial Peripheral Interface (SPI)

ESP32 features three SPIs (SPI, HSPI and VSPI) in slave and master modes in 1-line full-duplex and 1/2/4-line
half-duplex communication modes.

Features of General Purpose SPI (GP-SPI)

• Programmable data transfer length, in multiples of 1 byte

• Four-line full-duplex/half-duplex communication and three-line half-duplex communication support

• Master mode and slave mode

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• Programmable CPOL and CPHA

• Programmable clock

For details, see ESP32 Technical Reference Manual > Chapter SPI Controller.

Pin Assignment

For SPI, the pins are multiplexed with GPIO6 ~ GPIO11 via the IO MUX. For HSPI, the pins are multiplexed with
GPIO2, GPIO4, GPIO12 ~ GPIO15 via the IO MUX. For VSPI, the pins are multiplexed with GPIO5, GPIO18 ~
GPIO19, GPIO21 ~ GPIO23 via the IO MUX.

For more information about the pin assignment, see ESP32 Series Datasheet > Section Peripheral Pin
Configurations and ESP32 Technical Reference Manual > Chapter IO_MUX and GPIO Matrix.

5.2.3 Universal Asynchronous Receiver Transmitter (UART)

The UART in the ESP32 chip facilitates the transmission and reception of asynchronous serial data between
the chip and external UART devices. It consists of two UARTs in the main system, and one low-power LP
UART.

Feature List

• Programmable baud rate

• RAM shared by TX FIFOs and RX FIFOs

• Supports input baud rate self-check

• Support for various lengths of data bits and stop bits

• Parity bit support

• Asynchronous communication (RS232 and RS485) and IrDA support

• Supports DMA to communicate data in high speed

• Supports UART wake-up

• Supports both software and hardware flow control

For details, see ESP32 Technical Reference Manual > Chapter UART Controller.

Pin Assignment

The pins for UART can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32 Series Datasheet > Section Peripheral Pin
Configurations and ESP32 Technical Reference Manual > Chapter IO_MUX and GPIO Matrix.

5.2.4 I2C Interface

ESP32 has two I2C bus interfaces which can serve as I2C master or slave, depending on the user’s
configuration.

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Feature List

• Two I2C controllers: one in the main system and one in the low-power system

• Standard mode (100 Kbit/s)

• Fast mode (400 Kbit/s)

• Up to 5 MHz, yet constrained by SDA pull-up strength

• Support for 7-bit and 10-bit addressing, as well as dual address mode

• Supports continuous data transmission with disabled Serial Clock Line (SCL)

• Supports programmable digital noise filter

Users can program command registers to control I2C interfaces, so that they have more flexibility.

For details, see ESP32 Technical Reference Manual > Chapter I2C Controller.

Pin Assignment

For regular I2C, the pins used can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32 Series Datasheet > Section Peripheral Pin
Configurations and ESP32 Technical Reference Manual > Chapter IO_MUX and GPIO Matrix.

5.2.5 I2S Interface

The I2S Controller in the ESP32 chip provides a flexible communication interface for streaming digital data in
multimedia applications, particularly digital audio applications.

Feature List

• Master mode and slave mode

• Full-duplex and half-duplex communications

• A variety of audio standards supported

• Configurable high-precision output clock

• Supports PDM signal input and output

• Configurable data transmit and receive modes

For details, see ESP32 Technical Reference Manual > Chapter I2S Controller.

Pin Assignment

The pins for the I2S Controller can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32 Series Datasheet > Section Peripheral Pin
Configurations and ESP32 Technical Reference Manual > Chapter IO_MUX and GPIO Matrix.

5.2.6 Remote Control Peripheral

The Remote Control Peripheral (RMT) controls the transmission and reception of infrared remote control
signals.

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Feature List

• Eight channels for sending and receiving infrared remote control signals

• Independent transmission and reception capabilities for each channel

• Clock divider counter, state machine, and receiver for each RX channel

• Supports various infrared protocols

For details, see ESP32 Technical Reference Manual > Chapter Remote Control Peripheral.

Pin Assignment

The pins for the Remote Control Peripheral can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32 Series Datasheet > Section Peripheral Pin
Configurations and ESP32 Technical Reference Manual > Chapter IO_MUX and GPIO Matrix.

5.2.7 Pulse Counter Controller (PCNT)

The pulse counter controller (PCNT) is designed to count input pulses by tracking rising and falling edges of
the input pulse signal.

Feature List

• Eight independent pulse counter units

• Each pulse counter unit has a 16-bit signed counter register and two channels

• Counter modes: increment, decrement, or disable

• Glitch filtering for input pulse signals and control signals

• Selection between counting on rising or falling edges of the input pulse signal

For details, see ESP32 Technical Reference Manual > Chapter Pulse Count Controller.

Pin Assignment

The pins for the Pulse Count Controller can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32 Series Datasheet > Section Peripheral Pin
Configurations and ESP32 Technical Reference Manual > Chapter IO_MUX and GPIO Matrix.

5.2.8 LED PWM Controller

The LED PWM Controller (LEDC) is designed to generate PWM signals for LED control.

Feature List

• Sixteen independent PWM generators

• Maximum PWM duty cycle resolution of 20 bits

• Eight independent timers with 20-bit counters, configurable fractional clock dividers and counter
overflow values

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• Adjustable phase of PWM signal output

• PWM duty cycle dithering

• Automatic duty cycle fading

For details, see ESP32 Technical Reference Manual > Chapter LED PWM Controller.

Pin Assignment

The pins for the LED PWM Controller can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32 Series Datasheet > Section Peripheral Pin
Configurations and ESP32 Technical Reference Manual > Chapter IO_MUX and GPIO Matrix.

5.2.9 Motor Control PWM

The Pulse Width Modulation (PWM) controller can be used for driving digital motors and smart lights. The
controller consists of PWM timers, the PWM operator and a dedicated capture sub-module. Each timer
provides timing in synchronous or independent form, and each PWM operator generates a waveform for one
PWM channel. The dedicated capture sub-module can accurately capture events with external timing.

Feature List

• Three PWM timers for precise timing and frequency control

– Every PWM timer has a dedicated 8-bit clock prescaler

– The 16-bit counter in the PWM timer can work in count-up mode, count-down mode, or
count-up-down mode

– A hardware sync can trigger a reload on the PWM timer with a phase register. It will also trigger the
prescaler’ restart, so that the timer’s clock can also be synced, with selectable hardware
synchronization source

• Three PWM operators for generating waveform pairs

– Six PWM outputs to operate in several topologies

– Configurable dead time on rising and falling edges; each set up independently

– Modulating of PWM output by high-frequency carrier signals, useful when gate drivers are insulated
with a transformer

• Fault Detection module

– Programmable fault handling in both cycle-by-cycle mode and one-shot mode

– A fault condition can force the PWM output to either high or low logic levels

• Capture module for hardware-based signal processing

– Speed measurement of rotating machinery

– Measurement of elapsed time between position sensor pulses

– Period and duty cycle measurement of pulse train signals

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– Decoding current or voltage amplitude derived from duty-cycle-encoded signals of current/voltage

sensors

– Three individual capture channels, each of which with a 32-bit time-stamp register

– Selection of edge polarity and prescaling of input capture signals

– The capture timer can sync with a PWM timer or external signals

For details, see ESP32 Technical Reference Manual > Chapter Motor Control PWM.

Pin Assignment

The pins for the Motor Control PWM can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32 Series Datasheet > Section Peripheral Pin
Configurations and ESP32 Technical Reference Manual > Chapter IO_MUX and GPIO Matrix.

5.2.10 SD/SDIO/MMC Host Controller

An SD/SDIO/MMC host controller is available on ESP32.

Feature List

• Supports two external cards

• Supports SD Memory Card standard: version 3.0 and version 3.01)

• Supports SDIO Version 3.0

• Supports Consumer Electronics Advanced Transport Architecture (CE-ATA Version 1.1)

• Supports Multimedia Cards (MMC version 4.41, eMMC version 4.5 and version 4.51)

The controller allows up to 80 MHz clock output in three different data-bus modes: 1-bit, 4-bit, and 8-bit
modes. It supports two SD/SDIO/MMC4.41 cards in a 4-bit data-bus mode. It also supports one SD card
operating at 1.8 V.

For details, see ESP32 Technical Reference Manual > Chapter SD/MMC Host Controller.

Pin Assignment

The pins for SD/SDIO/MMC Host Controller are multiplexed with GPIO2, GPIO4, GPIO6 ~ GPIO15 via IO
MUX.

For more information about the pin assignment, see ESP32 Series Datasheet > Section Peripheral Pin
Configurations and ESP32 Technical Reference Manual > Chapter IO_MUX and GPIO Matrix.

5.2.11 SDIO/SPI Slave Controller

ESP32 integrates an SD device interface that conforms to the industry-standard SDIO Card Specification
Version 2.0, and allows a host controller to access the SoC, using the SDIO bus interface and protocol. ESP32
acts as the slave on the SDIO bus. The host can access the SDIO-interface registers directly and can access
shared memory via a DMA engine, thus maximizing performance without engaging the processor cores.

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Feature List

The SDIO/SPI slave controller supports the following features:

• SPI, 1-bit SDIO, and 4-bit SDIO transfer modes over the full clock range from 0 to 50 MHz

• Configurable sampling and driving clock edge

• Special registers for direct access by host

• Interrupts to host for initiating data transfer

• Automatic loading of SDIO bus data and automatic discarding of padding data

• Block size of up to 512 bytes

• Interrupt vectors between the host and the slave, allowing both to interrupt each other

• Supports DMA for data transfer

For details, see ESP32 Technical Reference Manual > Chapter SDIO Slave Controller.

Pin Assignment

The pins for SDIO/SPI Slave Controller are multiplexed with GPIO2, GPIO4, GPIO6 ~ GPIO15 via IO MUX.

For more information about the pin assignment, see ESP32 Series Datasheet > Section Peripheral Pin
Configurations and ESP32 Technical Reference Manual > Chapter IO_MUX and GPIO Matrix.

5.2.12 TWAI® Controller

The Two-wire Automotive Interface (TWAI® ) is a multi-master, multi-cast communication protocol designed for
automotive applications. The TWAI controller facilitates the communication based on this protocol.

Feature List

• Compatible with ISO 11898-1 protocol (CAN Specification 2.0)

• Standard frame format (11-bit ID) and extended frame format (29-bit ID)

• Bit rates:

– From 25 Kbit/s to 1 Mbit/s in chip revision v0.0/v1.0/v1.1

– From 12.5 Kbit/s to 1 Mbit/s in chip revision v3.0/v3.1

• Multiple modes of operation: Normal, Listen Only, and Self-Test

• 64-byte receive FIFO

• Special transmissions: single-shot transmissions and self reception

• Acceptance filter (single and dual filter modes)

• Error detection and handling: error counters, configurable error interrupt threshold, error code capture,
arbitration lost capture

For details, see ESP32 Technical Reference Manual > Chapter Two-wire Automotive Interface (TWAI).

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Pin Assignment

The pins for the Two-wire Automotive Interface can be chosen from any GPIOs via the GPIO Matrix.

For more information about the pin assignment, see ESP32 Series Datasheet > Section Peripheral Pin
Configurations and ESP32 Technical Reference Manual > Chapter IO_MUX and GPIO Matrix.

5.2.13 Ethernet MAC Interface

An IEEE-802.3-2008-compliant Media Access Controller (MAC) is provided for Ethernet LAN communications.
ESP32 requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to ESP32 through 17 signals of MII or nine signals of RMII.

Feature List

• 10 Mbps and 100 Mbps rates

• Dedicated DMA controller allowing high-speed transfer between the dedicated SRAM and Ethernet MAC

• Tagged MAC frame (VLAN support)

• Half-duplex (CSMA/CD) and full-duplex operation

• MAC control sublayer (control frames)

• 32-bit CRC generation and removal

• Several address-filtering modes for physical and multicast address (multicast and group addresses)

• 32-bit status code for each transmitted or received frame

• Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 512
words (32-bit)

• Hardware PTP (Precision Time Protocol) in accordance with IEEE 1588 2008 (PTP V2)

• 25 MHz/50 MHz clock output

For details, see ESP32 Technical Reference Manual > Chapter Ethernet Media Access Controller (MAC).

Pin Assignment

For information about the pin assignment of Ethernet MAC Interface, see ESP32 Series Datasheet > Section
Peripheral Pin Configurations and ESP32 Technical Reference Manual > Chapter IO_MUX and GPIO
Matrix.

5.3 Analog Peripherals

5.3.1 Analog-to-Digital Converter (ADC)
ESP32 integrates two 12-bit SAR ADCs and supports measurements on 18 channels (analog-enabled pins).
The ULP coprocessor in ESP32 is also designed to measure voltage, while operating in the sleep mode, which
enables low-power consumption. The CPU can be woken up by a threshold setting and/or via other
triggers.

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5 Peripherals

Table 9 describes the ADC characteristics.

Table 9: ADC Characteristics

Parameter Description Min Max Unit

RTC controller; ADC connected to an
DNL (Differential nonlinearity) –7 7 LSB
external 100 nF capacitor; DC signal input;
ambient temperature at 25 °C;
INL (Integral nonlinearity) –12 12 LSB
Wi-Fi&Bluetooth off
RTC controller — 200 ksps
Sampling rate
DIG controller — 2 Msps

Notes:

• When atten = 3 and the measurement result is above 3000 (voltage at approx. 2450 mV), the ADC
accuracy will be worse than described in the table above.

• To get better DNL results, users can take multiple sampling tests with a filter, or calculate the average
value.

• The input voltage range of GPIO pins within VDD3P3_RTC domain should strictly follow the DC
characteristics provided in Table 14. Otherwise, measurement errors may be introduced, and chip
performance may be affected.

By default, there are ±6% differences in measured results between chips. ESP-IDF provides couple of
calibration methods for ADC1. Results after calibration using eFuse Vref value are shown in Table 10. For higher
accuracy, users may apply other calibration methods provided in ESP-IDF, or implement their own.

Table 10: ADC Calibration Results

Parameter Description Min Max Unit

Atten = 0, effective measurement range of 100 ∼ 950 mV –23 23 mV
Atten = 1, effective measurement range of 100 ∼ 1250 mV –30 30 mV
Total error
Atten = 2, effective measurement range of 150 ∼ 1750 mV –40 40 mV
Atten = 3, effective measurement range of 150 ∼ 2450 mV –60 60 mV

For details, see ESP32 Technical Reference Manual > Chapter On-Chip Sensors and Analog Signal
Processing.

Pin Assignment

With appropriate settings, the ADCs can be configured to measure voltage on 18 pins maximum. For detailed
information about the pin assignment, see ESP32 Series Datasheet > Section Peripheral Pin Configurations
and ESP32 Technical Reference Manual > Chapter IO_MUX and GPIO Matrix.

5.3.2 Digital-to-Analog Converter (DAC)

Two 8-bit DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The
design structure is composed of integrated resistor strings and a buffer. This dual DAC supports power supply
as input voltage reference. The two DAC channels can also support independent conversions.

For details, see ESP32 Technical Reference Manual > Chapter On-Chip Sensors and Analog Signal
Processing.

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Pin Assignment

The DAC can be configured by GPIO 25 and GPIO 26. For detailed information about the pin assignment, see
ESP32 Series Datasheet > Section Peripheral Pin Configurations and ESP32 Technical Reference Manual >
Chapter IO_MUX and GPIO Matrix.

5.3.3 Touch Sensor

ESP32 has 10 capacitive-sensing GPIOs, which detect variations induced by touching or approaching the
GPIOs with a finger or other objects. The low-noise nature of the design and the high sensitivity of the circuit
allow relatively small pads to be used. Arrays of pads can also be used, so that a larger area or more points
can be detected.

Pin Assignment

The 10 capacitive-sensing GPIOs are listed in Table 11.

Table 11: Capacitive-Sensing GPIOs Available on ESP32

Capacitive-Sensing Signal Name Pin Name

T0 GPIO4
T1 GPIO0
T2 GPIO2
T3 MTDO
T4 MTCK
T5 MTDI
T6 MTMS
T7 GPIO27
T8 32K_XN
T9 32K_XP

For details, see ESP32 Technical Reference Manual > Chapter On-Chip Sensors and Analog Signal
Processing.

Note:
ESP32 Touch Sensor has not passed the Conducted Susceptibility (CS) test for now, and thus has limited application
scenarios.

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6 Electrical Characteristics

6.1 Absolute Maximum Ratings

Stresses above those listed in Table 12 Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions
beyond those indicated under Table 13 Recommended Operating Conditions is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.

Table 12: Absolute Maximum Ratings

Symbol Parameter Min Max Unit

VDD33 Power supply voltage –0.3 3.6 V
Tstore Storage temperature –40 105 °C

6.2 Recommended Operating Conditions

Table 13: Recommended Operating Conditions

Symbol Parameter Min Typ Max Unit

VDD33 Power supply voltage 3.0 3.3 3.6 V
IV DD Current delivered by external power supply 0.5 — — A
T Operating temperature –40 — 85 °C

6.3 DC Characteristics (3.3 V, 25 °C)

Table 14: DC Characteristics (3.3 V, 25 °C)

Symbol Parameter Min Typ Max Unit

CIN Pin capacitance - 2 - pF
1 1
VIH High-level input voltage 0.75×VDD - VDD +0.3 V
1
VIL Low-level input voltage –0.3 - 0.25×VDD V
IIH High-level input current - - 50 nA
IIL Low-level input current - - 50 nA
1
VOH High-level output voltage 0.8×VDD - - V
1
VOL Low-level output voltage - - 0.1×VDD V
Cont’d on next page

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6 Electrical Characteristics

Table 14 – cont’d from previous page

Symbol Parameter Min Typ Max Unit
VDD3P3_CPU
High-level source current - 40 - mA
1
power domain 1, 2
(VDD = 3.3 V,
VDD3P3_RTC
IOH VOH >= 2.64 V, - 40 - mA
power domain 1, 2
output drive strength set
VDD_SDIO power
to the maximum) - 20 - mA
domain 1, 3

Low-level sink current

IOL (VDD1 = 3.3 V, VOL = 0.495 V, - 28 - mA
output drive strength set to the maximum)
RP U Resistance of internal pull-up resistor - 45 - kΩ
RP D Resistance of internal pull-down resistor - 45 - kΩ
Low-level input voltage of CHIP_PU
VIL_nRST - - 0.6 V
to shut down the chip
1 Please see Appendix IO MUX of ESP32 Series Datasheet for IO’s power domain. VDD is the I/O
voltage for a particular power domain of pins.
2 For VDD3P3_CPU and VDD3P3_RTC power domain, per-pin current sourced in the same domain is
gradually reduced from around 40 mA to around 29 mA, VOH >=2.64 V, as the number of current-
source pins increases.
3 Pins occupied by flash and/or PSRAM in the VDD_SDIO power domain were excluded from the test.

6.4 Current Consumption in Active Mode

The current consumption measurements are taken with a 3.3 V supply at 25 °C ambient temperature.

TX current consumption is rated at a 100% duty cycle.

RX current consumption is rated when the peripherals are disabled and the CPU idle.

Table 15: Current Consumption for Wi-Fi (2.4 GHz) in Active Mode

Work Mode RF Condition Description Peak (mA)

802.11b, 1 Mbps, DSSS @ 19.5 dBm 350
802.11g, 54 Mbps, OFDM @ 14.0 dBm 243
TX
802.11n, HT20, MCS7 @ 13.0 dBm 233
802.11n, HT40, MCS7 @ 13.0 dBm 229
Active (RF working)
802.11b/g/n, HT20 108
RX
802.11n, HT40 113

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7 RF Characteristics
This section contains tables with RF characteristics of the Espressif product.

The RF data is measured at the antenna port, where RF cable is connected, including the front-end loss. The
external antennas used for the tests on the modules with external antenna connectors have an impedance of
50 Ω.Devices should operate in the center frequency range allocated by regional regulatory authorities. The
target center frequency range and the target transmit power are configurable by software. See ESP RF Test
Tool and Test Guide for instructions.

Unless otherwise stated, the RF tests are conducted with a 3.3 V (±5%) supply at 25 ºC ambient
temperature.

7.1 Wi-Fi Radio

Table 16: Wi-Fi RF Characteristics

Name Description
Center frequency range of operating channel 2412 ~ 2484 MHz
Wi-Fi wireless standard IEEE 802.11b/g/n

7.1.1 Wi-Fi RF Transmitter (TX) Characteristics

Table 17: TX Power with Spectral Mask and EVM Meeting 802.11 Standards

Min Typ Max

Rate
(dBm) (dBm) (dBm)
802.11b, 1 Mbps — 19.5 —
802.11b, 11 Mbps — 19.5 —
802.11g, 6 Mbps — 18.0 —
802.11g, 54 Mbps — 14.0 —
802.11n, HT20, MCS0 — 18.0 —
802.11n, HT20, MCS7 — 13.0 —
802.11n, HT40, MCS0 — 18.0 —
802.11n, HT40, MCS7 — 13.0 —

Table 18: TX EVM Test1

Min Typ Limit

Rate (dB) (dB) (dB)
802.11b, 1 Mbps, DSSS — –25.0 –10.0
802.11b, 11 Mbps, CCK — –25.0 –10.0
802.11g, 6 Mbps, OFDM — –24.0 –5.0
802.11g, 54 Mbps, OFDM — –28.0 –25.0
802.11n, HT20, MCS0 — –24.0 –5.0
Cont’d on next page

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7 RF Characteristics

Table 18 – cont’d from previous page

Min Typ Limit
Rate (dB) (dB) (dB)
802.11n, HT20, MCS7 — –30.0 –27.0
802.11n, HT40, MCS0 — –24.0 –5.0
802.11n, HT40, MCS7 — –30.0 –27.0
1 EVM is measured at the corresponding typical TX power provided
in Table 17 Wi-Fi RF Transmitter (TX) Characteristics above.

7.1.2 Wi-Fi RF Receiver (RX) Characteristics

For RX tests, the PER (packet error rate) limit is 8% for 802.11b, and 10% for 802.11g/n.
Table 19: RX Sensitivity

Min Typ Max

Rate
(dBm) (dBm) (dBm)
802.11b, 1 Mbps, DSSS — –97.0 —
802.11b, 2 Mbps, DSSS — –94.0 —
802.11b, 5.5 Mbps, CCK — –91.0 —
802.11b, 11 Mbps, CCK — –88.0 —
802.11g, 6 Mbps, OFDM — –93.0 —
802.11g, 9 Mbps, OFDM — –91.0 —
802.11g, 12 Mbps, OFDM — –90.0 —
802.11g, 18 Mbps, OFDM — –87.0 —
802.11g, 24 Mbps, OFDM — –84.0 —
802.11g, 36 Mbps, OFDM — –81.0 —
802.11g, 48 Mbps, OFDM — –77.0 —
802.11g, 54 Mbps, OFDM — –75.0 —
802.11n, HT20, MCS0 — –91.0 —
802.11n, HT20, MCS1 — –88.0 —
802.11n, HT20, MCS2 — –86.0 —
802.11n, HT20, MCS3 — -83.0 —
802.11n, HT20, MCS4 — –80.0 —
802.11n, HT20, MCS5 — –75.0 —
802.11n, HT20, MCS6 — –73.0 —
802.11n, HT20, MCS7 — –72.0 —
802.11n, HT40, MCS0 — –88.0 —
802.11n, HT40, MCS1 — –85.0 —
802.11n, HT40, MCS2 — –83.0 —
802.11n, HT40, MCS3 — –80.0 —
802.11n, HT40, MCS4 — –76.0 —
802.11n, HT40, MCS5 — –72.0 —
802.11n, HT40, MCS6 — –70.0 —
802.11n, HT40, MCS7 — –69.0 —

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Table 20: Maximum RX Level

Min Typ Max

Rate
(dBm) (dBm) (dBm)
802.11b, 1 Mbps — 5 —
802.11b, 11 Mbps — 5 —
802.11g, 6 Mbps — 0 —
802.11g, 54 Mbps — –8 —
802.11n, HT20, MCS0 — 0 —
802.11n, HT20, MCS7 — –8 —
802.11n, HT40, MCS0 — 0 —
802.11n, HT40, MCS7 — –8 —

Table 21: RX Adjacent Channel Rejection

Min Typ Max

Rate
(dB) (dB) (dB)
802.11b, 1 Mbps, DSSS — 35 —
802.11b, 11 Mbps, CCK — 35 —
802.11g, 6 Mbps, OFDM — 27 —
802.11g, 54 Mbps, OFDM — 13 —
802.11n, HT20, MCS0 — 27 —
802.11n, HT20, MCS7 — 12 —
802.11n, HT40, MCS0 — 16 —
802.11n, HT40, MCS7 — 7 —

7.2 Bluetooth Radio

Table 22: Bluetooth LE RF Characteristics

Name Description
Center frequency range of operating channel 2402 ~ 2480 MHz
RF transmit power range –12.0 ~ 9.0 dBm

7.2.1 Receiver – Basic Data Rate

Table 23: Receiver Characteristics – Basic Data Rate

Parameter Conditions Min Typ Max Unit

Sensitivity @0.1% BER — –90 –89 –88 dBm
Maximum received signal @0.1% BER — 0 — — dBm
Co-channel C/I — — +7 — dB
F = F0 + 1 MHz — — –6 dB
F = F0 – 1 MHz — — –6 dB
Cont’d on next page
Adjacent channel selectivity C/I

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7 RF Characteristics

Table 23 – cont’d from previous page

Parameter Conditions Min Typ Max Unit
F = F0 + 2 MHz — — –25 dB
F = F0 – 2 MHz — — –33 dB
F = F0 + 3 MHz — — –25 dB
F = F0 – 3 MHz — — –45 dB
30 MHz ~ 2000 MHz –10 — — dBm
2000 MHz ~ 2400 MHz –27 — — dBm
Out-of-band blocking performance
2500 MHz ~ 3000 MHz –27 — — dBm
3000 MHz ~ 12.5 GHz –10 — — dBm
Intermodulation — –36 — — dBm

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7 RF Characteristics

7.2.2 Transmitter – Basic Data Rate

Table 24: Transmitter Characteristics – Basic Data Rate

Parameter Conditions Min Typ Max Unit

RF transmit power1 — — 0 — dBm
Gain control step — — 3 — dB
RF power control range — –12 — +9 dBm
+20 dB bandwidth — — 0.9 — MHz
F = F0 ± 2 MHz — –55 — dBm
Adjacent channel transmit power F = F0 ± 3 MHz — –55 — dBm
F = F0 ± > 3 MHz — –59 — dBm
∆ f 1avg — — — 155 kHz
∆ f 2max — 127 — — kHz
∆ f 2avg /∆ f 1avg — — 0.92 — —
ICFT — — –7 — kHz
Drift rate — — 0.7 — kHz/50 µs
Drift (DH1) — — 6 — kHz
Drift (DH5) — — 6 — kHz
1 There are a total of eight power levels from 0 to 7, and the transmit power ranges from –12 dBm
to 9 dBm. When the power level rises by 1, the transmit power increases by 3 dB. Power level 4 is
used by default and the corresponding transmit power is 0 dBm.

7.2.3 Receiver – Enhanced Data Rate

Table 25: Receiver Characteristics – Enhanced Data Rate

Parameter Conditions Min Typ Max Unit

π/4 DQPSK
Sensitivity @0.01% BER — –90 –89 –88 dBm
Maximum received signal @0.01% BER — — 0 — dBm
Co-channel C/I — — 11 — dB
F = F0 + 1 MHz — –7 — dB
F = F0 – 1 MHz — –7 — dB
F = F0 + 2 MHz — –25 — dB
Adjacent channel selectivity C/I
F = F0 – 2 MHz — –35 — dB
F = F0 + 3 MHz — –25 — dB
F = F0 – 3 MHz — –45 — dB
8DPSK
Sensitivity @0.01% BER — –84 –83 –82 dBm
Maximum received signal @0.01% BER — — –5 — dBm
C/I c-channel — — 18 — dB
F = F0 + 1 MHz — 2 — dB
F = F0 – 1 MHz — 2 — dB
Cont’d on next page
Adjacent channel selectivity C/I

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7 RF Characteristics

Table 25 – cont’d from previous page

Parameter Conditions Min Typ Max Unit
F = F0 + 2 MHz — –25 — dB
F = F0 – 2 MHz — –25 — dB
F = F0 + 3 MHz — –25 — dB
F = F0 – 3 MHz — –38 — dB

7.2.4 Transmitter – Enhanced Data Rate

Table 26: Transmitter Characteristics – Enhanced Data Rate

Parameter Conditions Min Typ Max Unit

RF transmit power (see note under Table 24) — — 0 — dBm
Gain control step — — 3 — dB
RF power control range — –12 — +9 dBm
π/4 DQPSK max w0 — — –0.72 — kHz
π/4 DQPSK max wi — — –6 — kHz
π/4 DQPSK max |wi + w0| — — –7.42 — kHz
8DPSK max w0 — — 0.7 — kHz
8DPSK max wi — — –9.6 — kHz
8DPSK max |wi + w0| — — –10 — kHz
RMS DEVM — 4.28 — %
π/4 DQPSK modulation accuracy 99% DEVM — 100 — %
Peak DEVM — 13.3 — %
RMS DEVM — 5.8 — %
8 DPSK modulation accuracy 99% DEVM — 100 — %
Peak DEVM — 14 — %
F = F0 ± 1 MHz — –46 — dBm
F = F0 ± 2 MHz — –44 — dBm
In-band spurious emissions
F = F0 ± 3 MHz — –49 — dBm
F = F0 +/– > 3 MHz — — –53 dBm
EDR differential phase coding — — 100 — %

7.3 Bluetooth LE Radio

7.3.1 Receiver

Table 27: Receiver Characteristics – Bluetooth LE

Parameter Conditions Min Typ Max Unit

Sensitivity @30.8% PER — –94 –93 –92 dBm
Maximum received signal @30.8% PER — 0 — — dBm
Co-channel C/I — — +10 — dB
F = F0 + 1 MHz — –5 — dB
F = F0 – 1 MHz — –5 — dB

Adjacent channel selectivity C/I

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7 RF Characteristics

Parameter Conditions Min Typ Max Unit

F = F0 + 2 MHz — –25 — dB
F = F0 – 2 MHz — –35 — dB
F = F0 + 3 MHz — –25 — dB
F = F0 – 3 MHz — –45 — dB
30 MHz ~ 2000 MHz –10 — — dBm
2000 MHz ~ 2400 –27 — — dBm
Out-of-band blocking performance
MHz
2500 MHz ~ 3000 –27 — — dBm
MHz
3000 MHz ~ 12.5 GHz –10 — — dBm
Intermodulation — –36 — — dBm

7.3.2 Transmitter

Table 28: Transmitter Characteristics – Bluetooth LE

Parameter Conditions Min Typ Max Unit

RF transmit power (see note under Table — — 0 — dBm
24)
Gain control step — — 3 — dB
RF power control range — –12 — +9 dBm
F = F0 ± 2 MHz — –55 — dBm
Adjacent channel transmit power F = F0 ± 3 MHz — –57 — dBm
F = F0 ± > 3 MHz — –59 — dBm
∆ f 1avg — — — 265 kHz
∆ f 2max — 210 — — kHz
∆ f 2avg /∆ f 1avg — — +0.92 — —
ICFT — — –10 — kHz
Drift rate — — 0.7 — kHz/50 µs
Drift — — 2 — kHz

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 Espressif Systems

8 Module Schematics
8 Module Schematics
5 4 3 2 1

This is the reference design of the module.

GND

The values of C1 and C2 vary with GND GND

the selection of the crystal.

3
U1
VDD33 The value of R2 varies with the actual C1 C2

GND XOUT
GND
PCB board.
TBD TBD

XIN
D C3 C20

100pF 1uF

2
VDD33

GND GND

0
C9 GND

0.1uF
VDD33 GND
PCB ANTENNA
R1 20K(5%)

R2
GND 40MHz(±10ppm)
L5 2.0nH(0.1nH)
C5 C6 GPIO21
C13 C11 C10 C21 R3 499 U0TXD
10nF/6.3V(10%) 3.3nF/6.3V(10%) U0RXD
10uF 1uF 0.1uF NC GPIO22
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GND Pin.1 GND GND Pin.38

GND GND GND GND
VDD33 GND GND

49

48
47
46
45
44
43
42
41
40
39
1 ANT2 R14 0(NC) GND Pin.2 GPIO23 Pin.37
VDD33

VDDA
XTAL_P

VDDA
CAP1
CAP2

GPIO21

GPIO22
GND

XTAL_N

U0TXD
U0RXD
J39 3V3 IO23
2

IPEX(NC) D1 EN GPIO22
C4 Pin.3 Pin.36
VDD33 ESD
0.1uF
EN IO22
GND Pin.4 SENSOR_VP U0TXD Pin.35
ANT1 1 38 GPIO19
1 ANT1 R15 0 RF_ANT L4 TBD LNA_IN 2 VDDA GPIO19 37 SENSOR_VP U0TXD
2 3 LNA_IN VDD3P3_CPU 36 GPIO23 SENSOR_VN U0RXD
VDD3P3 GPIO23
GND Pin.5 Pin.34
C15 C14 4 35 GPIO18
PCB_ANT SENSOR_VP 5 VDD3P3 GPIO18 34 GPIO5 SENSOR_VN U0RXD
36

TBD TBD 6 SENSOR_VP GPIO5 33 SDI/SD1 GPIO34 GPIO21

SENSOR_CAPP SD_DATA_1 Pin.6 Pin.33
7 32 SDO/SD0
SENSOR_VN 8 SENSOR_CAPN SD_DATA_0 31 SCK/CLK IO34 IO21
EN 9 SENSOR_VN SD_CLK 30 SCS/CMD GPIO35
GND GND GND
CHIP_PU SD_CMD Pin.7 Pin.32
GPIO34 10 29 SWP/SD3
GPIO35 11 VDET_1 SD_DATA_3 28 SHD/SD2 IO35 NC
The values of C15, L4 and C14 VDET_2 SD_DATA_2 EPAD
C GPIO32 12 27 GPIO17 Pin.8 GPIO32 GPIO19 Pin.31
vary with the actual PCB board. GPIO33 13 32K_XP GPIO17 26
IO32 IO19
VDD3P3_RTC

GPIO25 14 32K_XN VDD_SDIO 25 GPIO16

GPIO25 GPIO16 GPIO33 GPIO18
NC: No component. Pin.9 Pin.30
GPIO26
GPIO27

IO33 IO18
GPIO2
GPIO0
GPIO4
MTDO
MTMS

MTCK
MTDI

C24 VDD_SDIO Pin.10 GPIO25 GPIO5 Pin.29

ESP32-WROVER-E & ESP32-WROVER-IE Datasheet v2.0

R4

U2 ESP32-D0WD-V3 2K(NC) 1uF IO25 IO5

15
16
17
18
19
20
21
22
23
24

ESP32-D0WDR2-V3 Pin.11 GPIO26 Pin.28

SCK/CLK R12 0 FLASH_CLK VDD33
GND GND IO26 NC
10K(NC) R9 Pin.12 GPIO27 Pin.27
VDD33
R11 IO27 NC
C19
GPIO26
GPIO27
GPIO14

GPIO13
GPIO15
GPIO12

0(NC)
GPIO2
GPIO0
GPIO4

Pin.13 GPIO14 GPIO4 Pin.26

0.1uF
GPIO17 R13 0 SRAM_CLK IO14 IO4
Pin.14 GPIO12 GPIO0 Pin.25
GND
IO12 IO0
Pin.15 GND GPIO2 Pin.24
VDD_SDIO Flash and PSRAM VDD_SDIO VDD_SDIO
GND IO2
Pin.16 GPIO13 GPIO15 Pin.23
IO13 IO15
R10
8

U3 Pin.17 Pin.22
SCS/CMD 1 5 SDI/SD1 10K
VCC

/CS DI U4
NC NC
FLASH_CLK 6 2 SDO/SD0 GPIO16 1 8 Pin.18 Pin.21
CLK DO SDO/SD0 2 CS# VDD 7 SHD/SD2
GND

SHD/SD2 7 3 SWP/SD3 SWP/SD3 3 SO/SIO1 SIO3 6 SRAM_CLK NC NC

/HOLD /WP 4 SIO2 SCLK 5 SDI/SD1
VSS SI/SIO0 Pin.19 Pin.20
FLASH
NC NC
4

PSRAM

B GND GND When ESP32-D0WDR2-V3 is used, U4 will be NC. ESP32-WROVER-E(pin-out)

Figure 8: Schematics of ESP32-WROVER-E

 5 4 3 2 1

Espressif Systems

8 Module Schematics
GND

The values of C1 and C2 vary with GND GND

the selection of the crystal.

3
U1
VDD33 The value of R2 varies with the actual C1 C2

GND XOUT
GND
PCB board.
TBD TBD

XIN
D C3 C20

100pF 1uF

2
VDD33

GND GND

0
C9 GND

0.1uF
VDD33 GND
PCB ANTENNA
R1 20K(5%)

R2
GND 40MHz(±10ppm)
L5 2.0nH(0.1nH)
C5 C6 GPIO21
C13 C11 C10 C21 R3 499 U0TXD
10nF/6.3V(10%) 3.3nF/6.3V(10%) U0RXD
10uF 1uF 0.1uF NC GPIO22
GND Pin.1 GND GND Pin.38
GND GND GND GND
VDD33 GND GND

49

48
47
46
45
44
43
42
41
40
39
1 ANT2 R14 0 GND Pin.2 GPIO23 Pin.37
VDD33

VDDA
XTAL_P

VDDA
CAP1
CAP2

GPIO21

GPIO22
GND

XTAL_N

U0TXD
U0RXD
J39 3V3 IO23
2

IPEX D1 EN GPIO22
C4
VDD33
Pin.3 Pin.36
ESD EN IO22
0.1uF
GND Pin.4 SENSOR_VP U0TXD Pin.35
ANT1 1 38 GPIO19
1 ANT1 R15 0(NC) RF_ANT L4 TBD LNA_IN 2 VDDA GPIO19 37 SENSOR_VP U0TXD
2 3 LNA_IN VDD3P3_CPU 36 GPIO23 SENSOR_VN U0RXD
VDD3P3 GPIO23
GND Pin.5 Pin.34
C15 C14 4 35 GPIO18
PCB_ANT SENSOR_VP 5 VDD3P3 GPIO18 34 GPIO5
SENSOR_VN U0RXD
TBD TBD SENSOR_VP GPIO5
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6 33 SDI/SD1 Pin.6 GPIO34 GPIO21 Pin.33

7 SENSOR_CAPP SD_DATA_1 32 SDO/SD0
SENSOR_VN 8 SENSOR_CAPN SD_DATA_0 31 SCK/CLK IO34 IO21
EN 9 SENSOR_VN SD_CLK 30 SCS/CMD GPIO35
GND GND GND
CHIP_PU SD_CMD Pin.7 Pin.32
GPIO34 10 29 SWP/SD3
GPIO35 11 VDET_1 SD_DATA_3 28 SHD/SD2 IO35 NC
The values of C15, L4 and C14 VDET_2 SD_DATA_2 EPAD
C GPIO32 12 27 GPIO17 Pin.8 GPIO32 GPIO19 Pin.31
vary with the actual PCB board. GPIO33 13 32K_XP GPIO17 26
IO32 IO19

VDD3P3_RTC
GPIO25 14 32K_XN VDD_SDIO 25 GPIO16
GPIO25 GPIO16 GPIO33 GPIO18
NC: No component. Pin.9 Pin.30

GPIO26
GPIO27
IO33 IO18

GPIO2
GPIO0
GPIO4
MTDO
MTMS

MTCK
MTDI
R4 C24 VDD_SDIO Pin.10 GPIO25 GPIO5 Pin.29
U2 ESP32-D0WD-V3 2K(NC) 1uF IO25 IO5
15
16
17
18
19
20
21
22
23
24
37

ESP32-D0WDR2-V3 Pin.11 GPIO26 Pin.28

SCK/CLK R12 0 FLASH_CLK VDD33
GND GND IO26 NC
10K(NC) R9 Pin.12 GPIO27 Pin.27
VDD33
R11 IO27 NC
C19
GPIO26
GPIO27
GPIO14

GPIO13
GPIO15
GPIO12

0(NC)
GPIO2
GPIO0
GPIO4 Pin.13 GPIO14 GPIO4 Pin.26
0.1uF
GPIO17 R13 0 SRAM_CLK IO14 IO4
Pin.14 GPIO12 GPIO0 Pin.25
GND
IO12 IO0
Pin.15 GPIO2 Pin.24
ESP32-WROVER-E & ESP32-WROVER-IE Datasheet v2.0

GND
VDD_SDIO Flash and PSRAM VDD_SDIO VDD_SDIO
GND IO2
Pin.16 GPIO13 GPIO15 Pin.23
IO13 IO15
R10
8

U3 Pin.17 Pin.22
SCS/CMD 1 5 SDI/SD1 10K
VCC

/CS DI U4
NC NC
FLASH_CLK 6 2 SDO/SD0 GPIO16 1 8 Pin.18 Pin.21
CLK DO SDO/SD0 2 CS# VDD 7 SHD/SD2
GND

SHD/SD2 7 3 SWP/SD3 SWP/SD3 3 SO/SIO1 SIO3 6 SRAM_CLK NC NC

/HOLD /WP 4 SIO2 SCLK 5 SDI/SD1
VSS SI/SIO0 Pin.19 Pin.20
FLASH
NC NC
4

PSRAM

B GND GND When ESP32-D0WDR2-V3 is used, U4 will be NC. ESP32-WROVER-IE(pin-out)

Figure 9: Schematics of ESP32-WROVER-IE

A
9 Peripheral Schematics

9 Peripheral Schematics
This is the typical application circuit of the module connected with peripheral components (for example,
power supply, antenna, reset button, JTAG interface, and UART interface).

U1
VDD33 39
P_GND GND VDD33
1 38
2 GND1 GND3 37 IO23 JP1
EN 3 3V3 IO23 36 IO22 1
SENSOR_VP 4 EN IO22 35 TXD0 2 1
SENSOR_VN 5 SENSOR_VP TXD0 34 RXD0 3 2
C1 C2 R1
IO34 6 SENSOR_VN RXD0 33 IO21 4 3
22uF 0.1uF TBD IO35 7 IO34 IO21 32 4
IO32 8 IO35 NC 31 IO19 UART
IO33 9 IO32 IO19 30 IO18
IO25 10 IO33 IO18 29 IO5 GND
C3 IO26 11 IO25 IO5 28
IO27 12 IO26 NC 27
TBD IO14 13 IO27 NC 26 IO4
IO12 14 IO14 IO4 25 IO0
15 IO12 IO0 24 IO2
GND GND IO13 16 GND2 IO2 23 IO15
17 IO13 IO15 22
NC NC

1
2
18 21 GND
19 NC NC 20

1
2
NC NC
ESP32-WROVER-E/ESP32-WROVER-IE JP2
GND Boot Option

JP3 SW1
IO14 TMS 1 R2 0R EN
IO12 TDI 2 1
IO13 TCK 3 2 C4 0.1uF
IO15 TDO 4 3
4
JTAG GND

IO12 should be kept low when the module is powered on.

Figure 10: Peripheral Schematics

• Soldering Pad 39 to the ground of the base board is not a must. If you choose to solder it, please apply
the correct amount of soldering paste. Too much soldering paste may increase the gap between the
module and the baseboard. As a result, the adhesion between other pins and the baseboard may be
poor.

• To ensure the power supply to the ESP32 chip during power-up, it is advised to add an RC delay circuit
at the EN pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 µF.
However, specific parameters should be adjusted based on the power-up timing of the module and the
power-up and reset sequence timing of the chip. For ESP32’s power-up and reset sequence timing
diagram, please refer to Section Power Scheme in ESP32 Datasheet.

• UART0 is used to download firmware and log output. When using the AT firmware, please note that the
UART GPIO is already configured (refer to Hardware Connection). It is recommended to use the default
configuration.
4 3 2

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10 Physical Dimensions

10 Physical Dimensions

10.1 Module Dimensions

Unit: mm

18±0.15 3.3±0.15
0.8
6.22

10.45
0.9
0.5
31.4±0.15

38 x Ø0.55
38 x 0.9
22.86

3.7
1.27

15.84
3.7

16.16
24.09

20.37

0.9
7.5

38 x 0.9
0.46
1.1

38 x 0.45 1.08 38 x 0.85

Top View Side View Bottom View

Figure 11: ESP32-WROVER-E Physical Dimensions

Unit: mm

18±0.15 3.3±0.15
0.8
6.22

2.25
10.45
0.9
0.5
31.4±0.15

38 x Ø0.55
38 x 0.9

23.05
22.86

3.7
1.27

15.84
3.7
16.16
24.09

20.37

0.9

7.5
38 x 0.9
0.46
1.1

38 x 0.45 1.08 38 x 0.85

Top View Side View Bottom View

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 38 x 0.45 1.08 38 x 0.85

10 Physical Dimensions
Top View Side View Bottom View

Unit: mm

18±0.15 3.3±0.15
0.8
6.22

2.25
10.45
0.9
0.5
31.4±0.15

38 x Ø0.55
38 x 0.9

23.05
22.86

3.7
1.27

15.84
3.7

16.16
24.09

20.37

0.9
7.5

38 x 0.9
0.46
1.1

38 x 0.45 1.08 38 x 0.85

Top View Side View Bottom View

Figure 12: ESP32-WROVER-IE Physical Dimensions

Note:
For information about tape, reel, and product marking, please refer to Espressif Module Packaging Information.

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10 Physical Dimensions

10.2 Dimensions of External Antenna Connector

ESP32-WROVER-IE uses the first generation external antenna connector as shown in Figure 13. This connector
is compatible with the following connectors:

• [Link] Series connector from Hirose

• MHF I connector from I-PEX

• AMC connector from Amphenol

Unit: mm

Figure 13: Dimensions of External Antenna Connector

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11 PCB Layout Recommendations

11 PCB Layout Recommendations

11.1 PCB Land Pattern

This section provides the following resources for your reference:

• Figures for recommended PCB land patterns with all the dimensions needed for PCB design. See Figure
14 Recommended PCB Land Pattern.

• Source files of recommended PCB land patterns to measure dimensions not covered in Figure 14. You
can view the source files for ESP32-WROVER-E and ESP32-WROVER-IE with Autodesk Viewer.

• 3D models of ESP32-WROVER-E and ESP32-WROVER-IE. Please make sure that you download the 3D
model file in .STEP format (beware that some browsers might add .txt).

Unit: mm
Via for thermal pad
Copper

18

7.44
6.22
38 x1.5 Antenna Area

1 38
0.9
0.5
38 x0.9

3.7

3.7
22.86

16.16

31.4
1.27

1.27

7.5
0.9
1.1

19 20
0.5
17.5

Figure 14: Recommended PCB Land Pattern

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11 PCB Layout Recommendations

11.2 Module Placement for PCB Design

If module-on-board design is adopted, attention should be paid while positioning the module on the base
board. The interference of the base board on the module’s antenna performance should be minimized.

For details about module placement for PCB design, please refer to ESP32 Hardware Design Guidelines >
Section Positioning a Module on a Base Board.

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12 Product Handling

12 Product Handling

12.1 Storage Conditions

The products sealed in moisture barrier bags (MBB) should be stored in a non-condensing atmospheric
environment of < 40 °C and 90%RH. The module is rated at the moisture sensitivity level (MSL) of 3.

After unpacking, the module must be soldered within 168 hours with the factory conditions 25 ± 5 °C and 60
%RH. If the above conditions are not met, the module needs to be baked.

12.2 Electrostatic Discharge (ESD)

• Human body model (HBM): ±2000 V
• Charged-device model (CDM): ±500 V

12.3 Reflow Profile

Solder the module in a single reflow.
Temperature (℃)

Peak Temp.
235 ~ 250 ℃
250
Preheating zone Reflow zone Cooling zone
150 ~ 200 ℃ 60 ~ 120 s 217 ℃ 60 ~ 90 s –1 ~ –5 ℃/s
217
200
Soldering time
> 30 s

Ramp-up zone
1 ~ 3 ℃/s
100

50

25
Time (sec.)
0
0 50 100 150 200 250

Ramp-up zone — Temp.: 25 ~ 150 ℃ Time: 60 ~ 90 s Ramp-up rate: 1 ~ 3 ℃/s

Preheating zone — Temp.: 150 ~ 200 ℃ Time: 60 ~ 120 s
Reflow zone — Temp.: >217 ℃ 60 ~ 90 s; Peak Temp.: 235 ~ 250 ℃ Time: 30 ~ 70 s
Cooling zone — Peak Temp. ~ 180 ℃ Ramp-down rate: –1 ~ –5 ℃/s
Solder — Sn-Ag-Cu (SAC305) lead-free solder alloy

Figure 15: Reflow Profile

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12 Product Handling

12.4 Ultrasonic Vibration

Avoid exposing Espressif modules to vibration from ultrasonic equipment, such as ultrasonic welders or
ultrasonic cleaners. This vibration may induce resonance in the in-module crystal and lead to its malfunction or
even failure. As a consequence, the module may stop working or its performance may deteriorate.

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13 Related Documentation and Resources

13 Related Documentation and Resources

Related Documentation
• ESP32 Series Datasheet – Specifications of the ESP32 hardware.
• ESP32 Technical Reference Manual – Detailed information on how to use the ESP32 memory and peripherals.
• ESP32 Hardware Design Guidelines – Guidelines on how to integrate the ESP32 into your hardware product.
• ESP32 ECO and Workarounds for Bugs – Correction of ESP32 design errors.
• ESP32 Series SoC Errata – Descriptions of errors in ESP32 series of SoCs from chip revision 0 forward.
• Certificates
[Link]
• ESP32 Product/Process Change Notifications (PCN)
[Link]
• ESP32 Advisories – Information on security, bugs, compatibility, component reliability.
[Link]
• Documentation Updates and Update Notification Subscription
[Link]

Developer Zone
• ESP-IDF Programming Guide for ESP32 – Extensive documentation for the ESP-IDF development framework.
• ESP-IDF and other development frameworks on GitHub.
[Link]
• ESP32 BBS Forum – Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions,
share knowledge, explore ideas, and help solve problems with fellow engineers.
[Link]
• The ESP Journal – Best Practices, Articles, and Notes from Espressif folks.
[Link]
• See the tabs SDKs and Demos, Apps, Tools, AT Firmware.
[Link]

Products
• ESP32 Series SoCs – Browse through all ESP32 SoCs.
[Link]
• ESP32 Series Modules – Browse through all ESP32-based modules.
[Link]
• ESP32 Series DevKits – Browse through all ESP32-based devkits.
[Link]
• ESP Product Selector – Find an Espressif hardware product suitable for your needs by comparing or applying filters.
[Link]

Contact Us
• See the tabs Sales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples
(Online stores), Become Our Supplier, Comments & Suggestions.
[Link]

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Revision History

Revision History

Date Version Release notes

• Improved the wording and structure of following sections:

– Updated Section ”Strapping Pins” and renamed to Boot Configura-
tions

2024-11-12 v2.0 – Added Chapter 5: Peripherals

– Updated Table ”Wi-Fi RF Standards” and renamed to Wi-Fi RF Char-
acteristics
– Section 9: Peripheral Schematics: Added a note about UART

• Table 1: Series Comparison: Added information about flash

• Figure 9: Peripheral Schematics: Updated the note about soldering
2023-11-21 v1.9 • Section 10.2: Dimensions of External Antenna Connector: Added infor-
mation about the antenna external connector

• Major updates:
– Removed contents about hall sensor according to PCN20221202

2023-02-09 v1.8 • Other updates:

– Added source files of PCB land patterns and 3D models of the mod-
ules (if available) in Section 11.1: PCB Land Pattern

2022-12-02 v1.7 Updated Figure 10.1: Module Dimensions and 11.1: PCB Land Pattern

• Added module variants embedded with ESP32-D0WDR2-V3 chip

• Added Table 1: ESP32-WROVER-E Series Comparison and Table 2:
ESP32-WROVER-IE Series Comparison

2022-07-20 v1.6 • Added Figure 6: Visualization of Timing Parameters for the Strapping Pins
and Table 5: Description of Timing Parameters for the Strapping Pins in
Section 4: Boot Configurations
• Updated Related Documentation and Resources

• Replaced Espressif Product Ordering Information with ESP Product

Selector
• Updated the description of TWAI in Section 1.1 Features

2022-02-22 v1.5 • Added a link to RF certificates in Section 1.1 Features

• Updated Ordering Information Table
• Updated Table 12: Absolute Maximum Ratings
• Fixed typos

• Updated Figure 11: ESP32-WROVER-E Physical Dimensions

2021-02-09 v1.4 • Updated Figure 14: Recommended PCB Land Pattern

Espressif Systems 47 ESP32-WROVER-E & ESP32-WROVER-IE Datasheet v2.0

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Revision History

Date Version Release notes

• Updated the trade mark from TWAI™ to TWAI®

• Deleted Reset Circuit and Discharge Circuit for VDD33 Rail in Section 9:
2021-02-02 v1.3 Peripheral Schematics
• Modified the note below Figure 15: Reflow Profile

• Updated Figure 3.1: Pin Layout

2020-11-02 v1.2 • Added a note to EPAD in Section 11.1: PCB Land Pattern
• Updated the note to RC delay circuit in Section 9: Peripheral Schematics

• Updated the following figures:

– Figure 1: ESP32-WROVER-E Block Diagram (with ESP32-D0WD-V3

2020-06-11 v1.1 embedded)

– Figure 2: ESP32-WROVER-E Block Diagram (with ESP32-D0WDR2-
V3 embedded)

2020-05-22 v1.0 Official release

Espressif Systems 48 ESP32-WROVER-E & ESP32-WROVER-IE Datasheet v2.0

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