Module 2
PREPARATION OF SINGLE CRYSTAL
SILICON
GROWTH OF SILICON CRYSTAL
For the fabrication of devices and chips,
extremely high purity single crystal silicon is
required. This level of purity can be
achieved through a series of purification
steps. Thus the silicon obtained from
quartzite in a series of purification steps,
obtaining first metallurgical grade, then
electronic grade and finally single crystal
silicon. The fine slices when cut from this
single crystal silicon ingot or rod are called
wafers.
Preparation of Metallurgical Grade
Silicon
Metallurgical grade silicon is obtained by reduction
of quartzite in a carbon-arc furnace, which
comprises of coal, coke and wood chips and the
reaction that takes place is as under :
2 C (s) + 2 SiO2 (s) = Si (I) + SiO (g) + 3 CO (g).
where s, I, g represents the solid, liquid and gaseous
state respectively.
A condensed silicon oxide (SiO) layer forms at the
top end of the molten SiO in the furnace, which
prevents entry of further oxygen into the furnace.
Schematic of MGS Preparation
The temperature of the upper part of the
furnace is around 1600oC and that at lower
half is 1780oC where silicon is formed. The
liquid silicon is tapped off from the bottom
of the furnace and solidified to yield MGS.
This MGS contain impurities like iron,
aluminium and mainly carbon and thus the
level of purity becomes 98%.
Preparation of Electronic Grade Silicon
The MGS can be converted into electronic grade
silicon (EGS) by distillation process to make the
level of purity 99.99 %. In this process the
powdered MGS is treated with anhydrous HCL in
a fluidized bed in the presence of a catalyst to
form SiHCl3 (trichlorosilane) at a temperature of
300oC and the overall reaction is :
Si(s) + 3 HCl (g) → SiHCl3 + H2 (g).
The unwanted impurities are removed in the form
of their chlorides from SiHCl3 through fractional
distillation process.
Finally the so called pure SiHCl3 is reduced in a
reactor and the reaction that takes place is :
SiHCl3 + H2 (g) → Si (s) + 3 HCl (g).
In the reactor the EGS forms as a polycrystalline
deposit (polysilicon) on the slim rod.
The alternative and cheaper process to form
EGS is decomposition of silane in a chemical vapor
deposition (CVD) reactor but safety hazards
associated with the handling of silane limit its use.
CRYSTAL GROWTH
Crystal growth is one of the major step to
obtain defect free single crystal silicon
from polysilicon rods. To understand
properly about a crystal one should know
some of the terms related to crystal
growth technology, such as :
Crystal Structure
A crystal may be a single crystal or may be
polycrystalline/ amorphous in nature. In a
single crystal the spacing between the
atoms are regular and this regularity is
substantially maintained over the entire
volume of the crystal so as to produce a
well defined planes as crystal faces.
On the other hand in a polycrystalline solid,
this regularity is maintained over limited
portions of the crystal; each such regular
region within the solid is called a grain.
Both silicon and GaAs belong to the cubic
class of crystals and exhibit the following
structures:
1. Simple Cubic : Polonium exhibits this structure
over a narrow range of temperature and which is
illustrated in Fig.1.
2. Body-Centered Cubic: Molybdenum tantalum,
and tungsten exhibit this crystal structure, which
is illustrated in fig.2.
3.Face-Centered Cubic : Most of the elements in the
periodic table like copper, gold, nickel, silver,
platinum, etc., exhibits this structure. This is
illustrated in fig.3
Cubic Crystal Lattice
4. Sphalerite or Zincblende structure :This
structure consists of two interpenetrating
face centered cubic sublattices, with one
atom of the second sublattice located at one
fourth of the distance along a major
diagonal of the first lattice. This
configuration is illustrated in fig.4 and 5,
where solid circles belong to the first
sublattice and open circles belong to the
second. Materials like silicon and diamond
belongs to this class.
Zincblende lattics
Growth of Single Crystal Silicon
Single crystal can be grown by controlled
freezing of a melt in a boat or ampoule. At
the same time problem of adherence of
the freezing melt with wall of the boat
results dislocation.
Czochralski (CZ) and float zone (FZ) are the
alternative techniques by which the crystal
can be grown with a free surface and thus
the above problem can be overcome.
Czochralski Method
The process starts with a large graphite
crucible into which electronic grade silicon
rods are broken and melted and kept in a
molten condition by heating.
A seed crystal, suitably oriented, is
suspended over the crucible in a chuck so
that it just touches the melt. Some of the
melt solidifies onto the seed crystal,
forming a larger crystal.
Fig.1 Arrangement for Czochralski method of
crystal grow
The seed crystal is slowly pulled upward so that it
should not detach from the surface of the liquid.
Eventually, most of the melt has condensed and a
very large bologna-shaped boule of single crystal
with several feet length and depending on pull rate
a variable diameter up to 6 inch can form.
The figure 1 shows the required arrangement for
the Czochralski method for growing single crystal
silicon.
The entire assembly is enclosed within a close
chamber which is water cooled and flushed with
an inert gas. A pull rate of about 50 – 100 mm/hr. is
typical for both silicon and GaAs. Also crystal
rotates along with the pull rod to grow an uniform
cylindrical single crystal rod/cylinder and rotation
of crucible ensures uniform mixing of the material
in the melt.
Either a trivalent or a pentavalent impurity can add
with the melt to convert the grown single crystal
into a p-type or an n-type.
Since silicon is a shallow donor and oxygen is
a deep donor thus fused silica can not be
used for the growth of GaAs. Materials like
graphite, graphite coated with pyrolytic
graphite, alumina etc., can be used as a
crucible for the GaAs melt.
Microscopically, the heat transfer conditions
about the interface of the melt and solidified
grown crystal can be modeled by the following
equation;
dm dT dT
L — + kl — A1 = ks — A2 (1)
dt dx1 dx2
where L is the latent heat of fusion, dm/dt is the
mass solidification rate, T is the temperature of
the melt, kl and ks are the thermal conductivities
of the liquid and solid
dT/dx1 and dT/dx2 are the thermal gradients at the
interface in the liquid and solid. Respectively, and
A1 and A2 are the areas of the isotherms at the
interface.
From equation (1) the maximum pull rate of
a crystal under the condition of zero thermal
gradient in the melt can be deduced as;
ks dT
vrms = — — (2)
Ld dx
where vmax is the maximum pull rate and d is the
density of solid silicon.
The pull rate influences the incorporation of
impurities into the crystal and is a factor for
defect generation. Also slow pull rates cause
re-melting of the silicon crystal and fast pull
rate is though economical but cause
solidification without single crystal
formation.
Pull rate also controls the diameter of the
grown solid single crystal and generally pull
rate varies inversely with the diameter.
Float Zone Technique
It is also called gradient freeze method. In this
method the starting polycrystalline material is
loaded into a long, horizontal boat, which is
melted and a seed crystal of the material is placed
at the narrow end to establish a specific
crystallographic orientation.
The melt is then cooled from one end, which is
usually necked down in order to restrict
nucleation to a single event during freezing. This
allows a single grain to propagate at the liquid-
solid interface and the frozen melt crystallizes to
form the single crystal.
Fig.2(a) Gradient Freeze system
One way to gradient freeze technique is such
where the boat or ampoule can move horizontally
through the furnace from high temperature zone
to low temperature, which is known as horizontal
gradient freeze (HGF) and demonstrated in fig 2(a).
On the other hand in the second way the boat or
ampoule moves vertically through the furnace
from high temperature zone to its low
temperature zone and called vertical gradient
freeze (VGF), as shown in fig.2(b).
Fig. 2(b) Arrangement for vertical gradient freeze
In the HGF process, the GaAs boat is placed
inside a sealed quartz ampoule of 50 – 100 cm.
long and about 75 mm wide. High purity arsenic
(99.99999%) is placed at one end of the ampoule.
During the growth a temperature profile is set in
such a way that the GaAs charge is in a molten
state, at 1241oC, and the arsenic is at 617oC.
With a heater travels across the ampoule at 15 –
20 mm/hr. maintains a temperature gradient of
10oC/cm and a pressure of 1 atmosphere is
maintained throughout the growth.
Either the furnace is moved or r.f. coil around
the furnace is moved very slowly to establish
a molten interface between the seed and the
charge and also to grow a single crystal of
GaAs.
In HGF technique a hot wall furnace with a
vertical temperature gradient of ± 0.5oC is
maintained and because of the gravitational effect
a liquid encapsulation can also be used. Here the
bottom of the crucible tapered to hold the seed
crystal. The ampoule is placed within a
microprocessor controlled adjustable temperature
gradient furnace having multiple heater windings.
Lower radial and axial thermal gradients in VGF
system reduces the dislocation content in the
grown crystal.
The ampoule is placed within a
microprocessor controlled adjustable
temperature gradient furnace having
multiple heater windings. Lower radial and
axial thermal gradients in VGF system
reduces the dislocation content in the grown
crystal.
Lower radial and axial thermal gradients in
VGF system reduces the dislocation content
in the grown crystal.
The boat or ampoule used in this method must be
of high purity to prevent crystal contamination
and at the same time the boat should not touch
the growing crystal at any point, since at point of
adhesion between the boat and the melt twinning
can be nucleated.
Also at each time after the formation of
the solid single crystal, it is to be taken out
by breaking the sealed ampoule, which is a
very costly affair.
Here the bottom of the crucible tapered to
hold the seed crystal.
The ampoule is placed within a
microprocessor controlled adjustable
temperature gradient furnace having
multiple heater windings.
Lower radial and axial thermal gradients
in VGF system reduces the dislocation
content in the grown crystal.
WAFER PREPARATION
The ingots or boules obtained from CZ or FZ
process are shaped into wafers in a series
of mechanical processes which follows
chemical etching and polishing to produce
a wafer of mirror finished surface.
Removal of ends of the boule
The tang and seed ends of the crystal are
cut off by using a high speed saw and some
lubricating oil is used to reduce the friction
between the crystal and the saw during
cut. The removed portions of the crystal
are usually recycled as EGS.
Surface Grinding
Temperature variation during crystal growth
causes a variation in the growth rate and
which ultimately affects the diameter of
the grown crystal. For this reason
purposely the boules are grown 15 to 20 %
more in diameter than the required and
then ground down to precise diameter by
using a rotating diamond grinding tool.
Finally X-ray diffraction technique is used
to verify the surface orientation.
Flats
Wafer flats are incorporated for proper
cleavage during dicing and for alignment
purposes. The larger flat is the primary
flats, lying along a particular
crystallographic direction, such that these
directions and their equivalents form an
orthogonal set on the wafer surface. The
secondary flat helps to code the wafer in
terms of its crystal surface orientation and
dopant type.
Flats on Silicon wafer
By using a scriber, rectangular shaped chips
can be separated from a wafer and for that
the scriber can move over the wafer either in
the direction of parallel to the flat or in the
direction which is perpendicular to the flat.
Wafer slicing
A high speed stainless steel saw having
diamond edge is used to slice down the
grown crystal to form wafers. As
mentioned earlier lubricating oil is used to
reduce high friction between the crystal
and the saw but still about 30 to 40% of
the material loss takes place during
cutting.
Edge Contouring
In this, the wafer is rotated against a concave
diamond tool resulting in a rounding off of
the edge of the wafer. It helps in the
smooth deposition of photoresist and also
prevents subsequent chipping of edges.
Now the wafer is ready for lapping or
polishing.
Schematic of Edge Contouring Process
Lapping
The sliced wafer should have uniform
thickness throughout and for that both
surfaces are lapped. A slurry (colloidal
suspension) containing the mixture of
carborandum powder, Al2O3 and water is
prepared and putting it on a hard plate or a
pad of the lapping machine the silicon
wafer is rubbed very slowly over it till the
required thickness is reached.
Schematic of Polishing Process
Very fast rubbing and at the same time
putting large pressure on the wafer may create lot
of damages on the surface of the wafer and even
the wafer may get crack. Polishing rate and surface
finish are a complex function of pressure, pad
properties, rotation speed, slurry composition and
pH.
Thus to reduce the surface roughness 90% of
the total thickness reduction can be done by
mechanical lapping and remaining 10% is done by
using chemical thinning, which gives a polished
mirror finished wafer.
