Freewheeling Diode Reverse Recovery Failure Modes in IGBT

Applications
M.T. Rahimo and N.Y.A Shammas

Institute of Electrical and Electronics Engineers, March/April 2001

Copyright © [2001] IEEE. Reprinted from the IEEE Transactions on Industry

Applications, vol. 37.

This material is posted here with permission of the IEEE. Such permission of the
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ABB Switzerland Ltd. Freewheeling Diode Reverse Recovery Failure Modes in IGBT Applications

Freewheeling Diode Reverse Recovery Failure Modes

in IGBT Applications
M.T. Rahimo and N.Y.A Shammas

Abstract- In this paper, reverse recovery failure modes One of the most common and catastrophic failure modes in
in modern fast power diodes are investigated. By the aid fast diodes is due to diode snappy recovery. Previous work
of semiconductor device simulation tools, a better view have shown that under adverse combinations of high
is obtained for the physical process, and operating commutating di/dt, large circuit stray inductance, low
conditions at which both diode snappy recovery and forward current and low junction temperature, it is likely
dynamic avalanching occur during the recovery period that all fast power diodes produce excessive voltage spikes
in modern high frequency power electronic due to snappy recovery [1]. This in turn can destroy the
applications. The work presented here confirms that the diode and ultimately cause a circuit failure due to excessive
reverse recovery process can by expressed by means of inrush duty in the recovery period. Experimental results are
diode capacitive effects which influence the reverse shown comparing a desirable soft recovery performance in
recovery characteristics. The paper also shows that the figure (1-a) to snappy recovery in figure (1-b).
control of the carrier gradient and the remaining stored Snappy recovery of fast power PIN diodes has been
charge in the drift region during the recovery phase investigated over the years [2]. These studies have shown
influence both failure modes and determine if the diode that the depletion of the remaining stored charge during the
exhibits a soft, snappy or dynamic avalanche recovery recovery period results in a current discontinuity (chop-off).
characteristics. This produces a very high dir/dt and hence a large voltage
overshoot which may result in the destruction of the device.
I. INTRODUCTION The second type of failure mode, termed as reverse
THE RISE of the converter frequency in power electronics recovery dynamic avalanching occurs at high di/dt
requires fast power semiconductor devices with low switching speeds. Normally, the process itself is safe if the
switching losses during the transient periods. Today, Mos- device does not exhibit any non-uniformaties in the
Bipolar Transistors such as the (IGBT) present interesting recovery current. However, dynamic avalanching can
characteristics combining both MOS and bipolar structures result in the generation of a hot spot in the silicon die due
to achieve a voltage driven device with low on-state losses, to non-uniform current crowding leading to the distruction
low switching losses and a high current density capability. of the device as shown in figure (1-c). The causes of these
These devices are increasingly used in many modern hot spots can range from process to material variations in a
converter applications, but their optimum performances are single diode silicon chip. To prevent this failure mode,
often restricted by the freewheeling diode reverse recovery certain design/process consideration must be taken into
characteristics. account to minimise the effects of any current non-
The freewheeling diode has always been said to be the uniformaties.
weak component in many applications because it reduces
the switching speed of the IGBT during the turn-on
transient period. The main two reverse recovery failure
modes in diodes operating under high stress condition are
Current
1- Snappy Recovery.
2- Reverse Recovery Dynamic Avalanche.
Voltage

(a) soft recovery

Voltage
Current

Voltage Spike

(b) snappy recovery

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-d +d
X

n e (x)
Voltage
Hole density
Voltage Collapse t0
Current
t1

t2
t3
(c) dynamic Avalanche t4
t5
Fig. 1 Reverse recovery waveforms for a fast diode, (a) soft P+ Space charge N- N+
recovery, (b) snappy recovery and (c) dynamic avalanching. (b) Excess carrier distribution during reverse recovery.
These diode failure modes can destroy the IGBT and
ultimately cause a circuit failure due to excessive inrush Fig. 3 Reverse Recovery Characteristics (a) with the
duty in the recovery period as shown in figure (2). The associated excess minority carrier distributions (b).
purpose of this investigation is to gain a better During Forward Conduction FC, the diode conducts a
understanding of the physical process, and causes of these constant steady state forward current IF, and a fixed
failure modes in modern fast power diodes. forward voltage drop Vf appears across the diode.
An increase in the diode current will lead to an increase in
IGBT Short Circuit Overcurrent Failure the number of excess minority carriers associated with a
Vce larger conductivity modulation in the drift region. The
Ic current flows only due to recombination and generation
processes where the total stored charge in the drift region is
dir /dt
a function of the current density, carrier lifetime, junction
temperature and carrier injection efficiency. The excess
Diode Reverse Recovery Failure minority carrier distribution in the drift region [3] is given
as
di/dt

I F ta cosh(x /La ) sinh(x /La )

ne ( x ) = [ -B ] (1)
Fig. 2 Freewheeling diode reverse recovery failure during 2 qAeff La sinh(d/La ) cosh(d/La )
IGBT turn-on.
where the boundary conditions are given as
II. DIODE REVERSE RECOVERY PROCESS
Figure (3-a) shows typical diode current and voltage
( -d + - £ x£d - + .) (2)
waveforms during reverse recovery, while figure (3-b) p n n n
shows the associated excess minority carrier distribution
(hole density) and space charge spreading in the drift La is the ambipolar diffusion coefficient, ta is the
region during reverse recovery. ambipolar lifetime value, B is the hole to electron mobility
ratio (B»3) and (d=WB / 2) where WB is the drift region
IF total thickness.
When the diode is subjected to a reverse voltage VR at
time t = t0 , a certain reverse recovery transient period elapses
t0 t1 t2 t3 t4 t5 before the diode can reach its full Reverse Blocking RB
Current
dv/dt state. This period can be divided into five phases :
di/dt dir /dt Voltage
Phase 1 (Commutating Phase): This phase begins with the
VR application of the reverse voltage VR at t = t0 . The current
drops at a rate di/dt until it reaches the zero crossing point
at t = t1 . This phase is fully dependent on the circuit
Ipr Vpr components, where the commutating di/dt is mainly a
FC Ph1 Ph2 Ph3 Ph4 Ph5 RB
function of the reverse voltage, circuit inductance and the
(a) Diode reverse recovery voltage and current waveforms. IGBT gate circuit components.

Phase 2 (Storage Phase): This phase starts after t = t1 as

the current turns negative. The phase ends at t = t2 when
+ -
the total excess carrier concentration at the p n junction is
reduced to zero.

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Phase 3 (Voltage build-up Phase): This phase marks the dQ Q( t )

= - i( t ) - (6)
start of the recovery period at which the depletion region
+ - dt t eff
starts to form across the p n junction sweeping out the
remaining excess carriers from the drift region. The voltage
across the diode will increase at a rate dv/dt as the which illustrates that the rate of change of the stored
depletion region widens, until it reaches the value of the charge dQ/dt is due to internal recombination and the
applied voltage VR at t = t 3 . Hence at that point di/dt=0 charge being swept out of the drift region due to the reverse
and the diode current reaches its peak value Ipr. recovery current. The swept out charge during the storage
phase is also known as the storage charge.
Phase 4 (Inductive Phase): This phase starts when the
recovery current begins to fall from its peak value Ipr, ii) Phase 3 and Phase 4 ( Capacitive Effects)
+ -
while the voltage continues to increase until it reaches the When the total excess carrier concentration at the p n
peak value Vpr at t = t4 . junction is reduced to zero, the depletion region starts to
Phase 5 (Recovery Phase): The final phase starts when the form sweeping out the remaining excess carriers from the
voltage begins to fall reaching its steady state reverse drift region. The voltage across the diode will begin to
blocking value at t = t5 , while the current continues to drop build up at a rate dv/dt as the depletion region widens. At
to its leakage level. The failure modes under investigation this point, two dominant charge storage effects control the
normally occur during this phase and are mainly dependent reverse recovery characteristics. The first effect takes place
- +
on the remaining excess carriers near the n n junction. In as the voltage across the diode increase, associated with an
the following sections, a detailed analysis of each phase is increase in the depletion region width Wd. This implies a
presented change in the charge within the depletion layer to balance
the change in the junction voltage. The magnitude of the
i) Phase 1 and Phase 2 (Storage Period) total charge on either side of the junction is the depletion
By assuming an ideal switch the diode current drops at a layer charge Qd, which is associated with the junction
rate (-di/dt) at the start of the reverse recovery period where capacitance C j where

di VR dQd
=- (3) Cj = (7)
dt Lc dV

therefore the diode current can be given as the current flowing through this capacitor is called the
displacement current id ( t )
i ( t ) = I F - ( V R Lc )t (4)
* dV
id ( t ) = C j (8)
The inductance Lc supports the full reverse voltage, while dt
the diode voltage drop will maintain the same value Vf as
long as there is a sufficient stored charge at the junction. assuming an average constant value for the junction
*
The diode current also stays positive as long as capacitance C j * for simplicity. The second effect is the
I F > ( V R Lc )t reaching its zero crossing point at t = t1 . stored charge Q(t) left in the bulk of the drift region after
At the start of phase 2, the current becomes negative when t = t2 . This charge effect is reduced during the recovery
I F < ( V R Lc )t but continues to drop at the same rate. The period either by recombination Qr ( t ) or by a drift current
diode voltage drop falls slightly from its normal value, and i D ( t ) due to the large electric field build up as the
the voltage remains supported by the circuit inductance depletion layer penetrates deeper into the drift region. The
until t = t 2 when the excess carriers near the junction edge charge associated with this current can be termed as the
are reduced to their equilibrium values. The rate of drift charge QD ( t ) where
reduction in carrier density (-dn/dt) is described by the
continuity equation. The time during this phase is known Q( t ) = Qr ( t ) + QD ( t ) (9)
as the storage period t s = t 2 - t1 where
where
i( t s ) » ( V R Lc )t s (5)
QD ( t ) = C D v ( t ) (10)
The storage time is dependent on both external operating
parameters and diode structure. The reduction of the stored
CD is termed as the drift capacitance because the reduction
charge during phase 1 and 2 can be described by the charge
in charge is due to a drift current and can also be given as
control equation.

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dQD
CD = (11) Rc Lc
dV diode model
Snap
The total recovery current flowing through the diode is

i R ( t ) = id ( t ) + i D ( t ) (12) VR v(t) g
D
CD C j
therefore the charge control equation can be given as

dQ Q( t )
= -i R ( t ) - (13)
dt t eff Fig. 4 Diode dynamic model in an RLC circuit.

hence At the beginning of phase 3, the current rate of change

becomes both circuit and device dependent and is termed
dQ dv Q( t ) dir/dt in the following analysis. By applying KVL we
*
= -i D ( t ) + C j - (14) obtain
dt dt t eff
dir
v ( t ) = V R - Lc - Rci R ( t ) (18)
From equation (10), and assuming CD ( t ) as a time dt
dependent variable, we can write:
therefore
dQD dv d dQD dir V R - v ( t ) - Rc i R ( t )
iD ( t ) = = CD + ( )v ( t ) (15) = (19)
dt dt dt dv dt Lc

where
When ( v ( t3 ) - i R ( t 3 ) Rc = V R ), the diode current reaches
its maximum peak value Ipr at t = t3 and (dir/dt=0). Also
dv
i D ( t ) = CD + g D ( t )v ( t ) (16) by rearranging (17), dv/dt can be given as
dt
dv iR ( t ) - g D v( t )
g D ( t ) represents a time dependent conductance for the = (20)
*
diode during recovery, where it can also be expressed as dt C j + CD
dCD / dt , therefore the total recovery current can be given
as At the start of Phase 4, dir/dt becomes positive. This
induces a positive voltage across the circuit inductance
dv which adds to the applied reverse voltage. Thus the diode
i R ( t ) = ( C j* + C D ) + g D ( t )v ( t ) (17) voltage continues to increase where
dt
dir
This equation describes the variation of the diode recovery v ( t ) = V R + Lc - Rc i R ( t ) (21)
current in which the diode can be represented by a dt
conductance g D ( t ) in parallel with two capacitors C D and
*
C j * as shown in figure (4) for a typical reverse recovery By differentiating (16) and (21) and by replacing dir/dt and
RLC circuit. From this diode model and circuit, equations dv/dt by their equivalents in (19) and (20), second order
governing the diode current and voltage characteristics differential equations for both the diode recovery current
during reverse recovery can be derived. and voltage can be obtained by assuming constant values
for both CD and g D

d 2v Rc (CT )+ g D Lc dv 1 + Rc VR
+ + v (t )= (22)
dt 2 Lc(CT ) dt Lc(CT ) Lc(CT )

and

d 2ir Rc(CT )+ gD Lc dir 1 + Rg D g V

2
+ + iR (t)= D R (23)
dt Lc(CT ) dt Lc(CT ) Lc(CT )

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this occurs prior to the diode normal inductive overshoot

* voltage. In this case, C D =0, which can be approximated to
where CT = Cj + CD . *
an ideal undamped case z » 0, and the junction
* capacitance become the dominate parameter in the recovery
Therefore, the average damping ratio z * for the system
characteristics
was found to be equal to
*
* ( CT ) + g D Lc 1 Cj
z = (24) zj = (27)
2 Lc ( CT )( 1 + g D ) 2 Lc

Thus, the value of the damping factor can become an *

Since C j * has a very small value compared to CD (see
indicator of for the type of recovery the diode exhibits in below), a large dv/dt is required to maintain the value of
the following phase. Phase 4 ends when the voltage reaches the reverse recovery current. A large dv/dt cannot be
its maximum value Vpr at the maximum dir/dt where sustained constantly and therefore a rapid decrease in the
recovery current occurs. The current appears to chop-off
dir producing a large dir/dt, and subsequently a large
V pr = V R + Lc (25) Lc ( dir / dt ) voltage spike across the diode. Experimental
dt MAX results presented in figure (6-a) shows soft recovery
characteristics for the diode tested for a low di/dt and low
iii) Phase 5 and Failure Modes reverse voltage, while figure (6-b) shows snappy recovery
The transient behavior in the final phase can be explained at a larger reverse voltage and higher di/dt.
using the damping ratio given in equation (24). Three types
of recovery can normally be distinguished dependent on the
device and operating conditions as shown in figure (5).

Current

c Voltage

b
(a) Soft Recovery (100 nsec/div, 5 A/div, 50 V/div).

a
Current
Fig. 5 Diode current waveforms showing three types of
recovery (a) Soft, (b) Oscillatory and (c) Snappy.
Voltage

(a) If the drift region contains a sufficient amount of

carriers, then CD >> C*j *, and g D < 1. The drift capacitance
*
dominates the recovery characteristics and z *³1. A soft (b) Snappy Recovery (100 nsec/div, 10 A/div, 300 V/div).
recovery current tail is produced and the current decays Fig. 6 Reverse recovery experimental results for a fast
*
with a low dir/dt, and z * can be approximated as recovery diode, (a) Soft recovery and (b) Snappy recovery.

* 1 CD From the experimental results shown in figure (6), figure

z » (26)
2 Lc (7) shows expanded diode voltage and current waveforms
during the diode recovery phase. In order to confirm the
previous analysis, the reverse recovery charge Qrr which
(b) If the number of carriers is relatively small at the peak represents the stored charge being swept out of the drift
recovery voltage, then the recovery current will region during the recovery period ( t r ) is calculated by
subsequently fall rapidly causing an oscillatory recovery integrating the recovery current over the recovery period.
waveform. This tends to occur in the underdamped case, By differentiating the charge with respect to voltage, where
*
where 0< z *<<1 for low values for CD . both are functions of time, a curve for CD is plotted as
(c) If the voltage reaches a certain critical value during shown in figure (7) for both the soft and snappy recovery
phase 4 causing a rapid reduction in minority carrier waveforms. Also measurements of the steady state junction
concentration, the diode then becomes snappy. Normally,

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*
capacitance C j * for the diode have been obtained using an remaining carriers during the recovery phase. Snappy
LCR meter. These measurements were in good agreement recovery is in fact dependent on all circuit and diode design
*
with the calculated values for the average C j * of an abrupt parameters as presented in the block diagram shown in
junction figure (8).
These parameters provide different mechanisms which
* 1 affect the amount and position of the rest charge left at the
Cj = ò
C j ( v )dv (28)
end of the storage phase. This in turn influences the
V2 - V1
recovery dir/dt as shown from the previous analysis and
subsequently determine the value of the inductive voltage
where V1 and V2 are the limits over which the voltage overshoot. By exceeding a critical value (Vc), snappy
*
across the diode varies. A curve for C j * is also plotted in recovery occurs causing the diode to produce destructive
figure (7) to compare both capacitive effects during diode voltage spikes.
recovery. For simplicity, the effect of approximating the In order to study the effects of both device and operating
junction capacitance to an average value was found to be condition parameters, it is necessary to outline the
negligible. Also CD can be treated as a constant before the principles of the minority carrier distribution profile and its
voltage starts to increase and the charge begins to drop. effect on the reverse recovery behavior.
Normally for the soft recovery case, CD would dominate From figure (3-b) and equation (1), we can determine the
the recovery characteristics having a larger value. excess carrier concentration at each end as
Eventually for the snappy case, the charge disappears as the
voltage reaches the critical value. Therefore, CD drops I F ta
rapidly to zero, and the only capacitance left is junction ne(- d) p +n -
= coth(d/La )+ B tanh(d/La ) (29)
* 2 qAL a
capacitance C j * having a very low value around 100pF
compared to CD having a value of 10nF before snap-off . also

C/pF I F ta
100000 ne(+ d) n -n + = coth(d/La )- B tanh(d/La ) (30)
Voltage 2 qAL a
CD
10000
Diode Snappy Recovery
dv/dt=1500V/us 1000
Diode Structure External
Cj Parameters Parameters
100
Current

10 Lifetime Effective Doping Junction Forward Commutating

Area Profile Temperature Current di/dt
(a) Soft recovery (100nsec/div, 250V/div, 5A/div).
Uniform Profiled N+ N- P+ Circuit Reverse IGBT
Cathode Base Anode Inductance Voltage Turn-on
C/pF
100000
Fig. 8 Diode and circuit parameters effecting snappy
Voltage
recovery.
Snap-off 10000
Current CD
The asymmetrical carrier distribution arises because of the
1000 unequal values of the electron and hole mobilities. Also the
dv/dt=144000V/us
reduction in the minority carrier concentration near the
+ -
Cj 100 p n junction is more rapid when compared to the other
end. A ratio K for the excess carrier concentration at each
10 junction can be defined as
(b) Snappy recovery (100nsec/div, 250V/div, 5A/div).
*
Fig. 7 Current, Voltage, CD and C j * waveforms during -
ne ( pn ) ne ( - d )
the recovery phase, soft recovery (a), snappy recovery (b). K= = (31)
- +
ne ( n n ) ne ( + d )
III. CAUSES OF SNAPPINESS IN DIODES
Power semiconductor device design rules have always been The gradient of the excess carrier concentration is
aimed at achieving the optimum trade-off curves between approximated as
the on-state losses, switching losses and the required
blocking capability. However, snappy recovery forces an dne ne ( - d ) - ne ( + d )
added requirement in the design of fast power diodes in = (32)
order to achieve soft recovery characteristics. The main dx WB
goal is to prevent the sudden disappearance of the

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3
Therefore the excess carrier concentration profile plays the 1E+19
Impurity Concentration /cm

main role in determining the shape of the reverse recovery 1E+18

Lc Rc

IF Diode Model
characteristics [3]. In addition, the critical voltage Vc is a 1E+17
VF P+

function of the drift region parameters and the excess VR

N-

1E+16
carrier profile. This is due to their influence on the N+

1E+15
depletion layer spreading during reverse recovery. Transient Circuit Model

Two different mechanism are observed by which the 1E+14

depletion layer removes the excess carriers from the drift 1E+13

region 1E+12
P+ N- N+
1E+11
1) One Sided Penetration of the depletion layer removing 0 10 20 30 40 50 60
x(um)
70 80 90 100 110

the excess carriers from one end if (K<1) or (K=1 for a Fig. 9 Doping profile for the p + n - n + diode model including
large excess carrier concentration). the transient circuit diagram.
2) Two sided Penetration of the depletion layer removing
the excess carriers from both ends (K>1) or (K=1 for a For the diode model, a reference set of parameters were
shallow excess carrier concentration). chosen. The P+ emitter doping level at the anode contact is
(5´1016/cm3). A gaussian function was selected to set the
For a one sided penetration, normally the critical voltage is + -
diffusion pattern for the layer with a p n junction depth of
approximated to the static punch-through voltage for a PIN 10mm. The drift region had a thickness of 90mm and a
structure, which is mainly dependent on the drift region doping level of (1´1014/cm3). These values were chosen to
thickness and doping level. However, under dynamic achieve a blocking voltage of 1200V and a punch through
conditions, an excess carrier profile with (K<1) tends to voltage of 650V. The N+ layer at the cathode contact had a
slow down the spreading of the depletion layer. This constant doping level of (5´1018/cm3) with a thickness of
increases the punch-through voltage results in soft recovery 10mm. The minority carrier lifetime in the drift region was
characteristics unless the inductive overshoot is still large given a value of 200nsec and the effective area of the diode
enough due to higher di/dts or larger stray inductances. was set at 0.5cm2.
This type of profile can be achieved using lower emitter The transient simulation were carried out at a junction
efficiency [4] or profiled lifetime control techniques [5] temperature of 300K using a ramp RL circuit model. The
both of which have an added advantage in reducing the circuit inductance Lc was given a value of 0.5mH, while Rc
reverse recovery charge. The value of the punch - through had a value of 0.1W. The diode conducted a forward
voltage can also be increased by increasing the drift region current of 20A which is then ramped by the application of a
thickness or doping concentration [6]. Other novel reverse voltage of 150V. The commutating di/dt is only
techniques include the use of buffer layers or deep diffused controlled via the circuit inductance and supply voltage,
N+ layers [7]. therefore di/dt is equal to 300A/msec. This circuit model is
For a two sided penetration, the critical value is reduced adequate for investigating the diode reverse recovery
below the static punch-through voltage and the diode characteristics. However, it is important to note that in an
exhibits a snappy behavior. This normally happens at low IGBT converter circuit, di/dt is also influenced by the
current densities, low temperatures, low uniform lifetime IGBT gate circuit components. This indicates that the
values and using high injection efficiency emitters. reverse recovery process experience lower voltages during
Simulation runs were performed to show the effect of the the storage phase than those in the recovery phase. This
excess carrier concentration profiles resulting from varying would lead to softer recovery characteristics for the diode
different parameters in the diode structure on the reverse when compared to the ideal switch case with the same
recovery performance. applied reverse voltage. Therefore the RL ramp circuit
model would provide us with the worst case for our purpose
IV. DIODE SIMULATION MODEL of investigation.
To analyse the diode reverse recovery characteristics, Finally, in order to show the effect of each parameter
device simulations were carried out using the ISE|TCAD independently on diode snappiness, one parameter was
semiconductor device simulation package. The PIN diode varied at a time, keeping the rest of the parameters at their
model doping profile and the ramp circuit model used in reference values.
performing the transient simulations are shown in figure
(9). V. SIMULATION RESULTS
Figure (10) shows the current and voltage waveforms for
the diode with the reference set of parameters, while the
second diode has the same specifications but with an
increased P emitter doping level of 5´1017/cm3. It is
+

clear that snappiness occurs at higher doping levels, while

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a softer recovery occurs at lower levels. A higher doping Double Sided Penetration
level will result in a higher concentration of minority
+ - - +
carriers stored near the p n junction than on the n n side
as shown in Fig. (11-b). The total amount of stored charge
is larger in this case, therefore a longer period is needed to
+ -
clear the p n junction from these excess carriers,
meanwhile this extra time will lead to an extra removal of
- +
carriers from the n n side, causing the depletion layer to
build up on both ends. This will lead to the disappearance
- +
of charge near the n n junction which is crucial for soft
recovery characteristics of the diode. +
(b) High P emitter doping.
As can be seen in this case the amount of stored excess Fig. 11 Excess minority carrier distribution during reverse
carriers is not necessarily important, but the shape and recovery
position of the carriers is vital to determine whether the 16 3
(50 nsec/step) ( 2. 5 ´ 10 / cm /div, 10 mm/div)
diode will be snappy or soft. A one sided penetration of the
depletion layer will provide a soft recovery. A conclusion
Figure (12) shows the voltage and current waveforms of
can be reached here that increasing the gradient of the
two diode settings one with a very low lifetime value of
excess carriers stored in the drift region from the p + n -
50nsec compared to the reference diode with 200nsec.
junction to the n - n + junction will result in softer
Lower lifetime values results in a harder snappy recovery
characteristics, reducing the possibility of a space charge
occurring at voltages lower than the punch-through value.
region building up at both ends. Similar effects can be
+ In this case, the stored charge disappears when the
achieved using shallower P emitters.
depletion region starts to build up at both ends pushing the
carriers into the middle of the drift region as shown in
Voltage
figure (13). A similar behavior is observed when the diode
is operating at lower current densities or lower
temperatures.
The punch through voltage can be varied by changing the
drift region properties (thickness or doping). A thinner
base region will result in a lower punch-through voltage.
Figure (14) shows the reverse recovery characteristics for a
Current snappy diode with a base width of 60mm compared to the
reference diode with a 90mm base width. The case is
Fig. 10 Reverse Recovery Current and Voltage. similar for different base doping levels, but although the
(10 A/div, 300 V/div, 50 nsec/div) actual amount and shape of the stored carriers is not
+ +
[Low P Doping (Black), High P Doping (Gray)] affected, the punch-through voltage will change. Therefore
at lower doping levels, snappiness occurs due to a higher
penetration of the depletion region at lower applied
Single Sided Penetration
voltages. At high doping levels or non punch-through
structures, the critical voltage is equal to the avalanche
breakdown value.

Current Voltage

+
(a) Low P emitter doping.

Fig. 12 Reverse Recovery Current and Voltage.

(10 A/div, 300 V/div, 50 nsec/div)

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[High Lifetime 200nsec (Black), Low Lifetime 50 nsec 1) The reverse recovery IV curve exceeds the power
(Gray)] dissipation capability of the chip (outside the SOA limits).
This failure mode normally occurs at high forward
Double Sided Penetration currents, high temperatures, high reverse overshoot
voltages and high di/dts.
2) The SOA curve is shifted due to very high current
densities flowing in a small area of the device. This occurs
due to material or process variations (Silicon dislocations,
diffusions, lifetime killing, contact uniformity, etc.).

At typical operating current densities (100-200)A/cm2, the

second term on the right hand side of eq. (33) becomes
irrelevant for doping concentrations above 1x1014. Hence,
Fig. 13 Excess minority carrier distribution during reverse for diodes with lower voltage ratings (<600V), this type of
recovery for a lifetime of 50nsec (50nsec/step) failure mode becomes less problematic. For higher voltage
16 3 diodes (>1200V) with lower doping concentrations, the
( 2. 5 ´ 10 / cm / div, 10mm/div)
uniformity of the current in the diode during dynamic
avalanching becomes very critical, and the second term
dominate especially at very high di/dts and reverse bias
Current Voltage voltages.
Earlier, it was shown that during the recovery phase, all the
holes near the n - n + junction are swept out across the space
charge. The high electric field barrier at that junction will
also prevent the holes from diffusing into the N+ emitter.
However, for the type of profile presented in figure (10-a),
a hole diffusion element is introduced. The larger the
remaining charge in the drift region during the recovery
phase, the higher the diffusion current across the space
Fig. 14 Reverse Recovery Current and Voltage. charge region and we are more likely to experience
(10 A/div, 300 V/div, 50 nsec/div) dynamic avalanching. This extra charge will also prolong
[Thick Base 90mm (Black), Thin Base 60mm (Gray)] the recovery phase increasing the possibility of current
crowding to form on the silicon chip.
VI. DYNAMIC AVALANCHING An increase in the P emitter doping level will increase the
Reverse recovery dynamic avalanching occurs when a injection efficiency at the pn - junction and the hole
diode suffers avalanche multiplication at values lower than diffusion current portion will be lower. This is likely to
the static breakdown voltage. Higher peak electric fields are reduce the dynamic avalanche process with a lower risk of
present due to the excess minority carrier concentration in current non-uniformity and device failure.
the drift region during reverse recovery. This can lead to an
increase in the effective background doping Neff, hence, I
generating extra amount of carriers and resulting in impact Im
(2) Current Crowding (Dynamic Avalanche)
ionization. The process itself is stable if the extra generated
holes and electrons are balanced in numbers and the (1) Excessive Power (Dynamic Avalanche)
current remains uniform across the device. Otherwise the High di/dt
process can get out of control leading to a device failure.
Ipr
Neff is a function of the hole current density Jp [8] and the Ppr

holes saturation velocity vp and can be given as IR Vpr

Safe Recovery SOA
Jp
N eff = N D + (33) V
qv p VR Vc Vbd

Fig. 15 Reverse Recovery Safe Operating Area in a Fast

The reverse recovery SOA-IV curve can be provided [9] for Diode.
a given chip area as shown in figure (15). Under normal
operating conditions the IV curve should remain within the VII. CONCLUSION
SOA limits. However, dynamic avalanching may occur if : A detailed study of the reverse recovery snappy behavior in
modern fast power diodes is presented in this paper. The
analyses have shown that capacitive effects due to the

IEEE Page 9 of 10 March/April 2001

ABB Switzerland Ltd. Freewheeling Diode Reverse Recovery Failure Modes in IGBT Applications

remaining stored charge in the drift region during the [7] M.T. Rahimo, W.J. Findlay , L. Coulbeck, "An
recovery phase will influence the recovery characteristics. Improved Design for Ultra Soft - Fast Recovery Diodes
Normally, for the soft recovery case, a large capacitance suitable for (600 - 1200V) IGBT Applications"
exists due to the stored charge in the drift region, hence, PCIM'98, Nurnburg, Germany, pp 409-417, May 1998.
this capacitance dominates the recovery characteristics. A [8] Z. Khatir, Ph. Larguier, D. Sebille, "Experimental and
reduction in drift region thickness and/or carrier lifetime numerical analysis of GTO's snubberless turn-off
leads to the snappy recovery case, where the stored charge operations", Microelectronics Journal, V(27), No. (2-
disappears as the voltage reaches the critical value. The 3), pp 231-241.
only capacitance then remaining is the junction capacitance [9] Ichiro Omira, Akio Nakagawa, "4.5kV GTO Turn-off
of the diode, and it is this discontinuity that causes the very failure analysis under inductive load snubber, gate
large current and voltage oscillations and potentially circuit and various parameters" ISPSD'92, Japan, pp
destructive voltage spikes. 112- 117.
The interaction of the diode capacitance with the main
circuit parameters is a key factor in determining the reverse
recovery characteristics of a diode, and whether the diode
adopts a soft or snappy recovery behavior for the given
operating conditions and design.
Also, the gradient of the minority carrier concentration in
the drift region plays a major role in the determining the
shape and type of recovery. By ensuring that the excess
carrier concentration during the forward conduction is
greater near the n - n + junction when compared to the p + n -
junction, this helps to slow down the removal of charge and
preventing the depletion layer from building up at both
junctions during reverse recovery. At the same time, the
higher gradient can degrade device ruggedness due to
dynamic avalanching at higher di/dts and reverse bias
voltages. Both failure modes can be prevented through
certain device/circuit design techniques in order to achieve
a safe operating condition for the application.

REFERENCES

[1] M.T. Rahimo, P.T. Hoban, N.Y.A. Shammas, "Effects

of Temperature, Forward Current and Commutating
di/dt on the Reverse Recovery Behavior of Fast Power
Diodes", EPE'95, Spain, pp 1.577-1.582., Sept. 1995.
[2] V. Benda, "Design Considerations for Fast Soft
Reverse Recovery Diodes" EPE'93, Brighton, UK pp
288-292, 1993.
[3] Benda and Spenke, "Reverse Recovery Processes in
Silicon Power Rectifiers" IEEE Trans. on Electron
Devices, pp 1331-1354, Aug. 1967.
[4] M.T. Rahimo, N.Y.A. Shammas, "Optimisation of the
Reverse Recovery Behavior of Fast Power Diodes using
Injection Efficiency Techniques and Lifetime Control
Techniques" EPE'97, Trondheim, Norway, pp 2.99-
2.104, Sept. 1997.
[5] J. Lutz, U. Scheuermann, "Advantages of the New
Controlled Axial Lifetime Diode", PCIM'94,
Nurnburg, Germany, pp 163-169, June 1994.
[6] M. Nemoto, Y. Takahashi, T. Fujii, N. Iwamuro, Y.
Seki, "Study on Voltage Oscillation Phenomenon in
High Voltage pin Diode" ISPSD'98, Kyoto, Japan, pp
305-308, June 1998.

IEEE Page 10 of 10 March/April 2001