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Verilog Case Statement Examples

The document explains different types of case statements in Verilog for conditional branching, including basic case, casez, and casex statements. It provides examples such as a traffic light controller and opcode matching for an ALU, illustrating how each case statement operates under various conditions. It also warns against using casex for hardware synthesis due to unpredictable behavior with unknown values.

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Rkrishna A
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438 views3 pages

Verilog Case Statement Examples

The document explains different types of case statements in Verilog for conditional branching, including basic case, casez, and casex statements. It provides examples such as a traffic light controller and opcode matching for an ALU, illustrating how each case statement operates under various conditions. It also warns against using casex for hardware synthesis due to unpredictable behavior with unknown values.

Uploaded by

Rkrishna A
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

Verilog Case Statements with example

In Verilog, there are different types of case statements used for conditional branching.
They are:

1. Basic case Statement (Standard)


This works just like an if-else ladder but in a cleaner way.

Example: Traffic Light Controller


Let's say we have a traffic light with three states:
 00 → Green Light
 01 → Yellow Light
 10 → Red Light
 Other values → Default (Turn Off Light)

Here’s how we can use a case statement:


module traffic_light (
input [1:0] state,
output reg [2:0] light // 3-bit output (Red, Yellow, Green)
);

always @(*) begin


case (state)
2'b00: light = 3'b001; // Green
2'b01: light = 3'b010; // Yellow
2'b10: light = 3'b100; // Red
default: light = 3'b000; // All off (invalid state)
endcase
end
endmodule

How It Works
 If state = 00, the output light = 001 (Green is ON).
 If state = 01, the output light = 010 (Yellow is ON).
 If state = 10, the output light = 100 (Red is ON).
 If state = anything else, the light is OFF.
2. casez Statement (Ignores z in Comparison)
 This is useful when some bits are unknown or high-impedance (z).
 The ? acts as a wildcard (can be 0 or 1).

Example: Opcode Matching (Simpler Decoder)


Let’s say we have an ALU where:
 1000 means ADD
 1001 means SUBTRACT
 1010 means MULTIPLY

But sometimes, the second bit might be z (unknown state). Instead of writing multiple cases,
we can use casez:

casez (opcode)
4'b10?0: operation = ADD; // Matches 1000, 1010
4'b10?1: operation = SUB; // Matches 1001, 1011
default: operation = NOP; // No operation
endcase

How It Works
 10?0 matches both 1000 (ADD) and 1010 (MULTIPLY).
 10?1 matches both 1001 (SUBTRACT) and 1011 (invalid but accepted).
 ? means it can be either 0 or 1.
3. casex Statement (Ignores Both x and z)
 This is dangerous for synthesis but useful in simulation.
 x (unknown) and z (high-impedance) are both treated as don't care.

Example: Matching Incomplete Data

casex (data)
4'b1xxx: result = 1; // Any value starting with '1' (1000, 1011, etc.)
4'b0xxx: result = 0; // Any value starting with '0' (0001, 0110, etc.)
default: result = -1;
endcase

How It Works
 1xxx means the first bit must be 1, but the other bits can be anything.
 0xxx means the first bit must be 0, but the other bits can be anything.

 Warning: casex is NOT recommended for hardware synthesis because unknown (x) values
behave unpredictably in real circuits.

Final Thought
 Use case for regular comparisons (FSMs, Traffic Lights, ALUs, etc.).
 Use casez when working with bus signals that might have z (decoders, opcode matching).
 Avoid casex in hardware because x values are unpredictable.

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