

CMOS MT88E43
Extended Voltage Calling Number
Preliminary Information Identification Circuit 2

Features ISSUE 3 March 1997

• Compatible with: Ordering Information

• British Telecom (BT) SIN227 & SIN242 MT88E43AE 24 Pin Plastic DIP
• U.K.’s Cable Communications Association (0.6 inch package only)
(CCA) specification TW/P&E/312 MT88E43AS 24 Pin SOIC
• Bellcore GR-30-CORE (formerly known as TR- -40 °C to +85 °C
NWT-000030) & SR-TSV-002476 • Feature phones, including Analog Display Services
• Bellcore "CPE Alerting Signal (CAS)" and BT "Idle Interface (ADSI) phones
State Tone Alert Signal" detection
• Phone set adjunct boxes
• Ring and line reversal detection
• FAX and answering machines
• 1200 baud Bell 202 and CCITT V.23 Frequency
• Database query and Computer Telephony
Shift Keying (FSK) demodulation
Integration (CTI) systems
• 3 or 5V ±10% supply voltage
• High input sensitivity (-40dBV Tone and FSK
Description
Detection)
The MT88E43 Calling Number Identification Circuit 2
• Selectable 3-wire data interface (microcontroller or
(ECNIC2) is a low power CMOS integrated circuit
MT88E43 controlled) intended for receiving physical layer signals transmitted
• Low power CMOS with powerdown mode according to BT (British Telecom) SIN227 & SIN242, the
• Input gain adjustable amplifier U.K.’s CCA (Cable Communications Association) TW/
• Carrier detect status output P&E/312 and Bellcore GR-30-CORE & SR-TSV-002476
specifications. The MT88E43 is suitable for applications
• Uses 3.58 MHz crystal using a fixed voltage power source between 3 and 5V
±10%.
Applications
• BT Calling Line Identity Presentation (CLIP), CCA
CLIP, and Bellcore Calling Identity Delivery (CID)
systems

FSKen MODE

IN+ + Anti-alias FSK DCLK

FSK Bandpass Data Timing
- Filter Demodulator Recovery DATA
IN- Filter
DR

GS
To internal
cct.
Carrier CD
Bias Detector
VRef Generator
Interrupt
Generator INT
CAP
PWDN
Alert Signal High
Tone Filter Guard StD
Tone Time
Detection St/GT
To internal cct.
Algorithm
Alert Signal Low ESt
Tone Filter
Oscillator VDD
VSS

OSCin OSCout TRIGin TRIGRC TRIGout

Figure 1- Functional Block Diagram

5-53
MT88E43 Preliminary Information

IN+ 1 24 VDD
IN- 2 23 St/GT
GS 3 22 ESt
VRef 4 21 StD
CAP 5 20 INT
TRIGin 6 19 CD
TRIGRC 7 18 DR
TRIGout 8 17 DATA
MODE 9 16 DCLK
OSCin 10 15 FSKen
OSCout 11 14 PWDN
VSS 12 13 IC

Figure 2 - Pin Connections

Pin Description

Pin # Name Description

1 IN+ Non-inverting Input of the internal opamp.

2 IN- Inverting Input of the internal opamp.
3 GS Gain Select (Output) of internal opamp. The opamp’s gain should be set according to the nominal Vdd
of the application using the information in Figure 10.
4 VRef Reference Voltage (Output). Nominally VDD/2. It is used to bias the input opamp.
5 CAP Capacitor. A 0.1µF decoupling capacitor should be connected across this pin and VSS.
6 TRIGin Trigger Input. Schmitt trigger buffer input. Used for line reversal and ring detection.
7 TRIGRC Trigger RC (Open Drain Output/Schmitt Input). Used to set the (RC) time interval from TRIGin
going low to TRIGout going high. An external resistor connected to VDD and capacitor connected to VSS
determine the duration of the (RC) time interval.
8 TRIGout Trigger Out (CMOS Output). Schmitt trigger buffer output. Used to indicate detection of line reversal
and/or ringing.
9 MODE 3-wire interface: Mode Select (CMOS Input). When low, selects interface mode 0. When high, selects
interface mode 1. See pin 16 (DCLK) description to understand how MODE affects the DCLK pin.
10 OSCin Oscillator Input. A 3.579545MHz crystal should be connected between this pin and OSCout. It may also
be driven directly from an external clock source.
11 OSCout Oscillator Output. A 3.579545MHz crystal should be connected between this pin and OSCin. When
OSCin is driven by an external clock, this pin should be left open.
12 VSS Power Supply Ground.
13 IC Internal Connection. Must be connected to VSS for normal operation.
14 PWDN Power Down (Schmitt Input). Active high. When high, the device consumes minimal power by
disabling all functionality except TRIGin, TRIGRC and TRIGout. Must be pulled low for device
operation.
15 FSKen FSK Enable (CMOS Input). Must be high for FSK demodulation. This pin should be set low to prevent
the FSK demodulator from reacting to extraneous signals (such as speech, alert signal and DTMF which
are all in the same frequency band as FSK).
16 DCLK 3-wire Interface: Data Clock (CMOS Input/Output). In mode 0 (MODE pin low), this pin is an
output. In mode 1 (MODE pin high), this pin is an input.
17 DATA 3-wire Interface: Data (CMOS Output). In mode 0 data appears at the pin once demodulated. In mode
1 data is shifted out on the rising edge of the microcontroller supplied DCLK.

5-54
Preliminary Information MT88E43
Pin Description

Pin # Name Description

18 DR 3-wire Interface: Data Ready (CMOS Output). Active low. In mode 0 this output goes low after the
last DCLK pulse of each data word. This identifies the 8-bit word boundary on the serial output stream.
Typically, DR is used to latch 8-bit words from a serial-to-parallel converter into a microcontroller. In
mode 1 this pin will signal the availability of data.
19 CD Carrier Detect (CMOS Output). Active low. A logic low indicates the presence of in-band signal at the
output of the FSK bandpass filter.
20 INT Interrupt (Open Drain Output). Active low. It is active when TRIGout or DR is low, or StD is high.
This output stays low until all three signals have become inactive.
21 StD Dual Tone Alert Signal Delayed Steering Output (CMOS Output). When high, it indicates that a
guard time qualified alert signal has been detected.
22 ESt Dual Tone Alert Signal Early Steering Output (CMOS Output). Alert signal detection output. Used in
conjunction with St/GT and external circuitry to implement the detect and non-detect guard times.
23 St/GT Dual Tone Alert Signal Steering Input/Guard Time (Analog Input/CMOS Output). A voltage
greater than VTGt (see figure 4) at the St/GT pin causes the device to indicate that a dual tone has been
detected by asserting StD high. A voltage less than VTGt frees the device to accept a new dual tone.
24 VDD Positive Power Supply.

The MT88E43 provides all the features and functions The MT88E43 is compatible with the caller identity
offered by Mitel’s MT8841 (CNIC), including 1200 baud specifications of BT, the U.K.’s CCA, and Bellcore.
Bell 202 and CCITT V.23 FSK demodulation. The 3-wire
serial data interface provided by CNIC has been enhanced BT specifications SIN227 and SIN242 describe the
to operate in two modes. In the CNIC compatible mode signalling mechanism between the network and the
data transfer is initiated by the device. A second mode Terminal Equipment (TE) for the Caller Display Service
allows a microcontroller to extract 8-bit data words from (CDS). CDS provides Calling Line Identity Presentation
the device. Furthermore, the MT88E43 offers Idle State (CLIP), which delivers to an on hook (idle state) TE the
Tone Alert Signal and line reversal detection capability identity of an incoming caller before the first ring.
for BT’s CLIP, ring burst detection for the U.K.’s CCA’s
CLIP, and ring and CAS detection for Bellcore’s CID.
An incoming CDS call is indicated by a polarity reversal
on the A and B wires (see Figure 3), followed by an Idle
Functional Overview State Tone Alert Signal. Caller ID FSK information is
then transmitted in CCITT V.23 format. MT88E43 can
detect the line reversal, tone alert signal, and demodulate
The MT88E43, Extended Voltage Calling Number
the incoming CCITT V.23 FSK signals.
Identification Circuit 2 (ECNIC2) is a device compatible
with BT, the U.K.’s CCA and Bellcore specifications. As
shown in Figure 1, the MT88E43 provides an FSK The U.K.’s CCA specification TW/P&E/312 proposes an
demodulator as well as a 3-wire serial interface similar to alternate CDS TE interface. According to TW/P&E/312,
that of it’s predecessor, the MT8841 (CNIC). The 3-wire data is transmitted after a single burst of ringing rather
interface has been enhanced to provide two modes of than before the first ringing cycle (as specified in the BT
operation - a mode whereby data transfer is initiated by standards). The Idle State Tone Alert Signal is not
the device and a mode whereby data transfer is initiated required as it is replaced by a single ring burst. MT88E43
by an external microcontroller. has the capability to detect the ring burst. It can also
demodulate either Bell-202 or CCITT V.23 FSK data
following the ring burst. The U.K.’s CCA specifies that
In addition to supporting all the features and functions of
data can be transmitted in either format.
the MT8841, the MT88E43 also provides line reversal
detection, ring detection and dual tone alert signal/CAS
detection. These new functions eliminate some external Bellcore specification GR-30-CORE is the generic
circuitry previously required with the MT8841. requirement for transmitting asynchronous voiceband data
to Customer Premises Equipment (CPE). Another

5-55
MT88E43 Preliminary Information

Bellcore specification SR-TSV-002476 describes the Figure 3 shows a circuit to detect any one of three CLIP/
same requirements from the CPE’s perspective. The data CID call arrival indicators: line reversal, ring burst and
transmission technique specified in both documents is ringing.
applicable in a variety of services like Calling Number
Delivery (CND), Calling Name Delivery (CNAM) and 1. Line Reversal Detection
Calling Identity Delivery on Call Waiting (CIDCW) -
Line reversal, or polarity reversal on the A and B wires
services promoted by Bellcore.
indicates the arrival of an incoming CDS call, as specified
in SIN227. When the event (line reversal) occurs, TRIGin
In CND/CNAM service, information about a calling party rises past the high going Schmitt threshold VT+ and
is embedded in the silent interval between the first and TRIGout, which is normally high, is pulled low. When the
second ring burst. The MT88E43 detects the first ring event is over, TRIGin falls back to below the low going
burst and can then be setup to receive and demodulate the Schmitt threshold VT- and TRIGout returns high. The
incoming Bell-202 FSK data. The device will output the components R5 and C3 (see Figure 3) at TRIGRC ensure
demodulated data onto a 3-wire serial interface. a minimum TRIGout low interval.

In CIDCW service, information about an incoming caller In a TE designed for CLIP, the TRIGout high to low
is sent to the subscriber, while he/she is engaged in transition may be used to interrupt or wake-up the
another call. A CPE Alerting Signal (CAS) indicates the microcontroller. The controller can thus be put into
arrival of CIDCW information. The MT88E43 can detect power-down mode to conserve power in a battery
the alert signal and then be setup to demodulate incoming operated TE.
FSK data containing CIDCW information. 2. Ring Burst Detection
Functional Description CCA does not support the dual tone alert signal (refer to
Dual Tone Alert Signal Detection section). Instead, CCA
Detection of CLIP/CID Call Arrival Indicators requires that the TE be able to detect a single burst of
ringing (duration 200-450ms) that precedes CLIP FSK
data. The ring burst may vary from 30 to 75Vrms and is
The circuit in Figure 3 illustrates the relationship between approximately 25Hz.
the TRIGin, TRIGRC and TRIGout signals. Typically, the
three pin combination is used to detect an event indicated
by an increase of the TRIGin voltage from VSS to above Again in a TE designed for CCA CLIP, the TRIGout high
the Schmitt trigger high going threshold VT+ (see DC to low transition may be used to interrupt or wake-up the
electrical characteristics). microcontroller. The controller can thus be put into
power-down mode to conserve power in a battery
operated TE.

VDD
C1=100nF
V1 V3 MT88E43
Tip/A
R1=499K max VT+ = 0.68 VDD
min VT+ = 0.48 VDD
R3=200K
TRIGin
R4=301K

C2=100nF
R5=150K

V2
Ring/B
V4 To determine values for C3 and R5:
R2=499K
Notes: R5C3=-t / ln(1-VTRIGRC/VDD)
TRIGRC
The application circuit must ensure that,
VTRIGin>max VT+
C3=220nF

where max VT+=3.74V @VDD=5.5V.

Tolerance to noise between A/B and VSS is:
max Vnoise = (min VT+)/0.30+0.7 =5.6Vrms @4.5V VDD
where min VT+ = 2.16V @VDD=4.5V.
Suggested R5C3 component values:
R5 from 10KΩ to 500KΩ TRIGout
C3 from 47nF to 0.68µF
An example is C3=220nF, R5=150KΩ; TRIGout low from To Microcontroller
21.6ms to 37.6ms after TRIGin Signal stops triggering the
circuit.

Figure 3 - Circuit to Detect Line Reversal, Ring Burst and Ringing

5-56
Preliminary Information MT88E43
3. Ring Detection
In Bellcore’s CND/CNAM scheme, the CID FSK data is
transmitted between the first and second ringing cycles. Item BT Bellcore
The circuit in Figure 3 will generate a ring envelope Low tone 2130Hz ±1.1% 2130Hz ±0.5%
signal (active low) at TRIGout for a ring voltage of at frequency
least 40Vrms. R5 and C3 filter the ring signal to provide
an envelope output. High tone 2750Hz ± 1.1% 2750Hz ± 0.5%
frequency
The diode bridge shown in Figure 3 works for both single Received -2dBV to -40dBV -14dBmb to
ended and balanced ringing. A fraction of the ring voltage signal level per tone on-hooka - 32dBm per tone
is applied to the TRIGin input. When the voltage at (0.22dBmb to off-hook
TRIGin is above the Schmitt trigger high going threshold -37.78dBm)
VT+, TRIGRC is pulled low as C3 discharges. TRIGout
stays low as long as the C3 voltage stays below the Signal reject -46dBV -45dBm
minimum VT+. level (-43.78dBm)
Signal level up to 7dB up to 6dB
In a CPE designed for CND/CNAM, the TRIGout high to differential
low transition may be used to interrupt or wake-up the (twist)
microcontroller. The controller can thus be put into Unwanted <= -20dB <= -7dBm ASLc
power-down mode to conserve power. signals (300-3400Hz) near end speech
Duration 88ms to 110msd 75ms to 85ms
If precise ring duration determination is critical, capacitor
C3 in Figure 3 may be removed. The microcontroller will Speech No Yes
now be able to time the ring duration directly. The result present
will be that TRIGout will be low only as long as the Table 1 - Dual Tone Alert Signal Characteristics
ringing signal is present. Previously the RC time constant
a. In the future BT may specify the off-hook signal level as
would cause only one interrupt. -15dBm to -34dBm per tone for BT CIDCW.
b. The signal power is expressed in dBm referenced to 600 ohm at the
CPE A/B (tip/ring) interface.
Dual Tone Alert Signal Detection c. ASL = active speech level expressed in dBm referenced to 600 ohm
at the CPE tip/ring interface. The level is measured according to
method B of Recommendation P.56 "Objective Measurement of
The BT on hook (idle state) caller ID scheme uses a dual Active Speech Level" published in the CCITT Blue Book, volume V
"Telephone Transmission Quality" 1989.
tone alert signal whose characteristics are shown in Table EPL (Equivalent Peak Level) = ASL+11.7dB
1. d. SIN227 suggests that the recognition time should be not less than
20ms if both tones are detected.

Bellcore specifies a similar dual tone alert signal called

CPE Alerting Signal (CAS) for use in off-hook data
transmission (see Table 1). Bellcore states that the CPE
should be able to detect the CAS in the presence of near
end speech. The CAS detector should also be immune to
imitation from near and far end speech.
In the MT88E43 the dual tone alert signal is separated
into a high and a low tone by two bandpass filters. A
detection algorithm examines the two filter outputs to
determine the presence of a dual tone alert signal. The ESt
pin goes high when both tones are present. Note that ESt
is only a preliminary indication. The indication must be
sustained over the tone present guard time to be
considered valid. Tone present and tone absent guard
times can be implemented with external RC components.
The tone present guard time rejects signals of insufficient
duration. The tone absent guard time masks momentary
detection dropout once the present guard time has been
satisfied. StD is the guard time qualified detector output.

5-57
MT88E43 Preliminary Information

Dual Tone Detection Guard Time

MT88E43
VDD
When the dual tone alert signal is detected by the Tones detected
MT88E43, ESt goes high. When the alerting signal ceases Q1
From P
to be detected, ESt goes low. detector C
St/GT
The ESt pin signals raw detection of CAS/Alerting Tones.
Since both Bellcore and BT applications require a +
- VTGt
minimum duration for valid signals, ESt detection must be Comparator R
guard time qualified. The StD pin provides guard time
Q2
qualified CAS/Alerting Tone detection. When the N SW1
A B
MT88E43 is used in a caller identity system, StD = VSS
indicates correct CAS/Alerting Tone detection. ESt
VSS
StD
Figure 4 shows the relationship between the St/GT, ESt
and StD pins. It also shows the operation of a guard time Figure 4 - Guard Time Circuit Operation
circuit.
MT88E43
The total recognition time is tREC = tGP + tDP, where tGP is VDD
the tone present guard time and tDP is the tone present C
VD=diode forward voltage
detect time (refer to timing between ESt, St/GT and StD in St/GT
Figures 17 and 20). R1 R2
ESt
The total tone absent time is tABS = tGA + tDA, where tGA (a) tGP > tGA
is the tone absent guard time and tDA is the tone absent tGP = R1C ln [VDD/(VDD-VTGt)]
detect time (refer to timing between ESt, St/GT and StD in tGA = RPC ln [(V DD-V D(R P/R2))/(VTGt-V D(R P/R2))]
Figures 17 and 20). RP = R1R2/(R1+R2)

Bellcore states that it is desirable to be able to turn off MT88E43

CAS detection for an off-hook capable CPE. The disable VDD
switch allows the subscriber who disconnects a service C
that relies on CAS detection (e.g., CIDCW) but retains the VD=diode forward voltage
St/GT
CPE, to turn off the detector and not be bothered by false
R1 R2
detection. ESt
(b) tGP < tGA
When SW1 in Figure 4 is in the B position the guard time
circuit is disabled. The detector will still process CAS/ tGP = RPC ln [VDD-VD(RP/R2))/(VDD-VTGt-VD(RP/R2))]
Alerting tones but the MT88E43 will not signal their tGA = R1C ln (VDD/VTGt)
presence by ensuring StD is low. RP = R1R2/(R1+R2)
Figure 5 - Guard Time Circuits with
BT specifies that the idle state tone alert signal Unequal Times
recognition time should not be less than 20ms when both
tones are used for detection. That is, both tones must be Input Configuration
detected together for at least 20ms before the signal can
be declared valid. This requirement can be met by setting
The MT88E43 provides an input arrangement comprised
the tGP (refer to Figure 5) to at least 20ms.
of an operational amplifier and a bias source (VRef); which
is used to bias the opamp inputs at VDD/2. The feedback
BT also specifies that the TE is required to apply a D.C. resistor at the opamp output (GS) can be used to adjust the
wetting pulse and an AC load 15-25ms after the end of the gain. In a single-ended configuration, the opamp is
alerting signal. If tABS=tDA+tGA is 15 to 25ms, the D.C. connected as shown in Figure 6. For a differential input
current wetting pulse and the A.C. load can both be configuration, Figure 7 shows the necessary connections.
applied at the falling edge of StD. The maximum tDA is
8ms so tGA should be 15-17ms. Therefore, tGP must be
greater than tGA. Figure 5(a) shows a possible
implementation. The values in Figures 9 and 11
(R2=R3=422K, C=0.1µF) will meet the BT timing
requirements.

5-58
Preliminary Information MT88E43

IN+ Item BT Bellcore

Mark 1300Hz 1200Hz

C RIN
IN- frequency ±1.5% ±1%
(logic 1)

GS Space 2100Hz 2200Hz

RF
frequency ±1.5% ±1%
(logic 0)
Voltage Gain VRef
(AV) = RF / RIN Received -8dBV to -12dBma to -
signal level - -40dBV 32dBm
Figure 6 - Single-Ended Input mark (-5.78dBm to
Configuration -37.78dBm)
Received -8dBV to -12dBm to
signal level - -40dBV -36dBm
C1 R1 IN+ space
Signal level up to 6dB up to 10dBb
IN- differential
(twist)
C2 R4 R5
GS Unwanted <= -20dB (300- <= -25dB
signals 3400Hz) (0-4kHz)c
R3 R2
Transmission 1200 baud 1200 baud
VRef rate ±± 1% ±± 1%
Differential Input Amplifier Word format 1 start bit (logic 1 start bit (logic
C1 = C2
R1 = R4 (For unity gain R5= R4)
0), 8 bit word 0), 8 bit word
R3 = (R2R5) / (R2 + R5) (LSB first), 1 to (LSB first),
Voltage Gain 10 stop bits 1 stop bit
(AVdiff) = R5/R1 (see Figure 9,10,11) (logic 1) (logic 1)d
Input Impedance Table 2 - FSK Characteristics
(ZINdiff) = 2 R12 + (1/ωC)2
a. The signal power is expressed in dBm referenced to 600 ohm at the
CPE tip/ring (A/B) interface.
Figure 7 - Differential Input Configuration b. SR-3004,Issue 2, January 1995.
c. The frequency range is specified in GR-30-CORE.
d. Up to 20 marks may be inserted in specific places in a single or
FSK Demodulation multiple data message.

The MT88E43 first bandpass filters and then demodulates The FSK characteristics described in Table 2 are listed in
the incoming FSK signal. The carrier detector provides an BT and Bellcore specifications. The BT signal frequencies
indication of the presence of signal at the bandpass filter correspond to CCITT V.23. The Bellcore frequencies
output. The MT88E43’s dual mode 3-wire interface correspond to Bell 202. The U.K.’s CCA requires that the
allows convenient extraction of the 8-bit data words in the TE be able to receive both CCITT V.23 and Bell 202, as
demodulated FSK bit stream. specified in the BT and Bellcore specifications. The
MT88E43 is compatible with both formats without any
adjustment.
Note that signals such as dual tone alert signal, speech and
DTMF tones lie in the same frequency band as FSK. They
will, therefore, be demodulated and as a result, false data • 3-wire User Interface
will be generated. To avoid demodulation of false data, an The MT88E43 provides a powerful dual mode 3-wire
FSKen pin is provided so that the FSK demodulator may interface so that the 8-bit data words in the demodulated
be disabled when FSK signal is not expected. There are FSK bit stream can be extracted without the need either
two events that if either is true, should be used to disable for an external UART or for the TE/CPE’s microcontroller
FSKen. The events are CD returning high or receiving all to perform the UART function in software. The interface
the data indicated by the message length word. is specifically designed for the 1200 baud rate and is
comprised of the DATA, DCLK (data clock) and DR (data
ready) pins. Two modes (modes 0 and 1) are selectable via
control of the device’s MODE pin: in mode 0, data

5-59
MT88E43 Preliminary Information

transfer is initiated by the MT88E43; in mode 1, data presence of a signal of sufficient amplitude at the output
transfer is initiated by the external microcontroller. of the FSK bandpass filter. The signal is qualified by a
digital algorithm before the CD output is set low to
Mode 0 indicate carrier detection. An 8ms hysteresis is provided
to allow for momentary signal drop out once CD has been
activated. CD is released when there is no activity at the
This mode is selected when the MODE pin is low. It is the FSK bandpass filter output for 8 ms.
MT8841 compatible mode where data transfer is initiated
by the device.
When CD is inactive (high), the raw output of the
demodulator is ignored by the data timing recovery circuit
In this mode, the MT88E43 receives the FSK signal, (refer to Figure 1). In mode 0, the DATA pin is forced
demodulates it, and outputs the data directly to the DATA high. No DCLK or DR signal is generated. In mode 1, the
pin (refer to Figure 14). For each received stop and start internal shift register is not updated. No DR is generated.
bit sequence, the MT88E43 outputs a fixed frequency If DCLK is clocked (in mode 1), DATA is undefined.
clock string of 8 pulses at the DCLK pin. Each clock
rising edge occurs in the centre of each DATA bit cell.
DCLK is not generated for the stop and start bits. Note that signals such as dual tone alert signal, speech and
Consequently, DCLK will clock only valid data into a DTMF tones also lie in the FSK frequency band and the
peripheral device such as a serial to parallel shift register carrier detector may be activated by these signals. The
or a micro-controller. The MT88E43 also outputs an end signals will be demodulated and presented as data. To
of word pulse (data ready) on the DR pin. The data ready avoid false data detection, the FSKen pin should be used
signal indicates the reception of every 10-bit word to disable the FSK demodulator when no FSK signal is
(including start and stop bits) sent from the network to the expected.
TE/CPE. This DR signal can be used to interrupt a micro-
controller. DR can also cause a serial to parallel converter Ringing, on the other hand, does not pose a problem as it
to parallel load its data into a microcontroller. The mode 0 is ignored by the carrier detector.
data pin can also be connected to a personal computer’s
serial communication port after converting from CMOS to Interrupt
RS-232 voltage levels.
To facilitate interfacing with microcontrollers running
Mode 1 interrupt driven firmwear, an open drain interrupt output
INT is provided. INT is asserted when TRIGout is low,
This mode is selected when the MODE pin is high. In this StD is high, or DR is low. When INT is asserted, these
mode, the microcontroller supplies read pulses (DCLK) to signals should be read (through an input port of the
shift the 8-bit data words out of the MT88E43, onto the microcontroller) to determine the cause of the interrupt
DATA pin. The MT88E43 asserts DR to denote the word (TRIGout, StD or DR) so that the appropriate response
boundary and indicate to the microprocessor that a new can be made.
word has become available (refer to Figure 16).
When system power is first applied, TRIGout will be low
Internal to the MT88E43, the demodulated data bits are because capacitor C3 at TRIGRC (see Figure 3) has no
sampled and stored. After the 8th bit, the word is parallel initial charge. This will result in an interrupt upon power
loaded into an 8 bit shift register and DR goes low. The up. Also when system power is first applied and the
shift register’s contents are shifted out to the DATA pin on PWDN pin is low, an interrupt will occur due to StD.
the supplied DCLK’s rising edge in the order they were Since there is no charge across the capacitor at the St/GT
received. pin in Figure 4, StD will be high triggering an interrupt.
The interrupts will not clear until both capacitors are
If DCLK begins while DR is low, DR will return to high charged. The microcontroller should ignore interrupt from
upon the first DCLK. This feature allows the associated these sources on initial power up until there is sufficient
interrupt (see section on "Interrupt") to be cleared by the time to charge the capacitors.
first read pulse. Otherwise DR is low for half a nominal bit
time (1/2400 sec). It is possible to clear StD and its interrupt by asserting
PWDN immediately after system power up. When PWDN
After the last bit has been read, additional DCLKs are is high, StD is low. PWDN will also force both ESt and
ignored. the comparator output low, Q2 will turn on so that the
capacitor at the St/GT pin charges up quickly (refer to
• Carrier Detect
Figure 4).
The carrier detector provides an indication of the presence
of a signal in the FSK frequency band. It detects the

5-60
Preliminary Information MT88E43
Power Down Mode VRef and CAP Inputs

For applications requiring reduced power consumption, VRef is the output of a low impedance voltage source
the MT88E43 can be powered up only when it is required, equal to VDD/2 and is used to bias the input opamp. A
that is, upon detection of one of three CLIP/CID call 0.1µF capacitor is required between CAP and VSS to
arrival indicators: line reversal, ring burst and ringing. eliminate noise on VRef.

The MT88E43 is powered down by asserting the PWDN

pin. In powerdown mode, the crystal oscillator, opamp
and all internal circuitry, except for TRIGin, TRIGRC and
TRIGout pins, are disabled. The three TRIG pins are not
affected by power down, such that, the MT88E43 can still
react to call arrival indicators. The MT88E43 can be
powered up by grounding the PWDN pin.

Crystal Oscillator

The MT88E43 requires a 3.579545MHz crystal oscillator

as the master timing source.

MT88E43 MT88E43 MT88E43

OSC1 OSC2 OSC1 OSC2 OSC1 OSC2

to the
next MT88E43
3.579545 MHz

Figure 8 - Common Crystal Connection

The crystal specification is as follows:

Frequency: 3.579545 MHz

Frequency tolerance: ±0.1%(-40oC+85oC)
Resonance mode: Parallel
Load capacitance: 18 pF
Maximum series resistance: 150 ohms
Maximum drive level (mW): 2 mW
e.g., CTS MP036S

Any number of MT88E43 devices can be connected as

shown in Figure 8 such that only one crystal is required.
The connection between OSC2 and OSC1
can be D.C. coupled as shown, or the OSC1 input on all
devices can be driven from a CMOS buffer (dc coupled)
with the OSC2 outputs left unconnected.

To meet BT and Bellcore requirements for proper tone

detection the crystal must have a frequency tolerance of
0.1%.

5-61
MT88E43 Preliminary Information

Vdd Vdd

R4

100nF
TIP / A 1N4003
MT88E43
22nF R1 1N4003
TISP4180, 5%
IN+ VDD Vdd
TISP5180, C
TPA150A12 or 100K
TPB150B12
Vdd IN- St/GT 20%
464K R3
RING / B 1N4003 R4

53K6
ESt

60K4
GS 1N914
R2
R1 1N4003 Vdd VRef StD
22nF
5% CAP INT

TRIGin CD
499K, 5% Vdd
TRIGRC DR
100nF 1N914 1N914 150K DATA
5% 5% TRIGout
MODE DCLK
1N914 200K FSKen
5% OSCin
499K, 5%
1N914 220nF
301K 100nF OSCout PWDN
100nF 5%
5% VSS IC

NOTE: Resistors must have 1% tolerance and capacitors have 20%

tolerance unless otherwise specified. = To microcontroller
: Crystal is 3.579545MHz, 0.1% frequency tolerance. = From microcontroller
: For BT Application C=0.1µF ±5%, R3=422kΩ ±1%, R2=422kΩ ±1%
: For applications where CAS speech immunity is required (e.g. CIDCW) (FSK Interface Mode 0 selected)
C=0.1µF ±5%, R3=825kΩ ±1%, R2=226kΩ ±1%
: R1 = 430K, R4 = 34K for VDD = 5V ± 10% (See Figure 10)
: R1 = 620K, R4 = 63K4 for VDD = 3V ± 10% (See Figure 10)

Figure 9 - Application Circuit

Application Circuits The circuit provides isolation from these high voltage faults
via R1 and the 12k1Ω resistors as well as the 22nF & 330nF
capacitors. IRC manufactures a resistor (part number GS3)
The circuits shown in Figures 9 and 11 are application that should be used for R1. This resistor is a 3W, 5%, 1kV
circuits for the MT88E43. As supply voltage (VDD ) is power resistor. The 12k1 resistor is manufactured by IRC
decreased, the threshold of the device’s tone and FSK (part number FA8425F). This resistor is a 1.5W, 5%, fusea-
detectors will be reduced. Therefore, to meet the BT or ble type resistor. The 22nF and 330nF capacitors have a
Bellcore tone reject level requirements the gain of the 400V rating.
internal opamp should be reduced according to the graph
in Figure 10. For example when VDD=5V (+/- 10%), R1
should equal 430kΩ and R4 should equal 34kΩ; and if See the application note "MSAN-164: Applications of the
VDD=3V (+/- 10%) R1 should equal 620kΩ and R4 should MT8843 Calling Number Identification Circuit 2" for
equal 63.4kΩ. Resistors R1 and R4 are shown in Figures 9 information on designing the MT88E43 into CID and
and 11. CIDCW systems.

The circuit shown in Figure 9 illustrates the use of the

MT88E43 in a proprietary system that doesn’t need to meet
FCC, DOC, and UL approvals. It should be noted that if
glitches on the tip/ring interface are of sufficient amplitude,
the circuit will falsely detect these signals as ringing or line
reversal.

The circuit shown in Figure 11 will provide common mode

rejection of signals received by the ringing circuit. This cir-
cuit should pass safety related tests specified by FCC Part 68,
DOC CS-03, UL 1459, and CSA C22.2. These safety tests
will simulate high voltage faults that may occur on the line.

5-62
Preliminary Information MT88E43

0.95

0.9

0.85
Gain Ratio

0.8

0.75

0.7
0.678

0.65

0.6
2 2.5 3 3.5 4 4.5 5 5.5 6
Nominal Vdd (Volts)
Figure 10: Gain Ratio as a function of Nominal Vdd

Note: In the application circuits shown in Figures 9 and 11, the Gain Ratio of MT88E43 opamp is

464k Ω
GainRatio = ------------------
R1 + R4

5-63
MT88E43 Preliminary Information

Vdd Vdd
22nF
R4

100nF
TIP / A 5% 1N4003

MT88E43
R1 1N4003
IN+ VDD
C Vdd
Vdd IN- St/GT
22nF 464K R3
RING / B 5% 1N4003 R4 100K

60K4
53K6
GS ESt 1N914 20%
R2
R1 VRef StD
1N4003
CAP INT

TRIGin CD
Vdd
TRIGRC DR
150K
5% DATA
TRIGout
100nF
10% MODE DCLK
1N5231B OSCin FSKen

220nF

100nF
OSCout PWDN
330nF 12K1 Vdd 200K VSS IC
10% 5% Motorola
4N25 5%

464K 10nF
5%

NOTE: Resistors must have 1% tolerance, capacitors have 20% = To microcontroller

tolerance unless specified otherwise.
: Bridge rectifier diodes are 1N914. = From microcontroller
: For BT Application C=0.1µF ±5%, R3=422kΩ ±1%, R2=422kΩ ±1%
: For applications where CAS speech immunity is required (e.g. CIDCW) (FSK Interface Mode 0 selected)
C=0.1µF ±5%, R3=825kΩ ±1%, R2=226kΩ ±1%
: R1 = 430K, R4 = 34K for VDD = 5V ± 10% (See Figure 10)
: R1 = 620K, R4 = 63K4 for VDD = 3V ± 10% (See Figure 10)

Figure 11 - Application Circuit with Improved Common Mode Noise Immunity and Isolation in Line
Interface
Approvals

FCC Part 68, DOC CS-03, UL 1459, and CAN/CSA-22.2

No. 225-M90 are all system (i.e. connectors, power
supply, cabinet, etc.) requirements. Since the MT88E43 is
a component and not a system, the application circuit
(Figure 11) has been designed to meet the CO Trunk
interface requirements of FCC, DOC, UL, and CSA; thus
enabling the complete system to be approved by these
standards bodies.

Products are designed in accordance with meeting the

above requirements; however, full conformance to these
standards is dependent upon the application in which the
MT88E43 is being used, and therefore, approvals are the
responsibility of the customer and Mitel will not have
tested the product to meet the above standards.

5-64
Preliminary Information MT88E43

Absolute Maximum Ratings* - Voltages are with respect to VSS unless otherwise stated.
Parameter Symbol Min Max Units

1 Supply voltage with respect to Vss VDD -0.3 6 V

2 Voltage on any pin other than supplies ** VPIN Vss-0.3 VDD+0.3 V
3 Current at any pin other than supplies IPIN 10 mA
4 Storage Temperature TST -65 150 oC

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
**
Under normal operating conditions voltage on any pin except supplies can be minimum VSS-1V to maximum VDD+1V for an input current
limited to less than 200µΑ
.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics Sym Min Typ‡ Max Units
1 Power Supplies VDD 2.7 - 5.5 V
2 Clock Frequency fOSC 3.579545 MHz
3 Tolerance on Clock Frequency ∆fc -0.1 +0.1 %
4 Operating Temperature TOP -40 85 oC

o
‡ Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing.

DC Electrical Characteristics†
Characteristics Sym Min Typ‡ Max Units Test Conditions

1 Standby Supply Current IDDQ 0.5 15 µA AlI inputs are VDD/

VSS except for
oscillator pins.
No analog input.
outputs unloaded.
S PWDN=VDD
U
2 P Operating Supply Current IDD All inputs are VDD/
P VSS except for
L VDD = 5V ±10% 4.7 8 mA oscillator pins.
Y
VDD = 3V ±10% 2.5 4.5 mA No analog input.
outputs unloaded.
PWDN=VSS
FSKen=VDD
3 Power Consumption PO 44 mW
4 Schmitt Input High VT+ 0.48*VDD 0.68*VDD V
Threshold
TRIGin,
TRIGRC, Schmitt Input Low VT- 0.28*VDD 0.48*VDD V
PWDN Threshold
5 Schmitt Hysteresis VHYS 0.2 V
6 DCLK, CMOS Input High Voltage VIH 0.7*VDD VDD V
MODE,
FSKen CMOS Input Low Voltage VIL VSS 0.3*VDD V

5-65
MT88E43 Preliminary Information

DC Electrical Characteristics† (continued)

Characteristics Sym Min Typ‡ Max Units Test Conditions

7 TRIGout, Output High Sourcing IOH 0.8 mA VOH=0.9*VDD

DCLK, Current
DATA,
DR, CD,
StD, ESt,
St/GT

8 TRIGout, Output Low Sinking IOL 2 mA VOL=0.1*VDD

DCLK, Current
DATA,
DR, CD,
StD, ESt,
St/GT
TRIGRC,
INT

9 IN+, IN-, Input Current Iin1 1 µA Vin=VDD to VSS

TRIGin

PWDN, Iin2 10 µA Vin=VDD to VSS

DCLK,
MODE,
FSKen

10 TRIGRC Output High-Impedance Ioz1 1 µA Vout =VDD to VSS

Current
11 INT Ioz2 10 µA
12 St/GT Ioz3 5 µΑ
13 VRef Output Voltage VRef 0.5VDD - 0.5VDD+ V No Load
0.05 0.05
14 Output Resistance RRef 2 kΩ
15 St/GT Comparator Threshold VTGt 0.5VDD- 0.5VDD+ V
Voltage 0.05 0.05
† DC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing.

AC Electrical Characteristics† - Dual Tone Alert Signal Detection

Characteristic Sym Min Typ‡ Max Unit Notes*

1 Low tone frequency fL - 2130 - Hz

5-66
Preliminary Information MT88E43
AC Electrical Characteristics† - Dual Tone Alert Signal Detection
Characteristic Sym Min Typ‡ Max Unit Notes*

2 High tone frequency fH - 2750 - Hz

3 Frequency deviation accept 1.1% - - range within which
tones are accepted
4 Frequency deviation reject 3.5% - - ranges outside of
which tones are
rejected
5 Accept signal level per tone -40 - -2 dBVa See Note 3
-37.78 0.22 dBmb
6 Reject signal level per tone - - -46 dBV See Note 3
-43.78 dBm
7 Positive and negative twist 7 - - dBc
accept
8 Signal to Noise Ratio SNRTONE 20 - - dB 1,2
a. dBV = decibels above or below a reference voltage of 1Vrms. Signal level is per tone.
b. dBm = decibels above or below a reference power of 1mW into 600 ohms, 0dBm = 0.7746Vrms. Signal level is per tone.
c. Twist = 20 log (fH amplitude / fL amplitude).

*Notes:
1. Both tones have the same amplitude.
2. Band limited random noise 300-3400Hz. Measurement valid only when tone is present.
3. With gain setting as shown in Figure 10. Production tested at 3V ±10%, 5V ±10%.

✝AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
‡Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing

AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels

Characteristics Sym Level Units Notes

1 CMOS Threshold Voltage VCT 0.5*VDD V

2 Rise/Fall Threshold Voltage High VHM 0.7*VDD V
3 Rise/Fall Threshold Voltage Low VLM 0.3*VDD V

5-67
MT88E43 Preliminary Information

Electrical Characteristics† - Gain Setting Amplifier

Characteristics Sym Min Max Units Test Conditions

1 Input Leakage Current IIN 1 µA VSS ≤ VIN ≤ VDD

2 Input Resistance Rin 10 MΩ
3 Input Offset Voltage VOS 25 mV
4 Power Supply Rejection Ratio PSRR 40 dB 1kHz ripple on VDD
5 Common Mode Rejection CMRR 40 dB VCMmin ≤ VIN ≤ VCMmax
6 DC Open Loop Voltage Gain AVOL 30 dB
7 Unity Gain Bandwidth fC 0.3 MHz
8 Output Voltage Swing VO 0.5 VDD-0.5 Vpp Load ≥ 50kΩ
9 Maximum Capacitive Load (GS) CL 100 pF
10 Maximum Resistive Load (GS) RL 50 kΩ
11 Common Mode Range Voltage VCM 1.0 VDD-1.0 V
† Electrical characteristics are over recommended operating conditions, unless otherwise stated.

AC Electrical Characteristics† - FSK Detection

Characteristics Sym Min Typ‡ Max Units Notes*

1 Input Detection Level -40 -8 dBVa 1,3

-37.78 -5.78 dBmb
10.0 398.1 mVrms
2 Transmission Rate 1188 1200 1212 baud
3 Input Frequency Detection
Bell 202 1 (Mark) 1188 1200 1212 Hz
Bell 202 0 (Space) 2178 2200 2222 Hz

CCITT V.23 1 (Mark) 1280.5 1300 1319.5 Hz

CCITT V.23 0 (Space) 2068.5 2100 2131.5 Hz
4 Signal to Noise Ratio SNRFSK 20 dB 1,2
a. dBV = decibels above or below a reference voltage of 1Vrms.
b. dBm = decibels above or below a reference power of 1mW into 600 ohms. 0dBm = 0.7746Vrms.
*Notes
1. Both mark and space have the same amplitude.
2. Band limited random noise (200-3400Hz). Present when FSK signal is present. Note that the BT band is 300-3400Hz, the Bellcore band is 0-
4kHz.
3. Production tested at V DD=3V ±10%, 5V ±10%.

† AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
‡ Typical figures are nominal values and are for design aid only: not guaranteed and not subject to production testing.

AC Electrical Characteristics† - Dual Tone Alert Signal Timing

Characteristics Sym Min Max Units Notes*
1 Alert Signal present detect time tDP 0.5 10 ms 1
2 Alert Signal absent detect time tDA 0.1 8 ms 1
*Notes
1. Refer to Figures 16 and 19

5-68
Preliminary Information MT88E43

AC Electrical Characteristics† - 3-Wire Interface Timing

Characteristics Sym Min Max Units Notes
1 PWDN Power-up time tPU 50 ms
OSC1
2 Power-down time tPD 1 ms
3 Input FSK to CD low delay tCP 25 ms
4 CD Input FSK to CD high delay tCA 8 ms
5 Hysteresis 8 ms
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.

AC Electrical Characteristics† - 3-Wire Interface Timing (Mode 0)

Characteristics Sym Min Typ‡ Max Units Notes*
1 Rise time tRR 200 ns into 50pF Load
2 DR Fall time tRF 200 ns into 50pF Load
3 Low time tRL 415 416 417 µs 2
4 Rate 1188 1200 1212 baud 1
DATA
5 Input FSK to DATA delay tIDD 1 5 ms
6 Rise time tR 200 ns into 50pF Load
7 DATA Fall time tF 200 ns into 50pF Load
DCLK
8 DATA to DCLK delay tDCD 6 416 µs 1, 2, 3
9 DCLK to DATA delay tCDD 6 416 µs 1, 2, 3
10 Frequency fDCLK0 1201.6 1202.8 1204 Hz 2
11 DCLK High time tCH 415 416 417 µs 2
12 Low time tCL 415 416 417 µs 2
13 DCLK DCLK to DR delay tCRD 415 416 417 µs 2
DR
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing.
*Notes:
1. FSK input data at 1200 ±12 baud.
2. OSC1 at 3.579545 MHz ±0.1%.
3. Function of signal condition.

AC Electrical Characteristics† - 3-Wire Interface Timing (Mode 1)

Characteristics Sym Min Max Units Notes
1 Frequency fDCLK1 1 MHz
2 DCLK Duty cycle 30 70 %
3 Rise time tR1 20 ns
4 DCLK, DCLK low set up to DR tDDS 500 ns
DR
5 DCLK low hold time after DR tDDH 500 ns
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.

5-69
MT88E43 Preliminary Information

tDCD tCDD

VHM
DATA VCT
VLM
tR tF

VHM
DCLK VCT
VLM
tCL tCH

tR tF

Figure 12 - DATA and DCLK Mode 0 Output Timing

tRF tRR

VHM
DR VCT
VLM
tRL

Figure 13 - DR Output Timing

start start start

stop stop stop
TIP/RING
(A/B) b7 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 b2 b3 b4 b5 b6 b7 1 0 b0 b1 b2
WIRES
tIDD

start start start

DATA b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2
stop stop stop
1/fDCLK0

DCLK
tRL
tCRD

DR

Figure 14 - Serial Data Interface Timing (MODE 0)

5-70
Preliminary Information MT88E43

VHM
DCLK
VLM

tR1

Figure 15 - DCLK Mode 1 Input Timing

word N word N+1

Demodulated
internal bit 7 stop start 0 1 2 3 4 5 6 7 stop
stream
tRL

DR ➀ ➁
1/fDCLK1
tDDS
tDDH
DCLK

DATA 6 7 0 1 2 3 4 5 6 7 0

word N-1 word N

➀ DCLK clears DR
➁ DCLK does not clear DR, so DR is low for maximum time (1/2 bit width)

Figure 16 - Serial Data Interface Timing (Mode 1)

5-71
MT88E43 Preliminary Information

Alerting Signal

Line Reversal

Ch. seizure Mark Data Packet Ring

A/B Wires
A B C D E F G

TRIGout Note 6
Note 1 Note 2

PWDN

tDP tDA
ESt 50-150ms

tGP tGA
St/GT VTGt
tREC
tABS Note 3
StD

15±1ms
TE DC load <120µµA
< 0.5mA (optional)
20±5ms Current wetting pulse (see SIN227)
TE AC load Zss (Refer to SIN227) Note 4

FSKen Note 5
tCP tCA
CD

A ≥ 100ms
DR B = 88-110ms
C ≥ 45ms (up to 5sec)
DCLK D = 80-262ms
E = 45-75ms
DATA ..101010.. Data F ≤ 2.5sec (typ. 500ms)
tPU tPD G > 200ms
OSCout Note: All values obtained
from SIN227 Issue 1

Figure 17 - Input and Output Timing for BT Caller Display Service (CDS), e.g., CLIP
Notes:
1) The total recognition time is t REC = t GP + tDP, where tGP is the tone present guard time and tDP is the tone present detect time (refer to section
“Dual Tone Detection Guard Time” on page 58 for details). V TGt is the comparator threshold (refer to Figure 4).
2) The total tone absent time is t ABS = tGA + t DA, where tGA is the tone absent guard time and tDA is the tone absent detect time (refer to section
“Dual Tone Detection Guard Time” on page 58 for details). V TGt is the comparator threshold (refer to Figure 4).
3) By choosing t GA=15ms, tABS will be 15-25ms so that the current wetting pulse and AC load can be applied right after the StD falling edge.
4) SIN227 specifies that the AC and DC loads should be removed between 50-150ms after the end of the FSK signal, indicated by CD returning to
high. The MT88E43 may also be powered down at this time.
5) FSKen should be set low when FSK is not expected to prevent the FSK demodulator from reacting to other in-band signals such as speech, tone
alert signal and DTMF tones.
6) TRIGout is the ring envelope during ringing.

5-72
Preliminary Information MT88E43

Ring Burst First Ring Cycle

Line Reversal

Ch. seizure Mark Data Packet

A/B Wires
A B C D E F
Note 3

TRIGout
Note 3
50-150ms

PWDN

250-400ms

TE DC load

TE AC load Note 1

FSKen Note 2
tCP tCA
CD
A = 200-450ms
DR B ≥ 500ms
C = 80-262ms
DCLK D = 45-262ms
E ≤ 2.5s (typ. 500ms)
F >200ms
DATA ..101010.. Data
tPU Note: Parameter F from
tPD
"CCA Exceptions
OSCout Document Issue 3"

Figure 18 - Input and Output Timing for CCA Caller Display Service (CDS), e.g., CLIP
Notes:
1) TW/P&E/312 specifies that the AC and DC loads should be removed between 50 to 150ms after the end of the FSK signal, indicated by CD
returning to high. The MT88E43 may also be powered down at this time.
2) FSKen should be set low when FSK is not expected to prevent the FSK demodulator from reacting to other in-band signals such as speech, and
DTMF tones.
3) TRIGout represents the ring envelope during ringing.

5-73
MT88E43 Preliminary Information

TIP/RING 1st Ring Ch. seizure Mark Data Packet 2nd Ring
A B C D E F

TRIGout

Note 4
PWDN Note 1 Note 3 Note 1
tPU
OSCout

tPD
FSKen Note 2 tCP
tCA

CD
A = 2sec typical
B = 250-500ms
DR C = 250ms
D = 150ms
E = feature specific
DCLK
Max C+D+E = 2.9 to 3.7sec
F ≥ 200ms
DATA .101010.. Data

Figure 19 - Input and Output Timing for Bellcore On-hook Data Transmission Associated with Ringing, e.g.,
CID
Notes:
This on-hook case application is included because a CIDCW (off-hook) CPE should also be capable of receiving on-hook data transmission (with
ringing) from the end office. TR-NWT-000575 specifies that CIDCW will be offered only to lines which subscribe to CID.
1) The CPE designer may choose to enable the MT88E43 only after the end of ringing to conserve power in a battery operated CPE. CD is not activated by
ringing.
2) The CPE designer may choose to set FSKen always high while the CPE is on-hook. Setting FSKen low prevents the FSK demodulator from
reacting to other in-band signals such as speech, CAS or DTMF tones.
3) The microcontroller in the CPE powers down the MT88E43 after CD has become inactive.
4) The microcontroller times out if CD is not activated.

5-74
Preliminary Information MT88E43

CPE unmutes handset

CPE goes off-hook CPE mutes handset & disables keypad and enables keypad
CPE sends
Mark Data
CAS ACK Packet
TIP/RING
Note 1 A B C D E F G
Note 5
PWDN

Note 2 Note 3 Note 4

FSKen
tPU
OSCout

tDP tDA

ESt
tGP tGA
VTGt
St/GT
tREC tABS

StD (Note 6)
Note 7 Note 8 tCP tCA
CD

A = 75-85ms
DR
B = 0-100ms
C = 55-65ms
DCLK D = 0-500ms
E = 58-75ms
F = feature specific
DATA
G ≤ 50ms
Data

Figure 20 - Input and Output Timing for Bellcore Off-hook Data Transmission, e.g., CIDCW
Notes:
1) In a CPE where AC power is not available, the designer may choose to switch over to line power when the CPE goes off-hook and use battery
power while on-hook. The CPE should also be CID (on-hook) capable because TR-NWT-000575 specifies that CIDCW will be offered only to
lines which subscribe to CID.
2) Non-FSK signals such as CAS, speech and DTMF tones are in the same frequency band as FSK. They will be demodulated and give false data.
The FSKen pin should be set low to disable the FSK demodulator when FSK is not expected.
3) FSKen may be set high as soon as the CPE has finished sending the acknowledgment signal ACK. TR-NWT-000575 specifies that ACK =
DTMF D for non-ADSI CPE, A for ADSI CPE.
4) FSKen should be set low when CD has become inactive.
5) In an unsuccessful attempt where the end office does not send the FSK signal, the CPE should unmute the handset and enable the keypad after
this interval.
6) SR-TSV-002476 states that it is desirable that the CPE have an on/off switch for the CAS detector. See SW1 in Figure 4.
7) The total recognition time is t REC = t GP + tDP, where tGP is the tone present guard time and tDP is the tone present detect time (refer to section
“Dual Tone Detection Guard Time” on page 58 for details). V TGt is the comparator threshold (refer to Figure 4).
8) The total tone absent time is t ABS = tGA + t DA, where tGA is the tone absent guard time and tDA is the tone absent detect time (refer to section
“Dual Tone Detection Guard Time” on page 58 for details). V TGt is the comparator threshold (refer to Figure 4).

5-75
MT88E43 Preliminary Information

Notes:

5-76
 For more information about all Zarlink products
visit our Web Site at

[Link]

Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.

This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.

Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Copyright Zarlink Semiconductor Inc. All Rights Reserved.

TECHNICAL DOCUMENTATION - NOT FOR RESALE