IS93C66-3

4,096-BIT SERIAL ELECTRICALLY

ISSI ®

ERASABLE PROM MARCH 2001

FEATURES OVERVIEW
• State-of-the-art architecture The IS93C66-3 is a low cost 4,096-bit, non-volatile, serial
— Non-volatile data storage E2PROM. It is fabricated using ISSI's advanced CMOS
— Low voltage operation: E2PROM technology. The IS93C66-3 provides efficient
3.0V (Vcc = 2.7V to 6.0V) non-volatile read/write memory arranged as 256 registers
— Full TTL compatible inputs and outputs of 16 bits each. Seven 11-bit instructions control the
— Auto increment for efficient data dump operation of the device, which includes read, write, and
mode enable functions. The data out pin (DOUT) indicates
• Low voltage read operation the status of the device during in the self-timed non-volatile
— Down to 2.7V programming cycle.
• Hardware and software write protection The self-timed write cycle includes an automatic erase-
— Defaults to write-disabled state at power-up before-write capability. To protect against inadvertent
— Software instructions for write-enable/disable writes, the WRITE instruction is accepted only while the
• Advanced low voltage CMOS E2PROM chip is in the write enabled state. Data is written in 16 bits
technology per write instruction into the selected register. If Chip
Select (CS) is brought HIGH after initiation of the write cycle,
• Versatile, easy-to-use interface
the Data Output (DOUT) pin will indicate the READY/BUSY
— Self-timed programming cycle status of the chip.
— Automatic erase-before-write
— Programming status indicator APPLICATIONS
— Word and chip erasable The IS93C66-3 is ideal for high-volume applications
— Stop SK anytime for power savings requiring low power and low density storage. This device
• Durable and reliable uses a low cost, space saving 8-pin package. Candidate
applications include robotics, alarm devices, electronic
— 10-year data retention after 100K write cycles
locks, meters and instrumentation settings.
— 100,000 write cycles
— Unlimited read cycles

FUNCTIONAL BLOCK DIAGRAM

DUMMY DOUT
DATA
BIT
REGISTER
(16 BITS)
INSTRUCTION
DIN REGISTER R/W
(11 BITS) AMPS

INSTRUCTION ADDRESS 1 OF 256 EEPROM

CS DECODE, REGISTER DECODER ARRAY
CONTROL,
AND (256 X 16)
CLOCK
SK GENERATION

WRITE HIGH VOLTAGE

ENABLE GENERATOR

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774 1

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PIN CONFIGURATION PIN CONFIGURATION PIN CONFIGURATION

8-Pin DIP 8-Pin JEDEC Small Outline “G” 8-Pin JEDEC Small Outline “GR”

CS 1 8 VCC NC 1 8 NC CS 1 8 VCC
SK 2 7 NC VCC 2 7 GND SK 2 7 NC
DIN 3 6 NC CS 3 6 DOUT DIN 3 6 NC
DOUT 4 5 GND SK 4 5 DIN DOUT 4 5 GND

PIN DESCRIPTIONS
CS Chip Select
SK Serial Data Clock
DIN Serial Data Input
DOUT Serial Data Output
NC Not Connected
Vcc Power
GND Ground

ENDURANCE AND DATA RETENTION Low Voltage Read

The IS93C66-3 is designed for applications requiring up The IS93C66-3 has been designed to ensure that data
to 100,000 programming cycles (WRITE, WRALL, ERASE read operations are reliable in low voltage environments.
and ERAL). It provides 10 years of secure data retention, The IS93C66-3 is guaranteed to provide accurate data
without power after the execution of 100,000 programming during read operations with Vcc as low as 2.7V.
cycles.
Auto Increment Read Operations
DEVICE OPERATION In the interest of memory transfer operation applications,
The IS93C66-3 is controlled by seven 11-bit instructions. the IS93C66-3 has been designed to output a continuous
Instructions are clocked in (serially) on the DIN pin. Each stream of memory content in response to a single read
instruction begins with a logical “1” (the start bit). This is operation instruction. To utilize this function, the system
followed by the opcode (2 bits), the address field (8 bits), asserts a read instruction specifying a start location
and data, if appropriate. The clock signal (SK) may be address. Once the 16 bits of the addressed word have
halted at any time and the IS93C66-3 will remain in its last been clocked out, the data in consecutively higher address
state. This allows full static flexibility and maximum locations (the address “000000” is assumed as the ad-
power conservation. dress of “111111") is output. The address will wrap around
continuously with CS HIGH until the chip select (CS)
Read (READ) control pin is brought LOW. This allows for single instruction
The READ instruction is the only instruction that outputs data dumps to be executed with a minimum of firmware
serial data on the DOUT pin. After the read instruction and overhead.
address have been decoded, data is transferred from the
selected memory register into a 16-bit serial shift register. Write Enable (WEN)
(Please note that one logical “0” bit precedes the actual The write enable (WEN) instruction must be executed
16-bit output data string.) The output on DOUT changes before any device programming (WRITE, WRALL, ERASE,
during the low-to-high transitions of SK (see Figure 3). and ERAL) can be done. When Vcc is applied, this device
powers up in the write disabled state. The device then

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remains in a write disabled state until a WEN instruction As with the WRITE instruction, if CS is brought HIGH after
is executed. Thereafter, the device remains enabled until a minimum wait of 250 ns (tCS), the DOUT pin indicates the
a WDS instruction is executed or until Vcc is removed. READY/BUSY status of the chip (see Figure 6).
(NOTE: Neither the WEN nor the WDS instruction has any
effect on the READ instruction.) (See Figure 4.) Write Disable (WDS)
The write disable (WDS) instruction disables all
Write (WRITE) programming capabilities. This protects the entire part
The WRITE instruction includes 16 bits of data to be against accidental modification of data until a WEN
written into the specified register. After the last data bit instruction is executed. (When Vcc is applied, this part
has been applied to DIN, and before the next rising edge of powers up in the write disabled state.) To protect data, a
SK, CS must be brought LOW. The falling edge of CS WDS instruction should be executed upon completion of
initiates the self-timed programming cycle. each programming operation. (NOTE: Neither the WEN
After a minimum wait of 250 ns (5V operation) from the nor the WDS instruction has any effect on the READ
falling edge of CS (tCS), if CS is brought HIGH, DOUT will instruction.) (See Figure 7.)
indicate the READY/BUSY status of the chip: logical “0” Erase Register (ERASE)
means programming is still in progress; logical “1” means
the selected register has been written, and the part is After the erase instruction is entered, CS must be brought
ready for another instruction (see Figure 5). (NOTE: The LOW. The falling edge of CS initiates the self-timed
combination of CS HIGH, DIN HIGH and the rising edge of internal programming cycle. Bringing CS HIGH after a
the SK clock, resets the READY/BUSY flag. Therefore, it minimum of tCS, will cause DOUT to indicate the READ/BUSY
is important if you want to access the READY/BUSY flag status of the chip: a logical “0” indicates programming is
not to reset it through this combination of control signals.) still in progress; a logical “1” indicates the erase cycle is
Before a WRITE instruction can be executed, the device complete and the part is ready for another instruction (see
must be write enabled (see WEN). Figure 8).

Write All (WRALL) Erase All (ERAL)

The write all (WRALL) instruction programs all registers Full chip erase is provided for ease of programming.
with the data pattern specified in the instruction. While the Erasing the entire chip involves setting all bits in the entire
WRALL instruction is being loaded, the address field memory array to a logical “1” (see Figure 9).
becomes a sequence of “Don’t Care” bits (see Figure 6).

INSTRUCTION SET
Instruction Start Bit OP Code Address Input Data
READ 1 10 (A7-A0)
WEN 1 00 11XXXXXX
(Write Enable)
WRITE 1 01 (A7-A0) D15-D0(1)
WRALL 1 00 01XXXXXX D15-D0(1)
(Write All Registers)
WDS 1 00 00XXXXXX
(Write Disable)
ERASE 1 11 (A7-A0)
ERAL 1 00 10XXXXXX
(Erase All Registers)
Note: 1. If input data is not 16 bits exactly, the last 16 bits will be taken as input data (a word).

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ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameter Value Unit
VGND Voltage with Respect to GND –0.3 tp +6.5 V
TBIAS Temperature Under Bias (IS93C46-3) 0 to +70 °C
TBIAS Temperature Under Bias (IS93C46-3I) –40 to +85 °C
TSTG Storage Temperature –65 to +125 °C
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 2.7V to 6.0V
Industrial –40°C to +85°C 2.7V to 6.0V

CAPACITANCE
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 5 pF
COUT Output Capacitance VOUT = 0V 5 pF

FIGURE 1. AC TEST CONDITIONS

+2.08V

800Ω

DOUT

100 pF
Vcc = 5.0V

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DC ELECTRICAL CHARACTERISTICS
TA = 0°C to +70°C for IS93C66-3 and –40°C to +85°C for IS93C66-3I.

Symbol Parameter Test Conditions Vcc Min. Max. Unit

VOL Output LOW Voltage IOL = 10 µA CMOS 2.7V to 3.3V — 0.2 V
VOL1 Output LOW Voltage IOL = 2.1 mA TTL 4.5V to 5.5V — 0.4 V
VOH Output HIGH Voltage IOH = –10 µA CMOS 2.7V to 3.3V VCC – 0.2 — V
VOH1 Output HIGH Voltage IOH = –400 µA TTL 4.5V to 5.5V 2.4 — V
VIH Input HIGH Voltage 2.7V to 3.3V 2.4 V CC V
4.5V to 5.5V 2 VCC
VIL Input LOW Voltage 2.7V to 3.3V –0.1 0.6 V
4.5V to 5.5V –0.1 0.8
ILI Input Leakage VIN = 0V to VCC (CS, SK, DIN) 1 1 µA
ILO Output Leakage VOUT = 0V to VCC, CS = 0V 1 1 µA

POWER SUPPLY CHARACTERISTICS

TA = 0°C to +70°C for IS93C66-3 and –40°C to +85°C for IS93C66-3I.

IS93C66-3 IS93C66-3I
Symbol Parameter Test Conditions Vcc Min. Typ. Max. Min. Typ. Max. Unit
ICC Vcc Operating CS = VIH, SK = 1 MHz 2.7V to 3.3V — 0.5 2 — 0.5 2 mA
Supply Current CMOS Input Levels
ICC Vcc Operating CS = VIH, SK = 1 MHz 4.5V to 5.5V — 4 6 — 4 6 mA
Supply Current CMOS Input Levels
ISB Standby Current CS = DIN = SK = 0V 2.7V to 3.3V — 2 10 — 2 10 µA
4.5V to 5.5V — 10 50 — 10 50

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AC ELECTRICAL CHARACTERISTICS
TA = 0°C to +70°C for IS93C66-3 and –40°C to +85°C for IS93C66-3.

IS93C66-3 IS93C66-3I
Symbol Parameter Test Conditions Vcc Min. Max. Min. Max. Unit
fSK SK Clock Frequency 2.7V to 6.0V 0 1 0 1 MHz
4.5V to 6.0V 0 1 0 1 MHz
tSKH SK HIGH Time 2.7V to 6.0V 500 — 500 — ns
4.5V to 6.0V 250 — 250 —
tSKL SK LOW Time 2.7V to 6.0V 1 — 1 — µs
4.5V to 6.0V 250 — 250 — ns
tCS Minimum CS LOW Time 2.7V to 6.0V 500 — 500 — ns
4.5V to 6.0V 250 — 250 —
tCSS CS Setup Time Relative to SK 2.7V to 6.0V 100 — 100 — ns
4.5V to 6.0V 50 — 50 — ns
tDIS DIN Setup Time Relative to SK 2.7V to 6.0V 200 — 200 — ns
4.5V to 6.0V 100 — 100 — ns
tCSH CS Hold Time Relative to SK 2.7V to 6.0V 0 — 0 — ns
4.5V to 6.0V 0 — 0 —
tDIH DIN Hold Time Relative to SK 2.7V to 6.0V 400 — 400 — ns
4.5V to 6.0V 100 — 100 —
tPD1 Output Delay to “1” AC Test 2.7V to 6.0V — 500 — 500 ns
4.5V to 6.0V — 500 — 500
tPD0 Output Delay to “0” AC Test 2.7V to 6.0V — 500 — 500 ns
4.5V to 6.0V — 500 — 500
tSV CS to Status Valid AC Test, CL = 100 pF 2.7V to 6.0V — 500 — 500 ns
4.5V to 6.0V — 500 — 500
tDF CS to DOUT in 3-state CS = VIL 2.7V to 6.0V — 200 — 200 ns
4.5V to 6.0V — 100 — 100
tWP Write Cycle Time 2.7V to 6.0V — 10 — 10 ms
4.5V to 6.0V — 10 — 10

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AC WAVEFORMS

FIGURE 2. SYNCHRONOUS DATA TIMING

CS
T
tCSS tSKH tSKL tCSH

SK

tDIS tDIH

DIN

tPD0 tPD1 tDF

DOUT
(READ)

tSV tDF
DOUT
(WRITE) STATUS VALID
(WRALL)
(ERASE)
(ERAL)

FIGURE 3. READ CYCLE TIMING

tCS

CS

SK

DIN 1 1 0 A5 A0

DOUT 0 D15 D0
*

*Address Pointer Cycles to the Next Register

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FIGURE 4. SYNCHRONOUS DATA TIMING

tCS

CS

SK

DIN 1 0 0 1 1

DOUT = 3-state

FIGURE 5. WRITE (WRITE) CYCLE TIMING

tCS

CS

SK

DIN 1 0 1 A5 A0 D15 D0

tSV tDF
DOUT BUSY READY

tWP

FIGURE 6. WRITE ALL (WRALL) TIMING

tCS

CS

SK

1 0 0 0 1 D15 D0
DIN
tSV

DOUT BUSY READY

tWP

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FIGURE 7. WRITE DISABLE (WDS) CYCLE TIMING

tCS

CS

SK

1 0 0 0 0
DIN

DOUT = 3-STATE

FIGURE 8. ERASE (REGISTER ERASE) CYCLE TIMING

SK

tCS

CS

DIN 1 1 1 A5 A4 A0

tSV tDF
DOUT BUSY READY

tWP

FIGURE 9. ERASE ALL (ERAL) CYCLE TIMING

SK

tCS

CS

DIN 1 0 0 1 0

tSV tDF
DOUT BUSY READY

tWP

Note for Figures 8 and 9:

After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT
indicates BUSY status) then performs another instruction would cause device malfunction.

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ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (MHz) Order Part No. Package
1 IS93C66-3P 300-mil Plastic DIP
1 IS93C66-3G Small Outline (JEDEC)
1 IS93C66-3GR Small Outline (JEDEC)

Industrial Range: –40°C to +85°C

Speed (MHz) Order Part No. Package
1 IS93C66-3PI 300-mil Plastic DIP
1 IS93C66-3GI Small Outline (JEDEC)
1 IS93C66-3GRI Small Outline (JEDEC)

ISSI ®

Integrated Silicon Solution, Inc.

2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@[Link]
[Link]

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