2nd Reading

May 27, 2023 14:55 WSPC/123-JCSC 2330005

Journal of Circuits, Systems, and Computers

Vol. 32, No. 15 (2023) 2330005 (41 pages)
by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

c World Scientific Publishing Company

DOI: 10.1142/S0218126623300052

A Comprehensive Study of Different

Techniques for Voltage References∗

Komal Duggal
Department of Electronics and Communication Engineering,
Indira Gandhi Delhi Technical University for Women,
J CIRCUIT SYST COMP Downloaded from [Link]

New Delhi 110006, India

kommalduggal@[Link]

Rishikesh Pandey†
Department of Electronics and Communication Engineering,
Thapar Institute of Engineering and Technology,
Patiala 147004, Punjab, India
riship23@[Link]

Vandana Niranjan
Department of Electronics and Communication Engineering,
Indira Gandhi Delhi Technical University for Women,
New Delhi 110006, India
vandana niranjan@[Link]

Received 13 August 2022

Accepted 5 March 2023
Published 29 May 2023

In the analog and mixed-signal integrated circuits, voltage references that are indepen-
dent of various factors such as temperature drift, noise, supply voltage, etc., and efficient
in terms of power as well as area, are highly in demand to improve the efficiency of the
overall circuits. Voltage references are one of those circuits that have applications in both
high-power systems and low-power system-on-chip (SoC) designs for wireless connectiv-
ity like the internet of the things (IoT) or the internet of the medical things (IoMT).
They are responsible for providing a stable bias or reference voltage. Thus, voltage ref-
erence influences directly or indirectly the performance of these systems. A comparative
study between the techniques used in bandgap voltage references and CMOS voltage
references, in terms of performance parameters such as line sensitivity, output noise,
PSRR, temperature coefficient, etc., is presented in this paper so that we can choose the
voltage references as per the applications and environment.

Keywords: CMOS; current mode; curvature compensation; PSRR; temperature coeffi-

cient; voltage mode; line sensitivity; voltage reference.

∗ This paper was recommended by Regional Editor Guiseppe Ferri.

† Corresponding author.

2330005-1
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

1. Introduction
The voltage reference (VR) is a versatile module that can be used in a vast variety
of applications in basic very large-scale integration circuits,1 like low drop-out reg-
ulators,2 comparators,3 amplifiers, analog to digital converters,4 phase lock loops,
filters, DC–DC converters as well in wearable5 or implantable medical devices,6
portable battery-operated devices,7 RF power systems,8 radio frequency identifica-
tion tags,9 internet of the things (IoT) systems,10 etc. VRs are intended to make
a constant voltage that is independent of change in process, supply voltage, and
temperature (PVT).11
The simplest approach to produce a VR is to force the current through a p–n
junction diode.12 However, diode-based VRs have low stability over temperature
J CIRCUIT SYST COMP Downloaded from [Link]

variations and suffer from wide process variations. The fundamental VR utilizes
a Zener or avalanche diode which works in a reverse-bias mode and the perfor-
mance of these diodes is stable over the temperature.13 Noise is the main prob-
lem with breakdown diodes, especially avalanche noise,14 which affects the devices
whose breakdown voltage is higher than 5V.15 To reduce noise considerably while
improving long-term stability, a buried structure with the Zener diode is used.
Although buried Zener diodes provide excessive overall performance, however, it
requires a supply voltage above 6 V, so their major drawback is the high supply
voltage requirement.16 This makes buried Zener diodes unsuitable for low-voltage
(LV)/low-power (LP) applications.
Bandgap reference (BGR) implemented in bipolar technology is classic and most
popular in the family of VRs. In 1971, Widlar proposed the first BGR,17 thereafter
several bandgap VRs have been stated in the literature for diverse applications.
With the advancement in CMOS technology, most applications operate with low
supply voltage like the IoT, internet of the medical things (IoMT), battery-operated
devices, etc.18 These systems usually consume nanowatts of power because of the
limited energy sources.19 To save energy, the power of their VR circuits should be
reduced to a pico-watt level,20 and the area of the reference circuit must also be
minimized for these applications.21 Thus, all MOS transistor-based VRs are also
gaining popularity.

Fig. 1. Reference voltage generation.26

2330005-2
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

The basic principle of VR is a linear combination of two voltages to produce

a constant voltage for temperature fluctuations.22 These voltages are diode/BJT’s
base-emitter voltage that exhibits a complement to absolute temperature (CTAT)
nature, and a thermal voltage that exhibits a proportional to absolute temperature
(PTAT) nature.23 As depicted in Fig. 1, if the CTAT voltage (VCTAT ) is accurately
balanced using the PTAT voltage (VPTAT ), then the sum of both would be persistent
across the temperature variation for the wide range.24 The output reference voltage
(VREF )25 can be stated by Eq. (1)

VREF = VCTAT + kV PTAT . (1)

The performance of VR circuits can be assessed using some of the common

J CIRCUIT SYST COMP Downloaded from [Link]

parameters like temperature coefficient (TC), power supply rejection ratio (PSRR),
line sensitivity (LS), and output noise which are defined as follows:

• TC reflects the temperature sensitivity,27 usual, most of the process parameters

are also varied with temperature, thus if the reference voltage is insensitive to
temperature variation then it’s generally process-independent as well.28 The unit
of TC is ppm/◦ C.
• PSRR: At the specified frequencies, PSRR estimates the capability of reference
circuits to discard the noise in the power supply and other unwanted signals.29
So PSRR is generally indicated in dB. VR circuits must have a high PSRR for
stable reference voltage generation.30
• LS: The VR not only desires to have a low-TC but also should not vary according
to the supply voltage to be used as a standard reference voltage.31 Thus, another
important performance parameter is LS, which measures the change in reference
voltage due to DC supply voltages.32 Unit of LS is %/V. VR circuits must have
low LS for stable reference voltage generation.33 The parameter LS34 is defined
by Eq. (2)
ΔV REF
LS = × 100%, (2)
ΔV DD × VREF,μ
where ΔVDD represents the supply voltage range of the operation, ΔV REF is a
difference in maximum VREF to minimum VREF , and VREF,μ represents the mean
value of reference voltage.34

• Output noise: Output noise is another efficiency parameter depending on the

frequency of the VR circuit.35 In addition to noise in the power supply, the noise
at the output of the circuit can be generated internally.36 In certain applications,
the VR circuitry should consider noise performance as the reference voltage is
impaired by flicker noise and thermal noise.37 For low-frequency systems such
as voltage regulators, circuit output noise can be defined as the peak-to-peak
voltage in the 0.1–10 Hz bandwidth. For higher frequency systems, the output
noise can be specified as the root mean square value in microvolts over the 10–
20 kHz bandwidth. Actually, the best way to specify high-frequency noise is to

2330005-3
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

√
display a graph of noise voltage spectral density in nV/ Hz with respect to
the frequency which enables the design engineer to compute the reference noise
according to the bandwidth of the system.38

Some other parameters are also there, which are important to achieve a VR in an
integrated chip (IC), like power consumption, device mismatch, supply voltage, size
of the circuit, noise, ease of output trimming, etc.39 These parameters are salient in
the performance of VRs, but still, for better performance, we cannot compromise
the initial accuracy.
The following sections are included in this paper: The VR classification is
addressed in Sec. 2. Classical VR topologies are discussed in Sec. 3. BGR tech-
niques are presented in Sec. 4, including the principle of operation, main advan-
J CIRCUIT SYST COMP Downloaded from [Link]

tages, disadvantages, and a literature survey of BGRs. Section 5 presents all MOS
transistor-based VRs. Section 6 focuses on gaps in research and future directions
for VR. Finally, the conclusion of the VR survey is outlined in Sec. 7.

2. Classification of VRs
VRs can be classified according to their performance, technology used, terminology,
applications, techniques, and components used in it. There are different architec-
tures for obtaining reference voltage at the output terminal. According to that, VRs
are divided into voltage mode and current mode VRs.40 When PTAT voltage and
CTAT voltage are added to the voltage domain then this approach is known as volt-
age mode.41 In the current mode approach, a current is produced by the summation
of PTAT current and CTAT current. Then, the reference voltage is generated by
converting current to voltage with a resistance.42 Some architecture does not use
any passive resistor to produce reference voltage and the output voltage depends
on device characteristics.43
VR circuits can be categorized into two types according to the type of component
used i.e., BGR and all MOS-based VRs.44

• BGR: This is the classical approach to VRs. As its name says it generates ref-
erence voltage related to the silicon bandgap energy or a fraction of it.45 In
this approach, the reference voltage is the addition of two voltages or currents
with different TCs where one or more voltages or currents are produced through
BJT.46 Traditional bandgap VRs offer reference voltage around 1.25 V47 which
requires a higher supply voltage (VREF < VDD ).48 So reverse BGR, sub-BGR,
and hybrid circuits come into existence for low supply voltage applications.
• All MOS transistor-based VR: To generate a reference voltage, all MOS
transistor-based VR uses only MOS transistors in the circuit.49 The bipolar and
MOS transistors exhibit a similar behavior if the MOS transistors operate in the
subthreshold region.50 So for generating PTAT and CTAT voltages, subtraction
of threshold voltages of MOS transistors or weighted difference of gate–source
voltages of MOS structure are used.51

2330005-4
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

To achieve a VR that does not depend on absolute temperature, topologies are

normally classified as follows:
• PTAT + CTAT approach: PTAT behavior which has a positive TC and CTAT
behavior which has a negative TC are added to produce a zero TC so it is called
the PTAT+CTAT approach.52 Some methods used a square of PTAT behavior
instead of generating only one PTAT behavior in the PTAT+CTAT approach.53
In addition, some methods used subtraction of two CTAT behaviors54 instead of
generating only one CTAT behavior in the CTAT+PTAT approach.
• CTAT-CTAT approach: Reference voltage with TC close to zero can be produced
through the subtraction of two voltages/currents which exhibit similar tempera-
ture behaviors.55 Therefore, if two CTAT voltages/currents are subtracted it is
J CIRCUIT SYST COMP Downloaded from [Link]

called the CTAT-CTAT approach.56 Only few researchers have worked on this
approach and this approach is available for MOS transistor based VRs.
If two PTAT voltages/currents are subtracted for generating a near-to-zero TC,
then it is called the PTAT-PTAT approach.57
For improvement in TC for a wide range of temperatures and to reduce the
nonlinearities, temperature compensation techniques are used.58 According to the
temperature compensation technique, VRs are also classified as first-order, second-
order, or higher order.59 First-order compensation techniques are usually limited by
the nonlinear component.60 Therefore several higher-order temperature compensa-
tion techniques are developed to reduce or eliminate the nonlinearities.61 Many
temperature compensation techniques exist, such as piecewise compensation,62
piecewise-linear curvature correction,63 exponential curvature compensation,64 cur-
vature compensation,65 segmented curvature temperature compensation,66 square
curvature compensation,67 adjusted temperature curvature compensation,68 resis-
tance compensation with different TCs, etc. Trimming techniques are also widely
used in the VR design for better TC and accuracy.69 After the fabrication of ICs
process variations can occur especially for MOS operating in subthreshold regions
which can affect the performance of ICs.70 Therefore by adding the trimming func-
tion, the reference voltage can be made to have a stable reference voltage regardless
the process variation.71

3. Classical VR Topologies
3.1. Widlar’s BGR
One of the first temperature-compensated VR circuits was proposed by Robert
Widlar in 1971. It is well known as Widlar’s BGR.17 The Widlar’s BGR circuit was
realized with the conventional bipolar technology as shown in Fig. 2. For generating
a zero TC reference voltage, the circuit utilized the negative TC by the emitter–base
voltage of Q3 in addition to the positive TC by the difference between transistors
Q1 and Q2 emitter–base voltages, illustrated in Eq. (3). Transistors Q1 and Q2 are
working in different current densities i.e., transistor Q1 has a higher current density

2330005-5
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.
J CIRCUIT SYST COMP Downloaded from [Link]

Fig. 2. Widlar’s BGR.17

as compared to transistor Q2 . The Widlar’s BGR circuit produces a stable, low TC

reference voltage at 1.23V
R2
Vref = VBE + ΔVBE . (3)
R3

3.2. Banba’s VR
Banba’s architecture is the most common among industries as well as academic
researchers. In the basic principle of a VR, the reference voltage Vref is the addition

Fig. 3. VR presented by Banba et al.72

2330005-6
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

of the thermal voltage VT i.e, PTAT voltage, and diode’s built-in voltage Vf i.e,
CTAT voltage, in which CTAT voltage is precisely compensated by using PTAT
voltage. Consequently, Vref is approximately 1.25 V, which restricts LV operation
below 1 V. Banba et al.72 present a sub-1 V circuit that is very popular among
researchers and one of the basic circuits for sub-1 V design. Figure 3 illustrates
Banba et al. current-mode VR, which performs the addition of the two currents
proportional to Vf and VT . The output voltage Vref is shown in Eq. (4)

 
V f 1 dV f
Vref = R4 + . (4)
R2 R3
J CIRCUIT SYST COMP Downloaded from [Link]

3.3. 2T VR
For ultra-low power systems like miniature sensor systems, where small chip area,
and low functional supply voltage are key requirements, Seok et al.73 introduce a
2T VR without amplifier and resistors as shown in Fig. 4.
In this design, two sub-threshold biased devices with different threshold voltage
levels are utilized. A native device is used in the M1 transistor and a thick oxide
device is used in the M2 transistor, for realizing a stable reference voltage. Native
devices are the same as a standard MOSFET but have an almost zero voltage
threshold. The reference voltage is shown in Eq. (5)

 
m1 m2 m1 m2 μ1 Cox1 W1 L2
Vref = (Vth2 − Vth1 ) + VT In , (5)
m1 + m2 m1 + m2 μ2 Cox2 W2 L1

where m represents the subthreshold slope factor m = 1 + Cd /Cox where Cd and

Cox are depletion capacitance and oxide capacitance, respectively.

Fig. 4. VR reported by Seok et al.73

2330005-7
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

4. BGR
BGRs are the most popular in the family of VRs. Basic elements usually used for
BGR circuit generations are BJTs, diodes, resistors, and MOSFETs.74 Conven-
tional bandgap VR performs the addition of two voltages that have different TCs
i.e., emitter–base voltage (VEB ) of BJT which indicates CTAT behavior, and a ther-
mal voltage which indicates PTAT behavior.75 BGR produces a reference voltage
approximately the same as the silicon band gap voltage i.e., 1.25 V76 which means
normally it requires a higher supply voltage than 1.25 V.77 BGR is the summation
of two voltages or currents with different TCs i.e., PTAT and CTAT,78 where at
least one PTAT or CTAT behavior is generated by BJT. Many advantages can be
obtained by using BGRs i.e., it offers accurate reference voltage and is very less
J CIRCUIT SYST COMP Downloaded from [Link]

sensitive to process variation.79 On the other hand, some drawbacks come with
the BGRs technique as BGRs utilized the BJTs which cause bulk leakage current
loss and this can affect the circuit performance,80 the presence of BJT or resistor
complicates the circuits with multiple BGR branches so it requires a larger area81
and power consumption will be high.82 So the cost of a BGR chip will be high,83
the resistances mismatch may affect the accuracy, and operational amplifiers are
often needed, which can also cause stability problems.84
As technology grows the demand for low-supply systems which can work on 1 V
or below, is increased.85 Therefore, BGR may be divided into reverse BGR and
sub-BGR for low-supply voltage applications. All these approaches are commonly
known by BGR only.

• Reverse bandgap: In the reverse bandgap voltage method, in place of the sum-
mation of a VBE i.e., base-emitter voltage to a scaled thermal voltage VT , it will
perform the addition of a thermal voltage VT to scaled voltage VBE .86
• Sub-bandgap: In sub-bandgap VR circuits, the reference voltage is lower than
1.25 V.87 Sub-BGRs are very popular as these circuits can reduce the supply
voltage and power dissipation effectively.88

4.1. Literature survey: A comparative analysis using the strategies

of the BGRs
This section provides a comparative study from the year 2011 to 2022 applying
various BGR techniques or methods, for accuracy, low voltage, and temperature
stability.

4.1.1. PTAT + CTAT approach

Zhao et al.89 suggested the BGR circuit shown in Fig. 5. The circuit contains
a PTAT current generator, a start-up circuit, and CTAT current generator. For
high PSRR, a high-precision CMOS amplifier with a self-bias circuit and miller
compensation is used, in a PTAT current generation.

2330005-8
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.
J CIRCUIT SYST COMP Downloaded from [Link]

Fig. 5. VR suggested by Zhao et al.89

From the circuit diagram it can be seen that Vref can be generated by combined
I10 which PTAT current and IDM9 which is CTAT current, together through R2 as
shown in Eq. (6)
 
VT ln(n) VGS3 (T0 ) + [VGS3 (T0 ) − VT H (T0 ) + KT ][ T0 −1]
T
Vref = R2 + .
R1 R0
(6)
Here KT is the TC of the threshold voltage and KT < 0, VGS3 is the gate souse
voltage of M3 transistor, T0 is the operating temperature. By adjusting the output
resistor, the proposed BGR can provide different reference voltages of 1.66 V and
825 mV, respectively, at the supply voltage of 3.5 V. Based on the experimental
results TC is 48.7 ppm/◦ C between −10 and 100◦ C, and PSRR is 76 dB in the
low-frequency range. However, the circuit operates at 3.5 V supply voltage and uses
an amplifier as well as resistors, resulting in increased power consumption. The
temperature range is also not good.
To cancel the nonlinear temperature dependencies of the first-order current
mode BGR, Li et al.90 proposed a VR, as shown in Fig. 6. The circuit contains
a start-up circuit to prevent an unwanted “zero” current state when the power
is provided, a first-order conventional BGR which produces a reference voltage
with a slightly negative TC, and a piecewise curvature corrected current generator
(PCCCG) is used to correct the nonlinear temperature dependencies as depicted

2330005-9
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.
J CIRCUIT SYST COMP Downloaded from [Link]

Fig. 6. VR proposed by Li et al.90

Fig. 7. Concept of piecewise nonlinear curvature corrected BGR used by Li et al.90

in Fig. 7. Negative feedback is achieved by using the operational rail amplifier

biased by PTAT current. The circuit attains a TC of 8.9 ppm/◦ C at TR between
−40 and 110◦ C without trimming. The output voltage is the sum of the first-order
conventional BGR voltage and the voltage which is generated through the PCCCG,
is given by Eq. (7)
 
VBE VT l(n)
VREF = + (R3 + R4 ) + INL R4 . (7)
R1 R2

For further improvement of the TC and low power consumption, Zhu et al.91
reported a resistor-less VR with second-order temperature compensation. The
design has four parts i.e., setup circuit is needed to restore the circuit to the
desired state, a PTAT circuit which is operating as the first-order temperature

2330005-10
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.
J CIRCUIT SYST COMP Downloaded from [Link]

Fig. 8. VR reported by Zhu et al.91

compensation, a voltage divider that can attain the second-order temperature

compensation, and output of the reference as depicted in Fig. 8. The reference
voltage is represented by Eq. (8)
1 √
VREF = Veb3 + AGVT ln N. (8)
3
Here, VT represents the thermal voltage, and A and G are the scale factors by
proper scaling then leads to temperature compensation. N represents the ratio of
the emitter area of the bipolar transistor Q1 to the emitter area of the bipolar
transistor Q2 . The circuit attains TC of 3.02 ppm/◦ C for TR between −20 and
120◦ C. Second-order temperature compensation is archived by a voltage divider to
enhance the TC.
For an extensive range of temperature, Andreou et al.92 introduced a simple
method by using poly-silicon resistors to enhance curvature compensation which
is realized with the help of a second op-amp as depicted in Fig. 9. This circuit
features a folded-cascode amplifier rather than two simple op-amps. The circuit
works on the current mode topology. PTAT current IPTAT is produced by the
transistor Q2 and Q1 through a resistor R1 and ICTAT is generated by transistor
Q1 across the resistance R2 , then these two currents are added to get a steady
reference voltage across the resistor R3 but it compensates only the linear term. So
to compensate for remaining nonlinearities to get the accurate reference voltage, a
current proportional to the nonlinearities voltage VNL has to be subtracted from
node D with the help of poly-silicon resistors R4 and R5 as illustrated in Eq. (9).
The TC of the circuit is 3.9 ppm/◦ C over a TR of −15 − 150◦C and for an extended
TR from −50◦ C to 150◦C, the TC is 13.7 ppm/◦ C. The circuit is susceptible to
mismatch variations of the resistors R4 and R2 . Consequently, appropriate trimming
is performed after fabrication to maintain performance. The architecture works for

2330005-11
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.
J CIRCUIT SYST COMP Downloaded from [Link]

Fig. 9. VR suggested by Andreou et al.92

a wide TR, but it increases the power consumption and chip area
ΔVBEQ12 R3 VBEQ1 R3 VNL R3 VNL R3
VREF = + − + . (9)
R1 R2 R4 R5
For high precision BGR, Yin et al.93 utilized an exponential curvature com-
pensation technique to propose a new VR. The circuit contains 5 sub-circuits i.e.,
bias circuit which is intended to provide bias current, an error amplifier that pro-
vides negative feedback, PTAT current generating circuit, a start-up circuit, and
an exponential curvature-compensation circuit which serves to compensate for the
nonlinear output voltage term. For low supply applications, Osaki et al.94 proposed
two resistor-less circuits in which one is using a 1.2 V supply known as BGR and
another uses less than 1.2 V called sub-BGR. The BGR circuit is made up of a start-
up circuit, current reference, and PTAT generator as depicted in Fig. 10, whereas
the sub-BGR circuit consists extra voltage divider as compared to BGR. To reduce
power consumption and area, these circuits do not use a passive resistor and con-
sist of a single BJT in the whole MOSFET structure. The results depict that the
power dissipation of sub-BGR is less. However, the TC has to be improved for both
circuits.
Ma et al.95 presented a higher-order curvature compensation technique for BGR.
In this technique, MOS-based VR and traditional BJT BGR circuits are utilized
to create reference voltage as depicted in Fig. 11. Since MOS-based VR and BJT-
based BGR have opposite second-order TC, second-order TC can be removed by
summation of these outputs. Therefore, the reference voltage consists of three parts
as shown in Eq. (10). The first part is the difference in base–emitter voltage of

2330005-12
 J CIRCUIT SYST COMP Downloaded from [Link]
by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.
May 27, 2023 14:55 WSPC/123-JCSC

Fig. 10.

Fig. 11.
2330005

2330005-13
VR presented by Ma et al.95
VR proposed by Osaki et al.94
2nd Reading

A Comprehensive Study of Different Techniques for Voltage References

 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

the two BJTs i.e., Q1 and Q2 . The second part is the base–emitter voltage of the
bipolar transistor Q1 . The third part is the difference in gate–source voltage of the
two MOSFETs i.e., MW1 and MW2 , operating in a weak inversion region

Vref = R4 (2(IPTAT + INEG ) + ICOMP ), (10)

 
2ΔVBE 2VBE ΔVGS
Vref = R4 + + . (11)
R1 R3 R2

The circuit achieves a TC of 4.5 ppm/◦ C between the TR of −40 and 120◦ C at
a supply voltage of 1.2 V. But the whole circuit consists of six passive resistors
which lead to high power consumption. Geng et al.96 presented the higher-order
curvature-corrected VR which uses n-poly and n-well resistors with the opposite
J CIRCUIT SYST COMP Downloaded from [Link]

TC to correct the BGR curvature error. But the structure is complex as well as
needed to improve the PSRR.
For reduction in power consumption, Mattia et al.97 proposed a resistor less
nano-watt sub-BGR. This circuit includes self-cascode PTAT generator in which
several PTAT cells can be cascaded for high-temperature derivatives. So the circuit
consists of BJT biased, and self-cascode PTAT generator with two PTAT cells as
depicted in Fig. 12. The reference voltage is shown in Eq. (12)
VE
Vref = + VPTAT . (12)
n+1
Here, n is the subthreshold factor and VE is the emitter voltage of Q1 transis-
tor. TC of 8 ppm/◦ C for the 0–125◦C range is attained by the circuit, with the
power consumption of the whole circuit is 8.25 nW under a 0.75 V power supply
at 27◦ C. However, the PSRR and area have to be improved for the circuit. Mattia
et al.98 modified the circuit for further improvement in the area consumed by the
√
circuit. The output noise of the circuit at 100 Hz is 2.9μ V Hz. However, area is

Fig. 12. VR reported by Mattia et al.97

2330005-14
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

reduced from 0.0043 mm2 to 0.0022 mm2 but TC and supply voltage are increased
as compared to Ref. 97.
Wang et al.99 proposed a high accuracy and ultra-power VR which utilized BJT
itself to reduce the nonlinearities. Neri et al.100 utilized unconventional design tech-
niques for start-up circuits i.e., a combination of extended gate metal-oxide semi-
conductor (EGMOS) and laterally-diffused metal-oxide-semiconductor (LDMOS).
This circuit contains a start-up circuit, OTA, and a cascaded current mirror buffer.
A trimming circuit is also included for process compensation. But TC is 33 ppm/◦ C
which is not as good as previous BGRs.
For more stability and further improvement in TC, Caicedo et al.101 introduced
a curvature compensated sub-BGR based on Ref. 102 as depicted in Fig. 13. But
J CIRCUIT SYST COMP Downloaded from [Link]

this structure is also similar to Ref. 97. Only the curvature compensation circuit and
start-up circuit with op-amp are included in Ref. 101 as compared to Ref. 97. TC of
the circuit is 5 ppm/◦ C for the TR between −40 and 125◦ C. The power consumed
by the circuit is 16.3 nW at a supply voltage of 0.75 V. The results highlight that
the circuit has a wide TR and consumes less power.
Wang et al.103 proposed a sub-BGR circuit for LP and LV applications. In this
design, a vertical PNP BJT and two resistors perform the CTAT characteristic.
For PTAT voltage generation two cascaded sub-PTAT circuits are used. But the
trimming circuit is used for PTAT voltage instead of CTAT.
For low power and voltage application, Gupta et al.104 presented a resistor-less
architecture of BGR, which consists of MOSFET and only one BJT. For stable
and temperature insensitive reference voltage, Ming et al.105 utilized the voltage
step compensation technique which cancels step-by-step thermal nonlinearities of
the diode voltage and the supply noise by passing technique (SNBP) for better
performance PSRR. The circuit has three parts i.e., a BGR core, two self-biased
current references with different TC, and a two-bit trim circuit as illustrated in
Fig. 14. The circuit produces a 1.196 V output voltage with a TC of 3.98 ppm/◦ C at

Fig. 13. VR suggested by Caicedo et al.101

2330005-15
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

Fig. 14. VR presented by Ming et al.105

a 3.6 V supply voltage. The circuit line regulation is 0.19 mV/V with 2.1–5 V supply
J CIRCUIT SYST COMP Downloaded from [Link]

voltage. The results indicate that the circuit has better temperature stability and
less noise, but may not be appropriate for LP applications in terms of TC and
power dissipation.
Lei et al.106 utilized a temperature compensation amplifier to calibrate the tem-
perature curve of reference voltage by adding extra positive voltage. The circuit has
a start circuit, PNP bipolar transistor for base–emitter voltage, a temperature com-
pensation amplifier to realize the trim function, and a PTAT generator illustrated
in Fig. 15. The results indicate that circuit performance is noteworthy in terms
of power consumption i.e., the circuit consumes nanowatt power, but the TC is
36.6 ppm/◦ C.
Ma et al.107 focus on the noise which is mostly introduced by operational ampli-
fiers in the output reference voltage, so they proposed a VR by utilizing the chopper
stabilization technique which significantly suppresses the noise. Que et al.108 used
an unconventional technique i.e., an extra PTAT2 current is added, to obtain a low
TC. In this technique, instead of only PTAT in the CTAT+PTAT method, they

Fig. 15. VR reported by Lei et al.106

2330005-16
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

VR proposed by Que et al.108

J CIRCUIT SYST COMP Downloaded from [Link]

Fig. 16.

used PTAT+PTAT2 where the PTAT2 circuit serves to reduce the TC and piece-
wise compensation is introduced by PTAT+PTAT2 as illustrated in Fig. 16. The
output of the circuit is shown in Eq. (13)
VBGR = VBE3 + R2 (IPTAT + IPTAT2 ). (13)
Here, VBE3 is the base–emitter voltage of Q3 transistor.
Experimental outcomes indicate a remarkable performance of the circuit in
terms of TC, and PSRR i.e., TC of 8.83 ppm/◦ C is attained with −40 − 125◦ C
TR and PSRR of 83 dB at 10 Hz is realized, however, it works with the 3.3 V sup-
ply voltage.
Liu et al.109 used a twice curvature compensated method in which two different
methods are used to compensate the reference voltage for better temperature stabil-
ity and PSRR. The proposed architecture consists of four parts i.e., start-up circuit,
first-order current mode BGR, and two temperature curvature compensation cir-
cuits. First-order current mode BGR uses folded cascade structure and provides a
first-order reference current after this current is compensated by a primary temper-
ature curvature compensation circuit. Under the same doping concentration, the
curvature of the N-type doped resistance is slightly lower than that of the P-type
doped resistance; therefore, P-type doped resistor R7 is used to complete the sec-
ondary curvature compensation. The circuit TC is 1.5 ppm/◦ C in a TR between
−40 and 120◦C, and the LS of the circuit is 0.05%/V. But the circuit used N-doped
and P-doped resistors which affects the power consumption and area.
Zhang et al.110 proposed a highly accurate, low temperature-coefficient VR using
a piece-wise compensation circuit and digital trimming. The results indicated that
the circuit worked very well in terms of TC and TR. But the circuit is complex.
For lower TC and higher PSRR, Liu et al.111 utilized the zero TC of MOSFET
(ZTC-MOS) for high-order curvature compensation. The circuit is made up of a
first-order BGR to provide convex current, a start-up circuit to remove the zero
operating point, the bias for the OTA block to provide the bias voltage, and the
compensation circuit which includes ZTC-MOS and trimming MOS as depicted in

2330005-17
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.
J CIRCUIT SYST COMP Downloaded from [Link]

Fig. 17. VR reported by Liu et al.111

Fig. 17. The circuit offered a low TC and attains −91.4 dB PSRR. However, the
power consumed by the circuit is moderate as the core circuit is conventional BGR.
Huang et al.112 presented a high-precision BGR, which utilized a combination
of MOSFETs, and BJTs for generating the high-order compensation current to
nullify the nonlinear term present in VBE . The circuit is made up of a bias circuit
that generated the bias current, a higher order compensation circuit in which the
compensation current ICOMP is generated by the I1 and I2 currents, and a bandgap
core circuit to generate the reference voltage in which I3 current behaves as PTAT
current and VBE of Q6 behaves as a CTAT voltage as depicted in Fig. 18. The
circuit performs effectively in terms of TC i.e., 0.706 ppm/◦ C and TR from −25◦ C
to 125◦ C. However, it works with 3.3 V supply.

Fig. 18. VR presented by Huang et al.112

2330005-18
 J CIRCUIT SYST COMP Downloaded from [Link]
by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

Table 1. Summarization of distinguished work of BGRs (2018–2022).

Ref. → Parameters ↓ Ref. 103 Ref. 105 Ref. 106 Ref. 108 Ref. 109 Ref. 110 Ref. 111 Ref. 112
Year 2018 2018 2019 2020 2020 2021 2021 2022
May 27, 2023 14:55 WSPC/123-JCSC

Technology (µ m) 0.18 0.5 0.065 0.5 0.18 0.18 0.18 0.18

Supply voltage (V) 0.9–2 2.1–5 1.2 3.3 1–2.4 1.2 1.2–2.4 3.2–3.7
Reference output 0.411 1.196 0.202 1.373 0.499 0.766 0.628 2.14
voltage (V)
TC (ppm/◦ C) 33.7 3.98 36.6 8.83 1.5 4.5 2.5 1.183
2330005

Temperature range (◦ C) −40–125 −5–125 −10–110 −40–125 −40–120 −40–120 −40–120 −55–125

2330005-19
Power (µ W) 0.085 — 0.068 — 22.9 — 77 —
LS (%/V) 0.06 — 0.181 — 0.05 — 0.03 0.0146
Area (mm2 ) 0.11 0.053 0.032 0.024 0.077 — 0.024 0.256
PSRR(dB) −61@ 10 Hz; — — −83@ 10Hz; −77.7@ 100 Hz; — −91.4@ 100 Hz −63.4@ 10 Hz;
−44@ 100 Hz; −74@ 10 kHz; −47.7@ 1 MHz −56.5@ 10 kHz
−46@ 1 MHz −49@ 100 kHz
√
Output noise (µV/ Hz) — — — — — — — 0.92@ 10 Hz
2nd Reading

A Comprehensive Study of Different Techniques for Voltage References

 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

The literature survey presents a comparative analysis using the strategies of the
BGR from the years 2011 to 2022. Table 1 summarizes some of the recent BGRs
from the year 2018 to 2022 for ease of the new researchers. It has been observed
that the BGRs105,108–112 have TCs less than 10 ppm/◦ C and the BGR103,106 have
a TC of more than 10 ppm/◦ C but less than 40 ppm/◦ C with a good temperature
range. All BGRs summarized in Table 1 can operate at minimum supply voltages
of 1.2 V except BGR103 which can work on 0.9 V minimum supply voltage. Further,
it has also been observed that the LS of BGRs103,109,111,112 is less than or equal
to 0.06%/V, and the area consumed by BGRs105,106,108,109,111 is less than or equal
to 0.077 mm.2 Therefore, from Table 1, it can be concluded that most of the
BGRs have TC under 10 ppm/◦ C for a wide temperature range (approximately
−40–120◦C) with minimum supply voltage of 0.9 V and consume chip area more
J CIRCUIT SYST COMP Downloaded from [Link]

than 0.024 mm.2 So the BGRs are more likely to be suitable for applications where
precision is the main concern, not the power and area.

5. All MOS Transistor-based VR

Modern applications like IoT, battery-operated devices, etc. demand a VR with
low power, low voltage, compact area and less chip area.113 BGR, which uses the
BJT transistor, cannot satisfy low voltage and low-cost demands.114 Consequently,
MOS transistors substituted the BJT transistors.115 In this approach, only MOS
transistors are utilized for the implementation of techniques. Many advantages can
be achieved using MOS transistor-based VRs i.e., power dissipation will be reduced
due to MOS transistors functioning in the subthreshold region,116 VRs will consume
less chip area as we can scale down MOS transistors easily,117 and overall imple-
mentation cost will be less as no other devices, like BJT, diode, Zener diode, etc.,
are utilized. On the other hand, some drawbacks come with MOS transistor-based
VRs i.e., circuit suffers from TC performance118 because of the larger nonlinearities
of the MOSFETs as compared to BJT transistors, it is more sensitive to process
variation,119 less accuracy,120 and additional manufacturing steps may be required
to fabricate MOSFETs with different threshold voltages.121
The reference voltage can be developed depending on the difference between
two quantities having a similar behavior to temperature variations. According to
that two techniques are popular in MOS transistor-based VRs difference between
the gate–source-voltage and difference between the threshold voltages.122

• Difference between the gate–source-voltage: In this technique, reference voltage

is proportional to the difference in the gate–source-voltages (ΔV GS ) of two MOS
transistors.123
• Difference between the threshold voltages: In this technique, reference voltage
is proportional to the difference in the threshold voltages (Vth ) of two MOS
transistors in which one transistor has probably a normal-Vth and the other has
high-Vth MOS transistors.

2330005-20
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

5.1. Literature survey: Comparative research using classification

techniques of all MOS transistor-based VR
This section presents the researchers’ contributions over the last years for LP, LV,
and high-precision methods for all MOS VRs.

5.1.1. PTAT + CTAT approach

Magnelli et al.124 proposed all MOS transistor-based VR based on the difference in
the threshold voltage technique. This resistor-less circuit contains three parts i.e.,
start-up to ensure bias current in the desired state, current reference is a self-biased
current source that produces the current to be injected in the load transistor, and
J CIRCUIT SYST COMP Downloaded from [Link]

active load circuits are shown in Fig. 19. To acquire the reference voltage which
is VREF < Vth , they used the subthreshold operation of the load transistor. The
circuit archives TC of 142 ppm/◦ C. So the major drawback of the circuit is high-
temperature sensitivity.
Samir et al.125 introduced a VR without resistors. Figure 20 illustrates the
circuit which consists of sub-circuits i.e., start-up circuit which provides the previous
steady state, the current generator generates the I0 bias current, and the active load
in which the I0 bias current is injected to produce the output. The op-amp is used
in the current generator to improve PSRR. Then the circuit archives good TC i.e.,
7.5 in the −40–125◦C of TR at supply voltage from 1.6 V to 3.6 V. This circuit is
therefore not a good option for LV applications.
For LV applications, Zeng et al.126 presented a VR that utilized a body-biased
technique for better temperature compensations without any special device. The

Fig. 19. VR proposed by Magnelli et al..124

2330005-21
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.
J CIRCUIT SYST COMP Downloaded from [Link]

Fig. 20. VR suggested by Samir et al.125

circuit attains 23.7 ppm/◦ C with minimum supply voltage of 0.6 V and the PSRR
is −40 dB at 10 kHz.
Zeng et al.127 used all MOS transistor-based differential amplifiers to improve
PSRR. The circuit involves a current source to produce a current independent of
the supply voltage, a start-up block, and an output block to produce the reference
voltage as presented in Fig. 21. The PSRR of the circuit without any filtering

Fig. 21. VR presented by Zeng et al.127

2330005-22
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.
J CIRCUIT SYST COMP Downloaded from [Link]

Fig. 22. VR suggested by Yousefi et al.128

capacitor at 10 Hz and 10 kHz are −88.2 and −36 dB, respectively. TC of the circuit
is 19.4 ppm/◦ C but not for the wide range.
Yousefi et al.128 utilized supply-independent (SI) biasing as illustrated in Fig. 22
to achieve high PSRR, especially at low frequencies. The circuit used two NMOS
transistors and a PMOS transistor to perform a weighted sum of the gate–source-
voltage (VGS ). M3 –M10 transistors operate within the saturation region, while all
other transistors operate within the sub-threshold region. Therefore, power con-
sumption is relatively lower, but a power supply voltage of 1.5–3.5 V is required for
operations.

Fig. 23. VR introduced by Wang et al.129

2330005-23
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

Wang et al.129 introduced a sub-threshold VR as depicted in Fig. 23 to reduce

the process variation. The current trimming circuit uses various body bias voltages
to control the threshold voltage of MOSFETs with a 0.45 V supply voltage. The core
reference circuit is made up of a bulk-driven current source and output stage, which
consist of three transistors M10 –M12 . The current produced through the bulk-driven
current generator is reflected in the transistor of the output stage by two stacked
transistors through M10 . The temperature stability is enhanced through second-
order compensation and for compensation of process variation a current trimming
circuit is adapted. However, TC of the circuit is not good i.e., 63.6 ppm/◦ C.
To nullify process variation in VR, Liu et al.130 presented a high accuracy VR
that employed the offset scaling down technique as depicted in Fig. 24. The circuit
J CIRCUIT SYST COMP Downloaded from [Link]

utilized three pseudo-series diodes (PSDs) for lowering TC in second-order thermal

compensation. The circuit has four sub-circuits i.e., the reference voltage core which
consists of PSD, the clamping OTA to improve the PSRR and equal the voltage
at node A and node B, the start-up, and the current bias circuit. Mp15 and Mp16
are a PSD that may be considered RP resistor, the resistance of which depends on
the voltage VGS and Vth . In the same way, MP 10 , MP 11 , and MP 12 , MP 13 are also
two other PSD, each with the equivalent resistance RP . The circuit has significant
performance in power, voltage, and PSRR, but the TR is not good.
For a wide range of temperatures, Oliveira et al.131 proposed two VRs in which
reference voltage is generated through the different threshold voltage techniques
with the help of NMOS transistors which operate in the subthreshold region. These
circuits are self-biased SCM and a self-biased NMOS VR which is based on self-
cascade MOSFET (SCM). The results show that the self-biased approach reduced
power consumption as well as worked on 0.45–0.6 V supply, but a 5 bit-trimming
circuit for both the scheme is required which may increase power consumption.
For further improvement of PSRR, Zeng et al.132 employed the negative feedback
technique and used body biased technique without any special devices in which the
reference voltage is obtained by different threshold voltage methods. With achieving
high PSRR, it is also important to maintain TC over the range of temperature so

Fig. 24. VR presented by Liu et al.130

2330005-24
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

with the help of the same technique presented in Ref. 126. Zeng et al.133 proposed
a circuit by using one special device which works on high threshold voltage (HVT)
with Vhth , while all other transistors work in standard threshold voltage (SVT) Vth .
Results indicate that at a temperature between −20 and 80◦ C, the circuit reaches
a remarkable TC i.e., 7.2 ppm/◦ C. For further improvement in TC, Liao et al.134
work on the same approach and proposed circuits with 3.9 ppm/◦ C TC.
Nagulapalli et al.135 used beta multiplier for realizing the VR for biomedical
applications which can work on 0.6 V supply voltage but the TC is 40 ppm/◦ C.
Wang et al.136 presented feedback concept, but instead of single feedback, they
use both a positive feedback loop and a negative feedback loop within the circuit
where the positive feedback loop gain must be smaller than the gain of the negative
J CIRCUIT SYST COMP Downloaded from [Link]

feedback loop for stabilization of VR. But the use of passive resistors makes the
design a little bulky and costly. Based on the SBNMOS approach in Ref. 125, Wang
et al.137 presented an improved self-biased high threshold drain output VR. This
approach has a zero-current start-up circuit and has lower sensitivity to the process.
Liu et al.138 presented a 3-transistor structure VR based on a temperature
compensation technique for an energy harvesting system which can work from 0.5 V
to 3 V supply voltage, consumed 205 pW, and obtained a TC as low as 3 ppm/◦ C.
However, PSRR is −45.76 at 100 Hz and LS is 0.594 %/V which needs improvement.
Park et al.139 suggested a new technique i.e., symmetric self-biased VR (SSVR)
to decrease the supply voltage while sustaining the performance of the circuit with-
out the need for extra bias voltage (VBIAS ). For a stable VR at −15–125◦C TR,
SSVR consists of a pair of diode-connected NMOS and PMOS which provide the
tendency of CTAT and PTAT respectively.
Bahramali et al.140 proposed a resistor-less auto-start-up CMOS VR using a
Dickson charge pump to compensate for temperature variation. The circuit is made
up of two parts i.e., one part generates a PTAT voltage by the Dickson charge pump,
and another part contains a series of stacked diodes connected to normal CMOS
devices which provide the characteristic of CTAT behavior as shown in Fig. 25. With
this setup, it is difficult to have a low TC, low ripple, and low power consumption
simultaneously. To improve the power consumption of Ref. 140, Bahramali et al.141
introduced a modified approach.
Nejad et al.142 presented a logarithmic curvature compensation technique
for obtaining insensitivity of TC and mobility temperature component for LV
applications. Figure 26 illustrates the circuit which consists of a current genera-
tor, Vth extractor, PTAT voltage generator, and reference core. Vth extractor is
used for the extraction of threshold voltage and produces the bias condition. The
current produced by the self-biased β multiplier current source is proportional to
T 2−γ where γ is the mobility temperature exponent. Then this current is introduced
in the VR core for compensation of the logarithmic temperature-dependent term
presented. The results indicate that the circuit is performing well in terms of TC
and TR but consuming more power. Further improving the circuit’s performance
in Ref. 142, Nejad et al.143 presented a VR with an offset voltage follower block.

2330005-25
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.
J CIRCUIT SYST COMP Downloaded from [Link]

Fig. 25. VR proposed by Bahramali et al.140

Fig. 26. VR suggested by Nejad et al.142

Fig. 27. VR presented by Thakur et al.144

For lower TC and low LS, Thakur et al.144 presented a higher order compensated
VR as depicted in Fig. 27. The circuit is composed of two supply-independent first-
order temperature compensated (SIFTC) with a curvature compensation circuit
(CCC). Both SIFTCs eliminate the need for op-amps through negative feedback.

2330005-26
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

This enhances the LS and PSRR of the circuit as the CTAT and PTAT currents
are supply-independent. Results show that it significantly reduces the TC. SIFTC-
I and SIFTC-II produce the reference currents i.e., IREF1 and IREF2 , respectively.
   
Then these currents are mirrored as IREF1 and IREF2 . IREF2 is subtracted by IREF1
using CCC for compensating the higher order temperature dependence. With this
subtracted current, the reference voltage is attained through the resistor RREF as
shown in Eq. (14)
 
Vref = RREF (IREF1 − IREF2 ). (14)

Pan et al.145 proposed a structure for leakage compensation. This work describes
the impact of leakage current and current mirror mismatch in VR. Naveed et al.53
J CIRCUIT SYST COMP Downloaded from [Link]

utilized the PTAT2 approach for the generation of the reference voltage as depicted
in Fig. 28. They use the modified current source which provides high PSSR to
generate PTAT2 . The TC of the circuit is 19.3 ppm/◦ C in the range of −30–80◦C at
0.65–2.5 V supply voltage with a PSRR of −75 dB at 100 Hz. The circuit has a chip
area of 0.0063 mm2 . According to simulation results, this approach has remarkable
performance, but it has been unable to attain a range of temperatures.
For high PSRR at low supply, Thakur et al.146 presented a current mode sub-1 V
VR, illustrated in Fig. 29 which utilized a single self-biased-cascode-branch (SBCB)
to produce the CTAT and PTAT behavior. The circuit used a starter circuit, a bias
current generator that generates bias currents for both of the operational amplifiers,
a single SBCB that produces CTAT and PTAT behavior, and a current adder
to add the PTAT current and CTAT current with scaling factor as illustrated
in Eq. (15). This current is subsequently converted to a reference voltage by the

Fig. 28. VR reported by Naveed et al.53

2330005-27
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.
J CIRCUIT SYST COMP Downloaded from [Link]

Fig. 29. VR presented by Thakur et al.146

reference resistor as indicated in Eq. (16). PSRR of the circuit is significant i.e.,
91.69 dB from 1 Hz to 10 kHz with a minimum supply voltage of 0.8 V.
ηVT ln(N ) VGS,13
IREF = αIPTAT + βICTAT or IREF = α +β , (15)
R1 R2
 
ηVT ln (N ) VGS,13
VREF = RREF α +β . (16)
R1 R2
For ultra-low power applications, Yu et al.147 presented an NMOS-only VR as
depicted in Fig. 30. To minimize the effect of the process variations from VTH or
ΔVTH, an optimum body selection (OBS) technique with body effect is used. All
transistors function in the subthreshold area to reduce power consumption. Tran-
sistors are manufactured by deep-n-well (DNW) technology. Although it consumes
23-pW power but required extra manufacturing steps to fabricate MOSFETs.

Fig. 30. VR (a) with OBS and (b) without OBS presented by Yu et. al.147

2330005-28
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

5.1.2. CTAT − CTAT approach

The reference voltage can be produced through the subtraction of two volt-
ages/currents which exhibit similar temperature behaviors. Therefore, if two CTAT
voltages/currents are subtracted it is called the CTAT–CTAT approach. Most of
the researchers apply this approach to all MOS transistor based VRs. As the gener-
ation of CTAT voltage/current is by the only MOS transistors, the implementation
of CTAT–CTAT approach is easy for MOS transistor based VRs.
Olivera et al.148 presented a VR in which the reference voltage depends on
the difference between two CTAT voltages i.e., CTAT–CTAT. For improvement in
PSRR, Olivera et al.149 worked on the same approach as depicted in Fig. 31. The
CTAT generation circuit uses NMOS transistors with the same threshold voltage.
J CIRCUIT SYST COMP Downloaded from [Link]

Fig. 31. VR reported by Olivera et al.149

Fig. 32. VR suggested by Thakur et al.150

2330005-29
 J CIRCUIT SYST COMP Downloaded from [Link]
by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

Table 2. Summarization of the distinguished works of all MOS-based VRs (2018–2022).

Ref.→ Parameters ↓ Ref. 140 Ref. 142 Ref. 144 Ref. 149 Ref. 150 Ref. 53 Ref. 146 Ref. 147
May 27, 2023 14:55 WSPC/123-JCSC

Year 2018 2019 2020 2020 2021 2021 2022 2022

Technology (μm) 0.040 0.065 0.18 0.18 0.18 0.065 0.18 0.18
K. Duggal, R. Pandey & V. Niranjan

Supply voltage (V) — 1.2 0.85–2.5 1.2–1.8 0.8–3 0.65–2.5 0.8–5 0.6–1.8
Reference output 1.515 0.590 0.118 0.500 0.312 0.575 424.85 0.431
voltage (V)
TC (ppm/◦ C) 88 7 21.5 22 38.85 19.3 29.5 52
2330005

Temperature −10–125 −40–125 −60–120 0–100 −40–125 −30–80 −55–125 0–85

range (◦ C)

2330005-30
Power (μW) — 1.4 5.168 — 2.75 0.036 6.1 —
LS (%/V) 0.031 — 0.035 0.280 0.027 0.026 0.0035 0.030
Area (mm2 ) 0.00036 — 0.00433 0.073 0.0027 0.0063 0.003 0.003
PSRR (dB) −47 @ 915MHz −43 dB @ 100 Hz −68.64 @ 100 Hz; −42 dB @ 100 Hz −80.84 @ 100 Hz; −75 @ 100 Hz −91.69 @ −47 @ 100 Hz
−60.37 @ 10 kHz −71.66 @ 100 kHz 1 Hz–10 kHz
Output noise — 2.8 @ 100 Hz 0.179 @ 1 Hz 0.54 @ 100 Hz — — 2.37 @ 1 Hz —
√
(μV/ Hz) 0.123 @ 10 kHz 0.045 @ 10 kHz
2nd Reading
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

With the adjustment of the output resistor R3 , the output voltage level can be
changed so that this approach delivers the adjustable output reference voltage. The
output reference voltage is given by Eq. (17)

VIOAT = β (αVCTAT2 − VCTAT1 ) (17)

where α = R 1 α2 N1 R3 α1
R2 α1 N2 , β = R1 N1 and α1 , α2 , N1 and N2 are current mirror factors
of CTAT generators. The TC of the circuit is 22 ppm/◦ C in a TR of 0–100◦C and
PSRR is −42 dB at 100 Hz.
To improve inline sensitivity and PSRR without increasing reference circuit
complexity and chip area, Thakur et al.150 presented a new approach based on
the same CTAT–CTAT approach as shown in Eqs. (18) and (19). The circuit con-
J CIRCUIT SYST COMP Downloaded from [Link]

sists of two supply-independent-CTAT-generators, SICG-I and SICG-II, and a cur-

rent subtractor as shown in Fig. 32. PSRR of the circuit is −80.84 at 100 Hz and
−71.66 dB at 100 kHz frequencies, and the chip area is 0.0027 mm2 . Results show
that this approach has remarkable performance in terms of PSRR without using
any capacitor while maintaining the simplicity and chip area.

IREF = ICTAT1 − N I CTAT2 , (18)

VREF = (ICTAT1 − N I CTAT2 )RREF . (19)

The literature review provides a benchmarking analysis using all MOS

transistor-based VR approaches between the years 2011 and 2022. However, Table 2
summarizes some of the recent VRs based on MOS-transistors from the year
2018 to 2022 to facilitate the work of new researchers. It has been observed that
most of MOS transistor-based VRs140,144,146,147,149,150 have TCs of more than
20 ppm/◦ C and VRs53,142 have TCs of less than 20 ppm/◦ C. The MOS transistor-
based VRs53,144,146,147,150 operate at minimum supply voltages of less than or equal
to 0.85 V except VRs,142,149 which use supply voltage of 1.2 V. The line sensitiv-
ities for MOS transistor-based VRs53,140,144,146,147,150 were also found to be less
than or equal to 0.035%/V. In addition, the area consumed by MOS transistor-
based VRs53,140,144,146,147,150 are less than or equal to 0.0063 mm2 except VR149
which uses area of 0.073 mm2 . The VRs149,150 are based on CTAT–CTAT approach
and have TC more than 20 ppm/◦ C. From Table 2, it can be concluded that most of
the MOS-based VRs have TC more than 20 ppm/◦ C with minimum supply voltage
of 0.6 V and consume chip area less than 0.0063 mm2 . Therefore, MOS transistor-
based VRs are more likely to be suitable for applications where supply and area
are the main concern.

6. Research Gaps and Future Directions

In recent years, as IoT is gaining attention, the need for LP circuits is enlarged,
which prompted researchers to intensively study CMOS integrated circuits with low
power supply voltage and it introduced a new challenge for analog ICs researchers

2330005-31
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

to upgrade the performance of several proven circuits that are not anymore oper-
ating at supply voltages substantially below 1 V. Therefore, new designs should be
generated to work in an ultra-low power supply voltage environment. One of those
circuits is VRs that are extensively exploited in analog and mixed-signal IC design.
Therefore, a resistor-less, high PSRR, LV, LP, and temperature insensitive, VR is
among the leading research topics.
From the literature survey of BGR and all MOS transistor-based VRs, it can
be concluded that all MOS transistor-based VRs need a lower power supply and
smaller chip area, whereas BGR has a good TC and temperature range. The simula-
tion/experimental results from the literature study demonstrated that VRs based
on all MOS transistors are more suitable for the new requirements than BJT-
J CIRCUIT SYST COMP Downloaded from [Link]

based VRs. VRs based on all MOS transistors have been recognized as area and
power-efficient circuits, but they need improvements in the temperature range, TC,
PSRR, etc. Notwithstanding its benefits, here are some vital challenges that must
be addressed while using all MOS-based VRs.

• There are many techniques to improve the TC, temperature compensation is also
there in the literature. However, it is difficult to accurately predict the tempera-
ture dependence of the threshold voltage in all MOS-based VRs.
• In all MOS transistor-based VRs, reference voltages are directly related to the
threshold voltage, which may lead to large process variations. So trimming is
required to achieve the accurate reference voltage but it will increase the power
as well as area, therefore their process parameter improvement is also a very
challenging factor.
• The VR circuit can be integrated with the other analog and digital modules
like digital control, demodulator, and high-density stimulator array. The various
modules of VR circuits like start-up circuits can be improved so that the overall
performance is improved.

However, most of all MOS transistor-based VR approaches are resistor-less. But

some approaches use resistors, but, in integrated circuit design, passive resistors
consume more power and it is difficult to properly match with technology scaling.
Thus a resistor-less structure is preferable. Although power consumption is less in
all MOS transistor-based VRs, still the power consumption is in microwatts and
can be reduced to serve IoT applications.

7. Conclusion
VRs are the essential component in analog design. However, the VR circuit is
expected to produce a DC voltage insensible to temperature and supply fluctua-
tions as well as ought to have LP consumption, high PSRR, low output noise, low
supply voltage, and less chip area. This review paper communicates the current
state-of-the-art research published in BGRs and all MOS-transistor-based VRs. For
new researchers, it also sheds light on the challenges and recommendations for the

2330005-32
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

future in the VR field. It can be concluded that most of the BGRs have TC under
10 ppm/◦ C for wide temperature range (approximately −40–120◦C) with minimum
supply voltage of 0.9 V and consume chip area more than 0.024 mm2 while MOS-
based VRs have TC more than 20 ppm/◦ C with minimum supply voltage of 0.6 V
and consume chip area less than 0.0063 mm2 . PTAT + CTAT approach is popular
and easier to implement with BGR as well as MOS transistor based VR. Therefore,
from the research done till now, it is very difficult to achieve all the features in a
single circuit. So it depends upon the applications. If the application demands high
accuracy with insensitivity to temperature for a wide range, then a BGR will be a
good option. For applications like IoT, IoMT, battery-operated devices, etc., where
LP, LV, and less chip area are the main requirements, MOS transistor-based VRs
J CIRCUIT SYST COMP Downloaded from [Link]

will be a superior choice.

References
1. B. Razavi, Design of Analog CMOS Integrated Circuits, 1st edn. (McGraw-Hill,
Boston, 2003).
2. M. C. Lee, C. C. Hu and Z. W. Lin, Implementation of low dropout regulator with
low bandgap reference voltage circuit for RFID tag applications, CSQRWC 2012,
New Taipei, Taiwan, 23–27 July 2012, pp. 40–43.
3. C. Summatta, T. Phurahong, W. Rattanangam and W. Chaiyong, Low-cost and
compact window comparator circuit with MOSFET-resistor voltage references, 2019
IEEE 2nd Int. Conf. Power and Energy Applications (ICPEA), Singapore, 27–30
April 2019, pp. 75–78.
4. W. C. Lai, T. H. Hsu, C. C. Chen and C. C. Hsieh, A 12-bit SAR ADC with reference
voltage ripple suppression, 2021 IEEE Int. Symp. Circuits and Syst. (ISCAS), Daegu,
Korea, 22–28 May 2021, pp. 1–4.
5. P. B. Basyurt, E. Bonizzoni, F. Maloberti and D. Y. Aksin, A low-power low-noise
CMOS voltage reference with improved PSR for wearable sensor systems, 2017 IEEE
Int. Symp. Circuits and Systems (ISCAS), Baltimore, MD, USA, 28–31 May 2017,
pp. 1–4.
6. R. B. A. Zawawi, H. Choi and J. Kim, High-PSRR wide-range supply-independent
CMOS voltage reference for retinal prosthetic systems, Electronics 9 (2020)
2028.
7. M. Caselli, C. van Liempd, A. Boni and S. Stanzione, A low-power native NMOS-
based bandgap reference operating from −55◦ C to 125◦ C with Li-ion battery com-
patibility, Int. J. Circuit Theory Appl. 49 (2021) 1327–1346.
8. A. Parisi, A. Finocchiaro, G. Papotto and G. Palmisano, Nano-power CMOS voltage
reference for RF-powered systems, IEEE Trans. Circuits Syst. II, Express Briefs 65
(2018) 1425–1429.
9. S. S. Chouhan and K. Halonen, A simple all MOS voltage reference for
RFID applications, 2013 NORCHIP, Vilnius, Luthuania, (11–12 November 2013),
pp. 1–3.
10. C. W. U, M. K. Law, C. S. Lam and R. P. Martins, Switched-capacitor bandgap
voltage reference for IoT applications, IEEE Trans. Circuits Syst. I, Regul. Pap. 69
(2022) 16–29.
11. R. J. Baker, CMOS: Circuit Design, Layout, and Simulation, 4th edn. (Wiley, United
States, 2019).

2330005-33
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

12. A. R. M. Gabriel, Voltage Reference-from Diodes to Precision, High Bandgap Circuits

(John Wiley & Sons, 2002).
13. A. Digvadekar, A sub 1V bandgap reference circuit, MS thesisRochester Institute of
Technology, New York (2006).
14. S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits,
Vol. 1988 (McGraw-Hill, New York, 2002).
15. K. E. Kuijk, A precision reference voltage source, IEEE J. Solid-State Circuits 8
(1973) 222–226.
16. A. P. Brokaw, A simple three-terminal IC bandgap reference, IEEE J. Solid-State
Circuits 9 (1974) 388–393.
17. R. J. Widlar, New developments in IC voltage regulators, IEEE J. Solid-State Cir-
cuits 6 (1971) 2–7.
18. O. Pereira-Rial, P. López, J. M. Carrillo, V. M. Brea and D. Cabello, Ultralow power
J CIRCUIT SYST COMP Downloaded from [Link]

voltage reference circuit for implantable devices in standard CMOS technology, Int.
J. Circuit Theory Appl. 47 (2019) 991–1005.
19. L. He, C. Zhan, Y. Nan, N. Zhang, L. Wang and G. Li, A 0.5 V 46.2 ppm/◦ C CMOS
voltage reference based on compensated ΔVTH with wide temperature range and
high PSRR, 2018 16th IEEE Int. New Circuits and Systems Conf. (NEWCAS),
Montreal, QC, Canada, 24–27 June 2018, pp. 66–69.
20. H. Zhuang, X. Liu and H. Wang, Voltage reference with linear-temperature-
dependent power consumption, IEEE Trans. Very Large Scale Integr. Syst. 28 (2020)
1043–1049.
21. Z. Zhang, C. Zhan, L. Wang and M. K. Law, A 40-125◦ C 0.4µ A low noise bandgap
voltage reference with 0.8 mA load driving capability using shared feedback resistors,
IEEE Trans. Circuits Syst. II, Express Briefs 69 (2022) 4033–4037.
22. C. J. B. Fayomi and S. J. Stratz, Novel approach to low-voltage low-power bandgap
reference voltage in standard CMOS process, 2006 13th IEEE Int. Conf. on Electron.,
Circuits, and Systems, Nice, France, 10–13 December 2006, pp. 208–211.
23. C. M. Andreou and J. Georgiou, A 0.75 V, 4µ W, 15 ppm/◦ C, 190◦ C temperature
range, voltage reference, Int. J. Circuit Theory Appl. 44 (2016) 1029–1038.
24. J. Heidrich et al., Design of a low-voltage reference circuit with reconfigurable tem-
perature range for RFID applications, 2010 IEEE MTT-S Int. Microwave Symp.,
Anaheim, CA, USA, 23–28 May 2010, pp. 1516–1519.
25. P. Khot and R. B. Shettar, Design of area efficient and low power bandgap voltage
reference using sub-threshold MOS transistors, 2015 19th Int. Symp. VLSI Design
and Test, Ahmedabad, India, 26–29 June 2015, pp. 1–5.
26. G. Souliotis, F. Plessas and S. V lassis, A high accuracy voltage reference generator,
Microelectron. J. 75 (2018) 61–67.
27. S. Huang, M. Li, P. Yin and F. Tang, A high-order temperature-compensated
bandgap voltage reference with low temperature coefficient, 2022 IEEE Int. IOT,
Electronics and Mechatronics Conf. (IEMTRONICS), Toronto, ON, Canada, 1–4
June 2022, pp. 1–5.
28. J. Lin, L. Wang, C. Zhan and Y. Lu, A 1-nW ultra-low voltage subthreshold CMOS
voltage reference with 0.0154%/V line sensitivity, IEEE Trans. Circuits Sys. II :
Express Briefs 66 (2019) 1653–1657.
29. M. Mohammed, K. Abugharbieh, M. Abdelfattah and S. Kawar, Design method-
ology for MOSFET-based voltage reference circuits implemented in 28 nm CMOS
technology, AEU-Int. J. Electron. Commun. 70 (2016) 568–577.
30. L. Wang, C. Zhan, S. Zhao, G. Cai, Y. Liu, Q. Huang and G. Li , Design of high-
PSRR current-mode bandgap reference with improved frequency compensation, 2016

2330005-34
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

IEEE Int. Conf. Electron Devices and Solid-State Circuits (EDSSC), Hong Kong,
China, 3–5 August 2016, pp. 410–413.
31. K. K. Lee, T. S. Lande and P. D. Häfliger, A sub-uW bandgap reference circuit with
an inherent curvature-compensation property, IEEE Trans. Circuits Syst. I, Regul.
Pap. 62 (2015) 1–9.
32. R. Sanjay, K. H. Kumar and B. Venkataramani, A PVT compensated nano-ampere
current reference in 0.18 µm CMOS, Analog Int. Circuits Signal Process. 98 (2019)
615–625.
33. D. Osmanović et al., Design of a tunable temperature coefficient voltage reference
with low-dropout voltage regulator in 180-nm CMOS technology, 2020 43rd Int.
Convention on Information, Comm. and Electronic Tec. (MIPRO), Opatija, Croatia,
28 September–2 October 2020, pp. 93–98.
34. Y. Liu, C. Zhan, L. Wang, J. Tang and G. Wang, A 0.4 V wide temperature range
J CIRCUIT SYST COMP Downloaded from [Link]

all-MOSFET subthreshold voltage reference with 0.027%/V line sensitivity, IEEE

Trans. Circuits Syst. II, Express Briefs 65 (2018) 969–973.
35. C. Hsieh, H. Huang and K. Chen, A 1-V, 16.9 ppm/◦ C, 250 nA switched-capacitor
CMOS voltage reference, IEEE Trans. Very Large Scale Integr. Syst. 19 (2011) 659–
667.
36. G. Giustolisi and G. Palumbo, A detailed analysis of power-supply noise attenuation
in bandgap voltage references, IEEE Trans. Circuits Syst. I, Fund. Theory Appl. 50
(2003) 185–197.
37. W. J. Zhang, M. L. Liu, L. Xie, L. J. Peng and X. L. Jin, Low noise voltage reference
for MEMS acceleration sensor readout circuit, 2016 13th IEEE Int. Conf. Solid-State
and Integrated Circuit Tech. (ICSICT), Hangzhou, China, 25–28 October 2016, pp.
943–945.
38. C. W. Kok and W. S. Tam, CMOS Voltage References: An Analytical and Practical
Perspective (John Wiley & Sons, 2012).
39. V. Hande and M. S. Baghini, Survey of bandgap and non-bandgap based voltage
reference techniques, Sci. Iranica 23 (2016) 2845–2861.
40. X. Liu, S. Yang, J. Wang and Z. Xu, A high-order curvature compensated voltage
reference based on lateral BJT, AEU-Int. J. Electron. Commun. 124 (2020) 153325.
41. R. Nagulapalli, R. K. Palani and S. Bhagavatula, A 24.4 ppm/◦ C voltage mode
bandgap reference with a 1.05 V supply, IEEE Trans. Circuits Syst. II, Express Briefs
68 (2021) 1088–1092.
42. R. Stair, J. A. Connelly and M. Pulkin, A current mode CMOS voltage reference,
2000 Southwest Symp. Mixed-Signal Design (Cat. No. 00EX390), San Diego, USA,
27–29 February 2000, pp. 23–26.
43. K. Kondo, K. Tanno, H. Tamura and S. Nakatake, Low voltage CMOS current
mode reference circuit without operational amplifiers, IEICE Trans. Fund. Electron.
Commun. Comput. Sci. 101 (2018) 748–754.
44. Y. Ji, J. Lee, B. Kim, H. Park and J. Sim, A 192-pW voltage reference generating
bandgap– Vth with process and temperature dependence compensation, IEEE J.
Solid-State Circuits 54 (2019) 3281–3291.
45. T. Vergine, M. De Matteis, S. Michelis, G. Traversi, F. De Canio and A. Baschirotto,
A 65 nm rad-hard bandgap voltage reference for LHC environment, IEEE Trans.
Nucl. Sci. 63 (2016) 1762–1767.
46. D. Albano, F. Crupi, F. Cucchi and G. Iannaccone, A picopower temperature-
compensated, subthreshold CMOS voltage reference, Int. J. Circuit Theory Appl.
42 (2014) 1306–1318.

2330005-35
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

47. H. Cao, Z. Yu, H. Deng and P. Li, A reference voltage source and its output buffer
for pipeline ADC, 2014 Int. Conf. Anti-Counterfeiting, Security and Identification
(ASID), Macao, China, 12–14 December 2014, pp. 1–5.
48. K. R. Francisco and J. A. Hora, Very low bandgap voltage reference with high
PSRR enhancement stage implemented in 90nm CMOS process technology for LDO
application, 2012 IEEE Int. Conf. on Electronics Design, Systems and Applications
(ICEDSA), Kuala Lumpur, Malaysia, 5–6 November 2012, pp. 216–220.
49. C. Huang, C. Zhan, L. He, L. Wang and Y. Nan, A 0.6-V minimum-supply,
23.5 ppm/◦ C subthreshold CMOS voltage reference with 0.45% variation coefficient,
IEEE Trans. Circuits Syst. II, Express Briefs 65 (2018) 1290–1294.
50. A. Parisi, A. Finocchiaro and G. Palmisano, An accurate 1-V threshold voltage
reference for ultra-low power applications, Microelectron. J. 63 (2017) 155–159.
51. S. S. Chouhan and K. Halonen, A 139 nW, 67ppm/◦ C BJT-CMOS-based voltage
reference circuit, Circuits, Syst., Signal Process. 36 (2017) 5062–5078.
J CIRCUIT SYST COMP Downloaded from [Link]

52. L. Wang, C. Zhan, J. Tang, S. Zhao, G. Cai, Y. Liu, Q. Huang and G. Li, Analysis and
design of a current-mode bandgap reference with high power supply ripple rejection,
Microelectron. J. 68 (2017) 7–13.
53. Naveed and J. Dix, A resistor-less, nano-watt CMOS voltage reference with high
PSRR, 2021 22nd Int. Symp. Quality Electronic Design (ISQED), 2021, pp. 19–23.
54. J. Hu, H. Xu, Y. Zhang, J. Sun, T. Du, C. Lu and G. Li, A 1.2 V supply 0.58 ppm/◦ C
CMOS bandgap voltage reference, IEICE Electron. Express 15 (2018) 1–6.
55. X. Xia, L. Xie, W. Sun and L. Shi, Temperature-stable voltage reference based
on different threshold voltages of NMOS transistors, IET Circuits, Devices Syst. 3
(2009) 233–238.
56. Z. Zhou et al., A CMOS voltage reference based on mutual compensation of Vtn
and Vtp, IEEE Trans. Circuits Syst. II, Express Briefs 59 (2012) 341–345.
57. Z. Cai and C. Chen, A 0.6 V temperature-stable CMOS voltage reference circuit with
sub-threshold voltage compensation technique, IEICE Electron. Express 15 (2018)
20180760.
58. N. Lyu, N. Yu and M. Yi, An improved voltage bandgap reference with high-order
curvature compensation, 2015 IEEE 11th Int. Conf. ASIC (ASICON), Chengdu,
China, 3–6 November 2015, pp. 1–4.
59. J. D. Chen and C. K. Ye, Design of a CMOS bandgap reference circuit with a wide
temperature range, high precision, and low temperature coefficient, J. Circuits, Syst.,
Comput. 23 (2014) 1450107.
60. G. Pan, Q. Hua and B. Zhang, A 1.8 V 0.918 ppm/◦ C CMOS bandgap voltage ref-
erence with curvature-compensated, IEICE Electron. Express 16 (2019) 20190616–
20190616.
61. X. Fu, D. M. Colombo, Y. Yin and K. El-Sankary, Low noise, high PSRR, high-order
piecewise curvature compensated CMOS bandgap reference, IEEE Access 10 (2022)
110970–110982.
62. R. A. Zawawi, O. Sidek, W. M. H. W. Hassin, M. I. A. Zulkipli and N. Rhaffor, An
improvement of a piecewise curvature-corrected CMOS bandgap reference, IEICE
Electron. Express 8 (2011) 1876–1881.
63. H. Y. Huang, R. J. Wang and S. C. Hsu, Piecewise linear curvature-compensated
CMOS bandgap reference, 2008 15th IEEE Int. Conf. Electronics, Circuits and Sys-
tems , Saint Julian’s, Malta, 31 August–3 September 2008, pp. 308–311.
64. Z. K. Zhou, X. C. Ou, Y. Shi, P. S. Zhu, Y. Q. Ma, S. Q., X. Ming and B. Zhang,
A 3.2ppm/◦ C curvature-compensated bandgap reference with wide supply voltage
range, Microelectron. J. 43 (2012) 863–868.

2330005-36
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

65. G. Zhu, Y. Yang and Q. Zhang, A 4.6-ppm/◦ C high-order curvature compensated

bandgap reference for BMIC, IEEE Trans. Circuits Systems II: Express Briefs 66
(2019) 492–1496.
66. T. Yan, C.-W. U., M. K. Law and C. S. Lam, A −40◦ C–125◦ C, 1.08 ppm/◦ C, 918 nW
bandgap voltage reference with segmented curvature compensation, Microelectron.
J. 105 (2020) 104897.
67. J. Shen, H. Chen, S. Ni and Z. Song, A curvature compensation technique for low-
voltage bandgap reference, Energies 14 (2021) 7193.
68. H. M. Chen, C. C. Lee, S. H. Jheng, W. C. Chen and B. Y. Lee, A sub-1 ppm/◦ C pre-
cision bandgap reference with adjusted-temperature-curvature compensation, IEEE
Trans. Circuits Syst. I, Regul. Pap. 64 (2017) 1308–1317.
69. H. Wang, J. Wang, J. Su, G. Zhang and F. Liang, A precision voltage reference circuit
with trimming for 16-Bit SAR ADC in 55nm CMOS technology, 2018 IEEE 3rd Int.
J CIRCUIT SYST COMP Downloaded from [Link]

Conf. Integrated Circuits and Microsystems (ICICM), Shanghai, China, 2018, pp.
94–97.
70. C. M. Andreou and J. Georgiou, A 0.7 V, 2.7 µW, 12.9 ppm/◦ C over 180◦ C CMOS
subthreshold voltage reference, Int. J. Circuits Theory Appl. 45 (2017) 1349–1368.
71. Z. Zhu, J. Hu, A 0.45 V, nano-watt 0.033% line sensitivity MOSFET-only sub-
threshold voltage reference with no amplifiers, IEEE Trans. Circuits Syst. I 63 (2016)
1370–1380.
72. H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi and K. Sakui,
A CMOS bandgap reference circuit with sub-1-V operation, IEEE J. Solid-State
Circuits 34 (1999) 670–674.
73. M. Seok, G. Kim, D. Blaauw and D. Sylvester, A portable 2-transistor picowatt
temperature-compensated voltage reference operating at 0.5 V, IEEE J. Solid-State
Circuits 47 (2012) 2534–2545.
74. H. Kumar, V. Sharma, Y. B. Kumar and M. H. Vasantha, A novel tunable bandgap
voltage and current reference generation circuit, Analog Integr. Circuits Signal Pro-
cess. 107 (2021) 331–338.
75. S. K. Koh and L. Lee, Low power CMOS bandgap reference circuit, 2014 IEEE
Student Conf. Research and Development, Penang, Malaysia, 16–17 December 2014,
pp. 1–5.
76. M. D. Ker and J. S. Chen, New curvature-compensation technique for CMOS
bandgap reference with sub-1-V operation, IEEE Trans. Circuits Syst. II, Express
Briefs 53 (2006) 667–671.
77. D. M. Colombo, G. Wirth and S. Bampi, Sub-1 V band-gap based and MOS
threshold-voltage based voltage references in 0.13 µm CMOS, Analog Integ. Circuits
Signal Process. 82 (2015) 25–37.
78. D. Ha, Y. Park and S. Kim, A current-mirror technique used for high-order curvature
compensated bandgap reference in automotive application, 2016 IEEE 59th Inter.
Midwest Symp. Circuits and Sys. (MWSCAS), Abu Dhabi, United Arab Emirates,
16–19 October 2016, pp. 1–4.
79. M. Pan, J. Xie and L. Pang, A 0.7 V 5 nW CMOS sub-bandgap voltage reference
without resistors, Analog Integr. Circuits Signal Process. 104 (2020) 71–79.
80. Guruprasad and K. Shama, MOS only voltage reference with improved line regula-
tion for LDO voltage regulator applications, 2020 5th Int. Conf. Devices, Circuits
and Syst. (ICDCS), Coimbatore, India, 5–6 March 2020, pp. 7–11.
81. C. Zhang, X. Wu, W. Deng and J. Huang, A novel low line regulation CMOS voltage
reference without BJTs and resistors, SAIEE Afr. Res. J. 111 (2020) 130–137.

2330005-37
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

82. Z. Zhou, J. Cao, Y. Wang, Y. Shi, Z. Wang and B. Zhang, A nanoscale low-power
resistorless voltage reference with high PSRR, Nanoscale Res. Lett. 14 (2019) 1–9.
83. L. Xie, J. Liu, Y. Wang, Y. Han and G. Wen, A low power CMOS voltage reference
generator with temperature and process compensation, Analog Integr. Circuits Signal
Process. 81 (2014) 313–324.
84. S. Yousefi and M. Jalali, A high-PSRR low-power CMOS voltage reference based on
weighted VGS difference, AEU-Int. J. Electronics and Comm. 70 (2016) 50–57.
85. A. Tsitouras and P. P. Sotiriadis, Design of a sub-1V CMOS reference voltage gen-
erator, Microelectron. J. 91 (2019) 92–99.
86. E. Barteselli, L. Sant, R. Gaggl and A. Baschirotto, Design techniques for low-power
and low-voltage bandgaps, Electricity 2 (2021) 271–284.
87. H. Aminzadeh and M. M. Valinezhad, 0.7-V supply, 21-nW All–MOS voltage refer-
ence using a MOS-Only current-driven reference core in digital CMOS, Microelectron.
J. 102 (2020) 104841.
J CIRCUIT SYST COMP Downloaded from [Link]

88. L. Liu, J. Mu and Z. Zhu, A 0.55-V, 28-ppm/◦ C, 83 nW CMOS sub-BGR With

UltraLow power curvature compensation, IEEE Trans. Circuits Syst. I, Regul. Pap.
65 (2018) 95–106.
89. C. Zhao and J. Huang, A new high performance bandgap reference, 2011 Int. Conf.
Electronics, Communications and Control (ICECC), Ningbo, China, 9–11 September
2011, pp. 64–66.
90. J. Li, X. Zhang and M. Yu, A 1.2-V piecewise curvature-corrected bandgap reference
in 0.5 CMOS process, IEEE Trans. Very Large Scale Integr. Syst. 19 (2011) 1118–
1122.
91. Z. Zhu, W. Wei, L. Liu and Y. Yang, A high precision CMOS voltage reference
without resistors, J. Circuits, Syst., Comput. 21 (2012) 1250019.
92. C. M. Andreou, S. Koudounas and J. Georgiou, A novel wide-temperature-range,
3.9 ppm/◦ C CMOS bandgap reference circuit, IEEE J. Solid-State Circuits 47 (2012)
574–581.
93. Y. Yin, D. Li and H. Deng, A high precision CMOS band-gap reference with expo-
nential curvature-compensation, 2013 Int. Conf. Anti-Counterfeiting, Security and
Identification (ASID), Shanghai, China, 25–27 October 2013, pp. 1–5.
94. Y. Osaki, T. Hirose, N. Kuroki and M. Numa, 1.2-V supply, 100-nW, 1.09-V bandgap,
and 0.7-V supply, 52.5-nW, 0.55-V subbandgap reference circuits for nanowatt
CMOS LSIs, IEEE J. Solid-State Circuits 48 (2013) 1530–1538.
95. B. Ma and F. Yu, A novel 1.2–V 4.5-ppm/◦ C curvature-compensated CMOS
bandgap reference, IEEE Trans. Circuits Syst. I, Regul. Pap. 61 (2014) 1026–
1035.
96. J. Geng, Y. Zhao and H. Zhao, A high-order curvature-corrected CMOS bandgap
voltage reference with constant current technique, Int. J. Circuit Theory Appl. 42
(2014) 43–52.
97. O. E. Mattia, H. Klimach and S. Bampi, 0.7 V supply, 8 nW, 8 ppm/◦ C resistorless
sub-bandgap voltage reference, 2014 IEEE 57th Int. Midwest Symp. Circuits and
Syst. (MWSCAS), College Station, TX, USA, 3–6 August 2014, pp. 479–482.
98. O. E. Mattia, H. Klimach and S, Bampi, Sub-1 V supply 5 nW 11 ppm/◦ C resistorless
sub-bandgap voltage reference, Analog Integr. Circuits Signal Process. 85 (2015) 17–
25.
99. B. Wang, M. K. Law and A. Bermak, A precision CMOS voltage reference exploiting
silicon bandgap narrowing effect, IEEE Trans. Electron Devices 62 (2015) 2128–
2135.
100. F. Neri, T. Brauner, E. De Mey and C. Schippel, Low-power, wide supply volt-
age bandgap reference circuit in 28 nm CMOS, 2015 IEEE Jordan Conf. Applied

2330005-38
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

Electrical Engineering and Computing Technologies (AEECT), Amman, Jordan, 3–5

November 2015, pp. 1–6.
101. J. A. G. Caicedo, O. E. Mattia, H. Klimach and S. Bampi, 0.75 V supply nanowatt
resistorless sub-bandgap curvature-compensated CMOS voltage reference, Analog
Integr. Circuits Signal Process. 88 (2016) 333–345.
102. O. E. Mattia, H. Klimach and S. Bampi, Resistorless BJT bias and curvature com-
pensation circuit at 3.4 nW for CMOS bandgap voltage references, Electron. Lett.
50 (2014) 863–864.
103. L. Wang, C. Zhan, J. Tang, Y. Liu and G. Li, A 0.9-V 33.7-ppm/◦ C 85-nW sub-
bandgap voltage reference consisting of subthreshold MOSFETs and single BJT,
IEEE Trans. Very Large Scale Integr. Syst. 26 (2018) 2190–2194.
104. M. Gupta and R. K. Sharma, Design of ultra low power, temperature independent
resistorless bandgap reference circuit in 40.18 µ m CMOS, 2018 5th Int. Conf. Signal
J CIRCUIT SYST COMP Downloaded from [Link]

Processing and Integrated Networks (SPIN), Noida, India, 22–23 February 2018, pp.
868–871.
105. X. Ming, L. Hu, Y.-L. Xin, X. Zhang, D. Gao and B. Zhang, A high-precision resistor-
less CMOS compensated bandgap reference based on successive voltage-step com-
pensation, IEEE Trans. Circuits Syst. I, Regul. Pap. 65 (2018) 4086–4096.
106. J. Lei, Z. Wang and X. Wang, A 68-nW novel CMOS sub-bandgap voltage reference
circuit, Microelectron. J. 89 (2019) 37–40.
107. Y. Ma, C. Bai, Y. Wang and D. Qiao, A low noise CMOS bandgap voltage reference
using chopper stabilization technique, 2020 IEEE 5th Int. Conf. Integrated Circuits
and Microsystems (ICICM), Nanjing, China, 23–25 October 2020, pp. 184–187.
108. L. Que, D. Min, L. Wei, Y. Zhou and J. Lv, A high PSRR bandgap voltage reference
with piecewise compensation, Microelectron. J. 95 (2020) 104660.
109. X. Liu, S. Yang and J. Lu, A twice curvature compensated voltage reference with
double frequency compensation, Microelectron. J. 105 (2020) 104921.
110. Y. Zhang, J. Li, X. Wang, Z. Luo and Y. Zhou, A 1.2-V 2.18-ppm/◦ C curvature-
compensated CMOS bandgap reference, IEICE Electron. Express 18 (2021)
20210162–20210162.
111. X. Liu, S. Liang, W. Liu and P. Sun, A 2.5 ppm/◦ C voltage reference combining tra-
ditional BGR and ZTC MOSFET high-order curvature compensation, IEEE Trans.
Circuits Syst. II, Express Briefs 68 (2021) 1093–1097.
112. S. Huang, M. Li, H. Li, P. Yin, Z. Shu, A. Bermak and F. Tang, A new voltage
reference based on threshold voltages summation in 0.18-µm CMOS process, IEEE
Trans. Circuits Syst. I, Regul. Pap. 69 (2022) 1408–1416.
113. W. A. Amaral, A new voltage reference based on threshold voltages summation
of CMOS Transistors, 2019 IEEE 62nd Int. Midwest Symposium on Circuits and
System (MWSCAS), Dallas, TX, USA, 4–7 August 2019, pp. 149–151.
114. K. Peng and Y. Xu, Design of low-power bandgap voltage reference for IoT RFID
communication, 2018 IEEE 3rd Int. Conf. Integrated Circuits and Microsystems
(ICICM), Shanghai, China, 24–26 November 2018, pp. 345–348.
115. A. Ria, A. Catania, P. Bruschi and M. Piotto, A low-power CMOS bandgap voltage
reference for supply voltages down to 0.5 V, Electronics 10 (2021) 1901.
116. M. Mohammed, K. Abugharbieh, M. Abdelfattah and S. Kawar, Design of a voltage
reference circuit based on subthreshold and triode MOSFETs in 90nm CMOS, 2014
IEEE Int. Conf. IC Design Technology, Austin, TX, USA, 28–30 May 2014, pp. 1–4.
117. H. Luo, Y. Han, R. C. C. Cheung, G. Liang and D. Zhu, Subthreshold CMOS voltage
reference circuit with body bias compensation for process variation, IET Circuits,
Devices Syst. 6 (2012) 198–203.

2330005-39
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

K. Duggal, R. Pandey & V. Niranjan

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

118. H. Zhuang, Z. Zhu and Y. Yang, A 19-nW 0.7-V CMOS voltage reference with no
amplifiers and no clock circuits, IEEE Trans. Circuits Syst. II, Express Briefs 61
(2014) 830–834.
119. X. Tong, A. Yang and S. Dong, A 17.6-nW 35.7-ppm/◦ C temperature coefficient all-
SVT-MOSFET subthreshold voltage reference in standard 0.18-µm N-well CMOS,
IEEE Access 8 (2020) 94043–94053.
120. V. R. Beatris and A. A. Fletcher, Low power CMOS voltage reference circuit for
high efficient power management chips, 2022 6th Int. Conf. Devices, Circuits and
Systems (ICDCS), Coimbatore, India, 21–22 April 2022, pp. 248–250.
121. V. Ivanov, R. Brederlow and J. Gerber, An ultra low power bandgap operational at
supply from 0.75 V, IEEE J. Solid-State Circuits 47 (2012) 1515–1523.
122. S. S. Chouhan and K. Halonen, Design and implementation of a micro-power CMOS
voltage reference circuit based on thermal compensation of Vgs, Microelectron. J.
46 (2015) 36–42.
J CIRCUIT SYST COMP Downloaded from [Link]

123. A. Hassan, B. Gosselin and M. Sawan, Ultra-low power CMOS voltage reference
for high temperature applications up to 300◦ C, 2015 IEEE Int. Conf. Electronics,
Circuits, and Systems (ICECS), Cairo, Egypt, 6–9 December 2015, pp. 77–80.
124. L. Magnelli, F. Crupi, P. Corsonello, C. Pace and G. Iannaccone, A 2.6 nW, 0.45 V
temperature-compensated subthreshold CMOS voltage reference, IEEE J. Solid-
State Circuits 46 (2011) 465–474.
125. A. Samir, E. Kussener, W. Rahajandraibe, L. Girardeau, Y. Bert and H. Barthélemy,
A sub-1-V, high precision, ultra-low-power, process trimmable, resistorless voltage
reference with low cost 90-nm standard CMOS technology, Analog Integr. Circuits,
Signal Process. 73 (2012) 693–706.
126. Y. Zeng, Y. Luo, J. Zhang, Z. Gong and H. Z. Tan, A low power CMOS voltage
reference based on body effect, IEICE Electron. Express 10 (2013) 20130154.
127. Y. Zeng, Y. Huang, Y. Luo and H. Z. Tan, An ultra-low-power CMOS voltage
reference generator based on body bias technique, Microelectron. J. 44 (2013) 1145–
1153.
128. S. Yousefi and M. Jalali, An ultra low-power, high-PSRR CMOS voltage reference,
2014 22nd Iranian Conf. on Electrical Engineering (ICEE), Tehran, Iran, 20–22 May
2014, pp. 428–432.
129. Y. Wang, Z. Zhu, J. Yao and Y. Yang, A 0.45-V, 14.6-nW CMOS subthreshold
voltage reference with no resistors and no BJTs, IEEE Trans. Circuits Syst. II,
Express Briefs 62 (2015) 621–625.
130. L. Liu, Y. Song, J. Mu, W. Guo, Z. Zhu and Y. Yang, A high accuracy CMOS
subthreshold voltage reference with offset cancellation and thermal compensation,
Microelectron. J. 60 (2017) 102–108.
131. A. C. de Oliveira, D. Cordova, H. Klimach and S. Bampi, Picowatt, 0.45–0.6 V self-
biased subthreshold CMOS voltage reference, IEEE Trans. Circuits Syst.I, Regul.
Pap. 64 (2017) 3036–3046.
132. Y. Zeng, Y. Li, X. Zhang and H. Z. Tan, Ultra-low-power, high PSRR CMOS voltage
reference with negative feedback, IET Circuits, Devices Syst. 11 (2017) 535–542.
133. Y. Zeng, S. Huang, X. Zhang and H-z. Tan, A 12.8 nA and 7.2 ppm/◦ C CMOS
voltage reference without amplifier, IEICE Electron. Express 15 (2018) 20171220–
20171220.
134. J. Liao, Y. Zeng, J. Li, J. Yang and H.-Z. Tan, A 3.9 ppm/◦ C, 31.5 ppm/V ultra-
low-power subthreshold CMOS-only voltage reference, Microelectron. J. 96 (2020)
104706.

2330005-40
 2nd Reading
May 27, 2023 14:55 WSPC/123-JCSC 2330005

A Comprehensive Study of Different Techniques for Voltage References

by NATIONAL AUTONOMOUS UNIVERSITY OF MEXICO (UNAM) on 08/28/23. Re-use and distribution is strictly not permitted, except for Open Access articles.

135. R. Nagulapalli, K. Hayatleh, S. Barker, S. Raparthy, N. Yassine and J. Lidgey, A 0.6

V MOS-only voltage reference for biomedical applications with 40 ppm/◦ C temper-
ature drift, J. Circuits, Syst. Comput. 27 (2018) 1850128.
136. L. Wang, C. Zhan, L. He, J. Tang, G. Wang, Y. Liu and G. Li, A low-power high-
PSRR CMOS voltage reference with active-feedback frequency compensation for IoT
applications, 2018 IEEE Int. Symp. Circuits and Systems (ISCAS), Florence, Italy,
27–30 May 2018, pp. 1–4.
137. Y. Wang, R. Zhang, Q. Sun and H. Zhang, A 0.5 V, 650 pW, 0.031%/V line regulation
subthreshold voltage reference, 2018 — IEEE 44th European Solid State Circuits
Conf. (ESSCIRC), Dresden, Germany, 3–6 September 2018, pp. 82–85. pp. 82–85.
138. J. Liu, Q. Li, X. Liu, Z. Li, Y. Liu, Z. Lin and X. Wu, Picowatt 0.5 V supply with
3 ppm/◦ C CMOS voltage reference for energy harvesting system, IEICE Electron.
Express 15 (2018) 20180372.
J CIRCUIT SYST COMP Downloaded from [Link]

139. M. Park and S. M. Park, A CMOS symmetric self-biased voltage reference, Micro-
electron. J. 80 (2018) 28–33.
140. A. Bahramali and M. L.-Vallejo, A temperature variation tolerant CMOS-only volt-
age reference for RFID applications, 2018 28th Int. Symp. Power and Timing Mod-
eling, Optimization and Simulation (PATMOS), Platja d’Aro, Spain, 2–4 July 2018,
pp. 62–67.
141. A. Bahramali and M. L.-Vallejo, A low power RFID based energy harvesting tem-
perature resilient CMOS-only reference voltage, Integration 67 (2019) 155–161.
142. T. G. Nejad, E. Farshidi, H. Sjöland and A. Kosarian, A high precision logarithmic-
curvature compensated all CMOS voltage reference, Analog Integr. Circuits Signal
Process. 99 (2019) 383–392.
143. T. G. Nejad, E. Farshidi, H. Sjöland and A. Kosarian, An ultra-low power high-
precision logarithmic-curvature compensated all-CMOS voltage reference in 65 nm
CMOS, Analog Integr. Circuits Signal Process. 107 (2021) 319–330.
144. A. Thakur, R. Pandey and S. K. Rai, Low-temperature coefficient and low line sensi-
tivity subthreshold curvature-compensated voltage reference, Int. J. Circuit Theory
Appl. 48 (2020) 1900–1921.
145. M. Pan, L. Pang, J. Xie, Y. Han and Q. Xu, A 0.6 V 44.6 ppm/◦ C subthreshold
CMOS voltage reference with wide temperature range and inherent leakage compen-
sation, Integration 72 (2020) 111–122.
146. A. Thakur, R. Pandey and S. K. Rai, A sub-1-V CMOS voltage reference with high
PSRR and high accuracy, J. Circuits, Syst. Comput. 31 (2022) 2250176.
147. K. Yu, Y. Zhou, S. Li and M. Huang, A 23-pW NMOS-only voltage reference with
optimum body selection for process compensation, IEEE Trans. Circuits Syst. II,
Express Briefs 69 (2022) 4213–4217.
148. F. Olivera and A. Petraglia, A computer-aided approach for voltage reference circuit
design, Analog Integr. Circuits Signal Process 89 (2016) 511–520.
149. F. Olivera and A. Petraglia, Adjustable output CMOS voltage reference design,
IEEE Trans. Circuits Syst. II, Express Briefs 67 (2020) 1690–1694.
150. A. Thakur, R. Pandey and S. K. Rai, A low supply voltage, low line sensitivity and
high PSRR subthreshold CMOS voltage reference, J. Circuits, Syst. Comput. 30
(2021) 2150227.

2330005-41