VLSI Design and Testing BEC602
ATME COLLEGE OF ENGINEERING
MYSURU-570028
VLSI Design
NOTES FOR 6TH SEMESTER
ELECTRONICS & COMMUNICATION ENGINERRING
SUBJECT CODE : BEC602
Department of ECE, ATME College of Engineering, Mysuru Page 1
INSTITUTIONAL MISSION AND VISION
Vision
• Development of academically excellent, culturally vibrant, socially responsible and globally
competent human resources.
Mission
• To keep pace with advancements in knowledge and make the students competitive and capable
at the global level.
• To create an environment for the students to acquire the right physical, intellectual, emotional
and moral foundations and shine as torch bearers of tomorrow's society.
• To strive to attain ever-higher benchmarks of educational excellence.
DEPARTMENTAL MISSION AND VISION
Vision
To develop highly skilled and globally competent professionals in the field of Electronics and
Communication Engineering to meet industrial and social requirements with ethical responsibility.
Mission
• To provide State-of-art technical education in Electronics and Communication at undergraduate
and post-graduate levels, to meet the needs of the profession and society and achieve excellence
in teaching-learning and research.
• To develop talented and committed human resource, by providing an opportunity for innovation,
creativity and entrepreneurial leadership with high standards of professional ethics, transparency
and accountability.
• To function collaboratively with technical Institutes/Universities/Industries, offer opportunities
for interaction among faculty-students and promote networking with alumni, industries and other
stake-holders.
• To provide State-of-art technical education in Electronics and Communication at undergraduate
and post-graduate levels to meet the needs of the profession and society.
Program outcomes (POs)
Engineering Graduates will be able to:
PO1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering problems.
PO2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics, natural
sciences, and engineering sciences.
PO3. Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate consideration for
the public health and safety, and the cultural, societal, and environmental considerations.
PO4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
PO5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.
PO6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
PO5. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
PO5. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms
of the engineering practice.
PO9. Individual and team work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
PO10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write effective
reports and design documentation, make effective presentations, and give and receive clear instructions.
PO11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and leader in a
team, to manage projects and in multidisciplinary environments.
PO12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.
Program Specific Outcomes (PSOs)
At the end of graduation the student will be able,
• To comprehend the fundamental ideas in Electronics and Communication Engineering and apply
them to identify, formulate and effectively solve complex engineering problems using latest
tools and techniques.
• To work successfully as an individual pioneer, team member and as a leader in assorted groups,
having the capacity to grasp any requirement and compose viable solutions.
• To be articulate, write cogent reports and make proficient presentations while yearning for
continuous self-improvement.
• To exhibit honesty, integrity and conduct oneself responsibly, ethically and legally; holding the
safety and welfare of the society paramount.
Program Educational Objectives (PEOs)
• Graduates will have a successful professional career and will be able to pursue higher education
and research globally in the field of Electronics and Communication Engineering thereby
engaging in lifelong learning.
• Graduates will be able to analyze, design and create innovative products by adapting to the
current and emerging technologies while developing a conscience for environmental/ societal
impact.
• Graduates with strong character backed with professional attitude and ethical values will have
the ability to work as a member and as a leader in a team.
• Graduates with effective communication skills and multidisciplinary approach will be able to
redefine problems beyond boundaries and develop solutions to complex problems of today’s
society.
MODULE 1 Basic MOS Technology
Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell
Labratories. In 1961, first IC was introduced.
Levels of Integration:-
i) SSI:- (10-100) transistors => Example: Logic gates
ii) MSI:- (100-1000) => Example: counters
iii) LSI:- (1000-20000) => Example:8-bit chip
iv) VLSI:- (20000-1000000) => Example:16 & 32 bit up
v) ULSI:- (1000000-10000000) => Example: Special processors, virtual reality machines,
smart sensors
Moore’s Law:- “The number of transistors embedded on the chip doubles after every one and a half
years.” The number of transistors is taken on the y-axis and the years in taken on the x- axis. The
diagram also shows the speed in MHz. the graph given in figure also shows the variation of speed of the
chip in MHz
Figure 1. Moore’s law
The graph in figure2 compares the various technologies available in ICs.
Figure 2.Comparison of available technologies
From the graph we can conclude that GaAs technology is better but still it is not used because of
growing difficulties of GaAs crystal. CMOS looks to be a better option compared to nMOS since it
consumes a lesser power. BiCMOS technology is also used in places where high driving capability is
required and from the graph it confirms that, BiCMOS consumes more power compared to CMOS.
Basic MOS Transistors:
Why the name MOS?
We should first understand the fact that why the name Metal Oxide Semiconductor transistor, because
the structure consists of a layer of Metal (gate), a layer of oxide (Sio2) and a layer of semiconductor.
Figure 3 below clearly tell why the name MOS.
.
Figure 3. Cross Section of a MOS structure
We have two types of FETs. They are Enhancement mode and depletion mode transistor. Also we have
PMOS and NMOS transistors.
In Enhancement mode transistor channel is going to form after giving a proper positive gate voltage.
We have NMOS and PMOS enhancement transistors.
In Depletion mode transistor channel will be present by the implant. It can be removed by giving a
proper negative gate voltage. We have NMOS and PMOS depletion mode transistors.
N-MOS enhancement mode transistor:-
This transistor is normally off. This can be made ON by giving a positive gate
voltage. By giving a +ve gate voltage a channel of electrons is formed between source drain.
P-MOS enhancement mode transistors:-
This is normally on. A Channel of Holes can be performed by giving a –ve gate
voltage. In P-Mos current is carried by holes and in N-Mos its by electrons. Since the mobility is of
holes less than that of electrons P-Mos is slower.
N-MOS depletion mode transistor:-
This transistor is normally ON, even with Vgs=0. The channel will be implanted
while fabricating, hence it is normally ON. To cause the channel to cease to exist, a –
ve voltage must be applied between gate and source.
NOTE: Mobility of electrons is 2.5 to 3 times faster than holes. Hence P-MOS devices will have more
resistance compared to NMOS.
Enhancement mode Transistor action:-
Figure5. (a)(b)(c) Enhancement mode transistor with different Vds Values
To establish the channel between the source and the drain a minimum voltage (Vt) must be
applied between gate and source. This minimum voltage is called as ―Threshold Voltage. The complete
working of enhancement mode transistor can be explained with the help of diagram a, b and c.
a) Vgs>Vt
Vds = 0
Since Vgs>Vt and Vds = 0 the channel is formed but no current flows between drain and source.
b) Vgs>Vt
Vds<Vgs - Vt
This region is called the non-saturation Region or linear region where the drain current increases
linearly with Vds. When Vds is increased the drain side becomes more reverse biased (hence more
depletion region towards the drain end) and the channel starts to pinch. This is called as the pinch off
point.
c) Vgs>Vt
Vds>Vgs–Vt
This region is called Saturation Region where the drain current remains almost constant. As the drain
voltage is increased further beyond (Vgs-Vt) the pinch off point starts to move from the drain end to the
source end. Even if the Vds is increased more and more, the increased voltage gets dropped in the
depletion region leading to a constant current. The typical threshold voltage for an enhancement mode
transistor is given by Vt = 0.2 * Vdd.
1.3.5 Depletion mode Transistor action: -
We can explain the working of depletion mode transistor in the same manner, as that of the
enhancement mode transistor only difference is, channel is established due to the implant even when
Vgs = 0 and the channel can be cut off by applying a -ve voltage between the gate and source.
Threshold voltage of depletion mode transistor is around 0.8*Vdd.
CMOS Logic
MOS Transistor Theory
Introduction, Long-channel I-V Characteristics, Non-ideal I-V Effects, DC Transfer Characteristics (2.1, 2.2, 2.4
and 2.5 of TEXT2)
Long-Channel I-V Characteristics
Non-ideal I-V Effects
Mobility Degradation and Velocity Saturation
The carrier drift velocity, and hence current, is proportional to the lateral electric field 𝐸𝑙𝑎𝑡 = 𝑉𝑑𝑠 /𝐿 between
source and drain. The constant of proportionality is called the carrier mobility, R. The long-channel model
assumed that carrier mobility is independent of the applied fields. This is a good approximation for low fields,
but breaks down when strong lateral or vertical fields are applied.
A high voltage at the gate of the transistor attracts the carriers to the edge of the channel, causing collisions
with the oxide interface that slow the carriers. This is called mobility degradation. Carriers approach a maximum
velocity 𝑣𝑠𝑎𝑡 when high fields are applied. This phenomenon is called velocity saturation.
Mobility degradation can be modelled by replacing R with a smaller 𝑅𝑒𝑓𝑓 that is a function of 𝑉𝑔𝑠 . A universal
model that matches experimental data from multiple processes reasonably well is
The α -power law model provides a simple approximation to capture this behavior. α is called the velocity
saturation index and is determined by curve fitting measured I-V data. Transistors with long channels or low VDD
display quadratic I-V characteristics in saturation and are modeled with α = 2. As transistors become more
velocity saturated, increasing 𝑉𝑔𝑠 has less effect on current and F decreases, reaching 1 for transistors that are
completely velocity saturated. For simplicity, the model uses a straight line in the linear region. Overall, the
model is based on three parameters that can be determined empirically from a curve fit of I-V characteristics: α,
𝛽Pc , and 𝑃𝑣 .
Where,
Channel Length Modulation
The depletion region effectively shortens the channel length to
To avoid introducing the body voltage into our calculations, assume the source voltage is close to the body
voltage so 𝑉𝑑𝑏 ≈ 𝑉𝑑𝑠. Hence, increasing 𝑉𝑑𝑠 decreases the effective channel length. Shorter channel length
results in higher current; thus, 𝐼𝑑𝑠 increases with 𝑉𝑑𝑠 in saturation. This can be crudely modelled by multiplying
by a factor of (1 + 𝑉𝑑𝑠 /𝑉𝐴 ), where 𝑉𝐴 is called the 𝐸𝑎𝑟𝑙𝑦 𝑣𝑜𝑙𝑡𝑎𝑔𝑒. In the saturation region, we find
Depletion region shortens effective channel length
Threshold Voltage Effects
Body Effect
When a voltage 𝑉𝑠𝑏 is applied between the source and body, it increases the amount of charge required to
invert the channel, hence, it increases the threshold voltage. The threshold voltage can be modelled as
where 𝑉𝑡0 is the threshold voltage when the source is at the body potential, Φ𝑠 is the surface potential at
threshold, and 𝛾 is the body effect coefficient, typically in the range 0.4 to 1𝑉1/2 .
In turn, these depend on the doping level in the channel, 𝑁𝐴 .
The body effect further degrades the performance of pass transistors trying to pass the weak value (e.g., nMOS
transistors passing a ‘1’)
For small voltages applied to the source or body, EQ (2.35) can be linearized to
Where,
Drain-Induced Barrier Lowering The drain voltage 𝑉𝑑𝑠 creates an electric field that affects the threshold voltage.
This drain-induced barrier lowering (DIBL) effect is seen more in short-channel transistors. It can be modelled as
where 𝜂 is the DIBL coefficient, typically on the order of 0.1 (often expressed as 100 mV/V).
Drain-induced barrier lowering causes 𝐼𝑑𝑠 to increase with 𝑉𝑑𝑠 in saturation, in much the same way as channel
length modulation does. This effect can be lumped into a smaller Early voltage 𝑉𝐴 . More significantly, DIBL
increases subthreshold leakage at high 𝑉𝑑𝑠 .
Short Channel Effect The threshold voltage typically increases with channel length. This phenomenon is
especially pronounced for small L where the source and drain depletion regions extend into a significant portion
of the channel, and hence is called the short channel effect or 𝑉𝑡 𝑟𝑜𝑙𝑙𝑜𝑓𝑓. In some processes, a reverse short
channel effect causes 𝑉𝑡 to decrease with length.
There is also a narrow channel effect in which 𝑉𝑡 varies with channel width; this effect tends to be less
significant because the minimum width is greater than the minimum length.
DC Transfer Characteristics
Beta Ratio Effects
Noise Margin
Pass Transistor DC Characteristics
