LECTURER: MR.
RANJIT SINGH SARBAN SINGH
LAB SESSION: 2
DIGITAL SIMULATION (COMBINATIONAL LOGIC CIRCUIT DESIGN)
NOOR HAFFIZAH BINTI RAMLI B020810068-BENC Universiti Teknikal Malaysia Melaka 14 July 2009 butterfly_junsu@[Link]
EQUIPMENTS AND MATERIAL
Computer Multisim software
QUESTION 1 Part A Figure 3: Design Truth Table Question 1
RESULTS AND DISCUSSION
Task Figure 1: Design Truth Table and K-Map Task A 0 0 1 1 B 0 1 0 1 X1 0 0 0 1
A B 0 1
0
0 0
1
0 1
X1
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
f 1 1 0 0 0 1 1 0
Equation from k-map: X1 = AB Figure 2: Simple Logic Circuit Simulation
The truth table is design based on the circuit in question 1. Figure 4: K-map Question 1
AB 00 C 0 1 1 1
01 0 0
11 1 0
10 0 1 f
Equation from k-map: f = ABC + BC + AB Figure 5: Design Combinational Logic Circuit Question 1
The light is on when both node A and B are connected to the VCC. If only one node is connected to the VCC, the light still off.
The design circuit is created from the equation that I get after it is simplified by k-map,
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LECTURER: MR. RANJIT SINGH SARBAN SINGH
LAB SESSION: 2
Part B QUESTION 2 Figure 6: Truth Table and Equation Part A Figure 10: Truth Table Question 2 Part A
In Part B, the truth table that get be use to get an equation for the circuit using logic converter. Figure 7: Simplified Equation
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
f 1 0 1 1 0 0 1 0
The equation also can be simplified using logic converter. Figure 8: Simplified Circuit
The truth table is created based on the question given where I need to create a 3-input combinational logic circuit. In the question, there is given the condition which is f = m(0,2,3,6). Figure 11: K-map Question 2 Part A
A 00 B 0 1 1 0
01 1 1
11 1 0
10 0 0 f
Equation from k-map: f = AC + AB + BC The logic converter can directly create a circuit from the simplified equation. Figure 9: Simulation Circuit Figure 12: Design 3-input Combinational Logic Circuit
Figure 13: Truth Table and Simplified Equation Part A
The light is on when node A, B and C is not connected to VCC. There are also another conditions based on the truth table.
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LECTURER: MR. RANJIT SINGH SARBAN SINGH
LAB SESSION: 2
Part B Figure 14: 3-input Combinational Logic Circuit Figure 17: Design Truth Table Question 2 Part B
Figure 15: NAND Logic Circuit Part A
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
f 1 1 0 1 1 1 0 0 1 0 0 0 1 0 0 0
From the logic converter, I can also create an allNAND circuit. Figure 16: NOR Logic Circuit Part A
The truth table is created based on the question where the question need to create a 4-input combinational circuit based on the condition f = m(0,1,3,4,5,8,12). Figure 18: K-map Question 2 Part A
AB 00 01 CD 1 00 1 01 1 1 11 1 10 0
While the all-NOR circuit is created based on the design combinational logic circuit.
11 1 0 0 0
10 1 0 0 0 f
0 0
Equation from the k-map: f = CD + AC + ABD
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LECTURER: MR. RANJIT SINGH SARBAN SINGH
LAB SESSION: 2
Figure 19: Design 4-input Combinational Logic Circuit
Figure 23: NOR Logic Circuit Part B
Question 3 (Design a 2-bit comparator) Figure 20: Truth Table and Simplified Equation Part B In question 3, I am required to design a 2-bit comparator, which can compare between two numbers (2-bit each). Figure 24: Design Truth Table Question 3
A>B A<B A=B A1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F2 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 F1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 F0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1
Figure 21: 4-input Combinational Logic Circuit
Figure 22: NAND Logic Circuit Part B
The conditions for the truth table are A>B for F2, A<B for F1 and A=B for F0.
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LECTURER: MR. RANJIT SINGH SARBAN SINGH
LAB SESSION: 2
Figure 25: K-map for F2
Figure 27: Design Combinational Logic Circuit for F2
CD 00 01 11 10
AB 00 0 0 0 0
01 1 0 0 0
11 10 1 1 0 1 1 1 0 0 F2
Figure 28: Design Combinational Logic Circuit for F1
Equation for F2 = A1B1 + A0B1B0 + A1A0B0 Figure 26: K-map for F1
CD
AB 00
1 0 0 0
01
0 1 0 0
11
0 0 1 0
10
0 0 0 1
Figure 29: Design Combinational Logic Circuit for F0
00 01 11 10
F0
Equation for F1 = A1B1 + A0B1B0 + A1A0B0 Figure 26: K-map for F0
AB 00 CD 00 01 11 10
0 1 1 1
01
0 0 1 1
11
0 0 0 0
10
0 0 1 0
Figure 30: NAND Combinational Logic Circuit for F2
F1
Equation for F0 = A1A0B1B0 + A1A0B1B0 + A1A0B1B0 + A1A0B1B0
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LECTURER: MR. RANJIT SINGH SARBAN SINGH
LAB SESSION: 2
Figure 31: NAND Combinational Logic Circuit for F1
Figure 35: NOR Combinational Logic Circuit for F0
Figure 32: NAND Combinational Logic Circuit for F0
In this lab session, I have learned to use the logic converter to make a truth table, create equation, simplified the equation, create a circuit and also create al-NAND circuit. Using the logic converter is easier and faster to make a combinational logic circuit. Furthermore, the circuit created is tidier. Although it can create all-NAND circuit, the logic converter still has weakness which it cannot create all-NOR circuit.
CONCLUSION
For this lab session 2, I learned to understand the concept of digital logic circuit design. I also learned to use Truth Table, Boolean algebra and Karnaugh map to simplify the combinational logic circuit. I have learned on converting combinational logic circuit to all-NAND or all-NOR logic by using De Morgans theorem. To simplify circuit and equation, I can use logic converter tool in the Multisim. After this lab session, I can design a simple application of combinational logic circuit by using Multisim. After I have done this lab session, I can conclude that I have achieve all the objectives.
Figure 33: NOR Combinational Logic Circuit for F2
References
1. Thomas L. Floyd, 2006, Ninth Edition, Digital Fundamentals. 2. Modul Bengkel Kejuruteraan, FKEKK. Figure 34: NOR Combinational Logic Circuit for F1
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