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constant.However there are applications,such as frequency modulation,tone generators and

frequency keying,where the frequency needs to be controlled by means of an input voltage
called controlled voltage.This function is achieved in the voltage controlled oscillator (VCO)
also called a voltage to frequency converter.

A typical example is the signetics NERSE 566 VCO,which provides simultaneous

square wave and triangular wave outputs as a function of input voltage.Figure(b) is a block
diagram of 566,the frequency of oscillation is determined by an external resistor R1 and
capacitor C1 and the voltage Vc applied to the control terminal 5.The triangular wave is
generated by alternately charging the external capacitor C1 by one current source and then
linearly discharging it by another.The discharge levels are determined by smitt trigger action.
The smitt trigger also provides the squar wave output.Both the output wave forms are buffered
so that the output impedance of each is 50ohms.The tipical amplitude of the triangular wave is
2.4 volts peak to peak and that of the squar wave is 5.4 volts peak to peak.-

UNIT-IV

TIMERS AND PHASE LOCKED LOOPS

4.1 INTRODUCTION TO 555 TIMER

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One of the most versatile linear integrated circuits is the 555 timer. A sample of these
applications includes mono-stable and astablemultivibrators, dc-dc converters, digital logic
probes, waveform generators, analog frequency meters and tachometers, temperature
measurement and control, infrared transmitters, burglar and toxic gas alarms, voltage regulators,
electric eyes, and many others.

The 555 is a monolithic timing circuit that can produce accurate and highly stable time
delays or oscillation. The timer basically operates in one of the two modes: either as monostable
(one-shot) multivibrator or as an astable (free running) multivibrator.The device is available as
an 8-pin metal can, an 8-pin mini DIP, or a 14-pin DIP.

The SE555 is designed for the operating temperature range from -55°Cto + 125°C, while
the NE555 operates over a temperature range of 0° to +70°C. The important features of the 555
timer are these: it operates on +5 to + 18 V supply voltage in both free-running (astable) and
one- shot (monostable) modes; it has an adjustable duty cycle; timing is from microseconds
hrough hours; it has a high current output; it can source or sink 200 mA; the output can drive
TTL and has a temperature stability of 50 parts per million (ppm) per degree Celsius change in
temperature, or equivalently 0.005%/°C.

Like general-purpose op-amps, the 555 timer is reliable, easy to us, and low cost.

Pin 1: Ground. All voltages are measured with respect to this terminal.

Pin 2: Trigger. The output of the timer depends on the amplitude of the external trigger pulse
applied to this pin. The output is low if the voltage at this pin is greater than 2/3 VCC.
However,when a negative-going pulse of amplitude larger than 1/3 VCC is applied to this pin, the
comparator 2 output goes low, which in turn switches the output of the timer high

. The output remains high as long as the trigger terminal is held at a low voltage.

Pin 3: Output. There are two ways a load can be connected to the output terminal: either between
pin 3 and ground (pin 1) or between pin 3 and supply voltage + VCC (pin 8) . When the output is
low, the load current flows through the load connected between pin 3 and + VCC into the output
terminal and is called the sink current.

However, the current through the grounded load is zero when the output is low. For this
reason, the load connected between pin 3 and + VCC is called the normally on load and that
connected between pin 3 and ground is called the normally off load.

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On the other hand, when the output is high, the current through the load connected
between pin 3and + VCC (normally on load) is zero. However, the output terminal supplies
current to the normally off load. This current is called the source current. The maximum value of
sink or source current is 200 mA.

Fig 4-1 Pin diagram of 555Timer

Pin 4: Reset. The 555 timer can be reset (disabled) by applying a negative pulse to this pin.
When the reset function is not in use, the reset terminal should be connected to + VCC to avoid
any possibility of false triggering.

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Fig 4-1(a) Block Diagram

Pin 5: Control voltage. An external voltage applied to this terminal changes the threshold as well

as the trigger voltage . In other words, by imposing a voltage on this pin or by connecting a pot
between this pin and ground, the pulse width of the output waveform can be varied. When not
used, the control pin should be bypassed to ground with a 0.01-μF capacitor to prevent any noise
problems.

Pin 6: Threshold. This is the non-inverting input terminal of comparator 1, which monitors the
voltage across the externalcapacitor . When the voltage at this pin is threshold voltage 2/3 V, the
output of comparator 1 goes high, which in turn switches the output of the timer low.

Pin 7: Discharge. This pin is connected internally to the collector of transistor Q1, as shown in
Figure 4-1(b). When the output is high, Q1 is off and acts as an open circuit to the external
capacitor C connected across it. On the other hand, when the output is low, Q1 is saturated and
acts as a short circuit, shorting out the external capacitor C to ground.

Pin 8: + VCC. The supply voltage of +5 V to +18 is applied to this pin with respect to ground
(pin 1).

4.2. FUNCTIONAL BLOCK DIAGRAM OF 555 TIMER

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Fig 4-1(b) Block diagram of timer

4.3 THE 555 AS A MONOSTABLE MULTIVIBRATOR

A monostablemultivibrator, often called a one-shot multivibrator, is a pulse- generating

circuit in which the duration of the pulse is determined by the RC network connected externally
to the 555 timer.

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In a stable or standby state the output of the circuit is approximately zero or at logic-low
level. When an external trigger pulse is applied, the output is forced to go high ( ≈VCC). The time
the output remains high is determined by the external RC network connected to the timer. At the
end of the timing interval, the output automatically reverts back to its logic-low stable state. The
output stays low until the trigger pulse is again applied. Then the cycle repeats.

The monostable circuit has only one stable state (output low), hence the name mono-
stable. Normally, the output of the mono- stable multivibrator is low. Fig 4.2 (a) shows the 555
configured for monostable operation. To better explain the circuit’s operation, the internal block
diagram is included in Fig 4-2(b).

Figure 4-2(a) IC555 as monostablemultivibrator

Mono-stable operation: According to Fig 4-2(b), initially when the output is low, that is, the
circuit is in a stable state, transistor Q is on and capacitor C is shorted out to ground. However,
upon application of a negative trigger pulse to pin 2, transistor Q is turned off, which releases the
short circuit across the external capacitor C and drives the output high. The capacitorC now starts
charging up toward Vcc through RA.

However, when the voltage across the capacitor equals 2/3 Va., comparator I ‘s output
switches from low to high, which in turn drives the output to its low state via the output of the
flip-flop. At the same time, the output of the flip-flop turns transistor Q on, and hence capacitor
C rapidly discharges through the transistor.

The output of the rnonostable remains low until a trigger pulse is again applied. Then the
cycle repeats. Figure 4-2(c) shows the trigger input, output voltage, and capacitor voltage
waveforms. As shownhere, the pulse width of the trigger input must be smaller than the expected
pulse width of the output waveform. Also, the trigger pulse must be a negative-going input signal
with amplitude larger than 1/3 the time during which the output remains high is given by where

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− 1.1

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Fig.4-2 (b)555 connected as a MonostableMultivibrator (c)input and output waveforms

where RA is in ohms and C is in farads. Figure 4-2(c) shows a graph of the various
combinations of RA and C necessary to produce desired time delays. Note that this graph can
only be used as a guideline and gives only the approximate value of R A and C for a given time
delay. Once triggered, the circuit’s output will remain in the high state until the set time 1,
elapses. The output will not change its state even if an input trigger is applied again during this
time interval T. However, the circuit can be reset during the timing cycle by applying a negative
pulse to the reset terminal. The output will then remain in the low state until a trigger is again
applied.

Often in practice a decoupling capacitor (10 F) is used between + (pin 8) and ground (pin
1) to eliminate unwanted voltage spikes in the output waveform. Sometimes, to prevent any
possibility of mistriggering the monostablemultivibrator on positive pulse edges, a wave
shapingcircuit consisting of R, C2, and diode D is connected between the trigger input pin 2 and
pin 8, as shown in Figure 4-3. The values of R and C2 should be selected so that the time
constant RC2

is smaller than the output pulse width.

Fig.4-3MonostableMultivibrator with wave shaping network to prevent +ve pulse edge

triggering

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4.3.1 MonostableMultivibrator Applications

(a) Frequency divider: The monostablemultivibrator of Figure 4-2(a) can be used as a

frequency divider by adjusting the length of the timing cycle t p, with respect to the tine period T
of the trigger input signal applied to pin 2. To use monostablemultivibrator as a divide-by-2
circuit, the timing interval t p must be slightly larger than the time period T of the trigger input
signal, as shown in Figure 4-4. By the same concept, to use the monostablemultivibrator as a
divide-by-3 circuit, tp must be slightly larger than twice the period of the input trigger signal, and

so on. The frequency-divider application is possible because the monostablemultivibrator cannot

betriggered during the timing cycle.

Fig 4-4 input and output waveforms of a monostable multi vibrator as a divide-by-2 network

(b) Pulse stretcher: This application makes use of the fact that the output pulse width (timing
interval) of the rnonostablemultivibrator is of longer duration than the negative pulse width of
the input trigger. As such, the output pulse width of the monostablemultivibrator can be viewed
as a stretched version of the narrow input pulse, hence the name pulse stretcher. Often, narrow-
pulse- width signals are not suitable for driving an LED display, mainly because of their very
narrow pulse widths. In other words, the LED may be flashing but is not visible to the eye
because its on time is infinitesimally small compared to its off time. The 555 pulse stretcher can
be used to remedy this problem

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Fig 4-5 Monostable multi vibrator as aPulse stretcher

Figure 4-5 shows a basic rnonostable used as a pulse stretcher with an LED indicator at
the output. The LED will be on during the timing interval tp = 1.1RAC, which can be varied by
changing the value of RA and/or C.

4.4 THE 555 AS AN ASTABLE MULTIVIBRATOR

The 555 as an AstableMultivibrator, often called a free-running multivibrator, is a

rectangular-wave-generating circuit. Unlike the monostablemultivibrator, this circuit does not
require an external trigger to change the state of the output, hence the name freerunning.
However, the time during which the output is either high or low is determined by the two
resistors and a capacitor, which are externally connected to the 555 timer. Fig 4-6(a) shows the
555 timer connected as an astablemultivibrator. Initially, when the output is high, capacitor C
starts charging toward V through RA and R8. However as soon as voltage across the capacitor
equals 2/3 Vcc, comparator I triggers the flip flop, and the output switches low [see Fig 4-6(b)].
Now capacitor C starts discharging through R8 and transistor Q. When the voltage across C
equals 1/3 comparator 2’s output triggers the flip-flop, and the output goes high. Then the cycle
repeats.

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Fig 4-6 The 555 as a AstableMultivibrator (a)Circuit(b)Voltage across Capacitor and O/P
waveforms.

The output voltage and capacitor voltage waveforms are shown in Figure 4-6(b). As
shown in this figure, the capacitor is periodically charged and discharged between 2/3 Vcc and
1/3 V, respectively. The time during which the capacitor charges from 1/3 V to 2/3 V. is equal to
the time the output is high and is given by

= 0.69( + )

where RA and R3 are in ohms and C is in farads. Similarly, the time during which the capacitor
discharges from 2/3 V to 1/3 V is equal to the time the output is low and is given by
= 0.69( )

where RB is in ohms and C is in farads. Thus the total period of the output waveform is

= + = 0.69( +2 )

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This, in turn, gives the frequency of oscillation as

1 1.45
= =
( +2 )

Above equation indicates that the frequency fo is independent of the supply voltage V.
Often the term duty cycle is used in conjunction with the astablemultivibrator. The duty cycle is
the ratio of the time t during which the output is high to the total time period T. It is generally
expressed as a percentage. In equation form,

% = × 100

+2
= × 100
+2

4.4.1 AstableMultivibrator Applications:

Square-wave oscillator: Without reducing RA = 0 , the astablemultivibrator can be used

to produce a square wave output simply by connecting diode D across resistor RB, as shown in

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Figure 4-7. The capacitor C charges through RA and diode D to approximately 2/3 Vcc and
discharges through RB and terminal 7 until the capacitor voltage equals approximately 1/3 Vcc;

Fig 4-7 AstableMultivibrator as a Square wave generator

then the cycle repeats. To obtain a square wave output (50% duty cycle), RA must be a
combination of a fixed resistor and potentiometer so that the potentiorneter can be adjusted for
the exact square wave.

Free-running ramp generator: The asab1e multivibrator can be used as a free-running

ramp generator when resistors RA and R3 are replaced by a current mirror. Figure 4-8(a) shows
an astablemultivibrator configured to perform this function. The current mirror starts charging
capacitor C toward Vcc at a constant rate.

Free-running ramp generator: The asab1e multivibrator can be used as a free-running

ramp generator when resistors RA and R3 are replaced by a current mirror. Figure 4-8(a) shows
an astablemultivibrator configured to perform this function. The current mirror starts charging
capacitor C toward Vcc at a constant rate.

When voltage across C equals 2/3 Vcc, comparator 1 turns transistor Q on, and C rapidly
discharges through transistor Q. However, when the discharge voltage across C is approximately
equal to 1/3 Vcc, comparator 2 switches transistor Q off, and then capacitor C starts charging up
again. Thus the charge—discharge cycle keeps repeating. The discharging time of the capacitor
is relatively negligible compared to its charging time; hence, for all practical purposes, the time
period of the ramp waveform is equal to the charging time and is approximately given by

=
3

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Where I = (Vcc— VBE)/R = constant current in amperes and C is in farads. Therefore, the
freerunningfrequency of the ramp generator is
3
=

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Fig 4-8(a)Free Running ramp generator (b)Output waveform.

4.5.SCHMITT TRIGGER

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The below fig 4.9 shows the use of 555 timer as a Schmitt trigger:

Fig 4.9 Timer as Schmitt trigger

The input is given to the pin 2 and pin 6 which are tied together.Pins 4 and 8 are connected to
supply voltage +Vcc.The common point of two pins 2 and 6 are externally biased at Vcc/2 through
the resistance network R1 and R2.Generally R1 =R2 to the gate biasing of V cc/2.The upper
comparator will trip at 2/3Vccwhile lower comparator at 1/3Vcc.The bias provided by R1 and R2
is centered within these two thresholds.

Thus when sine wave of sufficient amplitude,greater thanV cc/6 is applied to the circuit as
input,it causes the internal flip flop to alternately set and reset.Due to this,the circuit produces the
square wave at the output.

4.6 PHASE-LOCKED LOOPS

4.6.1 Introduction

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The phase-locked loop principle has been used in applications such as FM (frequency
modulation) stereo decoders, motor speed controls, tracking filters, frequency synthesized
transmitters and receivers, FM demodulators, frequency shift keying (FSK) decoders, and a
generation of local oscillator frequencies in TV and in FM tuners.

Today the phase-locked loop is even available as a single package, typical examples of
which include the Signetics SE/NE 560 series (the 560, 561, 562, 564, 565, and 567). However,
for more economical operation, discrete ICs can be used to construct a phase-locked loop.

4.6.2 Bloch Schematic and Operating Principle

Figure 4-10 shows the phase-locked loop (PLL) in its basic form. As illustrated in this
figure, the phase-locked loop consists of (1) a phase detector, (2) a low-pass filter, and, (3) a
voltage controlled oscillator.

Fig 4-10 Block Diagram of Phase Locked Loop

The phase detectors or comparator compares the input frequency fINwith the feedback
frequency fOUT..The output voltage of the phase detector is a dc voltage and therefore is often
referred to as the error voltage. The output of the phase is then applied to the low-pass filter,
which removes the high-frequency noise and produces a dc level.

This dc level, in turn, is the input to the voltage-controlled oscillator (VCO). The filter
also helps in establishing the dynamic characteristics of the PLL circuit. The output frequency of
the VCO is directly proportional to the input dc level. The VCO frequency is compared with the

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input frequencies and adjusted until it is equal to the input frequencies. In short, the phase-locked
loop goes through three states: free-running, capture, and phase lock.

Before the input is applied, the phase-locked loop is in the free-running state. Once the
input frequency is applied, the VCO frequency starts to change and the phase-locked loop is said
to be in the capture mode. The VCO frequency continues to change until it equals the input
frequency, and the phase-locked loop is then in the phase-locked state. When phase locked, the
loop tracks any change in the input frequency through its repetitive action.

Before studying the specialized phase-locked-loop IC, we shall consider the discrete
phaselocked loop, which may be assembled by combining a phase detector, a low-pass filter, and
a voltage-controlled oscillator.

(a) Phase detector:

The phase detector compares the input frequency and the VCO frequency and generates a
dc voltage that is proportional to the phase difference between the two frequencies. Depending
on the analog or digital phase detector used, the PLL is either called an analog or digital type,
respectively. Even though most of the monolithic PLL integrated circuits use analogphase
detectors, the majority of discrete phase detectors in use are of the digital type mainly because of
its simplicity.

A double-balanced mixer is a classic example of an analog phase detector. On the other

hand,examples of digital phase detectors are these:

1. Exclusive-OR phase detector

2. Edge-triggered phase detector

3. Monolithic phase detector (such as type 4044)

The following fig 4.11 shows Exclusive-OR phase detector:

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Fig 4-11(a) Exclusive-OR phase detector: connection and logic diagram. (b) Input and output
waveforms. (c) Average output voltage versus phase difference between fINand fOUTcurve.

(b) Low-pass filter.

The second block shown in the PLL block diagram of Figure 4-10 is a low-pass filter.
The function of the low-pass filter is to remove the high-frequency components in the output of
the phase detector and to remove high-frequency noise.

More important, the 1ow-pass filter controls the dynamic characteristics of the phase-
locked loop. These characteristics include capture and lock ranges, bandwidth, and transient
response. The lock range is defined as the range of frequencies over which the PLL system
follows the changes in the input frequency fIN. An equivalent term for lock range is tracking
range. On the other hand, the capture range is the frequency range in which the PLL acquires
phase lock. Obviously, the capture range is always smaller than the lock range.

(c) Voltage-controlled oscillator:

A third section of the PLL is the voltage-controlled oscillator.The VCO generates an

output frequency that is directly proportional to its input voltage.Typical example of VCO is
Signetics NE/SE 566 VCO, which provides simultaneous square wave and triangular wave
outputs as a function of input voltage. The block diagram of the VCO is shown in Fig 4.12. The
frequency of oscillations is determined by thee external R1 and capacitor C1 and the voltage VC
applied to the control terminal 5. The triangular wave is generated by alternatively charging the
external capacitor C1 by one current source and then linearly discharging it by another. The
charging and discharging levels are determined by Schmitt trigger action. The schmitt trigger
also provides square wave output. Both the wave forms are buffered so that the output
impedance of each is 50 ohms.

Fig 4.12 (c) is a typical connection diagram. In this arrangement the R1C1 combination
determines the free running frequency and the control voltage VC at pin 5 is set by voltage
divider formed with R2 and R3. The initial voltage VC at pin 5 must be in the range

3
(+ ) ≤ ≤ +
4

Where +V is the total supply voltage.The modulating signal is ac coupled with the capacitor C
and must be <3 VPP. The frequency of the output wave forms is approximated by

2(+ − )
≅
! (+ )

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whereR1 should be in the range 2KΩ < R1< 20KΩ. For affixed VC and constant C1, the frequency
fO can be varied over a 10:1 frequency range by the choice of R1 between 2KΩ < R1< 20KΩ.

Fig 4.12 VCO Block Diagram

4.7 MONOLITHIC PHASE LOCK LOOPS IC 565:

Monolithic PLLs are introduced bysignetics as SE/NE 560 series and by national semiconductors
LM 560 series.

Fig 4.13 Pin configuration of IC 565

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Fig 4.14 Block Diagram of IC 565

Fig 4.13 and 4.14 shows the pin diagram and block diagram of IC 565 PLL. It consists of
phase detector,amplifier,low pass filter and VCO.As shown in the block diagram the phase
locked feedback loop is not internally connected.Therefore,it is necessary to connect out put of
VCO to the phase comparator input,externally.In frequency multiplication applications a digital
frequency divider is inserted into the loop i.e between pin 4 and pin 5.

The centre frequency of the PLL is determined by the free-running frequency of the VCO
and it is given by

1.2
=
4 1 1

Where R1 and C1 are an external resistor and capacitor connected to pins 8 and 9,
respectively.The values of R1 and C1 are adjusted such that the free running frequency will be at
the centre of the input frequency range.The values of R1 are restricted from 2 kΩ to 20 kΩ,but a
capacitor can have any value.A capacitor C2 connected between pin 7 and the positive supply
forms a first order low pass filter with an internal resistance of 3.6 kΩ.The value of filter
capacitor C2 should be larger enough to eliminate possible demodulated output voltage at pin 7
in order to stabilize the VCO frequency

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The PLL can lock to and track an input signal over typically ±60% bandwidth w.r.t fo as
the center frequency. The lock range fL and the capture range fC of the PLL are given by the
following equations.

8 0
=±

Where fo=free running frequency

V=(+V)-(-V)Volts

And

=±
2 (3.6)10

From above equation the lock range increases with an increase in input voltage but
decrease with increase in supply voltage.The two inputs to the phase detector allows direct
coupling of an input signal,provided that there is no dc voltage difference between the pins and
the dc resistances seen from pins 2 and 3 are equal.

UNIT: 5

DATA CONVERTER INTEGRATED CIRCUITS

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5.1 INTRODUCTION

Fig 5.1 shows the application of A/D and D/A converters.

The transducer circuit will gives an analog signal. This signal is transmitted through the LPF
circuit to avoid higher components, and then the signal is sampled at twice the frequency of the
signal to avoid the overlapping. The output of the sampling circuit is applied to A/D converter
where the samples are converted into binary data i.e. 0’s and 1’s. Like this the analog data
converted into digital data.

The digital data is again reconverted back into analog by doing exact opposite operation of first
half of the diagram. Then the output of the D/A convertor is transmitted through the smoothing
filter to avoid the ripples.

5.2 BASIC DAC TECHNIQUES

The input of the block diagram is binary data i.e, 0 and 1,it contain ‘n’ number of input bits
designated as d1,d2,d3,…..dn .this input is combined with the reference voltage called V dd to give
an analog output.

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Where d1 is the MSB bit and dn is the LSB bit

Vo=Vdd(d1*2-1+d2*2-2+d3*2-3+…………………..+dn*2-n)

Fig 5.2: Basic DAC diagram

5.2.1 Weighted Resistor:

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Fig: 5.3 simple 4-bit weighted resistor

Fig. 5.3 shows a simplest circuit of weighted resistor. It uses a summing inverting amplifier. It
contains n-electronic switches (i.e. 4 switches) and these switches are controlled by binary input
bits d1, d2, d3, d4. If the binary input bit is 1 then the switch is connected to reference voltage –
VREF , if the binary input bit is 0 then the switch is connected to ground.

The output current equation is

Io=I1+I2+ I3+I 4

Io= VREF (d1*2-1+d2*2-2+d3*2-3+d4*2-4 )

The transfer characteristics are shown below (fig 5.4) for a 3-bit weighted resistor

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Fig 5.4 Transfer characteristics of 3-bit weighted resistor

Disadvantages of Weighted resistor D/A converter:

Wide range of resistor’s are required in this circuit and it is very difficult to fabricate such a wide
range of resistance values in monolithic IC. This difficulty can be eliminated using R-2R ladder
network.

5.2.2 R-2R LADDER DAC

Wide range of resistors required in binary weighted resistor type DAC. This can be avoided by
using R-2R ladder type DAC. The circuit of R-2R ladder network is shown in fig 5.5. The basic
theory of the R-2R ladder network is that current flowing through any input resistor (2R)
encounters two possible paths at the far end. The effective resistances of both paths are the same
(also 2R), so the incoming current splits equally along both paths. The half-current that flows
back towards lower orders of magnitude does not reach the op amp, and therefore has no effect
on the output voltage. The half that takes the path towards the op amp along the ladder can affect
the output. The inverting input of the op-amp is at virtual earth. Current flowing in the elements

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of the ladder network is therefore unaffected by switch positions.

Fig 5.5: A 4-bit R-2R Ladder DAC

If we label the bits (or inputs) bit 1 to bit N the output voltage caused by connecting a particular
bit to Vr with all other bits grounded is:
Vout=Vr/2N
where N is the bit number. For bit 1, Vout =Vr/2, for bit 2, Vout = Vr/4 etc.
Since an R/2R ladder is a linear circuit, we can apply the principle of superposition to calculate
Vout. The expected output voltage is calculated by summing the effect of all bits connected to
Vr. For example, if bits 1 and 3 are connected to Vr with all other inputs grounded, the output
voltage is calculated by:
Vout=(Vr/2)+(Vr/8)
which reduces to
Vout=5Vr/8.
An R/2R ladder of 4 bits would have a full-scale output voltage of 1/2 +1/4 + 1/8 + 1/16 =
15Vr/16 or 0.9375 volts (if Vr=1 volt) while a 10bit R/2R ladder would have a full-scale output
voltage of 0.99902 (if Vr=1 volt).

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NOTE:

The number of resistors required for an N-bit D/A converter is 2N in case of R-2R ladder D/A
converter whereas it is only N in the case of weighted resistor D/A converter.

5.2.3 INVERTED R-2R LADDER DAC

In weighted resistor and R-2R ladder DAC the current flowing through the resistor is
always changed because of the changing input binary bits 0 and 1. More power dissipation
causes heating, which in turn cerates non-linearity in DAC. This problem can be avoided by
using INVERTED R-2R LADDER DAC (fig 5.6)

In this MSB and LSB is interchanged. Here each input binary word connects the corresponding
switch either to ground or to the inverting input terminal of op-amp which is also at virtual
ground. When the input binary in logic 1 then it is connected to the virtual ground, when input
binary is logic 0 then it is connected to the ground i.e. the current flowing through the resistor is
constant.

Fig 5.6: Inverted R-2R ladder

5.3 DIFFERENT TYPES OF ADC’S

It provides the function just opposite to that of a DAC. It accepts an analog input voltage Va and
produces an output binary word d1,d2,d3….dn. Where d1 is the most significant bit and d n is the
least significant bit.

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ADCs are broadly classified into two groups according to their conversion techniques

1) Direct type

2) Integrating type

Direct type ADCs compares a given analog signal with the internally generated equivalent
signal. This group includes

i) Flash (Comparator) type converter

ii) Successive approximation type convertor
iii) Counter type
iv) Servo or Tracking type

Integrated type ADCs perform conversion in an indirect manner by first changing the analog
input signal to linear function of time or frequency and then to a digital code

i) Dual slope ADC

5.3.1 FLASH (COMPARATOR) TYPE CONVERTER:

A direct-conversion ADC or flash ADC has a bank of comparators sampling the input signal in
parallel, each firing for their decoded voltage range. The comparator bank feeds a logic circuit
that generates a code for each voltage range. Direct conversion is very fast, capable of gigahertz
sampling rates, but usually has only 8 bits of resolution or fewer, since the number of
comparators needed, 2N - 1, doubles with each additional bit, requiring a large, expensive circuit.
ADCs of this type have a large die size, a high input capacitance, high power dissipation, and are
prone to produce glitches at the output (by outputting an out-of-sequence code). Scaling to newer
submicrometre technologies does not help as the device mismatch is the dominant design
limitation. They are often used for video, wideband communications or other fast signals in
optical storage.

A Flash ADC (also known as a direct conversion ADC) is a type of analog-to-digital

converter that uses a linear voltage ladder with a comparator at each "rung" of the ladder to
compare the input voltage to successive reference voltages. Often these reference ladders are

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constructed of many resistors; however modern implementations show that capacitive voltage
division is also possible. The output of these comparators is generally fed into a digital encoder
which converts the inputs into a binary value (the collected outputs from the comparators can be
thought of as a unary value).

Also called the parallel A/D converter, this circuit is the simplest to understand. It is
formed of a series of comparators, each one comparing the input signal to a unique reference
voltage. The comparator outputs connect to the inputs of a priority encoder circuit, which then
produces a binary output.

Fig-5.7: flash (parallel comparator) type ADC

The following (fig-5.7) illustration shows a 3-bit flashADC circuit:

VR is a stable reference voltage provided by a precision voltage regulator as part of the converter
circuit, not shown in the schematic. As the analog input voltage exceeds the reference voltage at

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each comparator, the comparator outputs will sequentially saturate to a high state. The priority
encoder generates a binary number based on the highest-order active input, ignoring all other
active inputs.

5.3.2 COUNTER TYPE A/D CONVERTER

In the fig-5.8 the counter is reset to zero count by reset pulse. After releasing the reset
pulse the clock pulses are counted by the binary counter. These pulses go through the AND gate
which is enabled by the voltage comparator high output. The number of pulses counted increase
with

Fig-5.8 Countertype A/D converter

time. The binary word representing this count is used as the input of a D/A converter whose
output is a stair case. The analog output Vd of DAC is compared to the analog input inputVa by
the comparator. If Va>Vd the output of the comparator becomes high and the AND gate is
enabled to allow the transmission of the clock pulses to the counter. When Va<Vd the output of
the comparator becomes low and the AND gate is disabled.This stops the counting we can get
the digital data.

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5.3.3 SERVO TRACKING A/D CONVERTER

Fig: 5.9 A tracking A/D converter (b) waveforms associated with a tracking A/D converter

An improved version of counting ADC is the tracking or servo converter shown in fig
5.9. The circuit consists of an up/down counter with the comparator controlling the direction of
the count. The analog output of the DAC is V d and is compared with the analog input Va.If the
input Va is greater than the DAC output signal, the output of the comparator goes high and the
counter is caused to count up. The DAC output increases with each incoming clock pulse when it
becomes more than Va the counter reverses the direction and counts down.

5.3.4 SUCCESSIVE-APPROXIMATION ADC:

One method of addressing the digital ramp ADC's shortcomings is the so-called
successive-approximationADC. The only change in this design as shown in the fig 5.10 is a very
special counter circuit known as a successive-approximation register. Instead of counting up in
binary sequence, this register counts by trying all values of bits starting with the most-significant

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bit and finishing at the least-significant bit. Throughout the count process, the register monitors
the comparator's output to see if the binary count is less than or greater than the analog signal
input, adjusting the bit values accordingly. The way the register counts is identical to the "trial-
and-fit" method of decimal-to-binary conversion, whereby different values of bits are tried from
MSB to LSB to get a binary number that equals the original decimal number. The advantage to
this counting strategy is much faster results: the DAC output converges on the analog signal
input in much larger steps than with the 0-to-full count sequence of a regular counter.

Fig: 5.10 successive approximation ADC

The successive approximation analog to digital converter circuit typically consists of four
chief sub circuits:

1. A sample and hold circuit to acquire the input voltage (Vin).

2. An analog voltage comparator that compares Vin to the output of the internal DAC
and outputs the result of the comparison to the successive approximation register
(SAR).
3. A successive approximation register sub circuit designed to supply an
approximate digital code of Vin to the internal DAC.
4. An internal reference DAC that supplies the comparator with an analog voltage
equivalent of the digital code output of the SAR for comparison with Vin.

The successive approximation register is initialized so that the most significant bit (MSB)
is equal to a digital 1. This code is fed into the DAC, which then supplies the analog equivalent

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of this digital code (Vref/2) into the comparator circuit for comparison with the sampled input
voltage. If this analog voltage exceeds Vin the comparator causes the SAR to reset this bit;
otherwise, the bit is left a 1. Then the next bit is set to 1 and the same test is done, continuing this
binary searchuntil every bit in the SAR has been tested. The resulting code is the digital
approximation of the sampled input voltage and is finally output by the DAC at the end of the
conversion (EOC).

Mathematically, let Vin = xVref, so x in [-1, 1] is the normalized input voltage. The
objective is to approximately digitize x to an accuracy of 1/2n. The algorithm proceeds as
follows:

1. Initial approximation x0 = 0.
2. ith approximation xi = xi-1 - s(xi-1 - x)/2i.

where, s(x) is the signum-function(sgn(x)) (+1 for x ≥ 0, -1 for x < 0). It follows using
mathematical induction that |xn - x| ≤ 1/2n.

As shown in the above algorithm, a SAR ADC requires:

1. An input voltage source Vin.

2. A reference voltage source Vref to normalize the input.
3. A DAC to convert the ith approximation xi to a voltage.
4. A Comparator to perform the function s(xi - x) by comparing the DAC's voltage
with the input voltage.
5. A Register to store the output of the comparator and apply xi-1 - s(xi-1 - x)/2i.

A successive-approximation ADC uses a comparator to reject ranges of voltages,

eventually settling on a final voltage range. Successive approximation works by constantly
comparing the input voltage to the output of an internal digital to analog converter (DAC, fed by
the current value of the approximation) until the best approximation is achieved. At each step in
this process, a binary value of the approximation is stored in a successive approximation register
(SAR). The SAR uses a reference voltage (which is the largest signalthe ADC is to convert) for
comparisons. For example if the input voltage is 60 V and the reference voltage is 100 V, in the
1st clock cycle, 60 V iscompared to 50 V (the reference,divided by two. This is the voltage at the
output of the internal DAC when the input is a '1' followed by zeros), and the voltage from the

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comparator is positive (or '1') (because 60 V is greater than 50 V). At this point the first binary
digit (MSB) is set to a '1'. In the 2nd clock cycle the input voltage is compared to 75 V (being
halfway between 100 and 50 V: This is the output of the internal DAC when its input is '11'
followed by zeros) because 60 V is less than 75 V, the comparator output is now negative (or '0').
The second binary digit is therefore set to a '0'. In the 3rd clock cycle, the input voltage is
compared with 62.5 V (halfway between 50 V and 75 V: This is the output of the internal DAC
when its input is '101' followed by zeros). The output of the comparator is negative or '0'
(because 60 V is less than 62.5 V) so the third binary digit is set to a 0. The fourth clock cycle
similarly results in the fourth digit being a '1' (60 V is greater than 56.25 V, the DAC output for
'1001' followed by zeros). The result of this would be in the binary form 1001. This is also called
bit-weighting conversion, and is similar to a binary search. The analogue value is rounded to the
nearest binary value below, meaning this converter type is mid-rise (see above). Because the
approximations are successive (not simultaneous), the conversion takes one clock-cycle for each
bit of resolution desired. The clock frequency must be equal to the sampling frequency
multiplied by the number of bits of resolution desired. For example, to sample audio at 44.1 kHz
with 32 bit resolution, a clock frequency of over 1.4 MHz would be required. ADCs of this type
have good resolutions and quite wide ranges. They are more complex than some other designs.

5.3.5 DUAL-SLOPE ADC

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Fig 5.11 Functional diagram of dual slope ADC

An integrating ADC (also dual-slopeADC) shown in fig 5.11a applies the unknown input
voltage to the input of an integrator and allows the voltage to ramp for a fixed time period (the
run-up period). Then a known reference voltage of opposite polarity is applied to the integrator
and is allowed to ramp until the integrator output returns to zero (the run-down period). The
input voltage is computed as a function of the reference voltage, the constant run-up time period,
and the measuredrun-down time period. The run-down time measurement is usually made in
units of the converter's clock, so longer integration times allow for higher resolutions. Likewise,
the speed of the converter can be improved by sacrificing resolution. Converters of this type (or
variations on the concept) are used in most digital voltmeters for their linearity and flexibility.

Fig 5.11b o/p waveform of dual slope ADC

In operation the integrator is first zeroed (close SW2), then attached to the input (SW1 up) for a
fixed time M counts of theclock (frequency 1/t). At the end of that time it is attached to the
reference voltage (SW1 down) and the number of counts Nwhich accumulate before the

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integrator reaches zero volts output and the comparator output changes are determined. The
waveform of dual slope ADC is shown in fig 5.11b.

The equations of operation are therefore:

2
1 = 2 − 1 =

And
− =

For an integrator,
−1
∆ = (∆ )

The voltage Vowill be equal to V1 at the instant t2 and can be written as

−1
= ( − )

The voltage V1 is also given by

−1
= (− )( − )

So,
( − )=( )( − )

Putting the values of ( − ) = 2 and ( − )= , we get

(2 ) = ( )

Or,
=( )
2

5.4 SPECIFICATIONS FOR DAC/ADC

1. RESOLUTION: The Resolution of a converter is the smallest change in voltage which

may be produced at the output of the converter.

Resolution (in volts)=(VFS)/(2n-1)= 1 LSB increment

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Ex: an 8-bit D/A converter have 28-1=255 equal intervals. Hence the smallest change in output
voltage is (1/255) of the full scale output range.

An 8-bit DAC is said to have: 8 bit resolution

: a resolution of 0.392 of full scale

: a resolution of 1 part in 255

Similarly the resolution of an A/D converter is defined as the smallest change in analog input for
a one bit change at the output.

Ex: the input range of 8-bit A/D converter is divided into 255 intervals. So the resolution for a
10V input range is 39.22 mV(=10V/255)

2. LINEARITY: The linearity of an A/D or D/A converter is an important measure of its

accuracy and tells us how close the converter output is to its ideal characteristics.
3. GLITCHES (PARTICULARLY DAC): In transition from one digital input to the next,
like 0111 to 1000, it may effectively go through 1111 or 0000, which produces “unexpected”
voltage briefly. If can cause problems elsewhere.
4. ACCURACY: Absolute accuracy is the maximum deviation between the actual converter
output and the ideal converter output.
5. MONOTONIC: A monotonic DAC is the one whose analog output increases for an
increase in digital input. It is essential in control applications. If a DAC has to be monotonic, the
error should de lessthan±(1/2) LSB at each output level.
6. SETTLING TIME: The most important dynamic parameter is the settling time. It
represents the time it takes for the output to settle within a specified band ± (1/2) LSB of its final
value following a code change at the input. It depends upon the switching time of the logic
circuitry due to internal parasitic capacitances and inductances. Its ranges from 100ns to 10µs.
7. STABILITY: The performance of converter changes with temperature, age and power

supply variations. So the stability is required.

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