Unit7 :Sequential CMOS Logic

CIRCUITS

Prepared by: Dr. Ketki C Pathak

EC Dept.
SCET, Surat
CONTENTS

 INTRODUCTION
 BEHAVIOUR OF BISTABLE ELEMENTS
 SR LATCH CIRCUITS
 CLOCKED LATCH AND FLIPFLOP CIRCUITS
 CMOS D LATCH AND EDGE TRIGGERED FLIP FLOP
INTRODUCTION
 BISTABLE: as their name implies, two stable states or operation modes, each of which can be
attained under certain input and output conditions.

 MONOSTABLE: have only one stable operating point (state). Even if the circuit experiences an
external perturbation, the output eventually returns to the single stable state after a certain time
period.

 ASTABLE: there is no stable operating point or state which the circuit can preserve for a certain
time period. Consequently, the output of an astable circuit must oscillate without settling into a
stable operating mode.

 NOTE: Among these three main groups of regenerative circuit types, the bistable circuits are by
far the most widely used 'and the most important class. All basic latch and flip-flop circuits,
registers, and memory elements used in digital systems fall into this category
 Behavior of Bistable Elements

• There are two stable stated of bistable elements as shown.

• If the circuit is initially operating at one of the two stable points,
it will preserve this state unless it is forced externally to change its
state.
• the gain of each inverter circuit, i.e., the slope of the voltage
transfer curves, is smaller than unity at the two stable operating points.
Thus, in order to change the state by moving the operating point from
one stable point to the other, a sufficiently large external voltage
perturbation must be applied so that the voltage gain of the inverter
loop becomes larger than unity
 It is seen that the potential energy
is at its minimum at two of the
three operating points, since the
voltage gains of both inverters are
equal to zero. By contrast, the
energy attains a maximum at the
operating point at which the
voltage gains of both inverters are
maximum.
 at the unstable operating point of
this circuit, all four transistors are in
saturation, resulting in maximum
loop gain for the circuit. If the initial
operating condition is set at this
point, any small voltage
perturbation will cause significant
changes in the operating modes
of the transistors.
 Thus, we expect the output
voltages of the two inverters to
diverge and eventually settle at
VOH and VOL, respectively, as
illustrated
 SR Latch Circuit

 the circuit structure of the simple CMOS SR latch, which

has two such triggering inputs, S (set) and R (reset).
 the SR latch is also called an SR flip-flop, since two stable
states can be switched back and forth.
 The circuit consists of two CMOS NOR2 gates.
 One of the input terminals of each NOR gate is used to
cross-couple to the output of the other NOR gate, while
the second input enables triggering of the circuit.
 Truth table of NOR based SR latch circuit
S R 𝑸𝒏+𝟏 𝑸𝒏+𝟏 Operation
0 0 𝑄𝑛 𝑄𝑛 Hold
1 0 1 0 Set
0 1 0 1 Reset
1 1 0 0 Not allowed

if S is equal to "0" and R is equal to " 1," then the output node Q will be forced to "0" while Q is
forced to "1.“

Thus, with this input combination, the latch is reset, regardless of its previously held state.

Finally, consider the case in which both of the inputs S and R are equal to logic “1 .“

In this case, both output nodes will be forced to logic "0," which conflicts with the
complementarity of Q and Q.

Therefore, this input combination is not permitted during normal operation and is considered to
Operation of the CMOS SR Latch
 If the set input (S) is equal to VOH and the
reset input (R) is equal to VOL, both of the
parallel-connected transistors Ml and M2
will be on. Consequently, the voltage on
node Q will assume a logic-low level of
VOL = 0.
 At the same time, both M3 and M4 are
turned off, which results in a logic-high
voltage VOH at node Q. If the reset input
(R) is equal to VOH and the set input (S) is
equal to VOL, the situation will be
reversed (Ml and M2 turned off and M3
and M4 turned on).
 When both of the input voltages are
equal to VOL' on the other hand, there
are two possibilities. Depending on the
previous state of the SR latch, either M2 or
M3 will be on, while both of the trigger
transistors MI and M4 are off. This will
generate a logic-low level of VOL = O at
one of the output nodes, while the
complementary output node is at VOH.
SR Latch with NAND gate

NAND SR latch responds to active low input signals wh

NOR SR latch responds to active high input signals.
 Depletion load nMOS SR latch

CMOS SR Latch circuit based on NOR2 gate

CMOS SR Latch circuit based on NAND 2 gate
 CLOCKED LATCH AND FLIPFLOP CIRCUITS
CLOCKED SR
LATCH
• Asynchronous sequential circuits, which will respond
to the changes occurring in input signals at a circuit-delay-depe
time point during their operation.

• To facilitate synchronous operation,

the circuit response can be controlled simply by adding a
gating clock signal to the circuit,
so that the outputs will respond to the input levels only
during the active period of a clock pulse.

• It can be seen that if the clock (CK) is equal to logic "0," the input signals have no influence upon the c
• When the clock input goes to logic " 1," the logic levels applied to the S and R inputs are permitted to r
and possibly change its state.
• the circuit is strictly level-sensitive during active clock phases, i.e., any changes occurring. in the S and
when the CK level is equal to " 1 " will be reflected onto the circuit outputs.
Sample input and output waveforms illustrating the
operation of the clocked NOR based SR latch circuit. clocked NOR-based SR latch circuit.

Both input signals S and R as well as the clock signal CK are active low in case of NAND.
NAND based SR latch
 CLOCKED JK LATCH

• The J and K inputs in this circuit correspond

to the set and reset inputs of the basic SR
latch.
• When the clock is active, the latch can be
set with the input combination (J = '1," K =
"0"), and it can be reset with the input
combination (J = "0," K = "1").
• If both inputs are equal to logic "0," the Gate level schematic of the
latch preserves its current state. clocked NAND – based JK Latch
• If, on the other hand, both inputs are
equal to " 1 " during the active clock
phase, the latch simply switches its state
due to feedback.
 Detailed truth table of the JK Latch
circuit
J K 𝑸𝒏 𝑸𝒏 S R 𝑸𝒏+𝟏 𝑸𝒏+𝟏 Opera
ti-on
0 0 0 1 1 1 0 1 hold
1 0 1 1 1 0

0 1 0 1 1 1 0 1 reset
1 0 1 0 0 1

All NAND 1 0 0 1 0 1 1 0 set

implementation of the 1 0 1 1 1 0
clocked JK latch circuit
1 1 0 1 0 1 1 0 toggle
1 0 1 0 0 1
a) Gate level schematic of
the clocked NOR based JK
Latch
b) CMOS realization of the JK Latch
NOTE:
• If both inputs are equal to logic " 1 " during the active phase of
the clock pulse, the output of the circuit will oscillate (toggle)
continuously until either the clock becomes inactive (goes to
zero), or one of the input signals goes to zero.
• To prevent this undesirable timing problem, the clock pulse
width must be made smaller than the input-to-output
propagation delay of the JK latch circuit.
• This restriction dictates that the clock signal must go low
before the output level has an opportunity to switch again,
which prevents uncontrolled oscillation of the output.
MASTER SLAVE FLIP-FLOP

operating principle: the two cascaded stages are activated with

opposite clock phases.
WORKING:
• The input latch in called the "master," is
activated when the clock pulse is
high. During this phase, the inputs J
and K allow data to be entered into
the flip-flop, and the first-stage outputs
are set according to the primary
inputs.
• When the clock pulse goes to zero, the
master latch becomes inactive and
the second-stage latch, called the
"slave," becomes active. The output Master slave flip flop consisting of NAND based
levels of the flip-flop circuit are JK Latches.
determined during this second phase,
based on the master-stage outputs set
• The circuit is never transparent,
i.e., a change occurring in the
primary inputs is never reflected
directly to the outputs.

• Eliminates the possibility of

uncontrolled oscillations since
only one stage is active at any
given time.

• Has the potential problem of "

1’s catching." When the clock
pulse is high, a narrow glitch in
one of the inputs, for instance a
glitch in the J line (or K line),
may set (or reset) the master Input and output waveforms of the master-slave
latch and thus cause an flip-flop
unwanted state transition,
 CMOS D-Latch and Edge – Triggered
Flip-Flop
• Gate-level schematic that the output
Q assumes the value of the input D
when the clock is active, i.e., for CK =
"1.“
Gate level schematic view
• When the clock signal goes to zero, of the D-Latch

the output will simply preserve its state.

Thus, the CK input acts as an enable
signal which allows data to be
accepted into the D-latch.
Block diagram view
• Used for temporary storage of data or of the D-Latch
• The TG at the input is activated by the
CK signal, whereas the TG in the
inverter loop is activated by the
inverse of the CK signal, CK.

• Thus, the input signal is accepted

(latched) into the circuit when the
clock is high, and this information is
preserved as the state of the inverter
loop when the clock is low.

• The operation of the CMOS D-latch CMOS implementation of the D-Latch

circuit can be better visualized by
replacing the CMOS transmission
gates with simple switches
• D input must be stable for a short time
before (setup time, tsetup) and after (hold
time, thold) the negative clock transition,
during which the input switch opens and
the loop switch closes.

• Once the inverter loop is completed by

closing the loop switch, the output will
preserve its valid level.

• In the D-latch design, the requirements for Simplified schematic view

setup time and hold time should be met
carefully.

• Any violation of such specifications can

cause metastability problems which lead to
seemingly chaotic transient behavior, and
can result in an unpredictable state after
the transitional period.
Timing diagram of the CMOS D-
• The transparency property makes the Latch
 D Flip-flop with Tristate inverter

• The first tri-state inverter acts as

the input switch, accepting the
input signal when the clock is
high.

• At this time, the second tristate

inverter is at its high-impedance
state, and the output Q is
following the input signal.

• When the clock goes low, the CMOS implementation of D-

input buffer becomes inactive, Latch
and the second tristate inverter
completes the two-inverter loop,
Master–Slave D Flip-flop
• The two-stage master-slave flip-
flop circuit shown in Fig, which is
constructed by simply cascading
two, D-latch circuits.
• The first stage (master) is driven
by the clock signal, while the
second stage (slave) is driven by
the inverted clock signal.
• Thus, the master stage is positive
level-sensitive, while the slave
stage is negative level-sensitive.
• When the clock is, high, the
master stage follows the D input
while the slave stage holds the CMOS negative edge-triggered master –
previous value. slave DFF
• When the clock changes from
logic "1" to logic “0" the master
latch ceases to sample the input
• At the same time, the slave latch becomes transparent, passing the
stored master value Qm to the output of the slave stage, Qs.
• The input cannot affect the output because the master stage is
disconnected from the D input.
• When the clock changes again from logic 0" to 1," the slave latch
locks in the master latch output and the master stage starts sampling
the input again.

Output
waveform of
the
CMOS DFF
 Timing diagram of the positive edge-triggerd D
NAND based positive edge
DFF
THANK YOU