dsPIC33FJ32MC202/204 and

dsPIC33FJ16MC304
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Family
Silicon Errata and Data Sheet Clarification
The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 For example, to identify the silicon revision level using
family devices that you have received conform MPLAB IDE in conjunction with MPLAB ICD 3 or
functionally to the current Device Data Sheet PICkit™ 3:
(DS70283K), except for the anomalies described in this 1. Using the appropriate interface, connect the device
document. to the MPLAB ICD 3 programmer/debugger or
The silicon issues discussed in the following pages are PICkit 3.
for silicon revisions with the Device and Revision IDs 2. From the main menu in MPLAB IDE, select
listed in Table 1. The silicon issues are summarized in Configure>Select Device, and then select the
Table 2. target part number in the dialog box.
The errata described in this document will be addressed 3. Select the MPLAB hardware tool
in future revisions of the dsPIC33FJ32MC202/204 and (Debugger>Select Tool).
dsPIC33FJ16MC304 silicon. 4. Perform a “Connect” operation to the device
Note: This document summarizes all silicon (Debugger>Connect). Depending on the devel-
errata issues from all revisions of silicon, opment tool used, the part number and Device
previous as well as current. Only the Revision ID value appear in the Output window.
issues indicated in the last column of Note: If you are unable to extract the silicon
Table 2 apply to the current silicon revision level, please contact your local
revision (A6). Microchip sales office for assistance.
Data Sheet clarifications and corrections start on page 12,
The Device and Revision ID values for the various
following the discussion of silicon issues.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
The silicon revision level can be identified using the silicon revisions are shown in Table 1.
current version of MPLAB® IDE and Microchip’s
programmers, debuggers and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).

TABLE 1: SILICON DEVREV VALUES

Revision ID for Silicon Revision(2)
Part Number Device ID(1)
A2 A3 A4 A5 A6
dsPIC33FJ32MC202 0x0F09
dsPIC33FJ32MC204 0x0F0B 0x3001 0x3002 0x3004 0x3005 0x3006
dsPIC33FJ16MC304 0x0F03
Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
2: Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for detailed information on
Device and Revision IDs for your specific device.

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TABLE 2: SILICON ISSUE SUMMARY

Affected
Module Feature
Item
Issue Summary Revisions(1)
Number
A2 A3 A4 A5 A6
JTAG Flash 1. JTAG programming does not work. X X X X X
Programming
UART High-Speed 2. The auto-baud feature may not calculate the correct X X X X X
Mode baud rate when the Baud Rate Generator (BRG) is
set up for 4x mode.
UART Auto-Baud 3. With the auto-baud feature selected, the Sync Break X X X X X
character (0x55) may be loaded into the FIFO as data.
UART Auto-Baud 4. The auto-baud feature measures baud rate X X X X X
inaccurately for certain baud rate and clock speed
combinations.
UART Auto-Baud 5. When an auto-baud is detected, the receive interrupt X X X X X
may occur twice.
UART IR Mode 6. The 16x baud clock signal on the BCLK pin is present X X X X X
only when the module is transmitting.
UART High-Speed 7. When the UART is in 4x mode (BRGH = 1) and using X X X X X
Mode two Stop bits (STSEL = 1), it may sample the first
Stop bit instead of the second one.
SPI SCKx Pins 8. The SPIxCON1 DISSCK bit does not influence port X X X X X
functionality.
I2C™ SFR Writes 9. The BCL bit in I2CxSTAT can be cleared only with  X X X X X
16-bit operation and can be corrupted with 1-bit or 
8-bit operations on I2CxSTAT.
I2C 10-Bit 10. When the I2C module is configured for 10-bit X X X X X
Addressing addressing using the same address bits (A10 and
A9) as other I2C devices, A10 and A9 bits may not
work as expected.
Product Extended 11. Revision A2 devices marked as Extended X
Identification Temperature temperature range (E) devices support only Industrial
temperature range (I).
UART Interrupts 12. The UART error interrupt may not occur, or may X X X X X
occur at an incorrect time, if multiple errors occur
during a short period of time.
UART IR Mode 13. When the UART module is operating in 8-bit mode X X X X X
(PDSEL<1:0> = 0x) and using the IrDA® encoder/
decoder (IREN = 1), the module incorrectly transmits
a data payload of 80h as 00h.
Internal Voltage Sleep Mode 14. When the VREGS bit (RCON<8>) is set to a logic ‘0’, X X X X X
Regulator device may reset and higher Sleep current may be
observed.
PSV — 15. An address error trap occurs in certain addressing X X X X X
Operations modes when accessing the first four bytes of any
PSV page.
I2C 10-Bit 16. When the I2C module is configured as a 10-bit slave X X X X X
Addressing with an address of 0x02, the I2CxRCV register content
for the lower address byte is 0x01 rather than 0x02.
Note 1: Only those issues indicated in the last column apply to the current silicon revision.

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TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)

Affected
Module Feature
Item
Issue Summary Revisions(1)
Number
A2 A3 A4 A5 A6
I2C — 17. With the I2C module enabled, the PORT bits and X X X X X
external interrupt input functions (if any) associated
with SCLx and SDAx pins will not reflect the actual
digital logic levels on the pins.
I2C 10-Bit 18. The 10-bit slave does not set the RBF flag or load the X X X X X
Addressing I2CxRCV register, on address match if the Least
Significant bits (LSbs) of the address are the same as
the 7-bit reserved addresses.
I2C — 19. After the ACKSTAT bit is set when receiving a NACK, it X X X X X
may be cleared by the reception of a Start or Stop bit.
CPU EXCH 20. The EXCH instruction does not execute correctly. X X X X X
Instruction
PWM Debug Mode 21. PTMR does not keep counting down after halting X X X X X
code execution in Debug mode.
PWM Doze Mode 22. The Motor Control PWM module generates more X X X X X
interrupts than expected when Doze mode is used
and the output postscaler value is different than 1:1.
QEI Interrupts 23. The QEI module does not generate an interrupt in a X X X X X
particular overflow condition.
PGEC3/PGED3 Device 24. When using the PGEC3/PGED3 pins for device X X X X X
Programming Programming programming, the programming time may be slower as
Pins compared to other available PGECx/PGEDx pin pairs.
UART Break 25. The UART module will not generate back-to-back X X X X X
Character Break characters.
Generation
QEI Timer Gated 26. When timer gated accumulation is enabled, the QEI X X X X X
Accumulation does not generate an interrupt on every falling edge.
Mode
QEI Timer Gated 27. When timer gated accumulation is enabled and an X X X X X
Accumulation external signal is applied, the POSCNT increments and
Mode generates an interrupt after a match with MAXCNT.
ADC Current 28. If the ADC module is in an enabled state when the X X X X X
Consumption device enters Sleep mode, the power-down current
in Sleep Mode (IPD) of the device may exceed the device data sheet
specifications.
All 150ºC 29. These revisions of silicon only support 140ºC operation X X X X
Operation instead of 150ºC for high-temperature operation.
CPU Interrupt 30. When a previous DISI instruction is active (i.e., the X X X X X
Disable DISICNT register is non-zero), and the value of the
DISICNT register is updated manually, the DISICNT
register freezes and disables interrupts permanently.
CPU div.sd 31. When using the div.sd instruction, the Overflow bit X X X X X
is not getting set when an overflow occurs.
UART TX Interrupt 32. A Transmit (TX) interrupt may occur before the data X X X X X
transmission is complete.
JTAG Flash 33. JTAG Flash programming is not supported. X X X X X
Programming
UART Transmit Mode 34. TRMT bit is set before the Shift register is empty. X X X X X
Note 1: Only those issues indicated in the last column apply to the current silicon revision.

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Silicon Errata Issues 4. Module: UART

Note: This document summarizes all silicon The auto-baud feature may miscalculate for
errata issues from all revisions of silicon, certain baud rate and clock speed combinations,
previous as well as current. Only the resulting in a BRG value that is greater than or less
than the expected value by 1. This may result in
issues indicated by the shaded column in
reception or transmission failures.
the following tables apply to the current
silicon revision (A6). Work around
Test the auto-baud rate at various clock speed and
1. Module: JTAG baud rate combinations that would be used in an
application. If an inaccurate BRG value is
JTAG programming does not work. generated, manually correct the baud rate in user
Work around software.
None. Affected Silicon Revisions
Affected Silicon Revisions A2 A3 A4 A5 A6
A2 A3 A4 A5 A6 X X X X X
X X X X X

5. Module: UART
2. Module: UART When an auto-baud is detected, the receive
interrupt may occur twice. The first interrupt occurs
The auto-baud feature may not calculate the correct at the beginning of the Start bit and the second
baud rate when the High Baud Rate Enable bit, after reception of the Sync field character.
BRGH, is set. With the BRGH bit set, the baud rate
calculation used is the same as BRG = 0. Work around
Work around If an extra interrupt is detected, ignore the
additional interrupt.
If the auto-baud feature is needed, use the Low
Baud Rate mode by clearing the BRGH bit. Affected Silicon Revisions
Affected Silicon Revisions A2 A3 A4 A5 A6
A2 A3 A4 A5 A6 X X X X X
X X X X X

6. Module: UART
3. Module: UART When the UART is configured for IR interface
operations (UxMODE<9:8> = 11), the 16x baud
With the auto-baud feature selected, the Sync clock signal on the BCLK pin is present only when
Break character (0x55) may be loaded into the the module is transmitting. The pin is Idle at all
FIFO as data. other times.
Work around Work around
To prevent the Sync Break character from being Configure one of the output compare modules to
loaded into the FIFO, load the UxBRG register with generate the required baud clock signal when the
either 0x0000 or 0xFFFF prior to enabling the UART is receiving data or in an Idle state.
auto-baud feature (ABAUD = 1).
Affected Silicon Revisions
Affected Silicon Revisions
A2 A3 A4 A5 A6
A2 A3 A4 A5 A6
X X X X X
X X X X X

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7. Module: UART 10. Module: I2C

When the UART is in 4x mode (BRGH = 1) and If there are two I2C devices on the bus, one of
using two Stop bits (STSEL = 1), it may sample the them is acting as the Master receiver and the other
first Stop bit instead of the second one. as the Slave transmitter. Suppose that both
This issue does not affect the other UART devices are configured for 10-Bit Addressing
configurations. mode, and have the same value in the A10 and A9
bits of their addresses. When the Slave select
Work around address is sent from the Master, both the Master
Use the 16x baud rate option (BRGH = 0) and and Slave Acknowledges it. When the Master
adjust the baud rate accordingly. sends out the read operation, both the Master and
the Slave enter into Read mode and both of them
Affected Silicon Revisions transmit the data. The resultant data will be the
ANDing of the two transmissions.
A2 A3 A4 A5 A6
Work around
X X X X X
Use different addresses including the higher two
bits (A10 and A9) for different modules.
Affected Silicon Revisions
8. Module: SPI
When the SPI module is enabled, setting the A2 A3 A4 A5 A6
DISSCK bit in the SPIxCON1 register does not X X X X X
allow the user application to use the SCKx pin as
a general purpose I/O pin.
Work around 11. Module: Product Identification
None.
Revision A2 devices marked as Extended
Affected Silicon Revisions temperature range (E) devices support only the
Industrial temperature range (I).
A2 A3 A4 A5 A6
Work around
X X X X X
Use Revision A3 or newer devices marked as
Extended temperature range (E) devices.
Affected Silicon Revisions
9. Module: I2C
The BCL bit in I2CxSTAT can be cleared only with A2 A3 A4 A5 A6
16-bit operation and can be corrupted with 1-bit or X
8-bit operations on I2CxSTAT.
Work around
Use 16-bit operations to clear BCL. 12. Module: UART
Affected Silicon Revisions The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
A2 A3 A4 A5 A6 during a short period of time.
X X X X X Work around
Read the error flags in the UxSTA register
whenever a byte is received to verify the error
status. In most cases, these bits will be correct,
even if the UART error interrupt fails to occur.
Affected Silicon Revisions

A2 A3 A4 A5 A6
X X X X X

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13. Module: UART 15. Module: PSV Operations

When the UART is operating in 8-bit mode An address error trap occurs in certain addressing
(PDSEL<1:0> = 0x) and using the IrDA encoder/ modes when accessing the first four bytes of a
decoder (IREN = 1), the module incorrectly PSV page. This occurs only when using the
transmits a data payload of 80h as 00h. following addressing modes:
Work around • MOV.D
• Register Indirect Addressing (Word or Byte
None.
mode) with pre/post-decrement
Affected Silicon Revisions
Work around
A2 A3 A4 A5 A6 Do not perform PSV accesses to any of the first
X X X X X four bytes using the above addressing modes. For
applications using the C language, MPLAB C30
Version 3.11 or higher, provides the following
command-line switch that implements a work
14. Module: Internal Voltage Regulator around for the erratum.

When the VREGS bit (RCON<8>) is set to a logic -merrata=psv_trap

‘0’, the device may reset and a higher Sleep Refer to the readme.txt file in the MPLAB C30
current may be observed. v3.11 toolsuite for further details.
Work around Affected Silicon Revisions
Ensure the VREGS bit (RCON<8>) is set to a logic
A2 A3 A4 A5 A6
‘1’ for device Sleep mode operation.
X X X X X
Affected Silicon Revisions

A2 A3 A4 A5 A6
X X X X X 16. Module: I2C
When the I2C module is configured as a 10-bit
slave with an address of 0x02, the I2CxRCV
register content for the lower address byte is 0x01,
rather than 0x02; however, the module
Acknowledges both address bytes.
Work around
None.
Affected Silicon Revisions

A2 A3 A4 A5 A6
X X X X X

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17. Module: I2C 20. Module: CPU

With the I2C module enabled, the PORT bits and The EXCH instruction does not execute correctly.
external interrupt input functions (if any)
Work around
associated with the SCLx and SDAx pins do not
reflect the actual digital logic levels on the pins. If writing source code in assembly, the
recommended work around is to replace:
Work around EXCH Wsource, Wdestination
If the SDAx and/or SCLx pins need to be polled, with:
these pins should be connected to other port pins PUSH Wdestination
in order to be read correctly. This issue does not MOV Wsource, Wdestination
affect the operation of the I2C module. POP Wsource
Affected Silicon Revisions If using the MPLAB C30 C compiler, specify the
compiler option: -merrata=exch (Project > Build
A2 A3 A4 A5 A6 Options > Projects > MPLAB C30 > Use Alternate
X X X X X Settings).
Affected Silicon Revisions

A2 A3 A4 A5 A6
18. Module: I2C
X X X X X
In 10-Bit Addressing mode, some address
matches do not set the RBF flag or load the I2Cx
Receive register, I2CxRCV, if the lower address
byte matches the reserved addresses. In 21. Module: PWM
particular, these include all addresses with the
form ‘xx0000xxxx’ and ‘xx1111xxxx’, with the If the PTDIR bit is set (when PTMR is counting
following exceptions: down), and the CPU execution is halted (after a
breakpoint is reached), PTMR will start counting
• ‘001111000x’ up as if PTDIR was zero.
• ‘011111001x’
Work around
• ‘101111010x’
• ‘111111011x’ None.

Work around Affected Silicon Revisions

Ensure that the lower address byte in 10-Bit A2 A3 A4 A5 A6

Addressing mode does not match any 7-bit
X X X X X
reserved addresses.
Affected Silicon Revisions

A2 A3 A4 A5 A6 22. Module: PWM

X X X X X When the device is operated in Doze mode and
the Motor Control PWM module has a postscaler
set to any value different than 1:1 (PTOPS > 0 in
the PxTCON register), the Motor Control PWM
19. Module: I2C module generates more interrupts than expected.
When the I2C module is operating in either Master Work around
or Slave mode, after the ACKSTAT bit is set when
receiving a NACK, it may be cleared by the Do not use Doze mode with the Motor Control
reception of a Start or Stop bit. PWM if the time base output postscaler is different
than 1:1 (PTOPS > 0 in the PxTCON register).
Work around
Affected Silicon Revisions
Store the value of the ACKSTAT bit immediately
after receiving a NACK. A2 A3 A4 A5 A6
Affected Silicon Revisions X X X X X

A2 A3 A4 A5 A6
X X X X X

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23. Module: QEI 24. Module: PGEC3/PGED3 Programming

Pins
The Quadrature Encoder Interface (QEI) module
does not generate an interrupt when MAXCNT is When using the PGEC3/PGED3 pins for device
set to 0xFFFF and the following events occur: programming, the programming time may be
1. POSCNT underflows from 0x0000 to 0xFFFF. slower as compared to other available PGECx/
PGEDx pin pairs, because the Enhanced In-Circuit
2. POSCNT stops.
Serial Programming™ (ICSP™) algorithm cannot
3. POSCNT overflows from 0xFFFF to 0x0000. be executed on this pin pair.
This sequence of events occurs when the motor is Refer to the “dsPIC33F/PIC24H Flash
running in one direction, which causes POSCNT to Programming Specification” (DS70152) for
underflow to 0xFFFF. Then, if the motor stops and additional information on this limitation.
starts running in the opposite direction, an
overflow from 0xFFFF to 0x0000 will be Work around
generated. The QEI module does not generate an Use alternate PGECx/PGEDx programming pin
interrupt when this condition occurs. pairs.
Work around Affected Silicon Revisions
To prevent this condition from occurring, set
MAXCNT to 0x7FFF, which will cause an interrupt A2 A3 A4 A5 A6
to be generated by the QEI module. X X X X X
In addition, a global variable could be used to keep
track of bit 15, so that when an overflow or
underflow condition is present on POSCNT, the
variable will toggle bit 15. Example 1 shows the
code required for this global variable.
Affected Silicon Revisions

A2 A3 A4 A5 A6
X X X X X

EXAMPLE 1:
unsigned int POSCNT_b15 = 0;
unsigned int Motor_Position = 0;

int main(void)
{
// ... User's code

MAXCNT = 0x7FFF; // Instead of 0xFFFF

Motor_Position = POSCNT_b15 + POSCNT;

// ... User's code

}
void __attribute__((__interrupt__)) _QEIInterrupt(void)
{
IFSxbits.QEIIF = 0; // Clear QEI interrupt flag
// x=2 for dsPIC30F
// x=3 for dsPIC33F
POSCNT_b15 ^= 0x8000; // Overflow or Underflow
}

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25. Module: UART 28. Module: ADC

The UART module will not generate consecutive If the ADC module is in an enabled state when the
Break characters. Trying to perform a back-to- device enters Sleep mode as a result of executing
back Break character transmission will cause the a PWRSAV #0 instruction, the device power-down
UART module to transmit the dummy character current (IPD) may exceed the specifications listed
used to generate the first Break character instead in the device data sheet. This may happen even if
of transmitting the second Break character. Break the ADC module is disabled by clearing the ADON
characters are generated correctly if they are bit prior to entering Sleep mode.
followed by non-Break character transmission.
Work around 1:
Work around In order to remain within the IPD specifications
None. listed in the device data sheet, the user software
must completely disable the ADC module by
Affected Silicon Revisions
setting the ADC module disable bit in the
A2 A3 A4 A5 A6 corresponding Peripheral Module Disable register
(PMDx), prior to executing a PWRSAV #0
X X X X X instruction.
Note: The ADC module must be re-initialized by
the user application before resuming ADC
26. Module: QEI operation.
When the TQCS and TQGATE bits in the QEIxCON
Work around 2:
register are set, a QEI interrupt should be generated
after an input pulse on the QEA input. This interrupt If the ADC module was previously initialized and
is not generated in the affected silicon. enabled before entering Sleep, execute the lines
of code provided in Example 2.
Work around
None. Note: Unlike Work around 1, the user
application does not need to re-initialize
Affected Silicon Revisions the ADC module; however, it is necessary
to re-enable the ADC module by setting
A2 A3 A4 A5 A6
the ADON bit after waking from Sleep.
X X X X X
Affected Silicon Revisions

A2 A3 A4 A5 A6
27. Module: QEI X X X X X
When the TQCS and TQGATE bits in the
QEIxCON register are set, the POSCNT counter
should not increment, but erroneously does, and if
allowed to increment to match MAXCNT, a QEI
interrupt will be generated.
Work around
To prevent the erroneous increment of POSCNT
while running the QEI in Timer Gated
Accumulation mode, initialize MAXCNT = 0.
Affected Silicon Revisions

A2 A3 A4 A5 A6
X X X X X

EXAMPLE 2:
AD1CON1bits.ADON = 0; //Disable the ADC module
__asm__ volatile ("REPEAT #50"); //Wait 50 Tcy
__asm__ volatile ("NOP"); //Repeat NOP 51 times
Sleep(); // Execute PWRSAV #0 and go to Sleep

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29. Module: All 32. Module: UART

The affected silicon revisions listed below are not When using UTXISEL<1:0> = 01 (interrupt when
warranted for operation at +150ºC. last character is shifted out of the Transmit Shift
Register) and the final character is being shifted
Work around
out through the Transmit Shift Register, the
Only use the affected revisions of silicon for the Transmit (TX) interrupt may occur before the final
high-temperature operating range, from -40ºC to bit is shifted out.
+140ºC.
Work around
Affected Silicon Revisions
If it is critical that the interrupt processing occur
A2 A3 A4 A5 A6 only when all transmit operations are complete,
hold off the interrupt routine processing by adding
X X X X a loop at the beginning of the routine that polls the
Transmit Shift Register Empty bit (TRMT) before
processing the rest of the interrupt.
30. Module: CPU Affected Silicon Revisions
When a previous DISI instruction is active (i.e., A2 A3 A4 A5 A6
the DISICNT register is non-zero), and the value of
the DISICNT register is updated manually, the X X X X X
DISICNT register freezes and disables interrupts
permanently.
Work around 33. Module: JTAG
Avoid updating the DISICNT register manually. JTAG Flash programming is not supported.
Instead, use the DISI #n instruction with the
required value for ‘n’. Work around
Affected Silicon Revisions None.

A2 A3 A4 A5 A6 Affected Silicon Revisions

X X X X X A2 A3 A4 A5 A6
X X X X X

31. Module: CPU

When using the Signed 32-by-16-bit Division
instruction, div.sd, the Overflow bit does not
always get set when an overflow occurs.
Work around
Test for and handle overflow conditions outside of
the div.sd instruction.
Affected Silicon Revisions

A2 A3 A4 A5 A6
X X X X X

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34. Module: UART

When the UART is in Transmit mode, the TRMT bit
may be set before the Shift register is empty. In
back-to-back transmission, if the data is loaded
into the U1TXREG register when the TRMT bit is
set, the new byte transmission starts immediately
and the Stop bit may be abbreviated, as shown in
the condition below:
• When BRGH (U1MODE<3>) = 1, the Stop bit
will be shortened by 1/4th of a baud rate
period.
• When BRGH (U1MODE<3>) = 0, the Stop bit
will be shortened by 1/16th of a baud rate
period.
Work around
When using the TRMT bit to load the U1TXREG,
after the TRMT bit is set, insert a delay, as defined
below, before loading the U1TXREG.
When the TRMT bit is set:
• If BRGH = 1, insert a delay of at least 1/4th of
the baud rate period before loading 
U1TXREG.
• If BRGH = 0, insert a delay of at least 1/16th
of the baud rate period before loading 
U1TXREG.
Affected Silicon Revisions

A2 A3 A4 A5 A6
X X X X X

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Data Sheet Clarifications

The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS70283K):
Note: Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.

1. Module: Electrical Characteristics

The specifications for F21a in Table 24-19 have
been updated as shown in bold below.
TABLE 24-19: INTERNAL RC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Param
Characteristic Min Typ Max Units Conditions
No.
LPRC @ 32.768 kHz(1,2)
F21a LPRC -20 ±10 +20 % -40°C  TA +85°C VDD = 3.0-3.6V
F21b LPRC -40 — +40 % -40°C  TA +125°C VDD = 3.0-3.6V
Note 1: Change of LPRC frequency as VDD changes.
2: LPRC impacts the Watchdog Timer Time-out Period (TWDT1). See Section 19.4 “Watchdog Timer (WDT)”
for more information.

2. Module: 19.0 Universal Asynchronous

Receiver Transmitter (UART)
In Section 19.0, a note is added above Figure 19-1:

Note: This note applies to the applications using

the UART module for LIN/J2602 applica-
tions. The LIN/J2602 standard specifies
that the inter-byte space should be a non-
negative number. The inter-byte space is
defined as the time between the end of the
Stop bit of the preceding data and the start
of the following data. It is recommended to
load the data to the U1TXREG after the
received Stop bit is completed. Due to the
half-duplex nature of the LIN/J2602
transceiver, failing to provide non-negative
inter-byte space will result in a truncated
Stop bit. The loading of U1TXREG after the
receive interrupt should be delayed ¾ of
the Stop bit time.

DS80000463J-page 12  2009-2016 Microchip Technology Inc.

 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

APPENDIX A: REVISION HISTORY

Rev A Document (4/2009)
Initial release of this document; issued for revision A2,
A3, A4 and A5 silicon.
Includes silicon issues 1 (JTAG), 2-7 (UART), 8 (SPI),
9-10 (I2C), 11 (Product Identification), 12-13 (UART)
14 (Internal Voltage Regulator), 15 (PSV Operations),
16-19 (I2C), 20 (CPU), 21-22 (PWM) and 23 (QEI).
This document replaces the following errata document:
DS80338, “dsPIC33FJ32MC202/204 and
dsPIC33FJ16MC304 Rev. A2/A3/A4 Silicon Errata”
Rev B Document (8/2009)
Added silicon issues 24 (PGEC3/PGED3 Programming
Pins), 25 (UART), 26-27 (QEI).
Rev C Document (6/2010)
Updated silicon issue 20 (CPU).
Added silicon issue 28 (ADC) and data sheet
clarification 1 (DC Characteristics: I/O Pin Input
Specifications).
Rev D Document (10/2010)
Updated the work around in silicon issue 28 (ADC).
Added silicon issue 29 (All).
Rev E Document (12/2010)
Added silicon revision A6 references throughout the
document.
Rev F Document (3/2011)
Removed data sheet clarification issue 1.
Rev G Document (11/2011)
Added silicon issues 30 (CPU), 31 (CPU), 32 (UART),
and 33 (JTAG).
Rev H Document (12/2013)
Added data sheet clarification 1 (Electrical Characteristics).
Rev J Document (4/2016)
Added silicon issue 34 (UART).
Added data sheet clarification 2 (19.0 Universal
Asynchronous Receiver Transmitter (UART)).

 2009-2016 Microchip Technology Inc. DS80000463J-page 13

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

NOTES:

DS80000463J-page 14  2009-2016 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate,
and may be superseded by updates. It is your responsibility to
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
ensure that your application meets with your specifications.
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MICROCHIP MAKES NO REPRESENTATIONS OR
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
IMPLIED, WRITTEN OR ORAL, STATUTORY OR are registered trademarks of Microchip Technology
OTHERWISE, RELATED TO THE INFORMATION, Incorporated in the U.S.A. and other countries.
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR ClockWorks, The Embedded Control Solutions Company,
FITNESS FOR PURPOSE. Microchip disclaims all liability ETHERSYNCH, Hyper Speed Control, HyperLight Load,
arising from this information and its use. Use of Microchip IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
devices in life support and/or safety applications is entirely at registered trademarks of Microchip Technology Incorporated
the buyer’s risk, and the buyer agrees to defend, indemnify and in the U.S.A.
hold harmless Microchip from any and all damages, claims, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
suits, or expenses resulting from such use. No licenses are BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
conveyed, implicitly or otherwise, under any Microchip dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
intellectual property rights unless otherwise stated. EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and Silicon Storage Technology is a registered trademark of
Tempe, Arizona; Gresham, Oregon and design centers in California Microchip Technology Inc. in other countries.
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping GestIC is a registered trademarks of Microchip Technology
devices, Serial EEPROMs, microperipherals, nonvolatile memory and Germany II GmbH & Co. KG, a subsidiary of Microchip
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified. Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITY MANAGEMENT SYSTEM © 2009-2016, Microchip Technology Incorporated, Printed in
CERTIFIED BY DNV the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0516-0
== ISO/TS 16949 ==

 2009-2016 Microchip Technology Inc. DS80000463J-page 15

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DS80000463J-page 16  2009-2016 Microchip Technology Inc.