B 1200ECT3@,052402

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RegNo.: Name: ,*
APJ ABDUL KALAM TECHNOLOGICAL UMVERSITY
B.Tech Degree 56 (S, FE) / 54 (PT) (S, FE) Examination December 2024 (2019

Course Code: ECT304

Course Name: VLSI CIRCUIT DESIGN

Max. Marks: 100 Duration:3 Hours

PART A

Answel all questions, eoch carries 3 marks Marks

I What is ASIC? Draw the block diagram showing its various classifications. (3)

2 Comment on the performance features of FPGA based design. (3)

3 Draw the DC characteristics of CMOS inverter and mark the regions of operation of
NMOS and PMOS transistors as input is varied from 0 to Vaa. (3)

Show the output waveform, Vout for the following input pattern. Given

Vaa =3V, V,"=lVtpl=1V. Assume zero rise and fall delay. (3)

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11.52

5 logic.
Implement AB+CD in domino (3)
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6 Comparc DRAM and SRAM cells. (3)

7 Express sum and carry output of a full adder in terms of propagate and generate signal. (3)

8 Give the value for critical path delay for 16 bit carry bypass adder and 4* 4 tray
multiplier. Assume tsum: tmrx :tcarry : lOns and tsaup : G"a =5ns. ' (3)

9 Comment on Wet and Dry oxidation. (3)

l0 Draw the stick diagram of rwo input CMOS NAND gate. (3)

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1200ECT304052402

PART B

Answer onefull qu4stionfrom each module, each carries 14 nnrks.

b) Differentiate between Channelled arid channel less gate array. (6)

OR

12 a) With neat diagram explain the structure of an FPGA (9)

comment on rop down ar,rd methodologies. (s)

typ€ NMOS load operated in saturation region. (6)

b) Implement two input XOR and )O{OR in static CMOS logic and

pass transistor logic. (8)

OR

14 a) Derive the expression for Vllla Vn for a static CMOS inverter. (10)

b) Comparison between switch implemented using transmission logic and

pass transistor logic. (4)

Module III
15 a) Draw and explain NORA logiq. How will you connect NORA logic to a NMOS

domino logic ? (7)

b) Comment the working of 3 transistors (3-T) DRAM. (7)

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16 a) Comment on charge sharing issub in domino logic. Explain any method to tpduce it. (8)

b) Implement a4 * 4 NOR based ROM to store the following data I100,1010,

l00l and0llO. (6)

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Module IV
17 a) Explain the mechanism of carty bypassihg in improving critical path delay in

adder design. (4)

b) With neat implementation diagram explain the working of 4*4 array multiplier. (10)

OR
lE a) Explain with diagram liorking of an N bit square root carry select adder. (E)

b) Implement transistor structur€ of sum and carry of a full adder in static CMOS

structure. (6)

Module V

,i 19 a) Describe in detail the manufacturing st€ps of single crystal Silicon from

b) Describe the l. rule to be followed in connecting wires. (4)

OR

20 a)' With neat diagram explain molecular beam epitaxy. (8)

b) Draw the circuit diagram and layout of static CMOS inverter. (6)

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